TI1 LM2903N Low-power, low-offset voltage, dual comparator Datasheet

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LM193-N, LM2903-N, LM293-N, LM393-N
SNOSBJ6F – OCTOBER 1999 – REVISED DECEMBER 2014
LMx93-N, LM2903-N Low-Power, Low-Offset Voltage, Dual Comparators
1 Features
3 Description
•
The LM193-N series consists of two independent
precision voltage comparators with an offset voltage
specification as low as 2.0 mV max for two
comparators which were designed specifically to
operate from a single power supply over a wide range
of voltages. Operation from split power supplies is
also possible and the low power supply current drain
is independent of the magnitude of the power supply
voltage. These comparators also have a unique
characteristic in that the input common-mode voltage
range includes ground, even though operated from a
single power supply voltage.
1
•
•
•
•
•
•
•
•
•
•
•
Wide Supply
– Voltage Range: 2.0 V to 36 V
– Single or Dual Supplies: ±1.0 V to ±18 V
Very Low Supply Current Drain (0.4 mA) —
Independent of Supply Voltage
Low Input Biasing Current: 25 nA
Low Input Offset Current: ±5 nA
Maximum Offset voltage: ±3 mV
Input Common-Mode Voltage Range Includes
Ground
Differential Input Voltage Range Equal to the
Power Supply Voltage
Low Output Saturation Voltage: 250 mV at 4 mA
Output Voltage Compatible with TTL, DTL, ECL,
MOS and CMOS logic systems
Available in the 8-Bump (12 mil) DSBGA Package
See AN-1112 (SNVA009) for DSBGA
Considerations
Advantages
– High Precision Comparators
– Reduced VOS Drift Over Temperature
– Eliminates Need for Dual Supplies
– Allows Sensing Near Ground
– Compatible with All Forms of Logic
– Power Drain Suitable for Battery Operation
2 Applications
•
•
Battery powered applications
Industrial applications
Application areas include limit comparators, simple
analog to digital converters; pulse, squarewave and
time delay generators; wide range VCO; MOS clock
timers; multivibrators and high voltage digital logic
gates. The LM193-N series was designed to directly
interface with TTL and CMOS. When operated from
both plus and minus power supplies, the LM19-N
series will directly interface with MOS logic where
their low power drain is a distinct advantage over
standard comparators.
The LM393 and LM2903 parts are available in TI’s
innovative thin DSBGA package with 8 (12 mil) large
bumps.
Device Information(1)
PART NUMBER
LM193-N
LM293-N
LM393-N
LM2903-N
PACKAGE
BODY SIZE (NOM)
TO-99 (8)
9.08 mm x 9.08 mm
SOIC (8)
4.90 mm x 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM193-N, LM2903-N, LM293-N, LM393-N
SNOSBJ6F – OCTOBER 1999 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
1
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics: LM193A V+= 5 V, TA =
25°C ........................................................................... 5
7.6 Electrical Characteristics: LM193A (V+ = 5 V) ......... 5
7.7 Electrical Characteristics: LMx93 and LM2903 V+= 5
V, TA = 25°C .............................................................. 6
7.8 Electrical Characteristics: LMx93 and LM2903 (V+ =
5 V) (1) ......................................................................... 7
7.9 Typical Characteristics: LMx93 and LM193A............ 8
7.10 Typical Characteristics: LM2903 ............................ 9
8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Applications ................................................ 11
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision D (March 2013) to Revision E
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 1
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SNOSBJ6F – OCTOBER 1999 – REVISED DECEMBER 2014
6 Pin Configuration and Functions
8-Pin TO-99
LMC Package
Top View
8-Pin CDIP, PDIP, SOIC
P and D Package
Top View
8-Pin DSBGA
YZR Package
Top View
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
PDIP/SOIC/
TO-99
DSBGA
OUTA
1
A1
O
Output, Channel A
-INA
2
B1
I
Inverting Input, Channel A
+INA
3
C1
I
Noninverting Input, Channel A
GND
4
C2
P
Ground
+INB
5
C3
I
Noninverting Input, Channel B
-INB
6
B3
I
Inverting Input, Channel B
OUTB
7
A3
O
Output, Channel B
V+
8
A2
P
Positive power supply
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SNOSBJ6F – OCTOBER 1999 – REVISED DECEMBER 2014
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
Differential Input Voltage
(4)
−0.3
Input Voltage
(6)
UNIT
36
V
36
V
50
mA
PDIP
780
mW
TO-99
660
mW
SOIC
510
mW
DSBGA
568
mW
Input Current (VIN<−0.3 V)
Power
Dissipation
MAX
(5)
Output Short-Circuit to Ground
(7)
Continu
ous
Lead Temperature (Soldering, 10 seconds)
260
°C
Soldering
Information
PDIP Package Soldering (10 seconds)
260
°C
SOIC Package
Vapor Phase (60 seconds)
215
°C
Infrared (15 seconds)
220
°C
150
°C
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
(6)
(7)
-65
Absolute Maximum Ratings indicate limits beyond which damage may occur. Recommended Operating Conditions indicate conditions
for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
Refer to RETS193AX for LM193AH military specifications and to RETS193X for LM193H military specifications.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the
magnitude of the negative power supply, if used).
This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of
the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go
to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive
and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3V.
For operating at high temperatures, the LM393 and LM2903 must be derated based on a 125°C maximum junction temperature and a
thermal resistance of 170°C/W which applies for the device soldered in a printed circuit board, operating in a still air ambient. The
LM193/LM193A/LM293 must be derated based on a 150°C maximum junction temperature. The low bias dissipation and the “ON-OFF”
characteristic of the outputs keeps the chip dissipation very small (PD≤100 mW), provided the output transistors are allowed to saturate.
Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 20 mA independent of the magnitude of V+.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±1300
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply Voltage (V+) - Single Supply
2.0
NOM
MAX
UNIT
36
V
±1.0
±18
V
0
(V+) -1.5V
V
Operating junction temperature, TJ : LM193/LM193A
-55
125
°C
Operating junction temperature, TJ : LM2903
-40
85
°C
Operating junction temperature, TJ : LM293
-25
85
°C
Operating junction temperature, TJ : LM393
0
70
°C
Supply Voltage (V+) - Dual Supply
Operating Input Voltage on (VIN pin)
4
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SNOSBJ6F – OCTOBER 1999 – REVISED DECEMBER 2014
7.4 Thermal Information
LMx93
THERMAL METRIC (1)
TO-99
UNIT
8 PINS
RθJA
(1)
Junction-to-ambient thermal resistance
170
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics: LM193A V+= 5 V, TA = 25°C
Unless otherwise stated.
PARAMETER
LM193A
TEST CONDITIONS
MIN
(1)
Input Offset Voltage
See
Input Bias Current
IIN(+) or IIN(−) with Output In Linear Range, VCM = 0 V
Input Offset Current
IIN(+)−IIN(−) VCM = 0 V
Input Common Mode Voltage Range
.
V+ = 30 V
Supply Current
(2)
(3)
RL=∞
TYP
2.0
mV
25
100
nA
3.0
25
nA
+
V −1.5
V
V+=5 V
0.4
1
mA
V+=36 V
1
2.5
mA
0
+
RL≥15 kΩ, V =15 V
VO = 1 V to 11 V
Large Signal Response Time
VIN=TTL Logic Swing, VREF=1.4 V
VRL=5V, RL=5.1 kΩ
Response Time
VRL=5V, RL=5.1 kΩ
Output Sink Current
VIN(−)=1V, VIN(+)=0, VO≈1.5 V
Saturation Voltage
VIN(−)=1V, VIN(+)=0, ISINK≤4 mA
250
Output Leakage Current
VIN(−)=0, VIN(+)=1V, VO=5 V
0.1
(3)
(4)
UNIT
1.0
Voltage Gain
(1)
(2)
MAX
50
(4)
6.0
200
V/mV
300
ns
1.3
μs
16
mA
+
400
mV
nA
+
At output switch point, VO≃1.4V, RS= 0 Ω with V from 5V to 30V; and over the full input common-mode range (0V to V −1.5V), at 25°C.
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end
of the common-mode voltage range is V+−1.5 V at 25°C, but either or both inputs can go to 36 V without damage, independent of the
magnitude of V+.
The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 300 ns can be obtained, see
LMx93 and LM193A Typical Characteristics .
7.6 Electrical Characteristics: LM193A (V+ = 5 V) (1)
PARAMETER
See
Input Offset Current
IIN(+)−IIN(−), VCM=0 V
Input Bias Current
IIN(+) or IIN(−) with Output in Linear Range, VCM=0 V
+
V =30 V
Saturation Voltage
VIN(−)=1V, VIN(+)=0, ISINK≤4 mA
Output Leakage Current
VIN(−)=0, VIN(+)=1V, VO=30 V
(2)
(3)
(4)
(5)
TYP
MAX
(3)
(4)
Input Common Mode Voltage Range
(1)
MIN
(2)
Input Offset Voltage
Differential Input Voltage
LM193A
TEST CONDITIONS
0
−
Keep All VIN's≥0 V (or V , if Used),
(5)
UNIT
4.0
mV
100
nA
300
nA
+
V −2.0
V
700
mV
1.0
μA
36
V
These specifications are limited to −55°C≤TA≤+125°C, for the LM193/LM193A. With the LM293 all temperature specifications are limited
to −25°C≤TA≤+85°C and the LM393 temperature specifications are limited to 0°C≤TA≤+70°C. The LM2903 is limited to
−40°C≤TA≤+85°C.
At output switch point, VO≃1.4V, RS= 0 Ω with V+ from 5V to 30V; and over the full input common-mode range (0V to V+−1.5V), at 25°C.
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end
of the common-mode voltage range is V+−1.5 V at 25°C, but either or both inputs can go to 36 V without damage, independent of the
magnitude of V+.
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the
magnitude of the negative power supply, if used).
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7.7 Electrical Characteristics: LMx93 and LM2903 V+= 5 V, TA = 25°C
Unless otherwise stated.
LM193-N
PARAMETER
MIN
(1)
Input Offset Voltage
See
Input Bias Current
IIN(+) or IIN(−) with Output In
Linear Range, VCM = 0 V (2)
Input Offset Current
IIN(+)−IIN(−) VCM = 0 V
Input Common Mode
Voltage Range
V+ = 30 V
Supply Current
RL=∞
(3)
TYP
5.0
2.0
7.0
mV
25
250
25
250
nA
50
nA
V+−1
.5
V
50
V+−1
.5
5.0
0
1
0.4
1
0.4
1.0
1
2.5
1
2.5
1
2.5
VRL=5 V, RL=5.1 kΩ
Output Sink Current
VIN(−)=1 V, VIN(+)=0, VO≤1.5 V
Saturation Voltage
VIN(−)=1 V, VIN(+)=0, ISINK≤4 mA
250
Output Leakage Current
VIN(−)=0, VIN(+)=1V, VO=5 V
0.1
6
5.0
0
0.4
Response Time
(4)
25
V+−1.
5
VIN=TTL Logic Swing, VREF=1.4 V
VRL=5 V, RL=5.1 kΩ
(3)
TYP MAX
1.0
Large Signal Response
Time
6.0
UNIT
MIN
5.0
RL≥15 kΩ, V+=15 V
VO = 1 V to 11 V
(4)
TYP MAX
100
Voltage Gain
50
MIN
25
3.0
V+=5 V
MAX
LM2903-N
1.0
0
V+=36 V
(1)
(2)
LM293-N, LM393N
TEST CONDITIONS
200
50
200
25
mA
mA
100
V/mV
300
300
300
ns
1.3
1.3
1.5
μs
16
6.0
400
16
250
0.1
6.0
400
16
250
0.1
mA
400
mV
nA
At output switch point, VO≃1.4V, RS= 0 Ω with V+ from 5V to 30V; and over the full input common-mode range (0V to V+−1.5V), at 25°C.
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end
of the common-mode voltage range is V+−1.5 V at 25°C, but either or both inputs can go to 36 V without damage, independent of the
magnitude of V+.
The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 300 ns can be obtained, see
LMx93 and LM193A Typical Characteristics .
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7.8 Electrical Characteristics: LMx93 and LM2903 (V+ = 5 V) (1)
LM193-N
PARAMETER
MIN
Input Offset Voltage
LM293-N, LM393N
TEST CONDITIONS
See
(2)
TYP MAX
MIN
TYP MAX
LM290-N
UNIT
MIN
TYP
MAX
9
9
9
15
mV
Input Offset Current
IIN(+)−IIN(−), VCM=0 V
100
150
50
200
nA
Input Bias Current
IIN(+) or IIN(−) with Output in
Linear Range, VCM=0 V
300
400
200
500
nA
V+−2.
0
V
(3)
Input Common Mode
Voltage Range
V+=30V
Saturation Voltage
VIN(−)=1V, VIN(+)=0,
ISINK≤4 mA
700
700
Output Leakage Current
VIN(−)=0, VIN(+)=1V, VO=30 V
1.0
Differential Input Voltage
Keep All VIN's≥0 V (or V−, if
Used), (5)
36
(1)
(2)
(3)
(4)
(5)
(4)
0
V+−2
.0
0
V+−2
.0
0
400
700
mV
1.0
1.0
μA
36
36
V
These specifications are limited to −55°C≤TA≤+125°C, for the LM193/LM193A. With the LM293 all temperature specifications are limited
to −25°C≤TA≤+85°C and the LM393 temperature specifications are limited to 0°C≤TA≤+70°C. The LM2903 is limited to
−40°C≤TA≤+85°C.
At output switch point, VO≃1.4V, RS= 0 Ω with V+ from 5V to 30V; and over the full input common-mode range (0V to V+−1.5V), at 25°C.
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end
of the common-mode voltage range is V+−1.5 V at 25°C, but either or both inputs can go to 36 V without damage, independent of the
magnitude of V+.
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the
magnitude of the negative power supply, if used).
Copyright © 1999–2014, Texas Instruments Incorporated
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7.9 Typical Characteristics: LMx93 and LM193A
Figure 1. Supply Current
Figure 2. Input Current
Figure 3. Output Saturation Voltage
Figure 4. Response Time for Various Input
Overdrives—Negative Transition
Figure 5. Response Time for Various Input Overdrives—Positive Transition
8
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7.10 Typical Characteristics: LM2903
Figure 6. Supply Current
Figure 8. Output Saturation Voltage
Figure 7. Input Current
Figure 9. Response Time for Various Input
Overdrives—Negative Transition
Figure 10. Response Time for Various Input Overdrives—Positive Transition
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8 Detailed Description
8.1 Overview
The LM139 provides two independently functioning, high-precision, low VOS drift, low input bias current
comparators in a single package. The low power consumption of 0.4mA at 5V and the 2.0V supply operation
makes the LM139 suitable for battery powered applications.
8.2 Functional Block Diagram
Figure 11. Basic Comparator
8.3 Feature Description
The input bias current of 25 nA enables the LM193 to use even very high impedance nodes as inputs. The
differential voltage input range equals the supply voltage range.
The LM193 can be operated with a single supply, where V+ can be from 2.0 V to 36 V, or in a dual supply
voltage configuration, where GND pin is used as a V– supply. The supply current draws only 0.4 mA for both
comparators.
The output of each comparator in the LM193 is the open collector of a grounded-emitter NPN output transistor
which can typically draw up to 16mA.
8.4 Device Functional Modes
A basic comparator circuit is used for converting analog signals to a digital output. The output is HIGH when the
voltage on the non-inverting (+IN) input is greater than the inverting (-IN) input. The output is LOW when the
voltage on the non-inverting (+IN) input is less than the inverting (-IN) input. The inverting input (-IN) is also
commonly referred to as the "reference" or "VREF" input. All pins of any unused comparators should be tied to
the negative supply.
10
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM193 series are high gain, wide bandwidth devices which, like most comparators, can easily oscillate if the
output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only
during the output voltage transition intervals as the comparator change states. Power supply bypassing is not
required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling.
Reducing the input resistors to < 10 kΩ reduces the feedback signal levels and finally, adding even a small
amount (1.0 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to
stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause inputoutput oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse
waveform, with relatively fast rise and fall times, hysteresis is not required.
All input pins of any unused comparators should be tied to the negative supply.
The bias network of the LM193 series establishes a drain current which is independent of the magnitude of the
power supply voltage over the range of from 2.0 VDC to 30 VDC.
The differential input voltage may be larger than V+ without damaging the deviceTypical Applications . Protection
should be provided to prevent the input voltages from going negative more than −0.3 VDC (at 25°C). An input
clamp diode can be used as shown in Typical Applications .
The output of the LM193 series is the uncommitted collector of a grounded-emitter NPN output transistor. Many
collectors can be tied together to provide an output OR'ing function. An output pullup resistor can be connected
to any available power supply voltage within the permitted supply voltage range and there is no restriction on this
voltage due to the magnitude of the voltage which is applied to the V+ terminal of the LM193 package. The
output can also be used as a simple SPST switch to ground (when a pullup resistor is not used). The amount of
current which the output device can sink is limited by the drive available (which is independent of V+) and the β
of this device. When the maximum current limit is reached (approximately 16mA), the output transistor will come
out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the
approximately 60Ω rSAT of the output transistor. The low offset voltage of the output transistor (1.0mV) allows the
output to clamp essentially to ground level for small load currents.
9.2 Typical Applications
9.2.1 Basic Comparator
Figure 12. Basic Comparator
9.2.1.1 Design Requirements
The basic usage of a comparator is to indicate when a specific analog signal has exceeded some predefined
threshold. In this application, the negative input (IN–) is tied to a reference voltage, and the positive input (IN+) is
connected to the input signal. The output is pulled up with a resistor to the logic supply voltage, V+ with a pullup
resistor.
For an example application, the supply voltage is 5V. The input signal varies between 1 V and 3 V, and we want
to know when the input exceeds 2.5 V±1%. The supply current draw should not exceed 1 mA.
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www.ti.com
Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
First, we determine the biasing for the 2.5-V reference. With the 5-V supply voltage, we would use a voltage
divider consisting of one resistor from the supply to IN- and an second resistor from IN–. The 25 nA of input
current bias should be < 1% of the bias current for Vref. With a 100-kΩ resistor from IN– to V+ and an additional
100-KΩ resistor from IN– to ground, there would be 25 µA of current through the two resistors. The 3-kΩ pullup
shown will need 5 V/3 kΩ → 1.67 mA, which exceeds our current budget.
With the 400-µA supply current and 25 µA of VREF bias current, there is 575 µA remaining for output pullup
resistor; with 5-V supply, we need a pullup larger than 8.7 kΩ. A 10-kΩ pullup is a value that is commonly
available and can be used here.
9.2.1.3 Application Curve
Figure 13. Basic Comparator Response
12
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SNOSBJ6F – OCTOBER 1999 – REVISED DECEMBER 2014
Typical Applications (continued)
9.2.2 System Examples
9.2.2.1 Split-Supply Application
(V+=-15 VDC and V-=-15 VDC)
Figure 14. MOS Clock Driver
9.2.2.2 V+ = 5.0 VDC Application Circuits
Figure 15. Driving CMOS
Figure 16. Driving TTL
* For large ratios of R1/R2,
D1 can be omitted.
Figure 17. Squarewave Oscillator
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Figure 18. Pulse Generator
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www.ti.com
Typical Applications (continued)
V* = +30 VDC
+250 mVDC ≤ VC ≤ +50 VDC
700Hz ≤ fo ≤ 100kHz
14
Figure 19. Crystal Controlled Oscillator
Figure 20. Two-Decade High Frequency VCO
Figure 21. Basic Comparator
Figure 22. Non-Inverting Comparator With
Hysteresis
Figure 23. Inverting Comparator With Hysteresis
Figure 24. Output Strobing
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SNOSBJ6F – OCTOBER 1999 – REVISED DECEMBER 2014
Typical Applications (continued)
Figure 25. And Gate
Figure 26. Or Gate
Figure 27. Large Fan-In and Gate
Figure 28. Limit Comparator
Figure 29. Comparing Input Voltages of Opposite
Polarity
Figure 30. Oring the Outputs
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www.ti.com
Typical Applications (continued)
16
Figure 31. Zero Crossing Detector (Single Power
Supply)
Figure 32. One-Shot Multivibrator
Figure 33. Bi-Stable Multivibrator
Figure 34. One-Shot Multivibrator With Input Lock
Out
Figure 35. Zero Crossing Detector
Figure 36. Comparator With a Negative Reference
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SNOSBJ6F – OCTOBER 1999 – REVISED DECEMBER 2014
Typical Applications (continued)
Figure 37. Time Delay Generator
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LM193-N, LM2903-N, LM293-N, LM393-N
SNOSBJ6F – OCTOBER 1999 – REVISED DECEMBER 2014
www.ti.com
10 Power Supply Recommendations
Even in low frequency applications, the LM139-N can have internal transients which are extremely quick. For this
reason, bypassing the power supply with 1.0μF to ground will provide improved performance; the supply bypass
capacitor should be placed as close as possible to the supply pin and have a solid connection to ground. The
bypass capacitor should have a low ESR and also a SRF greater than 50MHz.
11 Layout
11.1 Layout Guidelines
Try to minimize parasitic impedances on the inputs to avoid oscillation. Any positive feedback used as hysteresis
should place the feedback components as close as possible to the input pins. Care should be taken to ensure
that the output pins do not couple to the inputs. This can occur through capacitive coupling if the traces are too
close and lead to oscillations on the output. The optimum placement for the bypass capacitor is closest to the V+
and ground pins. Take care to minimize the loop area formed by the bypass capacitor connection between V+
and ground. The ground pin should be connected to the PCB ground plane at the pin of the device. The
feedback components should be placed as close to the device as possible minimizing strays.
11.2 Layout Example
Figure 38. Layout Example
18
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SNOSBJ6F – OCTOBER 1999 – REVISED DECEMBER 2014
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM193-N
Click here
Click here
Click here
Click here
Click here
LM2903-N
Click here
Click here
Click here
Click here
Click here
LM293-N
Click here
Click here
Click here
Click here
Click here
LM393-N
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1999–2014, Texas Instruments Incorporated
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19
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM193AH
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
-55 to 125
( LM193AH ~
LM193AH)
LM193AH/NOPB
ACTIVE
TO-99
LMC
8
500
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-55 to 125
( LM193AH ~
LM193AH)
LM193H
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
-55 to 125
( LM193H ~ LM193H)
LM193H/NOPB
ACTIVE
TO-99
LMC
8
500
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-55 to 125
( LM193H ~ LM193H)
LM2903ITL/NOPB
ACTIVE
DSBGA
YZR
8
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C
03
LM2903ITLX/NOPB
ACTIVE
DSBGA
YZR
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C
03
LM2903M
ACTIVE
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 85
LM
2903M
LM2903M/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM
2903M
LM2903MX
NRND
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 85
LM
2903M
LM2903MX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM
2903M
LM2903N/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 85
LM
2903N
LM293H
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
-25 to 85
( LM293H ~ LM293H)
LM293H/NOPB
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
-25 to 85
( LM293H ~ LM293H)
LM393M
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
0 to 70
LM
393M
LM393M/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM
393M
LM393MX
NRND
SOIC
D
8
2500
TBD
Call TI
Call TI
0 to 70
LM
393M
LM393MX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM
393M
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
29-May-2015
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM393N/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
0 to 70
LM
393N
LM393TL/NOPB
ACTIVE
DSBGA
YZR
8
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
0 to 70
C
02
LM393TLX/NOPB
ACTIVE
DSBGA
YZR
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
0 to 70
C
02
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM2903ITL/NOPB
DSBGA
YZR
8
250
178.0
LM2903ITLX/NOPB
DSBGA
YZR
8
3000
LM2903MX
SOIC
D
8
2500
LM2903MX/NOPB
SOIC
D
8
LM393MX
SOIC
D
B0
(mm)
K0
(mm)
P1
(mm)
8.4
1.7
1.7
0.76
4.0
178.0
8.4
1.7
1.7
0.76
330.0
12.4
6.5
5.4
2.0
2500
330.0
12.4
6.5
5.4
8
2500
330.0
12.4
6.5
5.4
W
Pin1
(mm) Quadrant
8.0
Q1
4.0
8.0
Q1
8.0
12.0
Q1
2.0
8.0
12.0
Q1
2.0
8.0
12.0
Q1
LM393MX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM393TL/NOPB
DSBGA
YZR
8
250
178.0
8.4
1.7
1.7
0.76
4.0
8.0
Q1
LM393TLX/NOPB
DSBGA
YZR
8
3000
178.0
8.4
1.7
1.7
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM2903ITL/NOPB
DSBGA
YZR
8
250
210.0
185.0
35.0
LM2903ITLX/NOPB
DSBGA
YZR
8
3000
210.0
185.0
35.0
LM2903MX
SOIC
D
8
2500
367.0
367.0
35.0
LM2903MX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM393MX
SOIC
D
8
2500
367.0
367.0
35.0
LM393MX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM393TL/NOPB
DSBGA
YZR
8
250
210.0
185.0
35.0
LM393TLX/NOPB
DSBGA
YZR
8
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0008xxx
D
0.600±0.075
E
TLA08XXX (Rev C)
D: Max = 1.54 mm, Min = 1.479 mm
E: Max = 1.54 mm, Min = 1.479 mm
4215045/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
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