October 1996 ML4961 Adjustable Output Low Voltage Boost Regulator with Detect GENERAL DESCRIPTION FEATURES The ML4961 is a boost regulator designed for DC to DC conversion in 1 to 3 cell battery powered systems. The combination of BiCMOS process technology, internal synchronous rectification, variable frequency operation, and low supply current make the ML4961 ideal for 1 cell applications. The ML4961 is capable of start-up with input voltages as low as 1V, and the output voltage can be set anywhere between 2.5V and 6V by an external resistor divider connected to the SENSE pin. ■ ■ ■ ■ ■ ■ Guaranteed full load start-up and operation at 1V input Pulse Frequency Modulation and Internal Synchronous Rectification for high efficiency Minimum external components Low ON resistance internal switching FETs Micropower operation Adjustable output voltage (2.5V to 6V) An integrated synchronous rectifier eliminates the need for an external Schottky diode and provides a lower forward voltage drop, resulting in higher conversion efficiency. In addition, low quiescent battery current and variable frequency operation result in high efficiency even at light loads. The ML4961 requires a minimum number of external components to build a very small adjustable regulator circuit capable of achieving conversion efficiencies in excess of 90%. The circuit also contains a RESET output which goes low when the IC can no longer function due to low input voltage, or when the DETECT input drops below 200mV. BLOCK DIAGRAM L1 CIN* 1 6 VIN CFF* VL VOUT + 5 UVLO *RA R1 DETECT + 4 BOOST CONTROL – + – SENSE 3 COUT VREF *RB R2 PWR GND GND 8 2 – RESET 7 *OPTIONAL TO MICROPROCESSOR 1 ML4961 PIN CONNECTION ML4961 8-Pin SOIC (S08) VIN 1 8 PWR GND GND 2 7 RESET SENSE 3 6 VL DETECT 4 5 VOUT TOP VIEW PIN DESCRIPTION PIN NO. 2 NAME FUNCTION PIN NO. NAME FUNCTION 1 VIN Battery input voltage 5 VOUT Boost regulator output 2 GND Analog signal ground 6 VL Boost inductor connection 3 SENSE Programming pin for setting the output voltage 7 RESET 4 DETECT Pulling this pin below VREF, causes the RESET pin to go low Output goes low when regulation cannot be achieved, or when DETECT goes below 200mV 8 PWR GND Return for the NMOS output transistor ML4961 ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Temperature Range ML4961CS ................................................. 0°C to 70°C ML4961ES .............................................. –20°C to 70°C ML4961IS ............................................... –40°C to 85°C VIN Operating Range ML4961CS ..................................... 1.0V to VOUT –0.2V ML4961ES, ML4961IS ....................1.1V to VOUT –0.2V VOUT Operating Range ................................. 2.5V to 6.0V Voltage on any pin ....................................................... 7V Peak Switch Current, I(PEAK) ......................................... 2A Average Switch Current, I(AVG) .............................. 500mA Junction Temperature .............................................. 150°C Storage Temperature Range ...................... –65°C to 150°C Lead Temperature (Soldering 10 sec.) ...................... 260°C Thermal Resistance (θJA) ..................................... 160°C/W ELECTRICAL CHARACTERISTICS Unless otherwise specified, VIN = Operating Voltage Range, T A = Operating Temperature Range (Note 1) PARAMETER CONDITIONS MIN TYP. MAX UNITS 45 55 µA 3 5 µA 1 µA Supply VIN Current VIN = VOUT – 0.2V VOUT Quiescent Current VL Quiescent Current PFM Regulator Pulse Width (TON) VIN = 2.4V 9 10 11 µs 8.5 10 11.5 µs 194 200 206 mV 4.85 4.85 5.0 5.0 5.15 5.15 V V C/E Suffix 0.85 0.95 V I Suffix 0.95 1.05 V 200 210 mV 100 nA C/E Suffix I Suffix SENSE Comparator Threshold Voltage (VSENSE) Load Regulation See Figure 1 VIN = 1.2V, IOUT ≤ 25mA VIN = 2.4V, IOUT ≤ 135mA Undervoltage Lockout Threshold RESET Comparator DETECT Threshold 190 DETECT Bias Current –100 RESET Output High Voltage (VOH) IOH = –100µA RESET Output Low Voltage (VOL) IOL = 100µA Note 1: VOUT – 0.2 V 0.2 V Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. 3 ML4961 27µH (Sumida CD75) VIN ML4961 100µF VIN PWR GND GND RESET SENSE DETECT VL IOUT VOUT 97.6KΩ 0.1% 100µF 4.02KΩ 0.1% Figure 1. PFM Regulator Block Diagram. L1 VIN 6 VL Q2 START-UP + VOUT + 5 A2 C1 – R Q 10µs ONE SHOT Q1 R1 S – A1 + VREF Figure 2. PFM Regulator Block Diagram. 4 R2 VOUT – ML4961 RESET COMPARATOR FUNCTIONAL DESCRIPTION The ML4961 combines Pulse Frequency Modulation (PFM) and synchronous rectification to create a boost converter that is both highly efficient and simple to use. A PFM regulator charges a single inductor for a fixed period of time and then completely discharges before another cycle begins, simplifying the design by eliminating the need for conventional current limiting circuitry. Synchronous rectification is accomplished by replacing an external Schottky diode with an on-chip PMOS device, reducing switching losses and external component count. REGULATOR OPERATION A block diagram of the boost converter is shown in Figure 2. The circuit remains idle when VOUT is at or above the desired output voltage, drawing 45µA from VIN, and 8µA from VOUT through the feedback resistors R1 and R2. When VOUT drops below the desired output level, the output of amplifier A1 goes high, signaling the regulator to deliver charge to the output. Since the output of amplifier A2 is normally high, the flip-flop captures the A1 set signal and creates a pulse at the gate of the NMOS transistor Q1. The NMOS transistor will charge the inductor L1 for 10µs, resulting in a peak current given by: IL(PEAK) = TON × VIN 10µs × VIN ≈ L1 L1 (1) For reliable operation, L1 should be chosen so that IL(PEAK) does not exceed 2A. When the one-shot times out, the NMOS FET releases the VL pin, allowing the inductor to fly-back and momentarily charge the output through the body diode of PMOS transistor Q2. But, as the voltage across the PMOS transistor changes polarity, its gate will be driven low by the current sense amplifier A2, causing Q2 to short out its body diode. The inductor then discharges into the load through Q2. The output of A2 also serves to reset the flipflop and one-shot in preparation for the next charging cycle. A2 releases the gate of Q2 when its current falls to zero. If VOUT is still low, the flip-flop will immediately initiate another pulse. The output capacitor (C1) filters the inductor current, limiting output voltage ripple. Inductor current and one-shot waveforms are shown in Figure 3. An additional comparator is provided to detect low VIN, or any other error condition that is important to the user. The inverting input of the comparator is internally connected to VREF, while the non-inverting input is provided externally at the DETECT pin. The output of the comparator is the RESET pin, which swings from VOUT to GND when an error is detected. DESIGN CONSIDERATIONS INDUCTOR Selecting the proper inductor for a specific application usually involves a trade-off between efficiency and maximum output current. Choosing too high a value will keep the regulator from delivering the required output current under worst case conditions. Choosing too low a value causes efficiency to suffer. It is necessary to know the maximum required output current and the input voltage range to select the proper inductor value. The maximum inductor value can be estimated using the following formula: 2 LMAX = VIN(MIN) × TON(MIN) × η 2 × VOUT × IOUT(MAX) (2) where η is the efficiency, typically between 0.8 and 0.9. Note that this is the value of inductance that just barely delivers the required output current under worst case conditions. A lower value may be required to cover inductor tolerance, the effect of lower peak inductor currents caused by resistive losses, and minimum dead time between pulses. Another method of determining the appropriate inductor value is to make an estimate based on the typical performance curves given in Figures 4 and 5. Figure 4 shows maximum output current as a function of input voltage for several inductor values. These are typical performance curves and leave no margin for inductance and ON-time variations. To accommodate worst case conditions, it is necessary to derate these curves by at least 10% in addition to inductor tolerance. Interpolation between the different curves will give a reasonable starting point for an inductor value. INDUCTOR CURRENT Q(ONE SHOT) Q1 ON Q2 ON Q1 ON Q2 ON Q1 & Q2 OFF Figure 3. PFM Inductor Current Waveforms and Timing. 5 ML4961 ML4961(VOUT = 3.3V) L = 27µH L = 10µH L = 15µH L = 15µH 400 IOUT MAX (mA) ML4961(VOUT = 5.0V) 500 400 IOUT MAX (mA) 500 L = 27µH 300 200 L = 56µH 100 L = 10µH 300 L = 56µH 200 100 0 1.0 2.0 0 3.0 1.0 VIN (V) 2.0 3.0 4.0 VIN (V) Figure 4. Output Current vs. Input Voltage. ML4961-(VOUT = 3.3V) 95% ML4961-(VOUT = 5.0V) 95% L = 57µH L = 56µH EFFICIENCY AT IOUT MAX EFFICIENCY AT IOUT MAX 90% L = 27µH 85% 80% L = 15µH 75% 90% L = 27µH 85% L = 15µH 80% 75% L = 10µH L = 10µH 70% 65% 70% 0 1 2 0 1.0 2.0 3.0 4.0 VIN (V) 3 VIN Figure 5. Typical Efficiency as a Function of V IN. Figure 5 shows efficiency under the conditions used to create Figure 4. It can be seen that efficiency is mostly independent of input voltage and is closely related to inductor value. This illustrates the need to keep the inductor value as high as possible to attain peak system efficiency. As the inductor value goes down to 10µH, the efficiency drops to between 70% and 75%. With 56µH, the efficiency exceeds 90% and there is little room for improvement. At values greater than 100µH, the operation of the synchronous rectifier becomes unreliable because the inductor current is so small that it is difficult for the control circuitry to detect. After the appropriate inductor value is chosen, it is necessary to find the minimum inductor current rating required. Peak inductor current is determined from the following formula: IL(PEAK) 6 T × VIN(MAX) = ON(MAX) LMIN (3) When comparing various inductors, it is important to keep in mind that suppliers use different criteria to determine their ratings. Many use a conservative current level, where inductance has dropped to 90% of its normal level. In any case, it is a good idea to try inductors of various current ratings with the ML4961 to determine which inductor is the best choice. Check efficiency and maximum output current, and if a current probe is available, look at the inductor current to see if it looks like the waveform shown in Figure 3. For additional information, see Application Note 29. Suitable inductors can be purchased from the following suppliers: Coilcraft (708) 639-6400 Coiltronics (407) 241-7876 Dale (605) 665-9301 Sumida (708) 956-0666 ML4961 OUTPUT CAPACITOR The choice of output capacitor is also important, as it controls the output ripple and optimizes the efficiency of the circuit. Output ripple is influenced by three capacitor parameters: capacitance, ESR, and ESL. The contribution due to capacitance can be determined by looking at the change in capacitor voltage required to store the energy delivered by the inductor in a single charge-discharge cycle, as determined by the following formula: 2 ∆VOUT = 2 TON × VIN 2 × L × C × (VOUT − VIN) (4) For a 2.4V input, and 5V output, a 27µH inductor, and a 47µF capacitor, the expected output ripple due to capacitor value is 87mV. Capacitor Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL), also contribute to the output ripple due to the inductor discharge current waveform. Just after the NMOS transistor turns off, the output current ramps quickly to match the peak inductor current. This fast change in current through the output capacitor’s ESL causes a high frequency (5ns) spike that can be over 1V in magnitude. After the ESL spike settles, the output voltage still has a ripple component equal to the inductor discharge current times the ESR. This component will have a sawtooth shape and a peak value equal to the peak inductor current times the ESR. ESR also has a negative effect on efficiency by contributing I-squared R losses during the discharge cycle. An output capacitor with a capacitance of 100µF, an ESR of less than 0.1Ω, and an ESL of less than 5nH is a good general purpose choice. Tantalum capacitors which meet these requirements can be obtained from the following suppliers: AVX (207) 282-5111 Sprague (207) 324-4140 The value of R2 should be 40kΩ or less to minimize bias current errors. R1 is then found by rearranging the equation: V R1 = R2 × OUT − 1 0 . 2 (6) It is important to note that the accuracy of these resistors directly affects the accuracy of the output voltage. The SENSE pin threshold variation is ±3%, and the tolerances of R1 and R2 will add to this to determine the total output variation. In some applications, input noise may cause output ripple to become excessive due to “pulse grouping”, where the charge-discharge pulses are not evenly spaced in time. In such cases it may be necessary to add a small 20pF to 100pF ceramic feedforward capacitor (CFF) from the VIN pin to the SENSE pin. SETTING THE RESET THRESHOLD To use the RESET comparator as an input voltage monitor, it is necessary to use an external resistor divider tied to the DETECT pin as shown in the block diagram. The resistor values RA and RB can be calculated using the following equation: VIN(MIN) = 0.2 × (R A + RB ) RB (7) The value of RB should be 100kΩ or less to minimize bias current errors. RA is then found by rearranging the equation: V R A = RB × IN(MIN) − 1 0.2 (8) LAYOUT If ESL spikes are causing output noise problems, an EMI filter can be added in series with the output. INPUT CAPACITOR Unless the input source is a very low impedance battery, it will be necessary to decouple the input with a capacitor with a value of between 47µF and 100µF. This provides the benefits of preventing input ripple from affecting the ML4961 control circuitry, and it also improves efficiency by reducing I-squared R losses during the charge and discharge cycles of the inductor. Again, a low ESR capacitor (such as tantalum) is recommended. Good PC board layout practices will ensure the proper operation of the ML4961. Important layout considerations include: • Use adequate ground and power traces or planes • Keep components as close as possible to the ML4961 • Use short trace lengths from the inductor to the VL pin and from the output capacitor to the VOUT pin • Use a single point ground for the ML4961 ground pins, and the input and output capacitors SETTING THE OUTPUT VOLTAGE The adjustable output can be set to any voltage between 2.5V and 6V by connecting a resistor divider to the SENSE pin as shown in the block diagram. The resistor values R1 and R2 can be calculated using the following equation: VOUT = 0.2 × (R1 + R2) R2 (5) 7 ML4961 PHYSICAL DIMENSIONS inches (millimeters) Package: S08 8-Pin SOIC .187/.198 (4.75/5.03) .011/.021 TYP. (.280/.533) 8 5 1 4 .018 MIN (.475) (4 PLCS) .050 ± .008 (1.27 ± 0.20) .148/.159 (3.76/4.04) .007/.010 (.177/.254) .059/.070 (1.50/1.79) SEATING PLANE .014/.037 (.355/.940) .228/.246 (5.79/6.25) ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML4961CS 0°C to 70°C 8-Pin SOIC (S08) ML4961ES –20°C to 70°C 8-Pin SOIC (S08) ML4961IS –40°C to 85°C 8-Pin SOIC (S08) © Micro Linear 1996 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017, 5,559,470. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 8 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4961-01