Sanyo LA73026AV Double scart interface ic Datasheet

Ordering number : ENA0239
Monolithic Linear IC
LA73026AV
Double Scart Interface IC
Overview
This LA73026AV is a double scart (PAL/SECAM 21pin) interface IC.
Functions
• AV switches
• Changeable Gain AMP
• 6dB AMP + driver
• FSS output
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
VCCV max
24, 29 pin
VCCA max
14 pin
13.0
V
Ta ≤ 80°C∗
760
mW
Allowable power dissipation
Pd max
6.0
V
Operating temperature
Topr
-20 to +80
°C
Storage temperature
Tstg
-55 to +150
°C
∗ When mounted on a 114.3×76.1×1.6mm glass epoxy board.
3
Operating Conditions at Ta = 25°C
Parameter
Symbol
Recommending operation voltage
VCCV
24, 29 pin
VCCA
14 pin
Operating voltage range
Conditions
VCCV op
24, 29 pin
VCCA op
14 pin
Ratings
Unit
5.0
V
12.0
V
4.5 to 5.5
V
11.5 to 12.5
V
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
71906 MS OT B8-6889 No.A0239-1/13
LA73026AV
Electrical Characteristics at Ta = 25°C, VCC = ±5.0V, VCCA = 12.0V
Ratings
Parameter
Symbol
Conditions
min
typ
Unit
max
Current dissipation 1
ICCV1
Pin 24 Flow in current when non-signal
16.0
24.0
32.0
mA
Current dissipation 2
ICCV2
Pin 29 Flow in current when non-signal
12.0
18.0
24.0
mA
Current dissipation 3
ICCA
Pin 14 Flow in current when non-signal
13.0
21.0
29.0
mA
FSS output H voltage
VHFSS
Serial control select FSS OUT H VCCA<13.0V
VCCA-1.0
VCCA-0.5
VCCA
V
FSS output M voltage
VMFSS
Serial control select FSS OUT M VCCA<13.0V
5.0
6.0
7.0
V
FSS output L voltage
VLFSS
Serial control select FSS OUT L VCCA <13.0V
0
0.1
0.5
V
FSS output cut off current
ICUTOFF
External control terminal
Flow out current when Pin 20
M
2.0
3.61
10.0
mA
connecting to GND.
H
2.0
3.78
10.0
mA
VCCRL-0.2
VCCRL
VEXTH
RL = 1.8kΩ, VCCRL<13V
V
VEXTL
RL = 1.8kΩ, VCCRL = 5V
0
0.7
1.0
V
RL = 10kΩ, VCCRL = 5V
0
0.15
1.0
V
RL = 1.8kΩ, VCCRL = 5V
2.2
2.4
2.78
mA
485
H voltage
External control terminal
L voltage
External control terminal
IDR
drive current
RL = 10kΩ, VCCRL = 5V
400
500
µA
Power Save control H
VPSAVECTLH
Power Save H, control voltage of Pin 8.
3.0
VCCV
V
Power Save control L
VPSAVECTLL
Power Save L, control voltage of Pin 8.
0
1.0
V
External mute control H
VMUTECTLH
External mute H, control voltage of Pin 9.
3.0
VCCV
V
External mute control L
VMUTECTLL
External mute L, control voltage of Pin 9.
0
1.0
V
dB
Video switches part
Voltage gain V1
VG1V
25, 26pin output, 100% white
5.6
6.1
6.6
Voltage gain V2
VG2V
5 pin output G2 D6-L, 100% white
-0.4
0.1
0.6
dB
Voltage gain V3
VG3V
5 pin output G2 D6-H, 100% white
5.6
6.1
6.6
dB
dB
Frequency characteristics
VF
f = 100kHz/7MHz
-0.5
-0.0
0.5
DG differential gain
DG
VIN = 1Vp-p
-1.0
0.0
1.0
%
DP differential phase
DP
VIN = 1Vp-p
-1.5
0.0
1.5
deg
1.15
2.0
V
Output voltage
VOUT
Pin 25, 26 DC voltage when non-signal.
Audio switches part
Voltage gain 1A
VG1A
Serial control select 0dB.
-0.3
0.2
0.7
dB
Voltage gain 2A
VG2A
Serial control select 2dB.
1.7
2.2
2.7
dB
Voltage gain 3A
VG3A
Serial control select 4dB.
2.7
4.2
4.7
dB
Voltage gain 4A
VG4A
Serial control select 6dB.
5.7
6.2
6.7
dB
Voltage gain 5A
VG5A
Serial control select 12dB.
11.7
12.2
12.7
dB
Maximum output level
Total harmonic distortion
Output noise voltage
Cross talk between channel
VOMAX
THD
VONOISE
Output level at the time of f = 1kHz, THD = 2%
2
VOUT = 2Vrms, f = 1kHz, AMP 0dB
Rg = 1kΩ, JIS-A FILTER
3.0
Vrms
0.007
0.015
-100
-90
dBm
%
dB
VCTKA
VIN = 1Vrms, f = 1kHz
-90
-75
Mute attenuation
VMUTEA
VIN = 1Vrms, f = 1kHz
-90
-75
dB
Input impedance
ZIN
40
50
60
kΩ
-20
0
20
mV
Output off set voltage
VOFSET
Off set voltage at the time of changeover SW.
*VCCRL:see Test Circuit.
Design guarantee Items
Ratings
Parameter
Mute attenuation
Cross-talk between channel
Symbol
VMUTEV
VCTKV
Conditions
min
typ
Unit
max
VIN = 1Vp-p, f = 4.43MHz
-60
-50
dB
VIN = 1Vp-p, f = 4.43MHz
Driver output terminated with 75Ω.
-60
-50
dB
No.A0239-2/13
LA73026AV
Package Dimensions
unit : mm (typ)
3277
15.0
0.5
5.6
7.6
23
44
22
0.2
0.22
(1.5)
1.7max
(0.68)
0.65
0.1
1
SANYO : SSOP44(275mil)
No.A0239-3/13
LA73026AV
Block Diagram
0.01µF
75Ω
13
CLAMP
75Ω
VIN4
AIN2L
to DEC V_OUT
SW
3
6dB
AMP
75Ω
75Ω DR
VOUT75B
C
A SW2
L
B
C
D
36
11
BUF
10kΩ
PWRSAV(Power Save CTL)
100kΩ
to EXT_A_OUT_L
1µF
42
AOUT3L
0,2,4,6dB
select
BUF
10kΩ
10kΩ
39
AOUT1L
A SW3
L
B
C
AUMUTE (EXT MUTE CTL)
PWRMUTE1
1µF
10kΩ
MUTE
From Serial Control
Changeable
AMP
BUF
BUF
MUTE
3
VCC5B(Always VCC(5.0V))
8
41
MUTE
16
29
9
A SW1
L
B
33
75Ω
26
2.5kΩ
200Ω(IC<2.5mA)
EXTCTL1
VOUT
A
2
10kΩ
5
SW3B CTL
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
600Ω
600Ω
600Ω
600Ω
600Ω
AIN5L
1µF
BUF
2.5kΩ
FSS_Control(L,M,H)
FSSOUT
1µF
AIN3L
1µF
1µF
MUTE
20
AIN4L
1µF
0.6dB
AMP
CLAMP
1kΩ
AIN1L
1µF
to YC_OUT
SW
2
C
23
VOUT75A
MUTE
A
B
0.01µF
75Ω
25
1pF
B
C
D
10pF
75Ω
CLAMP
0.01µF
VIN2
75Ω DR
2.5kΩ
MUTE
A
18
75Ω
CLAMP
0.01µF
VIN3
6dB
AMP
C
VCC5A(CTL_VCC(5.0V))
to EXT V_OUT
SW
1
10pF
75Ω
VIN5
28
A
B
1pF
CLAMP
24
Serial_Control(IIL)
1pF
CLOCK 22
0.01µF
7
VIN1
DATA
CLOCK
10pF
75Ω
DATA 21
to HiFi_A_OUT_L
1µF
Changeable
AMP
10kΩ
30
AOUT2L
0,2,4,6,12dB
select
to DEC_A_OUT_L
To_Lch_Audio_Circuit_VCC
14 VCC12(12.0V)
200Ω(IC<2.5mA)
EXTCTL2
4
From Serial Control
10.5V
200Ω(IC<2.5mA)
EXTCTL3 19
BUF
1µF
From Serial Control
12
200Ω(IC<2.5mA)
REFFIL
BUF
EXTCTL4 35
From Serial Control
To_Rch_Audio_Circuit_VCC
AIN2R
10kΩ
A SW2
R
B
C
D
37
10
MUTE
6
A SW3
B R
C
27
MUTE
32
44
Changeable
AMP
100kΩ
PWRMUTE2
1µF
43
AOUT3R
0,2,4,6dB
select
1µF
BUF
BUF
10kΩ
BUF
10kΩ
AOUT1R
Changeable
AMP
0,2,4,6,12dB
select
to EXT_A_OUT_L
10kΩ
40
10pF
15
10pF
BUF
MUTE
17
GND
C
34
10pF
AIN5R
1µF
A
A SW1
B R
1
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
600Ω
AIN3R
1µF
600Ω
AIN4R
1µF
600Ω
AIN1R
1µF
600Ω
600Ω
1µF
1µF
to HiFi_A_OUT_L
10kΩ
31
AOUT2R
to DEC_A_OUT_R
38
No.A0239-4/13
LA73026AV
Pin Function
Pin No.
Pin name
1
AIN1R
AIN1L
16
AIN2R
AIN2L
AIN3R
AIN3L
36
AIN4L
AIN4R
AIN5L
37
AIN5R
33
34
REG10.5V
AIN
200Ω
2kΩ
15
5.58V
2kΩ
11
Equivalent circuit
PGND
3
EXTCTL1
General purpose output.
4
EXTCTL2
Open collector.
19
EXTCTL3
35
EXTCTL4
2.5mA, ON
VCC(5V)
→ 0.75V
OFF
ICmax=2.5mA
VCCmax=13V
200Ω
→ OPEN
EXTCTL
Design=2.5mA
10
Audio input terminal.
DC voltage
50kΩ
2
Function
SGND
5
VOUT
Video output terminal.
1.10V
VCC(5V)
200Ω
Push-pull output Low-impedance.
200Ω
VOUT
SGND
0V
6
GND
17
GND
27
GND
(EXT-75Ω Driver)
32
GND
(DEC-75Ω Driver)
38
GND
Continued on next page.
No.A0239-5/13
LA73026AV
Continued from preceding page.
Pin No.
Pin name
7
VIN1
VIN2
Video input terminal.
VIN3
VIN4
Hi-impedance.
23
28
VIN5
18
DC voltage
Equivalent circuit
1.8V
VCC(5V)
Sync-tip clamp input
2kΩ
13
Function
VIN
2kΩ
200Ω
SGND
Power save mode select pin.
0.2V
VCC(5V)
10kΩ
Floating
OPEN: L
60kΩ
PWRSAV
Parasitic Diode
8
40kΩ
100kΩ
40kΩ
Thyristor
PWRSAV
SGND
60kΩ
40kΩ
100kΩ
10kΩ
40kΩ
100kΩ
40kΩ
Thyristor
AMUTE
Floating
Floating
VCC(5V)
60kΩ
0.05V
OPEN: LOW
Parasitic Diode
Control terminal for audio mute.
40kΩ
AUMUTE
10kΩ
9
SGND
Terminal for Ref_DC ripple
removing.
4.94V
12.0V
VCC12
200kΩ
REFFIL
200kΩ
12
Buffer
1kΩ
to Audio Ref DC(5.0V)
REFFIL
100kΩ
110kΩ
to Audio VCC(10.5V)
PGND
14
VCC12
VCC for audio.
Continued on next page.
No.A0239-6/13
LA73026AV
Continued from preceding page.
Pin No.
Pin name
Function
20
FSSOUT
FSS control terminal.
DC voltage
Output H, M, L 3 values with
serial control.
Equivalent circuit
H: VCC-0.5V
VCC12
6V
M: 6V
FSSOUT
L: 0V
50kΩ
+
-
OFF→MID
ON→HIGH
PGND
21
DATA
Serial data input terminal.
Control VCC(5V)
12kΩ
30kΩ
2.5kΩ
15kΩ
Conformed to I2C BUS.
Floating
DATA
53kΩ
500Ω
SGND
22
CLOCK
Serial clock input terminal.
Control VCC(5V)
12kΩ
15kΩ
30kΩ
Conformed to I2C BUS.
Floating
CLOCK
53kΩ
500Ω
SGND
24
VCC5A
25
VOUT75A
VOUT75B
Control VCC for Video.
Power save → open
26
Video driver output terminal.
Push-pull output
1.10V
VCC(5V)
Low-impedance.
VOUT75
SGND
29
VCC5B
Always VCC for Video.
Continued on next page.
No.A0239-7/13
LA73026AV
Continued from preceding page.
Pin name
Function
30
AOUT2L
AOUT2R
Audio output terminal
AOUT3L
AOUT3R
Low-Impedance
42
43
Equivalent circuit
4.91V
Push-pull output
200Ω
31
DC voltage
VCC12V
200Ω
Pin No.
MUTE:
ON
AOUT
PGND
40
AOUT1L
AOUT1R
Audio output terminal
4.91V
VCC12V
200Ω
39
Push-pull output
Low-Impedance
200Ω
AOUT1
PGND
41
PWRMUTE1
44
PWRMUTE2
Output terminal of audio muting
0V
Always VCC(5V)
VCC12
REG10.5V
100kΩ
PWRMUTE
PGND
Power Save
LA73024AV has two supplies 5V for Video part and 12V for audio part and FSS output. LA73024AV separates
perfectly 5V system from 12V system, so it can be individually movement. For example when in the stand-by mode, if
you open 14 pins but 5V supplies 24 and 29 pins, Video part and serial control part work normally. In this case audio
part and FSS output don’t work normally. And when you pull up 8pin and open 24 pin , IC chooses automatically video
sw3-B.Consequently Ext input and Decoder output only move , you can save more power dissipation .
Audio Mute
LA73024AV builds in two mute transistors for reduce audio pop-noise when occur at power on and off. You can control
both on serial control and on external parallel control for audio mute.
No.A0239-8/13
LA73026AV
Serial Control Specification
Slave address
MSB
1
0
0
1
0
1
0
LSB
0
↑
Slave receiver
Data format
S
Slave address (8bit)
A
Sub address (8bit)
↑
↑
Start condition
Acknowledge
A
Data address (8bit)
A
P
↑
Stop condition
Sub address and data byte table
Data byte (Underline is initial setting.)
Sub address
MSB
LSB
Hexadecimal
D8
01
(0000 0001)
02
(0000 0010)
D7
D6
D5
D4
D3
D2
D1
SW1
SW2
SW3
FSSOUT
00: C
00: D
00: C
00: HIGH
01: B
01: C
01: B
01: HIGH
10: A
10: B
10: A
10: MID
11: A
11: A
11: *
11: LOW
EXT
EXT
AMP GAIN
AUDIO AMP GAIN1
AUDIO AMP GAIN2
CTL1
CTL2
VPS OUT
(DEC OUT)
(EXT OUT)
000: 0dB
00: 0dB
0: L
0: L
0: 0dB
001: 2dB
01: 2dB
1: H
1: H
1: 6dB
010: 4dB
10: 4dB
011: 6dB
11: 6dB
100:12dB
MUTE1
MUTE2
MUTE3
MUTE4
MUTE5
MUTE6
EXT
EXT
VSW1 OUT
VSW2 OUT
VSW3 OUT
ASW1 OUT
ASW2 OUT
ASW3 OUT
CTL3
CTL4
0: through
0: through
0: through
0: through
0: through
0: through
0: L
0: L
1: MUTE
1: MUTE
1: MUTE
1: MUTE
1: MUTE
1: MUTE
1: H
1: H
03
(0000 0011)
Data transfer
I2C-BUS control system is adopted in SW IC and SW IC is controlled by SCL (Serial Clock) and SDA (Serial Data) At
first, please set up the START condition*1 by these two terminals (SCL and SDA). And next, please input the 8bits data
which should be synchronized with SCL into SDA terminal. Still more, please give priority to high rank bit at data
transfer order (MSB → LSB). The 9th bit is called as ACK (Acknowledge), SW IC sends [0] to the SDA terminal
during SCL [1] period. So, please open the port of micro-processor during this period. LA73026AV adopt
auto-increment, so you input only first sub-address data (called as Group) and you can transfer data in order. As thus
the Data transfer Stop condition*2 is finished.
*1
SDA rise up during SCI is [1]
*2
SDA fall down during SCL is [1]
No.A0239-9/13
LA73026AV
Transfer data format
The transfer data is composed by START condition, Slave address data*3, and STOP condition.
After setting up the START condition, please transfer the Slave Address (regulated as “10010100” in SW IC). Group
and next control data (Please see “Data structure”)
Slave Address is composed by 7bits, and this bit 8th bit*4 should be set as [0].
But SW IC is not equipped with such a data out function, please keep this bit as [0].
The both of Group data and control data are composed by 8bits, and the one control action is defined with combination
of these two data. And if you want to control 2 or more groups at the same mode, you can realize it by sending some
control data together.
The data makes meaning with all bits, so you cannot stop the sending until all data transfer is over. But LA73026AV
adopt auto-increment, for example you can stop to transfer STOP condition after group 2 data . If you want to stop
transfer action, please transfer the STOP condition without fail.
*3
There are 3 control groups.
*4
This 8th bit called as R/W bit, and this bit shows the data transmission direction. [0] means send mode (accept mode
with SW IC) and [1] means accept mode (send mode with SW IC) fundamentally.
Data structure
START condition
Slave Address
R/W ACK Group ACK
Control data
ACK
…
STOP condition
Initialize
SW IC is initialized as the following mode for circuit protection. Please see “Sub address and data byte table” on page 9.
Characteristics of the SDA and SCL 1/0 stages for SW IC
Symbol
Min
Max
LOW level input voltage
Parameter
VIL
0
1.0
V
HIGH level input voltage
VIH
2.0
5.0
V
LOW level output current
IOL
3.0
mA
100
kHz
SCL clock frequency
fSCL
Unit
µs
Set-up time for a repeated START condition
tSU: STA
Hold time START condition. After this period, the first clock pulse is generated.
tHD: STA
4.0
µs
tLOW
4.7
µs
LOW period of the SCL clock
4.7
µs
tR
0
tHIGH
4.0
tF
0
tHD: DAT
0
Data set-up time
tSU: DAT
250
ns
Set-up time for STOP condition
tSU: STO
4.0
µs
tBUF
4.7
µs
Rise time of both SDA and SDL signals
HIGH period of the SCL clock
Fall time of both SDA and SDL signals
Data hold time
BUS free time between a STOP and START condition
1.0
µs
1.0
µs
µs
Definition of timing
No.A0239-10/13
LA73026AV
Test Circuit
VCCV(5V)
75Ω
0.01µF
T25A
T25
75Ω
75Ω
T23
75Ω
75Ω T26A
23
VIN4
24
VCC5A
25
330µF
ICCV1
0.1µF
AM
T23A
100µH
26
T26
VOUT75A
VOUT75B
CLOCK
DATA
FSSOUT
EXTCTL3
22
21
20
19
CLOCK
T22
DATA
T21
VM
VHFSS,VMFSS,VLFSS
Icutoff
AM
T20
1.8kΩ
AM
T19
75Ω
0.01µF
T28
AM
ICCV2
T30A
T31A
330µF
1µF
1µF
0.1µF
10kΩ
10kΩ
T30
T31
620Ω
0.1µF
T33A
T33
0.1µF
620Ω
T34A
T34
1.8kΩ
AM
620Ω
IDR
T35
0.1µF
T36A
T36
0.1µF
620Ω
T37A
T37
28
VIN5
29
VCC5B
30
AOUT2L
31
AOUT2R
[2.5V→N.C]
32
GND
33
AIN4L
34
AIN4R
[2.5V→N.C]
VIN3
18
GND
17
AIN3L
16
AIN3R
[2.5V→N.C]
15
VCC12
14
T18
T18A
620Ω
0.1µF
0.1µF
T28A
100µH
GND
47µF
0.01µF
27
LA73026AV
75Ω
T16
T16A
0.1µF
T15
REFFIL
AIN2L
AIN2R
[2.5V→N.C]
35
EXTCTL4
36
AIN5L
AUMUTE
37
AIN5R
[2.5V→N.C]
PWRSAV
38
GND
39
AOUT1L
40
AOUT1R
[2.5V→N.C]
41
PWRMUTE1
13
12
11
10
9
8
1µF
10kΩ
T39A
T39
1µF
10kΩ
T40A
T40
1µF
10kΩ
T42A
T43A
10kΩ
T42
T43
1µF
42
AOUT3L
7
GND
6
VOUT
5
EXTCTL2
4
EXTCTL1
3
ICCA
AM
T13
T13A
T12
620Ω
1µF
T11
T11A
620Ω
1µF
T10
T10A
2.2kΩ
open
2.2kΩ
open
T9
T8
T7
75Ω
T7A
1µF
T5
10kΩ
T5A
1.8kΩ
AM
T4
IDR
1.8kΩ
AM
T3
620Ω
0.1µF
43
AOUT3R
[2.5V→N.C]
AIN1L
2
44
AIN1R
PWRMUTE2
[2.5V→N.C] [2.5V→N.C]
1
VCCA(12V)
1µF
0.01µF
VIN1
T15A
620Ω
75Ω
0.01µF
VIN2
IDR
T2
T2A
0.1µF
T1
IDR
620Ω
T1A
VCCRL(5 to 13V)
No.A0239-11/13
17
0.01µF
MUTE
MUTE
MUTE
MUTE
MUTE
Video SW3
From Audio R Out(3pin) From Audio L Out(1pin)
6dB
AMP
6dB
AMP
75Ω
DR
75Ω
DR
18
19
20
24
21
CLAMP
25
Control VCC
(5V±0.5V)
LPF
LPF
0.1µF
0.01µF
100µH
75Ω
75Ω
VIDEO OUT
VIDEO IN
VIDEO IN
Modulator
VIDEO OUT
75Ω
TUNER VIDEO IN
TUNER AUDIO L IN
TUNER AUDIO R IN
From Y/C_IC(7pin)
21
From Audio R Out(3pin)
From Audio L Out(1pin)
Control VCC(5V)
21
From Y/C_IC(7pin)
SW1
B A
26
Data Clock
Interface
BLOCK
C
27
A
SW2
AUDIO L OUT
IF
47µF
D C B
Audio Out
FUNCTION SW
Multiplex
16
28
CLOCK
15
29
DATA
SW3
330µF
B A
AUDIO R IN
FSS Control
Terminal (L,M,H)
C
0.1µF
0.01µF
AUDIO L OUT
AUDIO R OUT
AUDIO L IN
Always VCC(5V)
20
CLAMP
100µH
18
External
Control_3
30
Always VCC
(5V±0.5V)
19
CLAMP
MUTE
Serial Control
10kΩ
10kΩ
17
FSS_OUT
14
20
EXTCTL3
1kΩ
13
19
0.01µF
12
1µF
1µF
16
100kΩ
Gain CTL
(0,2,4,6,12dB)
31
AMP
32
AMP
600Ω
VCC_max≤13.0V
IC_max≤2.5mA
600Ω
14
18
75Ω
11
15
110kΩ
33
17
0.1µF
10
13
To REF DC
34
16
600Ω
9
12
15
0.1µF
BUF
11
CLAMP
BUF
1µF
1µF
EXTCTL4
10
14
VCC 12V
(12V±0.5V)
35
13
600Ω
8
100µH
Extenal
Control_4
8
12
VCC=12V
7
BUF
11
0.01µF
LPF
9
75Ω
MUTE
10
10.5V_REG
SW1L
AUDIO L IN
1µF
MUTE
9
V-IN
MUTE
To Audio VCC
LPF
36
B A
37
C
1µF
A
SW2L
6
1µF
6
7
D C B
4
8
600Ω
Gain CTL
(0.6dB)
5
A-L-IN
SW3L
38
600Ω
600Ω
3
7
B A
39
1µF
1µF
2
6
C
BUF
1µF
5
1µF
100kΩ
BUF
1µF
4
600Ω
5
3
Ext Mute Control
(Open,Low→Normal)
(H→Ext Mute)
LPF
LPF
AMP
1
Power Save
(High→SW3B)
(Open,Low→Normal)
B A
2
22kΩ
4
CLAMP
C
L.P.F
1
22kΩ
A
AMP
40
0.01µF
AMP
D C B
SW1R
1µF
HiFi_IC
AUDIO R IN
75Ω
3
LPF
B A
BUF
BUF
C
BUF
41
1µF
2
42
EXTCTL2
1
External
Control_2
BUF
EXTCTL1
SW2R
Gain CTL
(0,2,4,6dB)
L
VCC_max≤13.0V
IC_max≤2.5mA
SW3R
100kΩ
43
External
Control_1
600Ω
LPF
1µF
1µF
600Ω
LPF
R
VCC_max≤13.0V
IC_max≤2.5mA
Y/C IC
44
FUNCTION SW
AUDIO R OUT
A-R-IN
SYSCON
DATA
CLOCK
DEC FUNCTION SW
LA73026AV
Sample Application Circuit
EURO SCART EXT
RF OUT
EURO SCART DEC
75Ω
330µF
23
22
VCC_max≤13.0V
IC_max≤2.5mA
Front AV IN
No.A0239-12/13
LA73026AV
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
products must not be exported without obtaining the export license from the authorities concerned in
accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or
otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and
reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
property rights or other rights of third parties.
This catalog provides information as of June, 2006. Specifications and information herein are subject
to change without notice.
PS No.A0239-13/13
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