CD4066BMS CMOS Quad Bilateral Switch December 1992 Features Description • For Transmission or Multiplexing of Analog or Digital Signals CD4066BMS is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin for pin compatible with CD4016B, but exhibits a much lower on state resistance. In addition, the on-state resistance is relatively constant over the full input signal range. • High Voltage Types (20V Rating) • 15V Digital or ±7.5V Peak-to-Peak Switching • 125Ω Typical On-State Resistance for 15V Operation • Switch On-State Resistance Matched to Within 5Ω Over 15V Signal Input Range • On-State Resistance Flat Over Full Peak-to-Peak Signal Range • High On/Off Output Voltage Ratio - 80dB Typ. at FIS = 10kHz, RL = 1kΩ • High Degree of Linearity: <0.5% Distortion Typ. at FIS = 1kHz, VIS = 5Vp-p, VDD - VSS ≥ 10V, RL = 10kΩ • Extremely Low Off-State Switch Leakage Resulting in Very Low Offset Current and High Effective Off-State Resistance: 10pA Typ. at VDD - VSS = 10V, TA = +25oC • Extremely High Control Input Impedance (Control Circuit Isolated from Signal Circuit): 1012Ω Typ. • Low Crosstalk Between Switches: -50dB Typ. at FIS = 8MHz, RL = 1kΩ • Matched Control Input to Signal Output Capacitance: Reduces Output Signal Transients • Frequency Response, Switch on = 40MHz (Typ.) The CD4066BMS consists of four independent bilateral switches. A single control signal is required per switch. Both the p and the n device in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the n channel device on each switch is either tied to the input when the switch is on or to VSS when the switch is off. This configuration eliminates the variation of the switch transistor threshold voltage with input signal, and thus keeps the on-state resistance low over the full operating signal range. The advantages over single channel switches include peak input signal voltage swings equal to the full supply voltage, and more constant on-state impedance over the input signal range. For sample and hold applications, however, the CD4016B is recommended. The CD4066BMS is supplied in these 14-lead outline packages: Braze Seal DIP H4Q Frit Seal DIP H1B Ceramic Flatpack H3W Pinout • 100% Tested for Quiescent Current at 20V CD4066BMS TOP VIEW • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of “B” Series CMOS Devices” Applications • Analog Signal Switching/Multiplexing - Signal Gating - Modulator - Squelch Control - Demodulator - Chopper - Commutating Switch IN/OUT A 1 14 VDD OUT/IN A 2 13 CONT A OUT/IN B 3 12 CONT D IN/OUT B 4 11 IN/OUT D CONT B 5 10 OUT/IN D CONT C 6 9 OUT/IN C VSS 7 8 IN/OUT C • Digital Signal Switching/Multiplexing • Transmission Gate Logic Implementation • Analog to Digital & Digital to Analog Conversion • Digital Control of Frequency, Impedance, Phase, and Analog Signal Gain CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-966 File Number 3319 Specifications CD4066BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current Input Leakage Current Input/Output Leakage Current (Switch OFF) IIL IIH IOZL VC = VDD or GND VC = VDD or GND VC = 0V, VIS = 18V, VOS = 0V, VIS = 0V, VOS = 18V VDD = 20 VDD = 18V IOZH VDD = 20 VDD = 18V On Resistance RON5 RON10 RON15 On Resistance On Resistance On Resistance Functional (Note 3) Switch Threshold RL = 100k to VDD N Threshold Voltage P Threshold Voltage RON5 RON10 RON15 VC = VDD, RL = 10kW VDD = 5V returned to VDD VDD = 10V VSS/2 VDD = 15V VIS = VSS to VDD VDD = 5V VDD = 10V GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25 - 0.5 µA 2 +125oC - 50 µA 3 -55oC - 0.5 µA 1 +25o C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1 +25oC 1050 - Ω 1 +25oC 400 - Ω 1 +25oC 240 - Ω 1, 2 +125oC - 1300 Ω -55oC - 800 Ω +125oC - 550 Ω -55oC - 310 Ω +125oC - 320 Ω -55oC - 220 Ω 1, 2 VDD = 15V LIMITS 1, 2 oC VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC SWTHRH5 VDD = 5V, VC = 1.5V, VIS = GND 1, 2, 3 +25oC, +125oC, -55oC 4.1 - V SWTHRH15 VDD = 15V, VC = 2V, VIS = GND 1, 2, 3 +25oC, +125oC, -55oC 14.1 - V 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V F VNTH VPTH VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA 7-967 VOH > VOL < VDD/2 VDD/2 V Specifications CD4066BMS TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Control Input Low Voltage (Note 2) |IIS| < 10µa, VIS = VSS, VOS = VDD and VIS = VDD, VOS = VSS VILC5 Control Input High Voltage (Note 2, Figure 2) VIS = VSS and VIS = VDD CONDITIONS (NOTE 1) TEMPERATURE MIN MAX UNITS 1, 2, 3 +25oC, +125oC, -55oC - 1 V 1, 2, 3 +25oC, - 2 V VDD = 5V VILC15 VDD = 15V VIHC VIHC LIMITS GROUP A SUBGROUPS +125oC, -55oC VDD = 5V, |IIS| = .51mA, 4.6V < VOS < 0.4V 1 +25oC 3.5 - V VDD = 5V, |IIS| = .36mA, 4.6V < VOS < 0.4V 2 +125oC 3.5 - V VDD = 5V, |IIS| = .64mA, 4.6V < VOS < 0.4V 3 -55oC 3.5 - V VDD = 15V, |IIS| = 3.4mA, 13.5V < VOS <1.5V 1 +25oC 11 - V VDD = 15V, |IIS| = 2.4mA, 13.5V < VOS < 1.5V 2 +125oC 11 - V VDD = 15V, |IIS| = 4.2mA, 13.5V < VOS <1.5V 3 -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. VDD = 2.8V/3.0V, RL = 100K to VDD VDD = 20V/18V, RL = 10K to VDD TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Signal Input to Signal Output Propagation Delay Turn-On, Turn-Off SYMBOL TPLH TPHL GROUP A SUBGROUPS TEMPERATURE CONDITIONS VC = VDD = 5V, VSS = GND (Notes 2, 3) TPHZ/ZH VIS = VDD = 5V (Notes 1, 2) TPLZ/ZL 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 40 ns - 54 ns 9 +25oC - 70 ns 10, 11 +125oC, -55oC - 95 ns MIN MAX UNITS - 0.25 µA NOTES: 1. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Control Input Low Voltage |IIS| < 10µa, VIS = VSS, VOS = VDD and VIS = VDD, VOS = VSS VILC10 VDD = 10V 1, 2 1, 2 1, 2 1, 2 7-968 TEMPERATURE -55oC, +25oC +125oC - 7.5 µA -55oC, +25oC - 0.5 µA +125oC - 15 µA - 0.5 µA +125oC - 30 µA +25oC, +125oC, -55oC - 2 V -55oC, +25oC Specifications CD4066BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Control Input High Voltage (See Figure 2) SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS VIHC10 VDD = 10V, VIS = VDD or GND 2 +25oC, +125oC, -55oC 7 - V VDD = 10V 1, 2, 3 +25oC - 20 ns VDD = 15V 1, 2, 3 +25oC - 15 ns TPHZ/ZH VDD = 10V TPLZ/ZL VDD = 15V 1, 2, 3 +25oC - 40 ns 1, 2, 3 +25oC - 30 ns 1, 2 +25oC - 7.5 pF Propagation Delay Signal Input to Signal Output Propagation Delay Turn-On, Turn-Off TPLH TPHL Input Capacitance CIN Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Supply Current IDD CONDITIONS VDD = 20V, VIN = VDD or GND NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC - 25 µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - SSI SYMBOL ±0.1µA IDD ON Resistance DELTA LIMIT RONDEL10 ± 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10 Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10 Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 7-969 READ AND RECORD IDD, IOL5, IOH5A, RONDEL10 Specifications CD4066BMS TABLE 6. APPLICABLE SUBGROUPS (Continued) MIL-STD-883 METHOD CONFORMANCE GROUP Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group B GROUP A SUBGROUPS Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR OPEN GROUND VDD Static Burn-In 1 (Note 1) FUNCTION 2, 3, 9, 10 1, 4-8, 11-13 14 Static Burn-In 2 (Note 1) 2, 3, 9, 10 7 1, 4-6, 8, 11-14 Dynamic Burn-In (Note 1) - 7 14 2, 3, 9, 10 7 1, 4-6, 8, 11-14 Irradiation (Note 2) 9V ± -0.5V 50kHz 25kHz 2, 3, 9, 10 5, 6, 12, 13 1, 4, 8, 11 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Functional Diagram TRUTH TABLE EACH SWITCH IN/OUT 1 SIG A OUT/IN OUT/IN 14 VDD 13 CONTROL A 2 3 SIG B IN/OUT 4 CONTROL B 5 CONTROL C 6 SW D SW B 12 CONTROL D 11 IN/OUT 9 7 OUTPUT VC VIS VOS 1 0 0 1 1 1 0 0 Open 0 1 Open Positive Logic: Switch ON VC = “1” Switch OFF VC = “0” SIG D 10 SW C VSS INPUT SW A OUT/IN OUT/IN SIG C 8 IN/OUT All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 970 CD4066BMS Schematic SWITCH CONTROL P N P N CONTROL VC NORMAL OPERATION CONTROL LINE BIASING: SWITCH ON, VC “I” = VDD SWITCH OFF, VC “O” = VSS IN VIS * OUT VOS VDD ALL CONTROL INPUTS ARE PROTECTED BY THE CMOS PROTECTION NETWORK N * VSS VSS NOTE: All “P” Substrates Connected to VDD SIGNAL LEVEL RANGE: VSS ≤ VIS ≤ VDD FIGURE 1. SCHEMATIC DIAGRAM OF 1 OF 4 IDENTICAL SWITCHES AND ITS ASSOCIATED CONTROL CIRCUITRY KEITHLY 160 DIGITAL MULTIMETER VDD IIS VIS TG “ON” 10kΩ CD4066BMS 1 OF 4 SWITCHES VOS 1kΩ RANGE Y X-Y PLOT TER VSS |VIS - VOS| RON = |IIS| HP MOSELEY 7030A X FIGURE 2. DETERMINATION OF RON AS A TEST CONDITION FOR CONTROL INPUT HIGH VOLTAGE (VIHC) SPECIFICATION FIGURE 3. CHANNEL ON-STATE RESISTANCE MEASUREMENT CIRCUIT CIOS VC = -5V VDD = +5V MEASURED ON BOONTON CAPACITANCE BRIDGE MODEL 75A (1MHz) TEST FIXTURE CAPACITANCE NULLED OUT CD4066BMS 1 OF 4 SWITCHES CIS VDD VC = VSS VIS = VDD CD4066BMS 1 OF 4 SWITCHES Ι COS VSS = -5V VSS FIGURE 4. CAPACITANCE TEST CIRCUIT VDD VC = VDD ViS VDD tr = tf = 20ns ALL UNUSED TERMINALS ARE CONNECTED TO VSS CD4066BMS 1 OF 4 SWITCHES FIGURE 5. OFF SWITCH INPUT OR OUTPUT LEAKAGE ALL UNUSED INPUTS ARE CONNECTED TO VSS +10V VC VOS 50 pF VDD tr = tf = 20ns VIS CD4066BMS 1 OF 4 SWITCHES ALL UNUSED TERMINALS ARE CONNECTED TO VSS VOS 200kΩ 1kΩ VSS FIGURE 6. PROPAGATION DELAY TIME SIGNAL INPUT (VIS) TO SIGNAL OUTPUT (VOS) VSS 10kΩ FIGURE 7. CROSSTALK CONTROL INPUT TO SIGNAL OUTPUT 7-971 CD4066BMS REP RATE VC tr = tf = 20ns 1 0 10% 20ns VOS 90% 20ns VDD VC = VDD VDD tr = tf = 20ns VDD CD4066BMS 1 OF 4 SWITCHES tr = tf = 20ns VIS = +10V VOS 50 pF 50 pF 1kΩ FIGURE 9. MAXIMUM ALLOWABLE CONTROL INPUT REPETITION RATE 10 2 3 7 9 PE J1 J2 J3 J4 J5 RESET 15 1 EXT RESET 13 CD4018B 1/ 4 1 4 CD4066B 5 9 12 J2 J3 J4 J5 4 7 1/ 5 3 13 6 12 9 8 5 6 2 1 CD4049B 9 4 3 CD4049B 7 Q1 Q2 5 2 1/ 3 CD4018B 2 3 2 PE J1 1 1 3 14 15 Q1 Q2 5 2 12 CLOCK 14 1kΩ VSS FIGURE 8. PROPAGATION DELAY TPLH, TPHL CONTROL SIGNAL OUTPUT. DELAY IS MEASURED AT VOS LEVEL OF +10% FROM GROUND (TURN ON) OR ON-STATE OUTPUT LEVEL (TURN OFF). CLOCK VOS = 1/2VOS AT 1kHz CD4066BMS 1 OF 4 SWITCHES VSS 10 ALL UNUSED INPUTS ARE CONNECTED TO VSS VDD = +10V VC +10V ALL UNUSED TERMINALS ARE CONNECTED TO VSS CD4001B 10 6 CD4001B 4 11 8 10 4 3 10 9 6 12 5 13 12 6 5 SIGNALS OUTPUTS 11 11 13 SIGNALS INPUTS CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 PACKAGE COUNT 2 - CD4001B 1 - CD4049B 3 - CD4066BMS 2 - CD4018B CD4066B 2 4 8 9 11 10 4 1/ CD4066B 4 3 8 3 CD4066B LPF 9 VDD CLOCK 30% (VDD - VSS) MAX. ALLOWABLE SIGNAL LEVEL VSS CHAN. 1 CHAN. 2 CHAN. 3 CHAN. 4 FIGURE 10. 4 CHANNEL PAM MULTIPLEX SYSTEM DIAGRAM 7-972 CHANNEL 2 10K 11 10K CHANNEL 1 1 5 3 LPF 10K 1/ CD4049B 6 2 1 4 12 11 12 LPF CHANNEL 3 10K 10 10K LPF CHANNEL 4 CD4066BMS +5 ANALOG INPUTS (±5V) -5 VDD = +5V VDD = 5V CD4066BMS 5V SWA 0 SWB IN CD4054B SWC SWD DIGITAL CONTROL INPUTS VSS = 0V VEE = -5V ANALOG OUTPUTS (±5V) VSS = -5V FIGURE 11. BIDIRECTIONAL SIGNAL TRANSMISSION VIA DIGITAL CONTROL LOGIC CHANNEL ON-STATE RESISTANCE (RON) (Ω) CHANNEL ON-STATE RESISTANCE (RON) (Ω) Typical Performance Characteristics SUPPLY VOLTAGE (VDD - VEE) = 5V 600 AMBIENT TEMPERATURE (TA) = +125oC 500 400 300 +25oC 200 -55oC 100 0 -4 -3 -2 -1 0 1 2 3 4 SUPPLY VOLTAGE (VDD - VEE) = 10V 300 AMBIENT TEMPERATURE (TA) = +125oC 250 200 +25oC 150 -55oC 100 50 0 -10.0 -7.5 SUPPLY VOLTAGE (VDD - VSS) = 15V 300 250 AMBIENT TEMPERATURE (TA) = +125oC 100 +25oC 50 -55oC 0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 0 2.5 5.0 7.5 10.0 FIGURE 13. TYPICAL ON-STATE vs INPUT SIGNAL VOLTAGE (ALL TYPES). CHANNEL ON-STATE RESISTANCE (RON) (Ω) CHANNEL ON-STATE RESISTANCE (RON) (Ω) FIGURE 12. TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 150 -2.5 INPUT SIGNAL VOLTAGE (VIS) (V) INPUT SIGNAL VOLTAGE (VIS) (V) 200 -5.0 7.5 10.0 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD - VSS) = 5V 500 400 300 200 10V 100 15V 0 -10.0 -7.5 INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE 14. TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 600 -5.0 -2.5 0 2.5 5.0 7.5 10.0 INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE 15. ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 7-973 CD4066BMS Typical Performance Characteristics RL = 100K 2 1 POWER DISSIPATION PER PACKAGE (PD) (µW) OUTPUT VOLTAGE (VO) (V) 3 AMBIENT TEMPERATURE (TA) = +25oC VDD = 2.5V, VSS = -2.5V INPUT = TERM 1, OUTPUT = TERM 2 (Continued) 10K 1K 500Ω 100Ω 0 VC = VDD 100Ω -1 VIS CD4066BMS VOS 1 OF 4 SWITCHES 500Ω -2 1K 10K RL 100K -3 -3 VDD -2 ALL UNUSED TERMINALS VSS ARE CONNECTED TO VSS -1 0 1 2 3 4 104 8 6 AMBIENT TEMPERATURE (TA) = +25oC 4 SUPPLY VOLTAGE (VDD) = 15V 2 103 8 10V 6 4 VDD 14 5V 2 102 6 8 6 12 4 13 7 VSS 10 4 10 FIGURE 16. TYPICAL ON CHARACTERISTICS FOR 1 OF 4 CHANNELS CD4066/ BMS 2 2 INPUT VOLTAGE (VI) (V) 5 f 6 8 2 4 6 102 SWITCHING FREQUENCY (f) (kHz) 8 103 FIGURE 17. POWER DISSIPATION PER PACKAGE vs SWITCHING FREQUENCY Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). Special Considerations In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load of the four CD4066B bilateral switches). This provision avoids any permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4066B. No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10. In certain applications, the external load-resistor current may include both VDD and signal line components. To avoid drawing VDD current when switch current flows into terminals 1, 4, 8 or 11 the voltage drop across the bidirectional switch must not exceed 0.8 volts (calculated from RON values shown). DIE THICKNESS: 0.0198 inches - 0.0218 inches METALLIZATION: PASSIVATION: BOND PADS: 7-974 Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN