IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI 9 Amp Low-Side Ultrafast MOSFET Driver Features General Description • Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes. • Latch Up Protected • High Peak Output Current: 9A Peak • Operates from 4.5V to 25V • Ability to Disable Output under Faults • High Capacitive Load Drive Capability: 2500pF in <15ns • Matched Rise And Fall Times • Low Propagation Delay Time • Low Output Impedance • Low Supply Current The IXDD409/IXDI409/IXDN409 are high speed high current gate drivers specifically designed to drive the largest MOSFETs and IGBTs to their minimum switching time and maximum practical frequency limits. The IXDD409/IXDI409/ IXDN409 can source and sink 9A of peak current while producing voltage rise and fall times of less than 30ns. The input of the drivers are compatible with TTL or CMOS and are fully immune to latch up over the entire operating range. Designed with small internal delays, cross conduction/ current shoot-through is virtually eliminated in the IXDD409/ IXDI409/IXDN409. Their features and wide safety margin in operating voltage and power make the drivers unmatched in performance and value. Applications • • • • • • • • • • Driving MOSFETs and IGBTs Motor Controls Line Drivers Pulse Generators Local Power ON/OFF Switch Switch Mode Power Supplies (SMPS) DC to DC Converters Pulse Transformer Driver Limiting di/dt under Short Circuit Class D Switching Amplifiers The IXDD409 incorporates a unique ability to disable the output under fault conditions. When a logical low is forced into the Enable input, both final output stage MOSFETs (NMOS and PMOS) are turned off. As a result, the output of the IXDD409 enters a tristate mode and achieves a Soft TurnOff of the MOSFET/IGBT when a short circuit is detected. This helps prevent damage that could occur to the MOSFET/ IGBT if it were to be switched off abruptly due to a dv/dt overvoltage transient. The IXDN409 is configured as a non-inverting gate driver, and the IXDI409 is an inverting gate driver. The IXDD409/IXDI409/IXDN409 are available in the standard 8pin P-DIP (PI), SOP-8 (SI), 5-pin TO-220 (CI) and in the TO-263 (YI) surface-mount packages. Figure 1A - IXDD409 Functional Diagram Figure 1B - IXDN409 Functional Diagram Ordering Information Part Number IXDD409PI IXDD409SI IXDD409YI IXDD409CI IXDI409PI IXDI409SI IXDI409YI IXDI409CI IXDN409PI IXDN409SI IXDN409YI IXDN409CI Package Type 8-Pin PDIP 8-Pin SOIC 5-Pin TO-263 5-Pin TO-220 8-Pin PDIP 8-Pin SOIC 5-Pin TO-263 5-Pin TO-220 8-Pin PDIP 8-Pin SOIC 5-Pin TO-263 5-Pin TO-220 Figure 1C - IXDI409 Functional Diagram Copyright © IXYS CORPORATION 2002 Patent Pending First Release Temp. Range Configuration -40°C to +85°C Non Inverting With Enable Line -40°C to +85°C Inverting -40°C to +85°C Non Inverting IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Absolute Maximum Ratings (Note 1) Operating Ratings Parameter Value Parameter Value Supply Voltage All Other Pins 25 V -0.3 V to VCC + 0.3 V Maximum Junction Temperature Operating Temperature Range Power Dissipation, TAMBIENT ≤25 oC 8 Pin PDIP (PI) 8 Pin SOIC (SI) TO220 (CI), TO263 (YI) Derating Factors (to Ambient) 8 Pin PDIP (PI) 150 oC -40 oC to 85 oC 975mW 1055mW 17W Thermal Impedance (Junction To Case) TO220 (CI), TO263 (YI) (θJC) 0.95 oC/W 8 Pin SOIC (SI) TO220 (CI), TO263 (YI) Storage Temperature Lead Temperature (10 sec) 7.6mW/oC 8.2mW/oC 0.14W/oC -65 oC to 150 oC 300 oC Electrical Characteristics Unless otherwise noted, TA = 25 oC, 4.5V ≤ VCC ≤ 25V . All voltage measurements with respect to GND. IXDD409 configured as described in Test Conditions. Symbol Parameter VIH High input voltage VIL Low input voltage VIN Input voltage range IIN Input current VOH High output voltage VOL Low output voltage ROH Output resistance @ Output high Output resistance @ Output Low Peak output current VCC is 18V VEN Continuous output current Enable voltage range Limited by package power dissipation IXDD409 Only VENH High En Input Voltage IXDD409 Only VENL Low En Input Voltage IXDD409 Only tR Rise time CL=2500pF Vcc=18V 8 tF Fall time CL=2500pF Vcc=18V tONDLY VCC On-time propagation delay Off-time propagation delay Enable to output high delay time Disable to output low Disable delay time Power supply voltage ICC Power supply current VIN = 3.5V VIN = 0V VIN = + VCC ROL IPEAK IDC tOFFDLY tENOH tDOLD Test Conditions Min Typ Max 3.5 0V ≤ VIN ≤ VCC Units V 0.8 V -5 VCC + 0.3 V -10 10 µA VCC - 0.025 V 0.025 V IOUT = 10mA, VCC = 18V 0.8 1.5 Ω IOUT = 10mA, VCC = 18V 0.8 1.5 Ω 9 - .3 A 2 A Vcc + 0.3 V 2/3 Vcc V 1/3 Vcc V 10 15 ns 8 10 15 ns CL=2500pF Vcc=18V 33 36 40 ns CL=2500pF Vcc=18V 31 33 36 ns IXDD409 Only, Vcc=18V 52 ns IXDD409 Only, Vcc=18V 30 ns 18 25 V 1 0 3 10 10 mA µA µA 4.5 Specifications Subject To Change Without Notice 2 IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Pin Configurations 1 2 1 VCC VCC 8 2 IN OUT 7 3 EN * OUT 6 3 4 4 GND GND 5 5 Vcc OUT GND IN EN * TO220 (CI) TO263 (YI) 8 PIN DIP (PI) SO8 (SI) Pin Description SYMBOL FUNCTION VCC Supply Voltage IN Input EN * Enable OUT Output GND Ground DESCRIPTION Positive power-supply voltage input. This pin provides power to the entire chip. The range for this voltage is from 4.5V to 25V. Input signal-TTL or CMOS compatible. The system enable pin. This pin, when driven low, disables the chip, forcing high impedance state to the output (IXDD409 Only). Driver Output. For application purposes, this pin is connected, through a resistor, to Gate of a MOSFET/IGBT. The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be connected to a low noise analog ground plane for optimum performance. * This pin is used only on the IXDD409, and is N/C on the IXDI409 and IXDN409. Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when handling and assembling this component. Figure 2 - Characteristics Test Diagram VIN 3 IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Typical Performance Characteristics Fig. 3 Fig. 4 Rise Times vs. Supply Voltage 40 Fall Times vs. Supply Voltage 30 35 25 25 11900 pF 20 8900 pF 15 5860 pF 10 2950 pF Fall Times (ns) Rise Time (ns) 30 20 11900 pF 8900 pF 15 5860 pF 10 1500 pF 2950 pF 1500 pF 5 5 0 0 8 9 10 11 12 13 14 15 16 17 18 8 9 10 11 Supply Voltage (V) Fig. 5 12 13 14 15 16 17 18 Supply Voltage (V) Rise And Fall Times vs. Temperature CL=2500pF, Vcc=18V Rise Time vs. Load Capacitance Fig. 6 12 35 8V 10 30 10V 25 12V 14V 16V 18V Rise time Rise time (ns) 8 Falltime 6 4 15 2 10 0 -40 20 -20 0 25 40 60 5 1.35 85 2.7 5.4 8.1 10.8 Tem perature Load Capacitance Fall Time vs. Load Capacitance Fig. 7 Fig. 8 25 Max / Min Input vs. Temperature 3.5 8V 23 10V 21 2.5 Max / Min Input (V) 19 Fall Time (ns) 3 Maximum Input High 12V 14V 16V 18V 17 15 13 2 1.5 Minimum Input Low 1 11 9 0.5 7 5 1.35 2.7 5.4 8.1 0 -40 10.8 -20 0 25 Temperature Load Capacitance (nF) 4 40 60 85 IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Fig. 9 Fig. 10 Supply Current vs. Load Capacitance Vcc = 18V S upply C urrent vs. F requency V cc = 18V 1000 1000 10800 pF 8100 pF 5400 pF 2700 pF 100 1350 pF 2MHz 1MHz Supply Current (mA) Supply Current (mA) 100 500kHz 10 100kHz 50kHz 1 10 1 10kHz 0.1 1000 0.1 10000 1 10 Fig. 11 100 1000 Frequenc y (kHz) Load Capacitance (pF) SupplyCurrent vs. Load Capacitance Vcc =12V Supply Current vs. Frequency Vcc = 12V Fig. 12 1000 1000 10800 pF 8100 pF 5400 pF 2700 pF 1350 pF 100 2MHz Supply Current (mA) Supply Current (mA) 100 1MHz 500kHz 10 100kHz 10 1 50kHz 1 0.1 10kHz 0.01 0.1 1000 1 10000 10 Load Capacitance (pF) Fig. 13 10000 1000 10800 pF 8100 pF 5400 pF 100 Supply Current (mA) 100 Supply Current (mA) 1000 Supply Current vs. Frequency Vcc = 8V Fig. 14 SupplyCurrent vs. Load Capacitance Vcc = 8V 1000 2MHz 1MHz 10 100 Frequency (kHz) 500kHz 100kHz 1 2700 pF 1350 pF 10 1 50kHz 0.1 10kHz 0.1 1000 0.01 10000 1 Load Capacitance (pF) 10 100 Frequency (kHz) 5 1000 10000 IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Propagation Delayvs. Supply Voltage 50 50 48 48 46 46 44 42 40 38 Tondly (DD409, DN409) Toffdly (DI409) 36 Propagation Delayvs. Input Voltage Fig. 16 Propagation Delay (ns) Propagation Delay (ns) Fig. 15 34 44 Tondly (DD409, DN409) Toffdly (DI409) 42 40 38 Toffdly (DD409, DN409) Tondly (DI409) 36 34 Toffdly(DD409, DN409) Tondly (DI409) 32 32 30 30 8 9 10 11 12 13 14 15 16 17 18 3 4 5 6 Supply Voltage (V) Propagation Delay Times vs. Junction Temperature Fig. 17 7 8 9 10 11 12 Input Voltage (V) Quiescent Supply Current vs. Junction Temperature Vcc=18v Vin=5v@1kHz Fig. 18 45 0.6 40 0.5 Quiescent Supply Current (mA) Tondly (DD409, DN409) Toffdly (DI409) 35 Time (ns) 30 25 Toffdly (DD409, DN409) Tondly (DI409) 20 15 10 0.4 0.3 0.2 0.1 5 0 -40 -20 0 25 40 60 0 -40 85 -20 0 Temperature (C) Fig. 19 Fig. 20 Vcc vs. P Channel Peak Output Current CL = 10 nF 0 40 60 85 Vcc vs. NChannel Peak Output Current CL=10 nF 20 18 -2 N Channel Peak Output Current (A) P Channel Peak Output Current (A) 25 Temperature (C) -4 -6 -8 -10 -12 16 14 12 10 8 6 4 2 -14 0 5 7.5 10 12.5 15 17.5 20 22.5 25 5 Vcc (V) 7.5 10 12.5 15 Vcc (V) 6 17.5 20 22.5 25 IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI 15 9.8 14.5 9.6 14 N Channel Output Current (A) P Channel Output Current (A) 10 9.4 9.2 9 8.8 8.6 13.5 13 12.5 12 11.5 8.4 11 8.2 10.5 8 -60 -40 -20 0 20 40 60 NChannel Peak Ouput Current vs. Temperature Vcc =18VCL =10nF Fig. 22 PChannel Output Current vs. Temperature Vcc =18VCL=10 nF Fig. 21 80 10 -60 100 -40 -20 0 Fig. 23 High State Output Resistance vs. Supply Voltage Fig. 24 1.6 40 60 80 100 Low State Output Resistance vs. Supply Voltage 1.2 1.4 Low State Output Resistance (Ohms) High State Output Resistance (Ohms) 20 Temperature (C) Temperature (C) 1.2 1 0.8 0.6 0.4 0.2 0 1 0.8 0.6 0.4 0.2 0 5 7.5 10 12.5 15 17.5 20 22.5 25 5 Supply Voltage (V) 7.5 10 12.5 15 17.5 Supply Voltage (V) Figure 25 - Typical Application Short Circuit di/dt Limit 7 20 22.5 25 IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI APPLICATIONS INFORMATION Short Circuit di/dt Limit ground. (Those glitches might cause false triggering of the comparator). A short circuit in a high-power MOSFET module such as the VM0580-02F, (580A, 200V), as shown in Figure 25, can cause the current through the module to flow in excess of 1500A for 10µs or more prior to self-destruction due to thermal runaway. For this reason, some protection circuitry is needed to turn off the MOSFET module. However, if the module is switched off too fast, there is a danger of voltage transients occuring on the drain due to Ldi/dt, (where L represents total inductance in series with drain). If these voltage transients exceed the MOSFET's voltage rating, this can cause an avalanche breakdown. The comparator's output should be connected to a SRFF(Set Reset Flip Flop). The flip-flop controls both the Enable signal, and the low power MOSFET gate. Please note that CMOS 4000series devices operate with a VCC range from 3 to 15 VDC, (with 18 VDC being the maximum allowable limit). A low power MOSFET, such as the 2N7000, in series with a resistor, will enable the VMO580-02F gate voltage to drop gradually. The resistor should be chosen so that the RC time constant will be 100us, where "C" is the Miller capacitance of the VMO580-02F. The IXDD409 has the unique capability to softly switch off the high-power MOSFET module, significantly reducing these Ldi/dt transients. For resuming normal operation, a Reset signal is needed at the SRFF's input to enable the IXDD409 again. This Reset can be generated by connecting a One Shot circuit between the IXDD409 Input signal and the SRFF restart input. The One Shot will create a pulse on the rise of the IXDD409 input, and this pulse will reset the SRFF outputs to normal operation. Thus, the IXDD409 helps to prevent device destruction from both dangers; over-current, and avalanche breakdown due to di/dt induced over-voltage transients. The IXDD409 is designed to not only provide ±9A under normal conditions, but also to allow it's output to go into a high impedance state. This permits the IXDD409 output to control a separate weak pull-down circuit during detected overcurrent shutdown conditions to limit and separately control dVGS/dt gate turnoff. This circuit is shown in Figure 26. When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected between the MOSFET Source and ground, increases. This triggers the comparator at a preset level. The SRFF drives a low input into the Enable pin disabling the IXDD409 output. The SRFF also turns on the low power MOSFET, (2N7000). Referring to Figure 26, the protection circuitry should include a comparator, whose positive input is connected to the source of the VM0580-02. A low pass filter should be added to the input of the comparator to eliminate any glitches in voltage caused by the inductance of the wire connecting the source resistor to In this way, the high-power MOSFET module is softly turned off by the IXDD409, preventing its destruction. Figure 26 - Application Test Diagram + Ld 10uH VCC VCCA Rg OUT IN EN VCC + - VIN High_Power VMO580-02F 1ohm Rsh 1600ohm GND SUB Rs Low_Power 2N7002/PLP Ls R+ 10kohm 20nH One ShotCircuit Rcomp 5kohm NAND CD4011A NOT1 CD4049A NOT2 CD4049A Ccomp 1pF Ros 0 Comp LM339 + V+ V- C+ 100pF + R 1Mohm REF Cos 1pF Q NOT3 CD4049A NOR1 CD4001A EN NOR2 CD4001A SR Flip-Flop 8 VB Rd 0.1ohm IXDD409 + - - S - IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Supply Bypassing and Grounding Practices, Output Lead inductance TTL to High Voltage CMOS Level Translation (IXDD409 Only) When designing a circuit to drive a high speed MOSFET utilizing the IXDD409/IXDI409/IXDN409, it is very important to keep certain design criteria in mind, in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance. The enable (EN) input to the IXDD409 is a high voltage CMOS logic level input where the EN input threshold is ½ VCC, and may not be compatible with 5V CMOS or TTL input levels. The IXDD409 EN input was intentionally designed for enhanced noise immunity with the high voltage CMOS logic levels. In a typical gate driver application, VCC =15V and the EN input threshold at 7.5V, a 5V CMOS logical high input applied to this typical IXDD409 application’s EN input will be misinterpreted as a logical low, and may cause undesirable or unexpected results. The note below is for optional adaptation of TTL or 5V CMOS levels. Say, for example, we are using the IXDD409 to charge a 5000pF capacitive load from 0 to 25 volts in 25ns… Using the formula: I= ∆V C / ∆t, where ∆V=25V C=5000pF & ∆t=25ns we can determine that to charge 5000pF to 25 volts in 25ns will take a constant current of 5A. (In reality, the charging current won’t be constant, and will peak somewhere around 8A). SUPPLY BYPASSING In order for our design to turn the load on properly, the IXDD409 must be able to draw this 5A of current from the power supply in the 25ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is a magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected, low inductance, low resistance, high-pulse currentservice capacitors). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IXDD409 to an absolute minimum. GROUNDING In order for the design to turn the load off properly, the IXDD409 must be able to drain this 5A of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path #1 is between the IXDD409 and it’s load. Path #2 is between the IXDD409 and it’s power supply. Path #3 is between the IXDD409 and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, (for instance), the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IXDD409. The circuit in Figure 27 alleviates this potential logic level misinterpretation by translating a TTL or 5V CMOS logic input to high voltage CMOS logic levels needed by the IXDD409 EN input. From the figure, VCC is the gate driver power supply, typically set between 8V to 20V, and VDD is the logic power supply, typically between 3.3V to 5.5V. Resistors R1 and R2 form a voltage divider network so that the Q1 base is positioned at the midpoint of the expected TTL logic transition levels. A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to the Q1 emitter will drive it on. This causes the level translator output, the Q1 collector output to settle to VCESATQ1 + VTTLLOW=<~2V, which is sufficiently low to be correctly interpreted as a high voltage CMOS logic low (<1/3VCC=5V for VCC =15V given in the IXDD409 data sheet.) A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high, V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in Figure 27 will cause Q1 to be biased off. This results in Q1 collector being pulled up by R3 to VCC=15V, and provides a high voltage CMOS logic high output. The high voltage CMOS logical EN output applied to the IXDD409 EN input will enable it, allowing the gate driver to fully function as an 8 Amp output driver. The total component cost of the circuit in Figure 27 is less than $0.10 if purchased in quantities >1K pieces. It is recommended that the physical placement of the level translator circuit be placed close to the source of the TTL or CMOS logic circuits to maximize noise rejection. Figure 27 - TTL to High Voltage CMOS Level Translator CC (From Gate Driver Power Supply) OUTPUT LEAD INDUCTANCE Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and it’s load as short and wide as possible. If the driver must be placed farther than 2” from the load, then the output leads should be treated as transmission lines. In this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connect directly to the ground terminal of the load. VDD (From Logic Power Supply) 10K 3.3K 9 R1 Q1 2N3904 3.3K or TTL Input) R3 R2 High Voltage CMOS EN Output (To IXDD409 EN Input) IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Package Information NOTE: Mounting or solder tabs on all packages are connected to ground IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 www.ixys.com e-mail: [email protected] IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: [email protected] 10 Directed Energy, Inc. An IXYS Company 2401 Research Blvd. Ste. 108 Ft. Collins, CO 80526 Tel: 970-493-1901; Fax: 970-493-1903 www.directedenergy.com e-mail: [email protected] Doc #9200-0252 R1