LTC2302/LTC2306
Low Noise, 500ksps,
1-/2-Channel, 12-Bit ADCs
FEATURES
DESCRIPTION
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The LTC®2302/LTC2306 are low noise, 500ksps, 1-/2-channel, 12-bit ADCs with an SPI/MICROWIRE compatible
serial interface. These ADCs include a fully differential
sample-and-hold circuit to reduce common mode noise.
The internal conversion clock allows the external serial
output data clock (SCK) to operate at any frequency up
to 40MHz.
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12-Bit Resolution
500ksps Sampling Rate
Low Noise: SINAD = 72.8dB
Guaranteed No Missing Codes
Single 5V Supply
Auto-Shutdown Scales Supply Current with Sample
Rate
Low Power: 14mW at 500ksps
70μW at 1ksps
35μW Sleep Mode
1-Channel (LTC2302) and 2-Channel (LTC2306)
Versions
Unipolar or Bipolar Input Ranges (Software
Selectable)
Internal Conversion Clock
SPI/MICROWIRE™ Compatible Serial Interface
Separate Output Supply OVDD (2.7V to 5.25V)
Software Compatible with the LTC2308
10-Pin (3mm × 3mm) DFN Package
The LTC2302/LTC2306 operate from a single 5V supply
and draw just 2.8mA at a sample rate of 500ksps. The
auto-shutdown feature reduces the supply current to 14μA
at a sample rate of 1ksps.
The LTC2302/LTC2306 are packaged in a tiny 10-pin 3mm
× 3mm DFN. The low power consumption and small size
make the LTC2302/LTC2306 ideal for battery-operated
and portable applications, while the 4-wire SPI compatible serial interface makes these ADCs a good match for
isolated or remote data acquisition systems.
TYPE
Int Reference
Ext Reference
APPLICATIONS
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High Speed Data Acquisition
Industrial Process Control
Motor Control
Accelerometer Measurements
Battery-Operated Instruments
Isolated and/or Remote Data Acquisition
1
NUMBER OF INPUT CHANNELS
2
8
LTC2308
LTC2302
LTC2306
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
8192 Point FFT, fIN = 1kHz (LTC2306)
5V
2.7V TO 5.25V
0.1μF
0.1μF
OVDD
VDD
LTC2302
LTC2306
SDI
ANALOG INPUTS
CH0 (IN+)
0V TO 4.096V UNIPOLAR
CH1 (IN–)
±2.048V BIPOLAR
ANALOG
INPUT
MUX
+
–
12-BIT
500ksps
ADC
SERIAL
PORT
SDO
SCK
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTER
CONVST
PIN NAMES IN PARENTHESIS
REFER TO LTC2302
GND
VREF
0.1μF
10μF
23026 TA01
MAGNITUDE (dB)
10μF
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
fSMPL = 500kHz
SINAD = 72.8dB
THD = –88.7dB
0
50
100
150
FREQUENCY (kHz)
200
250
23026 TA01b
23026f
1
LTC2302/LTC2306
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VDD, OVDD)......................... –0.3V to 6V
Analog Input Voltage (Note 3)
CH0(IN+)-CH1(IN–),
REF ..............................(GND – 0.3V) to (VDD + 0.3V)
Digital Input Voltage
(Note 3).............................(GND – 0.3V) to (VDD + 0.3V)
Digital Output Voltage ... (GND – 0.3V) to (OVDD + 0.3V)
Power Dissipation ...............................................500mW
Operating Temperature Range
LTC2302C/LTC2306C ............................... 0°C to 70°C
LTC2302I/LTC2306I.............................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
LTC2302
TOP VIEW
LTC2306
TOP VIEW
10 OVDD
SDO 1
10 OVDD
SDO 1
9 SCK
CONVST 2
8 SDI
VDD 3
IN+ 4
7 GND
CH0 4
7 GND
IN– 5
6 VREF
CH1 5
6 VREF
CONVST 2
VDD 3
11
9 SCK
11
8 SDI
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2302CDD#PBF
LTC2302CDD#TRPBF
LDGV
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC2302IDD#PBF
LTC2302IDD#TRPBF
LDGV
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC2306CDD#PBF
LTC2306CDD#TRPBF
LDGW
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC2306IDD#PBF
LTC2306IDD#TRPBF
LDGW
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
23026f
2
LTC2302/LTC2306
CONVERTER AND MULTIPLEXER CHARACTERISTICS
The l denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4, 5)
PARAMETER
CONDITIONS
MIN
l
Resolution (No Missing Codes)
Integral Linearity Error
(Note 6)
±0.3
LSB
±0.25
±1
LSB
l
±1
±6
LSB
(Note 7)
l
0.002
±1
LSB/°C
±6
0.002
Unipolar Zero Error Match (LTC2306)
(Note 8)
l
(Note 8)
l
Bipolar Full-Scale Error Drift
Unipolar Full-Scale Error
±1
l
Unipolar Zero Error Drift
Bipolar Full-Scale Error
UNITS
Bits
l
Bipolar Zero Error Drift
Unipolar Zero Error
MAX
(Note 7)
Differential Linearity Error
Bipolar Zero Error
TYP
12
LSB
LSB/°C
±0.3
±3
LSB
±1.5
±8
LSB
0.05
±1.2
Unipolar Full-Scale Error Drift
0.05
Unipolar Full-Scale Error Match (LTC2306)
±0.3
LSB/°C
±6
LSB
LSB/°C
±3
LSB
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MAX
UNITS
VIN+
Absolute Input Range (CH0, CH1, IN+)
(Note 9)
l
–0.05
VDD
V
–
Absolute Input Range (CH0, CH1, IN–)
Unipolar (Note 9)
Bipolar (Note 9)
l
l
–0.05
–0.05
VDD/2
VDD
V
V
VIN = VIN+ – VIN– (Unipolar)
VIN = VIN+ – VIN– (Bipolar)
l
l
VIN
VIN+ – VIN– Input Differential Voltage Range
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
CMRR
Input Common Mode Rejection Ratio
MIN
TYP
0 to VREF
±VREF/2
l
V
V
±1
Sample Mode
Hold Mode
μA
55
5
pF
pF
70
dB
REFERENCE INPUT
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
VREF Input Range
l
IREF
Reference Input Current
l
l
CREF
Reference Input Capacitance
fSMPL = 0ksps, VREF = 4.096V
fSMPL = 500ksps, VREF = 4.096V
TYP
0.1
50
230
55
MAX
UNITS
VDD
V
80
260
μA
μA
pF
23026f
3
LTC2302/LTC2306
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 4, 10)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
SINAD
Signal-to-(Noise + Distortion) Ratio
fIN = 1kHz
l
71
72.8
dB
SNR
Signal-to-Noise Ratio
fIN = 1kHz
l
71
73.2
dB
THD
Total Harmonic Distortion
fIN = 1kHz, First 5 Harmonics
l
SFDR
Spurious Free Dynamic Range
fIN = 1kHz
l
–88
79
MAX
UNITS
–78
dB
89
dB
Channel-to-Channel Isolation
fIN = 1kHz
–109
dB
Full Linear Bandwidth
(Note 11)
700
kHz
25
MHz
13
ns
240
ns
–3dB Input Linear Bandwidth
Aperature Delay
Transient Response
Full-Scale Step
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
l
VIL
Low Level Input Voltage
VDD = 4.75V
l
0.8
V
IIN
High Level Input Current
VIN = VDD
l
±10
μA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
MIN
OVDD = 4.75V, IOUT = –10μA
OVDD = 4.75V, IOUT = –200μA
l
OVDD = 4.75V, IOUT = 160μA
OVDD = 4.75V, IOUT = 1.6mA
l
l
TYP
MAX
UNITS
2.4
V
5
pF
4.74
V
V
4
0.05
0.4
V
V
±10
μA
IOZ
Hi-Z Output Leakage
VOUT = 0V to OVDD, CONVST High
COZ
Hi-Z Output Capacitance
CONVST High
15
pF
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = OVDD
10
mA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VDD
Supply Voltage
OVDD
Output Driver Supply Voltage
IDD
Supply Current
Sleep Mode
PD
Power Dissipation
Sleep Mode
CONDITIONS
CL = 25pF
CONVST = 5V, Conversion Done
MIN
TYP
MAX
UNITS
l
4.75
5
5.25
V
l
2.7
l
l
2.8
7
14
35
5.25
V
3.5
15
mA
μA
mW
μW
23026f
4
LTC2302/LTC2306
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
MAX
UNITS
fSMPL(MAX)
Maximum Sampling Frequency
CONDITIONS
l
MIN
500
kHz
fSCK
Shift Clock Frequency
l
40
MHz
tWHCONV
CONVST High Time
l
20
ns
tHD
Hold Time SDI After SCK↑
l
2.5
ns
tSUDI
Setup Time SDI Stable Before SCK↑
l
0
ns
(Note 9)
TYP
tWHCLK
SCK High Time
fSCK = fSCK(MAX)
l
10
ns
tWLCLK
SCK Low Time
fSCK = fSCK(MAX)
l
10
ns
tWLCONVST
CONVST Low Time During Data Transfer
(Note 9)
l
410
ns
(Note 9)
l
20
tHCONVST
Hold Time CONVST Low After Last SCK↓
tCONV
Conversion Time
tACQ
Acquisition Time
7th SCK↑ to CONVST↑ (Note 9)
l
tdDO
l
ns
1.3
1.6
240
μs
ns
SDO Data Valid After SCK↓
CL = 25pF (Note 9)
l
thDO
SDO Hold Time SCK↓
CL = 25pF
l
ten
SDO Valid After CONVST↓
CL = 25pF
l
11
15
ns
tdis
Bus Relinquish Time
CL = 25pF
l
11
15
ns
10.8
12.5
4
ns
ns
tr
SDO Rise Time
CL = 25pF
4
ns
tf
SDO Fall Time
CL = 25pF
4
ns
tCYC
Total Cycle Time
2
μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with VDD and OVDD
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above VDD without latchup.
Note 4: VDD = 5V, OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless
otherwise specified.
Note 5: Linearity, offset and full-scale specifications apply for a singleended analog input with respect to GND for the LTC2306 and IN+ with
respect to IN– tied to GND for the LTC2302.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from +0.5LSB
when the output code flickers between 0000 0000 0000 and 0000 0000
0001.
Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 9: Guaranteed by design, not subject to test.
Note 10: All specifications in dB are referred to a full-scale ±2.048V input
with a 4.096V reference voltage.
Note 11: Full linear bandwidth is defined as the full-scale input frequency
at which the SINAD degrades to 60dB or 10 bits of accuracy.
23026f
5
LTC2302/LTC2306
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2302) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted.
1.00
1.00
0.75
0.75
0.50
0.50
0.25
0.25
0
0
–0.25
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
0
1024
2048
3072
4096
1kHz Sine Wave
8192 Point FFT Plot
MAGNITUDE (dB)
Differential Nonlinearity vs
Output Code
DNL (LSB)
INL (LSB)
Integral Nonlinearity vs
Output Code
–1.00
0
1024
OUTPUT CODE
2048
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
0
4096
3072
SNR = 73.2dB
SINAD = 72.8dB
THD = –89.5dB
50
100
150
23026 G01
SINAD vs Input Frequency
SNR vs Input Frequency
80
75
75
70
70
250
23026 G03
23026 G02
80
200
FREQUENCY (kHz)
OUTPUT CODE
THD vs Input Frequency
–60
–65
65
THD (dB)
SINAD (dB)
SNR (dB)
–70
65
60
60
55
55
–75
–80
–85
–90
50
–95
–100
50
1
10
100
FREQUENCY (kHz)
1000
10
100
FREQUENCY (kHz)
1
1000
23026 G04
1
10
100
FREQUENCY (kHz)
23026 G06
23026 G05
Supply Current vs
Sampling Frequency
1000
Supply Current vs Temperature
4.0
3.5
3.8
3.6
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
3.0
2.5
2.0
1.5
1.0
3.4
3.2
3.0
2.8
2.6
2.4
0.5
2.2
0
1
10
100
SAMPLING FREQUENCY (ksps)
1000
23026 G07
2.0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
23026 G08
23026f
6
LTC2302/LTC2306
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2302) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted.
Analog Input Leakage Current vs
Temperature
Sleep Current vs Temperature
1000
9
900
INPUT LEAKAGE CURRENT (nA)
10
SLEEP CURRENT (μA)
8
7
6
5
4
3
2
800
700
600
500
400
300
200
100
1
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
0
–50
125
–25
50
25
0
75
TEMPERATURE (°C)
125
23026 G10
23026 G09
Offset Error vs Temperature
Full-Scale Error vs Temperature
2.0
2.5
2.0
1.5
FULL-SCALE ERROR (LSB)
1.5
OFFSET ERROR (LSB)
100
1.0
BIPOLAR
0.5
0
UNIPOLAR
–0.5
–1.0
BIPOLAR
1.0
UNIPOLAR
0.5
0
–0.5
–1.0
–1.5
–1.5
–2.0
–2.5
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
23026 G11
–2.0
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
125
23026 G12
23026f
7
LTC2302/LTC2306
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2306) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted.
1.00
1.00
0.75
0.75
0.50
0.50
0.25
0.25
0
0
–0.25
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
0
2048
1024
3072
4096
1kHz Sine Wave
8192 Point FFT Plot
MAGNITUDE (dB)
Differential Nonlinearity vs
Output Code
DNL (LSB)
INL (LSB)
Integral Nonlinearity vs
Output Code
–1.00
0
1024
OUTPUT CODE
2048
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
0
4096
3072
SNR = 73.2dB
SINAD = 72.8dB
THD = –88.7dB
50
100
150
23026 G13
SINAD vs Input Frequency
SNR vs Input Frequency
80
75
75
70
70
250
23026 G15
23026 G14
80
200
FREQUENCY (kHz)
OUTPUT CODE
THD vs Input Frequency
–60
–65
65
THD (dB)
SINAD (dB)
SNR (dB)
–70
65
60
60
55
55
–75
–80
–85
–90
50
1
10
100
FREQUENCY (kHz)
1000
–95
–100
50
1
10
100
FREQUENCY (kHz)
1000
23026 G16
1
10
100
FREQUENCY (kHz)
23026 G18
23026 G17
Supply Current vs
Sampling Frequency
1000
Supply Current vs Temperature
4.0
3.5
3.8
3.0
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
3.6
2.5
2.0
1.5
1.0
3.4
3.2
3.0
2.8
2.6
2.4
0.5
2.2
0
1
10
100
SAMPLING FREQUENCY (ksps)
1000
23026 G19
2.0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
23026 G20
23026f
8
LTC2302/LTC2306
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2306) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted.
Analog Input Leakage Current vs
Temperature
Sleep Current vs Temperature
1000
9
900
INPUT LEAKAGE CURRENT (nA)
10
SLEEP CURRENT (μA)
8
7
6
5
4
3
2
800
700
600
500
400
300
200
100
1
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
0
–50
125
–25
50
25
0
75
TEMPERATURE (°C)
Full-Scale Error vs Temperature
2.0
2.0
1.5
1.5
FULL-SCALE ERROR (LSB)
OFFSET ERROR (LSB)
Offset Error vs Temperature
1.0
0.5
UNIPOLAR
BIPOLAR
–0.5
–1.0
–1.5
–2.0
–50 –25
125
23026 G22
23026 G21
0
100
1.0
0.5
UNIPOLAR
0
–0.5
BIPOLAR
–1.0
–1.5
75
50
25
TEMPERATURE (°C)
0
100
125
23026 G23
–2.0
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
125
23026 G24
23026f
9
LTC2302/LTC2306
PIN FUNCTIONS
LTC2302
LTC2306
SDO (Pin 1): Three-State Serial Data Out. SDO outputs
the data from the previous conversion. SDO is shifted
out serially on the falling edge of each SCK pulse. SDO is
enabled by a low level on CONVST.
SDO (Pin 1): Three-State Serial Data Out. SDO outputs
the data from the previous conversion. SDO is shifted
out serially on the falling edge of each SCK pulse. SDO is
enabled by a low level on CONVST.
CONVST (Pin 2): Conversion Start. A rising edge at
CONVST begins a conversion. For best performance,
ensure that CONVST returns low within 40ns after the
conversion starts or after the conversion ends.
CONVST (Pin 2): Conversion Start. A rising edge at
CONVST begins a conversion. For best performance,
ensure that CONVST returns low within 40ns after the
conversion starts or after the conversion ends.
VDD (Pin 3): 5V Supply. The range of VDD is 4.75V to 5.25V.
Bypass VDD to GND with a 0.1μF ceramic capacitor and a
10μF tantalum capacitor in parallel.
VDD (Pin 3): 5V Supply. The range of VDD is 4.75V to 5.25V.
Bypass VDD to GND with a 0.1μF ceramic capacitor and a
10μF tantalum capacitor in parallel.
IN+, IN– (Pin 4, Pin 5): Positive (IN+) and Negative (IN–)
Differential Analog Inputs.
CH0, CH1 (Pin 4, Pin 5): Channel 0 and Channel 1 Analog
Inputs. CH0, CH1 can be configured as single-ended or
differential input channels. See the Analog Input Multiplexer section.
VREF (Pin 6): Reference Input. Connect an external reference at VREF . The range of the external reference is 0.1V
to VDD. Bypass to GND with a minimum 10μF tantalum
capacitor in parallel with a 0.1μF ceramic capacitor.
GND (Pin 7): Ground. All GND pins must be connected to
a solid ground plane.
SDI (Pin 8): Serial Data Input. The SDI serial bit stream
configures the ADC and is latched on the rising edge of
the first 6 SCK pulses.
SCK (Pin 9): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
OVDD (Pin 10): Output Driver Supply. Bypass OVDD to
GND with a 0.1μF ceramic capacitor close to the pin. The
range of OVDD is 2.7V to 5.25V.
Exposed Pad (Pin 11): Exposed Pad Ground. Must be
soldered directly to ground plane.
VREF (Pin 6): Reference Input. Connect an external reference at VREF .The range of the external reference is 0.1V
to VDD. Bypass to GND with a minimum 10μF tantalum
capacitor in parallel with a 0.1μF ceramic capacitor.
GND (Pin 7): Ground. All GND pins must be connected to
a solid ground plane.
SDI (Pin 8): Serial Data Input. The SDI serial bit stream
configures the ADC and is latched on the rising edge of
the first 6 SCK pulses.
SCK (Pin 9): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
OVDD (Pin 10): Output Driver Supply. Bypass OVDD to
OGND with a 0.1μF ceramic capacitor close to the pin.
The range of OVDD is 2.7V to 5.5V.
Exposed Pad (Pin 11): Exposed Pad Ground. Must be
soldered directly to ground plane.
23026f
10
LTC2302/LTC2306
BLOCK DIAGRAM
OVDD
VDD
LTC2302
LTC2306
SDI
CH0 (IN+)
CH1 (IN–)
+
–
ANALOG
INPUT
MUX
12-BIT
500ksps
ADC
SDO
SERIAL
PORT
SCK
CONVST
VREF
PIN NAMES IN PARENTHESIS
REFER TO LTC2302
23026 BD
GND
TEST CIRCUITS
Load Circuit for tdis Waveform 1
Load Circuit for tdis Waveform 2, ten
VDD
3k
SDO
SDO
TEST POINT
CL
TEST POINT
3k
CL
23026 TC01
23026 TC02
TIMING DIAGRAMS
Voltage Waveforms for SDO Delay Times, tdDO and thDO
SCK
Voltage Waveforms for tdis
VIH
CONVST
VIL
tdDO
thDO
VOH
SDO
SDO
WAVEFORM 1
(SEE NOTE 1)
tdis
VOL
23026 TD01
90%
SDO
WAVEFORM 2
(SEE NOTE 2)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
23026 TD02
23026f
11
LTC2302/LTC2306
TIMING DIAGRAMS
tWLCLK (SCK Low Time)
tWHCLK (SCK High Time)
tHD (Hold Time SDI After SCK↑)
tSUDI (Setup Time SDI Stable Before SCK↑)
tWLCLK
Voltage Waveforms for ten
CONVST
tWHCLK
SDO
23026 TD04
ten
SCK
tHD
Voltage Waveforms for SDO Rise and Fall Times tr, tf
SDI
tSUDI
23026 TD03
VOH
SDO
VOL
tr
tf
23004 TD05
APPLICATIONS INFORMATION
Overview
The LTC2302/LTC2306 are low noise, 500ksps, 1-/2-channel, 12-bit successive approximation register (SAR) A/D
converters. The LTC2306 includes a 2-channel analog
input multiplexer (MUX) while the LTC2302 includes an
input MUX that allows the polarity of the differential input
to be selected. Both ADCs include an SPI-compatible serial port for easy data transfers and can operate in either
unipolar or bipolar mode. Unipolar mode should be used
for single-ended operation with the LTC2306, since singleended input signals are always referenced to GND. The
LTC2302/LTC2306 can be put into a power-down sleep
mode during idle periods to save power.
Conversions are initiated by a rising edge on the CONVST
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, a 6-bit input word (DIN)
at the SDI input configures the MUX and programs various modes of operation. As the DIN bits are shifted in,
data from the previous conversion is shifted out on SDO.
After the 6 bits of the DIN word have been shifted in, the
ADC begins acquiring the analog input in preparation for
the next conversion as the rest of the data is shifted out.
The acquire phase requires a minimum time of 240ns
for the sample-and-hold capacitors to acquire the analog
input signal.
During the conversion, the internal 12-bit capacitive
charge-redistribution DAC output is sequenced through a
successive approximation algorithm by the SAR starting
from the most significant bit (MSB) to the least significant
bit (LSB). The sampled input is successively compared
with binary weighted charges supplied by the capacitive
DAC using a differential comparator. At the end of a conversion, the DAC output balances the analog input. The SAR
contents (a 12-bit data word) that represent the sampled
analog input are loaded into 12 output latches that allow
the data to be shifted out.
Programming the LTC2306 and LTC2302
The software compatible LTC2302/LTC2306/LTC2308 family features a 6-bit DIN word to program various modes of
operation. Don’t care bits (X) are ignored. The SDI data
bits are loaded on the rising edge of SCK, with the S/D bit
loaded on the first rising edge (see Figure 6 in the Timing
23026f
12
LTC2302/LTC2306
APPLICATIONS INFORMATION
and Control section). The input data word for the LTC2306
is defined as follows:
S/D O/S
X
X
UNI
X
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
X = DON’ T CARE
For the LTC2302, the input data word is defined as:
O/S
X
X
UNI
X
Analog Input Multiplexer
The analog input MUX is programmed by the S/D and O/S
bits of the DIN word for the LTC2306 and the O/S bit of the
DIN word for the LTC2302. Table 1 and Table 2 list MUX
configurations for all combinations of the configuration
bits. Figure 1a shows several possible MUX configurations
and Figure 1b shows how the MUX can be reconfigured
from one conversion to the next.
2 Single-Ended
1 Differential
+ (–)
– (+) {
+
+
CH0
CH1
S/D
O/S
0
0
+
–
0
1
–
+
1
0
+
1
1
LTC2306
+
WITH RESPECT
TO GND
CH0
CH1
Table 2. Channel Configuration
for the LTC2302
O/S
IN+
IN–
0
+
–
1
–
+
Driving the Analog Inputs
The analog inputs of the LTC2302/LTC2306 are easy to
drive. Each of the analog inputs of the LTC2306 (CH0
and CH1) can be used as a single-ended input relative
to GND or as a differential pair. The analog inputs of the
LTC2302 (IN+, IN–) are always configured as a differential
pair. Regardless of the MUX configuration, the “+” and “–”
inputs are sampled at the same instant. Any unwanted
signal that is common to both inputs will be reduced by
the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while
LTC2306
1st Conversion
(–) GND
+
–{
1 Differential
+ (–)
– (+) {
CH0 CH1
NOTE: UNIPOLAR MODE SHOULD BE USED
FOR SINGLE-ENDED OPERATION, SINCE INPUT
SIGNALS ARE ALWAYS REFERENCED TO GND
UNI = UNIPOLAR/BIPOLAR BIT
X
Table 1. Channel Configuration
for the LTC2306
CH0
CH1
LTC2306
IN+
IN–
2nd Conversion
+
+
CH0
CH1
LTC2306
(–) GND
LTC2302
23026 F01b
23026 F01a
Figure 1b. Changing the MUX Assignment “On the Fly”
Figure 1a. Example MUX Configurations
23026f
13
LTC2302/LTC2306
APPLICATIONS INFORMATION
charging the sample-and-hold capacitors during the acquire
mode. In conversion mode, the analog inputs draw only
a small leakage current. If the source impedance of the
driving circuit is low, the ADC inputs can be driven directly.
Otherwise, more acquisition time should be allowed for a
source with higher impedance.
Reference
A low noise, stable reference is required to ensure full
performance. The LT®1790 and LT6660 are adequate
for most applications. The LT6660 is available in 2.5V,
3V, 3.3V and 5V versions, and the LT1790 is available in
1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V versions. The
exceptionally low input noise allows the input range to be
optimized for the application by changing the reference
voltage. The VREF input must be decoupled with a 10μF
capacitor in parallel with a 0.1μF capacitor, so verify that
the device providing the reference voltage is stable with
capacitive loads.
If the voltage reference is 5V and can supply 5mA, it can
be used for both VREF and VDD. VDD must be connected
to a clean analog supply, and a quiet 5V reference voltage
makes a convenient supply for this purpose.
Input Filtering
The noise and distortion of the input amplifier and other
circuitry must be considered since they will add to the
ADC noise and distortion. Therefore, noisy input circuitry
RSOURCE
INPUT
(CH0, CH1
IN+, IN–)
VIN
C1
should be filtered prior to the analog inputs to minimize
noise. A simple 1-pole RC filter is sufficient for many
applications.
The analog inputs of the LTC2302/LTC2306 can be modeled
as a 55pF capacitor (CIN) in series with a 100Ω resistor
(RON) as shown in Figure 2a. CIN gets switched to the
selected input once during each conversion. Large filter
RC time constants will slow the settling of the inputs. It
is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle to
12-bit resolution within the acquisition time (tACQ) if DC
accuracy is important.
When using a filter with a large CFILTER value (e.g., 1μF),
the inputs do not completely settle and the capacitive input
switching currents are averaged into a net DC current
(IDC). In this case, the analog input can be modeled by
an equivalent resistance (REQ = 1/(fSMPL • CIN)) in series
with an ideal voltage source (VREF/2) as shown in Figure
2b. The magnitude of the DC current is then approximately
IDC = (VIN – VREF/2)/REQ, which is roughly proportional
to VIN. To prevent large DC drops across the resistor
RFILTER, a filter with a small resistor and large capacitor
should be chosen. When running at the minimum cycle
time of 2μs, the input current equals 106μA at VIN = 5V,
which amounts to a full-scale error of 0.5LSB when using
a filter resistor (RFILTER) of 4.7Ω. Applications requiring
lower sample rates can tolerate a larger filter resistor for
the same amount of full-scale error.
LTC2302
LTC2306
RFILTER
RON
100Ω
LTC2302
LTC2306
INPUT
(CH0, CH1
IDC IN+, IN–)
VIN
CIN
55pF
23026 F02a
Figure 2a. Analog Input Equivalent Circuit
REQ
1/(fSMPL • CIN)
CFILTER
+
–
VREF/2
23026 F02b
Figure 2b. Analog Input Equivalent Circuit for
Large Filter Capacitances
23026f
14
LTC2302/LTC2306
APPLICATIONS INFORMATION
Figures 3a and 3b show respective examples of input
filtering for single-ended and differential inputs. For the
single-ended case in Figure 3a, a 50Ω source resistor
and a 2000pF capacitor to ground on the input will limit
the input bandwidth to 1.6MHz. High quality capacitors
and resistors should be used in the RC filter since these
components can add distortion. NPO and silver mica type
dielectric capacitors have excellent linearity. Carbon surface
mount resistors can generate distortion from self heating
and from damage that may occur during soldering. Metal
film surface mount resistors are much less susceptible
to both problems.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 4 shows a typical SINAD of 72.8dB with
a 500kHz sampling rate and a 1kHz input. A SNR of 73.2dB
can be achieved with the LTC2302/LTC2306.
FFT (fast fourier transform) test techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm, the
ADC’s spectral content can be examined for frequencies
outside the fundamental.
MAGNITUDE (dB)
Dynamic Performance
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
SNR = 73.2dB
SINAD = 72.8dB
THD = –88.7dB
0
5V
0.1μF
ANALOG
INPUT
50Ω
150
200
250
CH0, CH1
23026 F04
2000pF
Figure 4. 1kHz Sine Wave 8192 Point FFT Plot (LTC2306)
LTC2306
LT1790A-4.096
Total Harmonic Distortion (THD)
VOUT
VREF
10μF
0.1μF
23026 F03a
Figure 3a. Optional RC Input Filtering for Single-Ended Input
DIFFERENTIAL
ANALOG
INPUTS 50Ω
CH0, IN+
LTC2302
LTC2306
1000pF
CH1, IN–
VIN
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics.
1000pF
LT1790A-4.096
VOUT
VREF
10μF
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency(fSMPL/2).
THD is expressed as:
V22 + V32 + V42 ... + VN2
THD = 20 log
V1
1000pF
50Ω
0.1μF
100
FREQUENCY (kHz)
VIN
5V
50
0.1μF
23026 F03b
Figure 3b. Optional RC Input Filtering for Differential Inputs
23026f
15
LTC2302/LTC2306
APPLICATIONS INFORMATION
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieve a typical conversion time (tCONV) of 1.3μs and a
maximum conversion time of 1.6μs over the full operating
temperature range. With a minimum acquisition time of
240ns, a throughput sampling rate of 500ksps is tested
and guaranteed.
Digital Interface
The LTC2302/LTC2306 communicate via a standard
4-wire SPI compatible digital interface. The rising edge
of CONVST initiates a conversion. After the conversion
is finished, pull CONVST low to enable the serial output
(SDO). The ADC then shifts out the digital data in 2’s
complement format when operating in bipolar mode or
in straight binary format when in unipolar mode, based
on the setting of the UNI bit.
For best performance, ensure that CONVST returns low
within 40ns after the conversion starts (i.e., before the first
bit decision) or after the conversion ends. If CONVST is
low when the conversion ends, the MSB bit will appear at
SDO at the end of the conversion and the ADC will remain
powered up.
Timing and Control
The start of a conversion is triggered by the rising edge
of CONVST. Once initiated, a new conversion cannot be
restarted until the current conversion is complete. Figures 6
and 7 show the timing diagrams for two different examples
of CONVST pulses. Example 1 (Figure 6) shows CONVST
staying HIGH after the conversion ends. If CONVST is high
after the tCONV period, the LTC2302/LTC2306 enter sleep
mode (see Sleep Mode for more details).
When CONVST returns low, the ADC wakes up and the
most significant bit (MSB) of the output data sequence at
SDO becomes valid after the serial data bus is enabled. All
other data bits from SDO transition on the falling edge of
each SCK pulse. Configuration data (DIN) is loaded into the
LTC2302/LTC2306 at SDI, starting with the first SCK rising
edge after CONVST returns low. The S/D bit is loaded on
the first SCK rising edge.
Example 2 (Figure 7) shows CONVST returning low before the conversion ends. In this mode, the ADC and all
internal circuitry remain powered up. When the conversion is complete, the MSB of the output data sequence
at SDO becomes valid after the data bus is enabled. At
this point(tCONV 1.3μs after the rising edge of CONVST),
pulsing SCK will shift data out at SDO and load configuration data (DIN) into the LTC2302/LTC2306 at SDI. The first
SCK rising edge loads the S/D bit. SDO transitions on the
falling edge of each SCK pulse.
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar modes. Data is output at SDO in 2’s
complement format for bipolar readings or in straight
binary for unipolar readings.
Sleep Mode
The ADC enters sleep mode when CONVST is held high
after the conversion is complete (tCONV). The supply current decreases to 7μA in sleep mode between conversions,
thereby reducing the average power dissipation as the
sample rate decreases. For example, the LTC2302/LTC2306
draw an average of 14μA with a 1ksps sampling rate. The
LTC2302/LTC2306 power down all circuitry when in sleep
mode.
Board Layout and Bypassing
To obtain the best performance, a printed circuit board with
a solid ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. Care should be taken
not to run any digital signal alongside an analog signal.
All analog inputs should be shielded by GND. VREF and
VDD should be bypassed to the ground plane as close to
the pin as possible. Maintaining a low impedance path
for the common return of these bypass capacitors is
essential to the low noise operation of the ADC. These
traces should be as wide as possible. See Figure 5 for a
suggested layout.
23026f
16
LTC2302/LTC2306
APPLICATIONS INFORMATION
VDD, BYPASS
0.1μF||10μF, 0603
INPUT FILTER
CAPACITORS
SOLID GROUND
PLANE
OVDD, BYPASS
0.1μF, 0603
23026 F05
VREF, BYPASS
0.1μF||10μF 0603
Figure 5. Suggested Layout
tWLCONVST
tACQ
CONVST
tCONV
SLEEP
tCYC
1
2
3
4
5
6
7
8
9
10 11 12
SCK
S/D BIT IS A DON’T CARE (X) FOR THE LTC2302
SDI
S/D O/S
UNI
MSB
SDO
Hi-Z
LSB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Hi-Z
23026 F06
Figure 6. LTC2302/LTC2306 Timing with a Long CONVST Pulse
23026f
17
LTC2302/LTC2306
APPLICATIONS INFORMATION
tWHCONV
tHCONVST
tACQ
CONVST
tCYC
tCONV
1
2
3
4
5
6
7
8
9
10 11 12
SCK
S/D BIT IS A DON’T CARE (X) FOR THE LTC2302
SDI
SDO
S/D O/S
Hi-Z
UNI
MSB
LSB
B11
B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Hi-Z
23026 F07
011...111
111...111
BIPOLAR
ZERO
011...110
111...110
000...001
OUTPUT CODE
OUTPUT CODE (TWO’S COMPLEMENT)
Figure 7. LTC2302/LTC2306 Timing with a Short CONVST Pulse
000...000
111...111
111...110
FS = 4.096V
1LSB = FS/2N
1LSB = 1mV
100...001
100...000
–FS/2
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
23026 F08
Figure 8. LTC2302/LTC2306 Bipolar Transfer Characteristics
(2’s Complement)
100...001
100...000
011...111 UNIPOLAR
ZERO
011...110
FS = 4.096V
1LSB = FS/2N
1LSB = 1mV
000...001
000...000
0V
FS – 1LSB
INPUT VOLTAGE (V)
20026 F09
Figure 9. LTC2302/LTC2306 Unipolar Transfer Characteristics
(Straight Binary)
23026f
18
LTC2302/LTC2306
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
R = 0.115
TYP
6
0.38 ± 0.10
10
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD) DFN 1103
5
0.200 REF
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.00 – 0.05
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
23026f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2302/LTC2306
TYPICAL APPLICATION
Clock Squaring/Level Shifting Circuit Allows Testing with RF Sine Generator,
Convert Re-Timing Flip-Flop Preserves Low Jitter Clock Timing
10μF
0.1μF
0.1μF
LTC2302
LTC2306
OVDD
VDD
SDI
ANALOG
INPUT
MUX
CH0 (IN+)
CH1 (IN–)
+
–
SDO
12-BIT
500ksps
ADC
SERIAL
PORT
VCC
SCK
CONVST
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
Q PRE D
NL17SZ74
Q CLR
CONVERT ENABLE
VREF
GND
0.1μF
RF SIGNAL
GENERATOR
OR OTHER LOW
JITTER SOURCE
MASTER
CLOCK
••••••
CONVERT
ENABLE
••••••
CONVST
••••••
10μF
VCC
0.1μF 1k
MASTER
CLOCK
23026 TA02
50Ω
1k
NC7SVU04P5X
••••••
••••••
JITTER
••••••
DATA TRANSFER
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1417
14-Bit, 400ksps Serial ADC
20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
LTC1468/LT1469
Single/Dual 90MHz, 22V/μs, 16-Bit Accurate Op Amps
Low Input Offset: 75μV/125μV
LTC1609
16-Bit, 200ksps Serial ADC
65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
LTC1790
Micropower Low Dropout Reference
60μA Supply Current, 10ppm/°C, SOT-23 Package
LTC1850/LTC1851
10-Bit/12-Bit, 8-channel, 1.25Msps ADCs
Parallel Output, Programmable MUX and Sequencer, 5V Supply
LTC1852/LTC1853
10-Bit/12-Bit, 8-channel, 400ksps ADCs
Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
LTC1860/LTC1861
12-Bit, 1-/2-Channel 250ksps ADCs in MSOP
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
LTC1860L/LTC1861L
3V, 12-bit, 1-/2-Channel 150ksps ADCs
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
LTC1863/LTC1867
12-/16-Bit, 8-Channel 200ksps ADCs
6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
LTC1863L/LTC1867L
3V, 12-/16-bit, 8-Channel 175ksps ADCs
2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
LTC1864/LTC1865
16-Bit, 1-/2-Channel 250ksps ADCs in MSOP
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
LTC1864L/LTC1865L
3V, 16-Bit, 1-/2-Channel 150ksps ADCs in MSOP
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
LTC2308
12-Bit, 8-Channel 500ksps ADC
5V, Internal Reference, 4mm × 4mm QFN Packages
23026f
20 Linear Technology Corporation
LT 0108 • PRINTED IN USA
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