TI DRV8305 Drv8305 three phase gate driver with current shunt amplifiers and voltage regulator Datasheet

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DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator
1 Features
3 Description
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•
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The DRV8305 is a gate driver IC for three phase
motor drive applications. It provides three highaccuracy trimmed and temperature compensated half
bridge drivers, each capable of driving a high-side
and low-side N-type MOSFET.
1
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•
•
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•
•
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4.4-V to 45-V Operating Voltage
1.25-A/1-A Peak Gate Driver Currents
Programmable, Independent HS/LS Slew
Rate/Slope Control
Charge Pump Gate Driver for 100% Duty Cycle
Three Integrated Current Shunt Amplifiers
Integrated 50-mA LDO (3.3-V/5-V Option)
Control of 3-PWM or 6-PWM Inputs up to 200 kHz
Built-In Commutation Tables for Using 1 PWM
Programmable Dead Time
MOSFET Shoot Through Prevention
Programmable VDS Protection of MOSFETs
Reverse Battery Protection Support
Supports Both 3.3-V/5-V Digital Interface
SPI Interface
Thermally Enhanced 48-Pin QFP (7 × 7 mm)
Protection Features
VM Undervoltage Lockout (UVLO2)
Logic Undervoltage (UVLO1)
Charge Pump Undervoltage (CPUVL)
Temperature Warnings and Shutdown
Watchdog Timer
A charge pump driver supports 100% duty cycle and
low voltage operation. The gate driver can also
handle load dumps up to 45 V.
The gate driver uses automatic handshaking when
switching to prevent current shoot through. Accurate
VDS of both the high-side and low-side MOSFETs
conditions are sensed to protect external MOSFETs
during over current.
The DRV8305 includes three current shunt amplifiers
for accurate current measurements that support bidirectional current sensing with adjustable gain.
The DRV8305 has an integrated voltage regulator
and controller to support a MCU or additional system
power needs.
The SPI provides detailed fault reporting and flexible
parameter settings such as gain options for the
current shunt amplifier, slew rate control of the gate
drivers, various protection features.
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2 Applications
DRV8305
•
•
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Phase BLDC and PMSM Motors
CPAP and Pumps
Robotics and RC Toys
Power Tools
Industrial Automation
HTQFP (48)
(1)
7.00 mm × 7.00 mm
Simplified Schematic
4.4 to 45 V
MCU
PWM
SPI
Shunt Amps
nFAULT
DRV8305
3-Phase
Brushless
Pre-Driver
Gate Drive
LDO
Sense
N-Channel
MOSFETs
EN_GATE
M
Shunt Amps
Protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8305
SLVSCX2A – AUGUST 2015 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
SPI Timing Requirements (Slave Mode Only) ........ 13
Typical Characteristics ............................................ 14
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 28
7.5 Programming........................................................... 30
7.6 Register Maps ......................................................... 31
8
Application and Implementation ........................ 39
8.1 Application Information............................................ 39
8.2 Typical Application ................................................. 40
9
Power Supply Recommendations...................... 44
9.1 Bulk Capacitance ................................................... 44
10 Layout................................................................... 45
10.1 Layout Guidelines ................................................. 45
10.2 Layout Example .................................................... 45
11 Device and Documentation Support ................. 46
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
12 Mechanical, Packaging, and Orderable
Information ........................................................... 46
4 Revision History
Changes from Original (August 2015) to Revision A
Page
•
Change the Electrical Characteristics Condition From: TJ = –40°C to 150°C To: TA = 25°C ............................................... 7
•
Changed Table 18 - Bit 10 , 9, and 8 DEFAULT From: = 0x1 To: 0x0 ............................................................................... 37
2
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5 Pin Configuration and Functions
37
38
39
40
41
42
43
44
45
46
1
36
2
35
3
34
4
33
5
32
1
2 PAD
POWER
3
(GND)
6
7
31
30
8
29
24
23
22
21
GHA
SHA
SLA
GLA
GLB
SLB
SHB
GHB
GHC
SHC
SLC
GLC
PWRGD
GND
AVDD
SO1
SO2
SO3
SN3
SP3
SN2
SP2
SN1
SP1
20
25
19
12
18
26
16
11
15
27
14
28
13
9
10
17
EN_GATE
INHA
INLA
INHB
INLB
INHC
INLC
nFAULT
nSCS
SDI
SDO
SCLK
47
48
VREG
WAKE
DVDD
GND
VDRAIN
CP1H
CP1L
PVDD
CP2L
CP2H
VCPH
VCP_LSD
PHP Package
48-Pin HTQFP
Top View
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
EN_GATE
I
Enable gate
Enables the gate driver and current shunt amplifiers; internal
pulldown
2
INHA
I
Bridge PWM input
PWM input signal for bridge A high-side
3
INLA
I
Bridge PWM input
PWM input signal for bridge A low-side
4
INHB
I
Bridge PWM input
PWM input signal for bridge B high-side
5
INLB
I
Bridge PWM input
PWM input signal for bridge B low-side
6
INHC
I
Bridge PWM input
PWM input signal for bridge C high-side
7
INLC
I
Bridge PWM input
PWM input signal for bridge C low-side
8
nFAULT
OD
Fault indicator
When low indicates a fault has occurred; open drain; external
pullup to MCU power supply needed (1 kΩ to 10 kΩ)
9
nSCS
I
SPI chip select
Select/enable for SPI; active low
10
SDI
I
SPI input
SPI input signal
11
SDO
O
SPI output
SPI output signal; referred to VREG
12
SCLK
I
SPI clock
SPI clock signal
13
PWRGD
Power Good
VREG and MCU watchdog fault indication; open drain; external
pullup to MCU power supply needed (1 kΩ to 10 kΩ)
OD
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Pin Functions (continued)
PIN
NO.
NAME
I/O
DESCRIPTION
14
45
GND
P
Device ground
Must be connected to ground
15
AVDD
P
Analog regulator
5.0 V analog internal supply regulator; bypass to GND with a 6.3V, 1-µF ceramic capacitor
16
SO1
O
Current amplifier output
Output of current sense amplifier 1
17
SO2
O
Current amplifier output
Output of current sense amplifier 2
18
SO3
O
Current amplifier output
Output of current sense amplifier 3
19
SN3
I
Current amplifier negative input
Negative input of current sense amplifier 3
20
SP3
I
Current amplifier positive input
Positive input of current sense amplifier 3
21
SN2
I
Current amplifier negative input
Negative input of current sense amplifier 2
22
SP2
I
Current amplifier positive input
Positive input of current sense amplifier 2
23
SN1
I
Current amplifier negative input
Negative input of current sense amplifier 1
24
SP1
I
Current amplifier positive input
Positive input of current sense amplifier 1
25
GLC
O
Low-side gate driver
Low-side gate driver output for half-bridge C
26
SLC
I
Low-side source connection
Low-side source connection for half-bridge C
27
SHC
I
High-side source connection
High-side source connection for half-bridge C
28
GHC
O
High-side gate driver
High-side gate driver output for half-bridge C
29
GHB
O
High-side gate driver
High-side gate driver output for half-bridge B
30
SHB
I
High-side source connection
High-side source connection for half-bridge B
31
SLB
I
Low-side source connection
Low-side source connection for half-bridge B
32
GLB
O
Low-side gate driver
Low-side gate driver output for half-bridge B
33
GLA
O
Low-side gate driver
Low-side gate driver output for half-bridge A
34
SLA
I
Low-side source connection
Low-side source connection for half-bridge A
35
SHA
I
High-side source connection
High-side source connection for half-bridge A
36
GHA
O
High-side gate driver
High-side gate driver output for half-bridge A
37
VCP_LSD
P
Low-side gate driver regulator
Internal voltage regulator for low-side gate driver; connect 1-µF
capacitor to GND
38
VCPH
P
High-side gate driver regulator
Internal voltage regulator for high-side gate driver; connect 2.2-µF
capacitor to PVDD
39
CP2H
P
40
CP2L
P
Charge pump flying capacitor
Flying capacitor for charge pump; connect 0.047-µF capacitor
between CP2H and CP2L
PPAD
External Components
COMPONENT
PIN 1
PIN 2
RECOMMENDED
CPVDD
PVDD
GND
4.7-µF ceramic capacitor rated for 50 V
CAVDD
AVDD
GND
1.0-µF ceramic capacitor rated for 6.3 V
CDVDD
DVDD
GND
1.0-µF ceramic capacitor rated for 6.3 V
CVCPH
VCPH
PVDD
2.2-µF ceramic capacitor rated for 16 V
CVCP_LSD
VCP_LSD
GND
1.0-µF ceramic capacitor rated for 16 V
CCP1
CP1H
CP1L
0.047-µF ceramic capacitor rated for 16 V
CCP2
CP2H
CP2L
0.047-µF ceramic capacitor rated for 16 V
CVREG
VREG
GND
1.0-µF ceramic capacitor rated for 6.3 V
RVDRAIN
VDRAIN
PVDD
100-Ω series resistor
RnFAULT
(1)
4
nFAULT
VCC
(1)
1 to 10 kΩ pulled up the MCU power supply
VCC is not a pin on the DRV8305, but a VCC supply voltage pullup is required for open-drain output nFAULT
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
Power supply voltage (PVDD)
(1)
MIN
MAX
UNIT
–0.3
45
V
Power supply voltage ramp rate (VM)
0
2
V/µs
–0.3
PVDD + 12
V
High side gate driver voltage (GHA, GHB, GHC)
–3
57
V
Low-side gate driver voltage (GHA, GHB, GHC)
–2
12
V
High side gate driver source pin voltage (SHA, SHB, SHC)
–5
45
V
Low-side gate driver source pin voltage (SLA, SLB, SLC)
–3
5
V
Internal phase clamp pin voltage difference {(GHA-SHA), (GHB-SHB), (GHC-SHC),
(GLA-SLA), (GLB-SLB), (GLC-SLC)}
–0.3
15
V
Drain pin voltage drain (VDRAIN)
–0.3
45
Max source current (VDRAIN) – limit current with external series resistor
–20
Charge pump voltage (CP1H,CP1L, CP2L,CP2H, VCPH, VCP_LSD)
V
mA
Max sink current (VDRAIN)
2
mA
Voltage difference between supply and VDRAIN (PVDD-VDRAIN)
–10
10
V
Control pin voltage range (INHA, INLA, INHB, INLB, INHC, INLC, EN_GATE, SCLK,
SDI, SCS, SDO, nFAULT, PWRGD)
–0.3
5.5
V
7
mA
–0.3
45
V
1
mA
–2
5
V
–0.3
5.5
V
100
µA
Open drain pins skink current (nFAULT, PWRGD)
Wake pin voltage (WAKE)
Wake pin sink current (WAKE) – limit with external series resistor
Sense amp voltage (SPA, SNA, SPB, SNB, SPC, SNC)
Externally applied reference voltage (VREG) – when vreg_vref = 1
Externally applied reference sink current (VREG) – when vreg_vref = 1
Operating ambient temperature, TA
–40
125
°C
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
VPVDD
Power supply voltage range
4.4
45
(1)
VPVDD
Power supply voltage range for voltage regulator operation
4.3
45
(2)
V
VPVDDRAMP
Power supply voltage ramp rate (PVDD = 0 to 20 V rising <3-mA pin sink
current)
1
V/µs
VPVDD-SH_X
Total voltage drop from PVDD to SH_X pins
4.5
V
ISRC_VCPH
External load on VCPH pin (current limit resistor in series to load)
10
mA
CO_OPA
Maximum external capacitive load on shunt amplifier (no external resistor on
output, excluding internal pin capacitance)
60
pF
InFAULT
nFAULT sink current (VnFAULT = 0.3 V)
Fgate
Operating switching frequency of gate driver
IGATE
Total average gate driver current (HS + LS) – charge pump limited
TA
Operating ambient temperature
(1)
(2)
-40
7
mA
200
kHz
30
mA
125
°C
IC is fully functional and tested in the range 4.4 to 45 V.
Subject to thermal dissipation limits.
6.4 Thermal Information
DRV8305
THERMAL METRIC
(1)
PHP (HTQFP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
26.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
12.9
°C/W
RθJB
Junction-to-board thermal resistance
7.6
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
7.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.6
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
PVDD = 4.4 to 45 V, TA = 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (PVDD, DVDD, AVDD)
4.4
45
4.3
45
VPVDD
PVDD operating voltage
IPVDD_Operating
PVDD operating supply
current
EN_GATE = enabled; LDO reg =
enabled at no load; outputs HiZ
15
IPVDD_Standby
PVDD standby supply
current
EN_GATE = disabled; LDO reg =
enabled at no load
4
7
mA
IPVDD_Sleep
PVDD sleep supply current
EN_GATE = disabled; LDO reg =
disabled; ready for WAKE
60
175
μA
5.15
VAVDD
Internal regulator voltage
VDVDD
Internal regulator voltage
VREG (voltage regulator) operational
PVDD = 5.3 to 45 V
4.85
5
PVDD = 4.4 to 5.3 V
PVDD –
0.22
PVDD
V
mA
V
3.3
V
VOLTAGE REGULATOR (VREG)
PVDD = 5.3 to 45 V
VVREG
VREG DC output voltage
PVDD = 4.3 to 5.3 V; 5-V regulator
PVDD = 4.3 to 5.3 V; 3.3-V regulator
VLineReg
Line regulation ΔVOUT/ΔVIN
5.3 V ≤ VIN ≤ 12 V; IO = 1 mA
VLoadReg
Load regulation
ΔVOUT/ΔIOUT
100 µA ≤ IOUT ≤ 50 mA
Vdo
Dropout voltage
VSET –
(0.03 ×
VSET)
VSET
PVDD – 0.4
V
VSET –
(0.03 ×
VSET)
VSET +
(0.03 ×
VSET)
PVDD
V
VSET
VSET +
(0.03 ×
VSET)
10
30
mV
30
mV
IOUT = 100 µA; 3.3 V
0.05
0.1
IOUT = 50 mA; 3.3 V
0.2
0.4
V
LOGIC-LEVEL INPUTS (INHA, INLA, INHB, INLB, INHC, INLC, EN_GATE, SCLK, nSCS)
VIL
Input logic low voltage
VIH
Input logic high voltage
RPD
Internal pull down resistor
0
0.8
2
To GND
5
100
V
V
kΩ
CONTROL OUTPUTS (nFAULT, SDO, PWRGD)
VOL
Output logic low voltage
VOH
Output logic high voltage
IOH
Output logic high leakage
IO = 5 mA
0.5
V
–1
1
μA
2.4
VO = 3.3 V
V
HIGH VOLTAGE TOLERANT LOGIC INPUT (WAKE)
VIL_WAKE
Output logic low voltage
1.1
1.41
V
VIH_WAKE
Output logic high voltage
1.42
1.75
V
GATE DRIVE OUTPUT (GHA, GHB, GHC, GLA, GLB, GLC)
VGHS
High side gate driver Vgs
voltage
VPVDD = 8 to 45 V; IGATE < 30 mA, CVCPH
= 2.2 μF, CCP1/CP2 = 0.047 μF, CVCP_LSD
= 1 μF
9
VPVDD = 5.5 to 8 V; IGATE < 6 mA, CVCPH
= 2.2 μF, CCP1/CP2 = 0.047 μF, CVCP_LSD
= 1 μF
7.2
9
5
7.2
VPVDD = 4.4 to 5.5 V; IGATE < 6 mA,
CVCPH = 2.2 μF, CCP1/CP2 = 0.047 μF,
CVCP_LSD = 1 μF
10
10.5
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, TA = 25°C, unless specified under test condition
PARAMETER
Low-side gate driver Vgs
voltage
VGLS
TEST CONDITIONS
MIN
TYP
MAX
VPVDD = 8 to 45 V; IGATE < 30 mA, CVCPH
= 2.2 μF, CCP1/CP2 = 0.047 μF, CVCP_LSD
= 1 μF
9
10
10.5
VPVDD = 5.5 to 8 V; IGATE < 6 mA, CVCPH
= 2.2 μF, CCP1/CP2 = 0.047 μF, CVCP_LSD
= 1 μF
9
10.5
VPVDD = 4.4 to 5.5 V; IGATE < 6 mA,
CVCPH = 2.2 μF, CCP1/CP2 = 0.047 μF,
CVCP_LSD = 1 μF
8
9
UNIT
V
PEAK CURRENT DRIVE TIMES
Peak sink or source current
drive time
tDRIVE
TDRIVEP = 00; TDRIVEN = 00
220
TDRIVEP = 01; TDRIVEN = 01
440
TDRIVEP = 10; TDRIVEN = 10
880
TDRIVEP = 11; TDRIVEN = 11
1660
ns
HIGH SIDE (GHA, GHB, GHC) PEAK CURRENT GATE DRIVE
IDRIVEP_HS
High side peak source
current
IDRIVEP_HS = 0000
0.01
IDRIVEP_HS = 0001
0.02
IDRIVEP_HS = 0010
0.03
IDRIVEP_HS = 0011
0.04
IDRIVEP_HS = 0100
0.05
IDRIVEP_HS = 0101
0.06
IDRIVEP_HS = 0110
0.07
IDRIVEP_HS = 0111
0.125
IDRIVEP_HS = 1000
0.25
IDRIVEP_HS = 1001
0.5
IDRIVEP_HS = 1010
0.75
IDRIVEP_HS = 1011
IDRIVEN_HS
8
High side peak sink current
1
IDRIVEP_HS = 1100, 1101, 1110, 1111
0.05
IDRIVEN_HS = 0000
0.02
IDRIVEN_HS = 0001
0.03
IDRIVEN_HS = 0010
0.04
IDRIVEN_HS = 0011
0.05
IDRIVEN_HS = 0100
0.06
IDRIVEN_HS = 0101
0.07
IDRIVEN_HS = 0110
0.08
IDRIVEN_HS = 0111
0.25
IDRIVEN_HS = 1000
0.5
IDRIVEN_HS = 1001
0.75
IDRIVEN_HS = 1010
1
IDRIVEN_HS = 1011
1.25
IDRIVEN_HS = 1100, 1101, 1110, 1111
0.06
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, TA = 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW SIDE (GLA, GLB, GLC) PEAK CURRENT GATE DRIVE
IDRIVEP_LS
Low-side peak source
current
IDRIVEP_HS = 0000
0.01
IDRIVEP_HS = 0001
0.02
IDRIVEP_HS = 0010
0.03
IDRIVEP_HS = 0011
0.04
IDRIVEP_HS = 0100
0.05
IDRIVEP_HS = 0101
0.06
IDRIVEP_HS = 0110
0.07
IDRIVEP_HS = 0111
0.125
IDRIVEP_HS = 1000
0.25
IDRIVEP_HS = 1001
0.5
IDRIVEP_HS = 1010
0.75
IDRIVEP_HS = 1011
1
IDRIVEP_HS = 1100, 1101, 1110, 1111
A
0.05
LOW SIDE (GLA, GLB, GLC) PEAK CURRENT GATE DRIVE
IDRIVEN_LS
Low-side peak sink current
IDRIVEN_HS = 0000
0.02
IDRIVEN_HS = 0001
0.03
IDRIVEN_HS = 0010
0.04
IDRIVEN_HS = 0011
0.05
IDRIVEN_HS = 0100
0.06
IDRIVEN_HS = 0101
0.07
IDRIVEN_HS = 0110
0.08
IDRIVEN_HS = 0111
0.25
IDRIVEN_HS = 1000
0.5
IDRIVEN_HS = 1001
0.75
IDRIVEN_HS = 1010
1
IDRIVEN_HS = 1011
1.25
IDRIVEN_HS = 1100, 1101, 1110, 1111
0.06
A
GATE PULL DOWN, MOTOR OFF STATE (BRIDGE IN HI-Z)
RSLEEP_PD
Gate pull down resistance,
SLEEP, under voltage and
sleep mode
2 V < PVDD < PVDD_UVLO2
GHX to GND; GLX to GND
RSTANDBY_PD
Gate pull down resistance,
STANDBY, standby mode
(Parallel with ISTANDBY_PD)
IOPERATING_PD
Gate pull down current,
OPERATING, operating
mode
2000
Ω
PVDD > PVDD_UVLO2; EN_GATE =
low;
GHX to GND; GLX to GND
750
Ω
PVDD > PVDD_UVLO2; EN_GATE =
high;
GHX to SHX; GLX to SLX
50
mA
mA
GATE PULL DOWN, MOTOR ON STATE (IDRIVE/tdrive)
IHOLD
Gate pull down current,
holding
PVDD > PVDD_UVLO2; EN_GATE =
high;
GHX to SHX; GLX to SLX
50
IPULLDOWN
Gate pull down current,
strong
PVDD > PVDD_UVLO2; EN_GATE =
high;
GHX to SHX; GLX to SLX
1.25
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, TA = 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GATE TIMING
tpd_lf-O
Positive input falling to
GHS_x falling
PVDD = 12 V; CL = 1 nF; 50% to 50%
200
ns
tpd_lr-O
Positive input rising to
GHS_x rising
PVDD = 12 V; CL = 1 nF; 50% to 50%
200
ns
td_min
Minimum dead time after
hand shaking
280
ns
Dead time in addition to
td_min
tdtp
DEAD_TIME = 000
35
DEAD_TIME = 001
52
DEAD_TIME = 010
88
DEAD_TIME = 011
440
DEAD_TIME = 100
880
DEAD_TIME = 101
1760
DEAD_TIME = 110
3520
DEAD_TIME = 111
5280
ns
tPD_MATCH
Propagation delay matching
between high-side and lowside
50
ns
tDT_MATCH
Dead time matching
50
ns
CURRENT SHUNT AMPLIFIER
GCSA
Current sense amplifier gain
Current sense amplifier gain
error
GERR
tSETTLING
Current sense amplifier
settling time
GAIN_CSx = 00
10
GAIN_CSx = 01
20
GAIN_CSx = 10
40
GAIN_CSx = 11
80
Input differential > 0.025 V
–3%
V/V
3%
Settling time to 1%; no blanking; TJ = 40 – 150°C, GCSA = 10; Vstep = 0.46 V
300
Settling time to 1%; no blanking; TJ = 40 – 150°C, GCSA = 20; Vstep = 0.46 V
600
Settling time to 1%; no blanking; TJ = 40 – 150°C, GCSA = 40; Vstep = 0.46 V
1.2
Settling time to 1%; no blanking; TJ = 40 – 150°C, GCSA = 80; Vstep = 0.46 V
2.4
ns
µs
VIOS
DC input offset
GCSA = 10; input shorted; RTI
–4
VVREF_ERR
Reference buffer error (DC)
Internal or external VREF
VDRIFTOS
Input offset error drift
GCSA = 10; input shorted; RTI
IBIAS
Input bias current
VIN_COM = 0; SOx open
IOFFSET
Input bias current offset
IBIAS (SNx-SPx); VIN_COM = 0; SOx
open
VIN_COM
Common input mode range
–0.15
0.15
V
VIN_DIFF
Differential input range
-0.48
0.48
V
CMRR
Common mode rejection
ration
–2%
µV/C
100
1
External input resistance matched; DC;
GCSA = 10
60
80
External input resistance matched; 20
kHz; GCSA = 10
60
80
µA
µA
dB
DC (<120 Hz); GCSA = 10
150
Power supply rejection ratio
VSWING
Output voltage swing
PVDD > 5.3 V
0.3
VSLEW
Output slew rate
GCSA = 10; RL = 0 Ω; CL = 60 pF
5.2
20 kHz; GCSA = 10
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mV
2%
10
PSRR
10
4
dB
90
4.7
10
V
V/µs
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, TA = 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
IVO
Output short circuit current
SOx shorted to ground
UGB
Unity gain bandwidth
product
GCSA = 10
MIN
TYP
MAX
UNIT
20
mA
2
MHz
VOLTAGE PROTECTION
VAVDD_UVLO
AVDD undervoltage Fault
Relative to GND
3.3
3.5
VREG_UV_LEVEL = 00
VSET-10%
VREG_UV_LEVEL = 01
VSET-20%
VREG_UV_LEVEL = 10
VSET-30%
VREG_UV_LEVEL = 11
VSET-30%
VVREG_UV
VREG undervoltage Fault
VVREG_UV_DGL
VREG undervoltage monitor
deglitch time
VPVDD_UVFL
Undervoltage protection
Warning, PVDD
VPVDD_UVLO1
Undervoltage protection
lockout, PVDD
PVDD falling
4.1
PVDD rising
4.3
VPVDD_UVLO2
Undervoltage protection
Fault, PVDD
PVDD falling
4.2
4.4
PVDD rising
4.4
4.6
VPVDD_OVFL
Overvoltage protection
Warning, PVDD
PVDD falling
33.5
36
PVDD rising
32.5
35
VVCPH_UVFL
Charge pump under voltage
protection Warning, VCPH
VVCPH_UVLO
Charge pump under voltage
protection Fault, VCPH
VVCP_LSD_UVLO
1.5
2
PVDD falling
7.7
8.1
PVDD rising
7.9
8.3
Relative to PVDD
8
V
V
µs
V
V
V
V
V
Relative to PVDD, SET_VCPH_UV = 0
4.5
4.9
Relative to PVDD, SET_VCPH_UV = 1
4.2
4.6
Low-side charge pump
under voltage Fault,
VCP_LSD
Relative to PVDD
6.4
7.5
V
VVCPH_OVLO
Charge pump over voltage
protection FAULT, VCPH
Relative to PVDD
14
18
V
VVCPH_OVLO_ABS
Charge pump over voltage
protection FAULT, VCPH
Relative to GND
V
60
V
TEMPERATURE PROTECTION
OTW_CLR
Junction temperature for
resetting over temperature
(OT) warning (1)
140
°C
OTW_SET/
OTSD_CLR
Junction temperature for
over temperature warning
and resetting over
temperature shutdown (1)
155
°C
OTSD_SET
Junction temperature for
over temperature
shutdown (1)
175
°C
TEMPFLAG1
Junction temperature flag
setting 1 (no warning) (1)
105
°C
TEMPFLAG2
Junction temperature flag
setting 2 (no warning) (1)
125
°C
TEMPFLAG3
Junction temperature flag
setting 3 (no warning) (1)
135
°C
TEMPFLAG4
Junction temperature flag
setting 4 (no warning) (1)
175
°C
(1)
Specified by design and characterization data
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, TA = 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PROTECTION CONTROL
tpd,E-L
Delay, error event to all
gates low
tpd,E-SD
Delay, error event to
nFAULTx low
24
µs
7
µs
FET CURRENT PROTECTION (VDS SENSING)
VDS_TRIP
tVDS
tBLANK
12
Drain-source voltage
protection limit
VDS sense deglitch time
VDS sense blanking time
VDS_LEVEL = 00000
0.06
VDS_LEVEL = 00001
0.068
VDS_LEVEL = 00010
0.076
VDS_LEVEL = 00011
0.086
VDS_LEVEL = 00100
0.097
VDS_LEVEL = 00101
0.109
VDS_LEVEL = 00110
0.123
VDS_LEVEL = 00111
0.138
VDS_LEVEL = 01000
0.155
VDS_LEVEL = 01001
0.175
VDS_LEVEL = 01010
0.197
VDS_LEVEL = 01011
0.222
VDS_LEVEL = 01100
0.25
VDS_LEVEL = 01101
0.282
VDS_LEVEL = 01110
0.317
VDS_LEVEL = 01111
0.358
VDS_LEVEL = 10000
0.403
VDS_LEVEL = 10001
0.454
VDS_LEVEL = 10010
0.511
VDS_LEVEL = 10011
0.576
VDS_LEVEL = 10100
0.648
VDS_LEVEL = 10101
0.73
VDS_LEVEL = 10110
0.822
VDS_LEVEL = 10111
0.926
VDS_LEVEL = 11000
1.043
VDS_LEVEL = 11001
1.175
VDS_LEVEL = 11010
1.324
VDS_LEVEL = 11011
1.491
VDS_LEVEL = 11100
1.679
VDS_LEVEL = 11101
1.892
VDS_LEVEL = 11110
2.131
VDS_LEVEL = 11111
2.131
TVDS = 00
0
TVDS = 01
1.75
TVDS = 10
3.5
TVDS = 11
7
TBLANK = 00
0
TBLANK = 01
1.75
TBLANK = 10
3.5
TBLANK = 11
7
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µs
µs
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Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, TA = 25°C, unless specified under test condition
PARAMETER
tVDS_PULSE
TEST CONDITIONS
MIN
TYP
nFAULT pin reporting pulse
stretch length for VDS event
MAX
UNIT
56
µs
2
V
PHASE SHORT PROTECTION
VSNSOCP_TRIP
Phase short protection limit
Fixed voltage
6.6 SPI Timing Requirements (Slave Mode Only)
MIN
tSPI_READY
SPI read after power on
tCLK
Minimum SPI clock period
tCLKH
PVDD > VPVDD_UVLO1
NOM
MAX
5
10
UNIT
ms
100
ns
Clock high time
40
ns
tCLKL
Clock low time
40
ns
tSU_SDI
SDI input data setup time
20
ns
tHD_SDI
SDI input data hold time
30
tD_SDO
SDO output data delay time, CLK high to SDO valid
tHD_SDO
SDO output hold time
40
ns
tSU_SCS
SCS setup time
50
ns
tHD_SCS
SCS hold time
50
ns
tHI_SCS
SCS minimum high time before SCS active low
tACC
SCS access time, SCS low to SDO out of high impedance
10
ns
tDIS
SCS disable time, SCS high to SDO high impedance
10
ns
ns
CL = 20 pF
20
400
ns
ns
Figure 1. SPI Slave Mode Timing Definition
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Figure 2. SPI Slave Mode Timing Diagram
6.7 Typical Characteristics
6
30
5.9
25
T A = 40°C
S u p p ly C u r r e n t ( m A )
S u p p ly C u r r e n t ( m A )
5.8
T A = 25°C
5.7
T A = 125°C
5.6
5.5
5.4
20
15
10
5.3
T A = 40°C
5
T A = 25°C
5.2
T A = 125°C
5.1
0
0
10
20
30
40
50
PVDD (V)
0
10
20
30
40
PVDD (V)
D001
Figure 3. Standby Current
50
D002
Figure 4. Operating Current
200
12
180
10
140
8
120
V C P H (V )
S u p p ly C u r r e n t ( m A )
160
100
80
6
4
60
40
T A = 40°C
T A = 40°C
2
T A = 25°C
20
T A = 25°C
T A = 125°C
T A = 125°C
0
0
0
10
20
30
PVDD (V)
40
50
0
D003
Figure 5. Sleep Current
14
10
20
30
PVDD (V)
40
50
D004
Figure 6. VCPH Voltage
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7 Detailed Description
7.1 Overview
The DRV8305 is a 4.4-V to 45-V gate driver IC for three-phase motor driver applications. This device reduces
external component count by integrating three half-bridge drivers, three current shunt amplifiers, and a LDO. The
DRV8305 provides overcurrent, overtemperature, and undervoltage protection. Fault conditions are indicated by
the nFAULT pin and specific fault indication can be read back from the SPI registers.
Adjustable dead time control and peak gate drive current allows for finely tuning the switching of the external
MOSFETs. Internal hand-shaking is used to prevent FET shoot through.
VDS sensing of the external MOSFETs allows for the DRV8305 to detect overcurrent conditions and respond
appropriately. Individual MOSFET overcurrent conditions are reported through the SPI status registers.
There are three versions of DRV8305 with separate part numbers:
• DRV8305N – VREG pin is used as input that supplies the reference for the CSA and SPI.
• DRV83053 – VREG is a 3.3-V LDO output pin.
• DRV83055 – VREG is a 5.0-V LDO output pin.
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DVDD
AVDD
CP1L
CP1H
CP2L
CP2H
VCP_LSD
AVDD
DVDD
7.2 Functional Block Diagram
VCP_LSD
VCPH
DVDD
LDO
AVDD
LDO
Low Side
Gate Drive
LDO
VCPH
High Side Gate Drive
2-Stage Charge Pump
PVDD
VREG
WAKE
PVDD
VREG
VDRAIN
VREG
LDO
VDRAIN
PWRGD
VDRAIN
VCPH
GHA
+
HS
VDS
-
SHA
EN_GATE
VCP_LSD
GLA
+
INHA
LS
VDS
-
SLA
INLA
Phase A Pre-Driver
INHB
INLB
VDRAIN
Digital
Inputs
and
Outputs
PVDD
VCPH
GHB
+
HS
VDS
-
SHB
Core Logic
INHC
VCP_LSD
GLB
+
INLC
LS
VDS
Control
-
SLB
nFAULT
Configuration
Phase B Pre-Driver
VDRAIN
PVDD
VCPH
GHC
Timing
+
HS
VDS
SCLK
-
SHC
Protection
VCP_LSD
nSCS
GLC
SPI
+
LS
VDS
SDI
SDO
-
SLC
Thermal
Sensor
Voltage
Monitoring
SO1
Phase C Pre-Driver
VREG
Current
Sense
Amplifier 1
Ref/k
VREG
VREG
Ref/k
GND
16
Current
Sense
Amplifier 2
Ref/k
GND
SP1
SN2
AVDD
SO2
SO3
SN1
AVDD
SP2
SN3
AVDD
Current
Sense
Amplifier 3
SP3
PowerPAD
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7.3 Feature Description
7.3.1 Three-Phase Gate Driver
The DRV8305 provides three half-bridge drivers, each driver is capable of driving two N-type MOSFETs, one for
the high side and one for the low side.
Both the high side (GHX to SHX) and the low side (GLX to SLX) are implemented as floating gate drivers.
The gate driver uses a charge pump architecture which enables an extended voltage operating range to support
a variety of application requirements.
7.3.2 Operating Modes
The DRV8305 can be operated in three modes, to support various commutation schemes.
• Table 1 shows six independent PWM inputs with the truth table.
Table 1. 6-PWM Truth Table
•
INHX
INLX
GHX
GLX
1
1
1
L
L
0
H
L
0
1
L
H
0
0
L
L
Three independent high-side PWM inputs (low-side complimentary PWMs generated internally).
In this mode all activity on INLA, INLB and INLC is ignored.
Table 2. 3-PWM Truth Table
•
INHX
INLX
GHX
1
X
H
GLX
L
0
X
L
H
One single PWM that uses internally stored 6-step block commutation tables. In this mode of operation,
DRV8305 can be operated using a single PWM sourced from a low cost microcontroller. The PWM is applied
on pin PWM_IN (INHA) from the microcontroller along with three GPIO pins PHC_0 (INLA), PHC_1 (INHB),
PHC_2 (INLB) that serve to set the bits of a three bit register. The PWM may be operated from 0-100% duty
cycle. The three bit register is used to select the state of each of the phases for a total of eight states
including an align and stop state. The 1-PWM mode tables will use all the applicable settings from the control
registers as set up by the user.
An additional and optional GPIO (INHC) can be used to facilitate the insertion of dwell states or phase current
overlap states between the six commutation steps. This may be used to reduce acoustic noise and improve
motion through the reduction of abrupt current direction changes when switching between states. INHC must
be high when the states are changed and the dwell state will exist until INHC is taken low. If the dwell states
are not being used, the INHC pin can be simply tied low.
In this mode all activity on INLC is always ignored.
The commutation tables ( Table 3 and Table 4) may be selected through the appropriate SPI register.
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Table 3. 1-PWM Active Freewheeling
INLA : INHB : INLB : INHC
AH
AL
BH
BL
CH
CL
AB
0110
PWM
!PWM
LOW
HIGH
LOW
LOW
AB_CB
0101
PWM
!PWM
LOW
HIGH
PWM
!PWM
CB
0100
LOW
LOW
LOW
HIGH
PWM
!PWM
CB_CA
1101
LOW
HIGH
LOW
HIGH
PWM
!PWM
CA
1100
LOW
HIGH
LOW
LOW
PWM
!PWM
CA_BA
1001
LOW
HIGH
PWM
!PWM
PWM
!PWM
BA
1000
LOW
HIGH
PWM
!PWM
LOW
LOW
BA_BC
1011
LOW
HIGH
PWM
!PWM
LOW
HIGH
BC
1010
LOW
LOW
PWM
!PWM
LOW
HIGH
BC_AC
0011
PWM
!PWM
PWM
!PWM
LOW
HIGH
AC
0010
PWM
!PWM
LOW
LOW
LOW
HIGH
AC_AB
0111
PWM
!PWM
LOW
HIGH
LOW
HIGH
Align
1110
PWM
!PWM
LOW
HIGH
LOW
HIGH
Stop
0000
LOW
LOW
LOW
LOW
LOW
LOW
CH
CL
Table 4. 1-PWM Diode Freewheeling
INLA : INHB : INLB : INHC
AH
AL
BH
BL
AB
0110
PWM
LOW
LOW
HIGH
LOW
LOW
AB_CB
0101
PWM
LOW
LOW
HIGH
PWM
LOW
CB
0100
LOW
LOW
LOW
HIGH
PWM
LOW
CB_CA
1101
LOW
HIGH
LOW
HIGH
PWM
LOW
CA
1100
LOW
HIGH
LOW
LOW
PWM
LOW
CA_BA
1001
LOW
HIGH
PWM
LOW
PWM
LOW
BA
1000
LOW
HIGH
PWM
LOW
LOW
LOW
BA_BC
1011
LOW
HIGH
PWM
LOW
LOW
HIGH
BC
1010
LOW
LOW
PWM
LOW
LOW
HIGH
BC_AC
0011
PWM
LOW
PWM
LOW
LOW
HIGH
AC
0010
PWM
LOW
LOW
LOW
LOW
HIGH
AC_AB
0111
PWM
LOW
LOW
HIGH
LOW
HIGH
Align
1110
PWM
LOW
LOW
HIGH
LOW
HIGH
Stop
0000
LOW
LOW
LOW
LOW
LOW
LOW
7.3.3 Charge Pump
A regulated triple charge pump scheme is used to create sufficient VGS to drive standard FETs under low voltage
operation.
The high-side FETs are directly driven by the tripler charge pump output while the low-side FETs are driven by a
voltage that is internally regulated but derived from the tripler charge pump. This allows both the high side and
low side to maintain sufficient VGS through low voltage transients. This topology also supports 100% duty cycle
operation.
Between 4.4 to 18 V the charge pump regulates the voltage in tripler mode; beyond 4.4 to 18 V, it switches over
to doubler mode until the operating max voltage. The charge pump is monitored for undervoltage and
overvoltage conditions to prevent underdriven or overdriven FET conditions.
7.3.4 Gate Driver Architecture
The DRV8305 gate driver is a complimentary push-pull topology for both the high-side and the low-side drivers.
The peak currents for the drivers are adjustable; their benefits are described in detail in the Slew Rate/Slope
Control section.
18
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The gate driver is implemented as constant current sources for up to 80 mA (sink)/70 mA (source) currents in
order to maintain the accuracy required for precise slew rate control. Beyond that, resistors are switched to
create the desired settings up to 1.25 A (sink)/1 A (source).
7.3.5 IDRIVE/TDRIVE
The DRV8305 gate driver has an integrated state machine (TDRIVE/IDRIVE scheme) to protect against high
current events on the outputs (shorts or inadvertent clamp activation) and also dV/dt turn on due to switching on
the phase nodes.
When changing the state of the gate driver, the peak current (source or sink, IDRIVE) is applied for a fixed period
of time (TDRIVE) until the gate capacitances are charged or discharged completely. After this time has expired, a
fixed current source of IHOLD is used to hold the gate at the desired state (pulled up or pulled down).
INHX
GHX (V)
tDRIVEP
tDRIVEN
IDRIVEP
IHOLD
GHX (mA)
-IHOLD
-IPULLDOWN
-IPULLDOWN
IDRIVEN
tDEAD
`
IDRIVEP
GLX (mA)
IHOLD
IHOLD
- IHOLD
-IPULLDOWN
IDRIVEN
tDRIVEN
tDRIVEP
GLX
INLX
Figure 7. TDRIVE/IDRIVE Waveforms
This fixed TDRIVE time ensures that under abnormal circumstances like a short on the FET gate, or the
inadvertent turning on of a FET VGS clamp, the high peak current through the DRV8305 gate drivers is limited to
the energy of the peak current during TDRIVE. Limiting this energy helps to prevent the gate driver from
damage.
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Select a TDRIVE time that is longer than the time needed to charge or discharge the gate capacitances. IDRIVE
and TDRIVE are selected based on the size of external FETs used and the desired rise and fall times. These
registers must be configured so that the FET gates are charged completely during TDRIVE. If IDRIVE and
TDRIVE are too low for a given FET, then the FET may not turn on completely. TI suggests to adjust these
values in-system with the required external FETs to determine the best possible setting for any application.
Note that TDRIVE will not increase the PWM time and will simply terminate if a PWM command is received while
it is active. A good starting point is to select a TDRIVE that is about 2× longer than the external FET switching
rise (turn ON) and fall (turn OFF) times.
The IDRIVE/TDRIVE state machine protects against dV/dt turn on of a FET due to switching of the phase nodes.
A strong pulldown current source of value IPULLDOWN is switched on between (GHX to SHX) or (GLX to SLX),
every time an opposing FET is commanded to turn on.
7.3.6 Slew Rate/Slope Control
Control of the FET VDS rise and fall times during the Miller region of the FET is one of the most important
parameters for optimizing emitted radiations and power. The rise and fall times also influence the energy and
duration of the diode recovery inductive spikes and also dV/dt turn on of the LS FET.
The ability of a driver to control the rise and fall times across the entire range of gate drive temperature, voltage,
and process variation is essential to design robust systems. The key control knob is the ability to turn on and turn
off the external FET with the least amount of variation.
The DRV8305 uses temperature compensated constant current sources up to 80-mA (sink) and 70-mA (source)
current. The current source architecture helps eliminate the temperature, process, and load-dependent variation
associated with internal and external series limiting resistors.
For higher currents, internal series resistors are used to minimize the power losses associated with mirroring
such large currents.
The 12 settings that are available on the DRV8305 allow the user to optimize the system using only SPI
commands. This flexibility allows the system designer to tune the performance of the driver for different operating
conditions through software alone.
The slew rate settings may be set separately for source and sink values and can also be set separately for the
high-side FETs (the high sides of all three phases share the same setting) and the low-side FETs (the low sides
of all three phases share the same settings)
7.3.7 Current Shunt Amplifiers
The DRV8305 includes three high performance low-side current shunt amplifiers for accurate current
measurement. The current amplifiers provide output bias up to 2.5 V to support bidirectional current sensing.
Current shunt amplifier has following features:
• Each of the three current sense amplifiers can be programmed and calibrated independently.
• The independent current shunt amplifiers may be used either for sensing current through individual phase
shunt resistors or the total current delivered to the motor through a single shunt resistor.
• Programmable gain: four gain settings through SPI command
• Internally or externally provided reference voltage to set output bias for amplifiers. Reference voltage is
internally sourced from DRV8305 voltage regulator VREG, if also used to power microcontroller. It can
alternatively be applied externally on the VREG pin.
• Programmable output bias scaling. The scaling factor k can be programmed through SPI to be equal to, half
or a fourth of the reference voltage.
• Programmable blanking time (delay) of the amplifier outputs. The blanking time is implemented from any
rising or falling edge (any of the outputs) of the internal gate driver gate signals. The blanking time is applied
to all three current sense amplifiers equally. In case the current sense amplifiers are already being blanked
when another gate driver rising or falling edge is seen, the blanking interval will be restarted at the edge.
Note that the blanking time options do not include delay from internal amplifier loading or delays from the
trace or component loads on the amplifier output. The programmable blanking time may be overridden to
have no delay (default value).
• Minimize DC offset and drift through temperature with DC calibrating through SPI command. When DC
calibration is enabled, device will short input of current shunt amplifier and disconnect the load. DC calibrating
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can be done at anytime, even when the FET is switching because the load is disconnected. For best result,
perform the DC calibrating during switching off period when no load is present to reduce the potential noise
impact to the amplifier.
The output of current shunt amplifier can be calculated as:
VVREF
VO
G u SNX SPX
k
where
•
•
•
•
VREF is the reference voltage.
G is the gain of the amplifier.
k = 2, or 4
SNx and SPx are the inputs of channel x. SPx should connect to resistor ground for the best common mode
rejection.
(1)
Figure 8 shows current amplifier simplified block diagram.
S4
400
DC _ CAL(SPI)
SN
200 kO
S3
100 kO
S2
50 kO
S1
5 kO
AVDD
_
100 O
S5
SO
5 kO
+
SP
50 kO
S1
100 kO
S2
200 kO
S3
400 kO
S4
DC _ CAL(SPI)
VREF/k
VREF
_
AVDD
k = 2, 4
+
Figure 8. Current Shunt Amplifier Simplified Block Diagram
7.3.8 Internal Regulators (DVDD and AVDD)
The DRV8305 has two internal regulators, DVDD and AVDD, that power internal circuits. These regulators
cannot be used to drive external loads and may not be supplied externally.
DVDD is the voltage regulator for the internal logic circuits and is maintained at a value of about 3.3 V through
the entire operating range of the device. DVDD is derived from the PVDD supply.
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AVDD is the voltage regulator that provides the voltage rail for the internal analog circuit blocks including the
current sense amplifiers. AVDD is derived from the PVDD voltage supply.
Because the allowed operating range of the device permits operation below the nominal value of AVDD, this
regulator operates in two regimes: namely a linear regulating regime and a dropout region. In the dropout region,
the AVDD will simply track the PVDD voltage minus a voltage drop.
If the device is expected to operate within the dropout region, take care while selecting current sense amplifier
components and settings to accommodate this reduced voltage rail.
7.3.9 Voltage Regulator Output for Driving External Loads (VREG)
The DRV8305 integrates an LDO voltage regulator (VREG) that is dedicated for driving external loads like an
MCU directly. The two versions of the device provide different voltages: DRV83053 provides 3.3 V, DRV83055
provides 5.0 V. Because the user can supply microcontroller and other system power from the DRV8305, the
user does not need to add an external regulator IC for system power.
The DRV8305 voltage regulator is standalone, uncommitted, and is not used internally.
The DRV8305 voltage regulator also features a PWRGD pin to protect against brownouts on externally driven
devices. The PWRGD pin is often tied to a reset pin on a microcontroller to ensure that the microcontroller is
always reset when the voltage is outside of its recommended operation area.
When the voltage output of the LDO drops or exceeds the set threshold (programmable).
• The PWRGD pin will go low for a period of 64 µs.
• After the 64-µs period has expired, the LDO voltage will be checked and PWRGD will be held low until the
LDO voltage has recovered.
The voltage regulator also has undervoltage protection implemented for both the input voltage (PVDD) and
output voltage (VREG).
7.3.10 Protection Features
Fault / Warning Classes and Recovery summarizes the protection features, fault responses, and recovery
sequences.
7.3.10.1 Fault and Protection Handling
The DRV8305 handles fault (latched fault) and warnings (unlatched faults) separately. Both latched and
unlatched faults are reported in status registers and can be read through SPI.
• A latched nFAULT pin indicates an error event has occurred that has caused part of the gate driver to shut
down and force outputs to a safe state (external FETs in high impedance).
– A latched fault is indicated by the nFAULT pin going low (and staying low) and reporting the details of the
fault in the status registers (0x02 and 0x03). The appropriate recovery sequence must be performed in
order to reset the latched fault. In addition, the register (0x01) contains a single status bit if any latched
faults are detected.
– The nFAULT pin will stay low until the appropriate recovery sequence is performed.
TI recommends to inspect the system and board when a latched nFAULT faults occurs.
• An unlatched warning on nFAULT pin indicates that an event that requires a warning to be communicated has
occurred.
– An unlatched fault is indicated by the nFAULT pin going low for a period of 64 µs, reporting the warning
and then recovering back high for a period of 64 µs before reporting any subsequent errors.
– When a warning has been read by SPI through the warning register (0x01), that same warning will not be
reported through nFAULT again unless that warning or condition passes and then reoccurs.
However, the SPI registers will continue to report the latest status of the condition even after it has been
cleared by the read, that is, if the condition has cleared, then the warning will clear in the SPI registers.
Note that if the microprocessor does not read the warning, then the nFAULT pin will continue to toggle.
– In case another warning or warnings are received during the 64-µs period but after the warning register
has been read, then after the expiration of 64 µs, the nFAULT pin will go high for another 64 µs and then
report those warning or warnings by going low for another 64 µs.
– If a latched fault occurs during a period where nFAULT is low, then the nFAULT pin will stay low.
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Note that nFAULT is an open-drain signal and must be pulled up through an external resistor.
7.3.10.2 Shoothrough Protection
DRV8305 integrates analog and digital monitors to prevent shoot-through in the external FETs.
• An Internal handshake through analog comparators is performed between high-side and low-side FETs
during switching transition.
• A minimum dead time (digital) of 40 ns is always inserted after a successful handshake. This digital dead-time
is programmable and is in addition to the time taken for the handshake.
7.3.10.3 VDS Sensing – External FET Protection and Reporting (OC Event)
To protect the external FETs from damage due to high currents, VDS sensing circuitry is implemented in the
DRV8305.
The VDS sensing is implemented for both the high-side and low-side MOSFET through these pins:
• High-side MOSFET: VDS measured between VDRAIN and SHX pins
• Low-side MOSFET: VDS measured between SHX and SLX pins
Based on RDS(on) of the power MOSFETs and the maximum allowed IDS, a voltage threshold can be calculated,
which when exceeded, triggers the VDS protection feature.
This voltage threshold level is programmable through SPI command and may be programmed during operation if
needed.
The VDS protection logic also has an adjustable blanking time and deglitch time to prevent false trips.
VDS blanking time (tBLANK): This time is inserted digitally and is programmable. The tBLANK time is a delay inserted
at each output after that particular output has been commanded to turn ON. During tBLANK time, the VDS
comparators are not being monitored in order to prevent false trips when the FETs first turn ON.
VDS deglitch time (tVDS): This time is inserted digitally and is programmable. The tVDS time is a delay inserted after
the VDS sensing comparators have tripped to when the protection logic is informed that a VDS event has
occurred.
Note that the dead time and blanking time are overlapping counters as shown in Figure 9
INx_x
Gx_x
1
2
3
tDead
Input Signal
Output Slew
Expiration of Blanking
tBLANK
1
tdeglitch
2
3
Figure 9. VDS Protection Timing
Three overcurrent responses are possible depending on the configuration option selected through SPI.
• VDS event latch shutdown mode
When a VDS event occurs, device will pull all outputs low in order to take all six external FETs into highimpedance mode. The Fault will be reported on nFAULT and details of the FET that reported the fault can be
read back through SPI.
• VDS event Reporting only mode
In this mode, VDS event will be reported on the nFAULT pin and the SPI register. Gate drivers will continue
to operate.
• VDS event disable mode
Device ignores all the VDS event detections and does not report them.
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7.3.10.4 Low-Side Source Monitoring (SNS_OCP)
The DRV8305 monitors the voltage on the SLX pins for high-current events like phase shorts that may cause the
voltage on those pins to exceed 2 V. The device will put the FETs into a high-impedance state to avoid damage.
7.3.11 Undervoltage Reporting and Undervoltage Lockout (UVLO) Protection
The DRV8305 implements appropriate undervoltage responses in order to protect the system. Fault / Warning
Classes and Recovery lists the details of the monitors and their response and recovery sequences.
Under-voltage is monitored on PVDD, AVDD, VCPH, and VCP_LSD.
The UVLO protection fault may be completely disabled for the PVDD undervoltage condition using a SPI register
command. In this case, the fault is still reported in the register.
The UVLO protection may never be completely disabled for the VCPH or VCP_LSD in OPERATING mode
because this may indicate a short condition that could damage the DRV8305.
7.3.11.1 Battery Overvoltage Protection (PVDD_OV)
The DRV8305 implements appropriate overvoltage responses in order to protect the system.
PVDD is monitored for overvoltage conditions. If the overvoltage threshold is tripped, a warning is issued and the
event is reported in the status registers. The device takes no action.
7.3.11.2 Charge Pump Overvoltage Protection (VCPH_OV/VCP_LSD_OV)
If VCPH or VCP_LSD exceed the overvoltage threshold due to potential issue related to the charge pumps (for
example, short of external charge pump capacitor or charge pump, an overvoltage fault is triggered).
7.3.11.3 Overtemperature (OT) Warning and Protection
A multi-level temperature detection circuit is implemented:
• Flag Level 1: Level 1 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set
to indicate flag and can be read through SPI.
• Flag Level 2: Level 2 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set
to indicate flag and can be read through SPI.
• Flag Level 3: Level 3 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set
to indicate flag and can be read through SPI.
• Flag Level 4: Level 4 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set
to indicate flag and can be read through SPI.
• Warning Level: Overtemperature warning only. Warning is reported on nFAULT for 64 µs and can be read
through SPI.
• Fault Level: Overtemperature fault and latched shut down of gate driver and charge pump Fault will be
reported to nFAULT pin.
SPI operation is still available and register settings will be retained in the device during OTSD operation as long
as PVDD is still within defined operation range.
The details of the fault will be reported into a register that can be read back through SPI.
7.3.11.4 dV/dt Protection
The DRV8305 gate driver implements a strong pulldown scheme for preventing dV/dt turn on of external FETs.
After a FET has been turned off using the selected sink slew rate setting, the internal state machine will turn on a
stronger pulldown if it senses that the opposite FET on that phase has been commanded to turn on. This allows
the systems designer to decouple the optimum slew rate setting selection for EMI and power from the pull down
required to prevent dV/dt turn on.
7.3.11.5 VGS Protection
The DRV8305 gate driver uses a multilevel level protection scheme to protect the external FET from VGS
voltages that may damage the gate of the external FET.
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The device integrates VGS clamps inside the gate driver that will turn on when the GHX voltage exceeds SHX
voltage by a value that could be damaging to the FETs. If the voltage continues to rise, in spite of the clamps
turning on, the TDRIVE architecture ensures that the energy through the clamps is limited. If the high VGS
voltage is due to an abnormal condition on the charge pump, the charge pump overvoltage fault will trip in order
to protect the FETs from damage.
7.3.11.6 Gate Driver Faults
The DRV8305 protects against abnormal short to battery or short to ground conditions on the gate driver outputs
that could result in an incorrect state of the gate driver outputs. The gate driver integrates VGS comparators that
check the status of the gate driver output against the commanded PWM signal to ensure that they match. This
comparison occurs shortly after the expiration of the TDRIVE time. If the comparison indicates a mismatch, a
gate driver fault is indicated.
7.3.11.7 Reverse Battery Protection
The VCPH pin on the DRV8305 is designed to be able to supply an external load of up to 10 mA. This feature
allows implementation of an external reverse battery protection scheme using a MOS and a BJT. The MOS gate
can be driven through VCP through a current limiting resistor to limit the current drawn from VCP. The current
limit resistor must be sized not to exceed the maximum external load on VCPH.
The VDRAIN pin (sense) may also be protected against negative transients on it by use of a current limiting
resistor. The current limit resistor must be sized not to exceed the maximum current load on the VDRAIN pin.
BATTERY
CP2H CP2L CP1H CP1L
VCPH
PVDD
PVDD
VDRAIN
Figure 10. Typical Scheme for Reverse Battery Protection Using VCPH
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7.3.11.8 MCU Watchdog
An MCU watchdog function may be enabled to ensure that the external controller that is instructing the DRV8305
is active and not in an unknown state.
SPI Watchdog must be enabled by writing a 1 to the WD_EN bit through SPI (default is disabled = 0).
When the SPI watchdog is enabled, an internal timer starts to countdown to an interval set by WD_dly bit.
To reset the watchdog, the address 0x01 (Status register) must be read by the microcontroller within the interval
set by the register WD_dly.
If the timer is allowed to expire without the address 0x01 being read, the WD fault will get enabled.
Response to this fault is as follows:
• A Latched + PWRGD fault occurs on the DRV8305 and gate drivers are put into a safe state. The appropriate
recovery sequence must be performed.
• PWRGD pin is taken low for 64 µs and then back high in order to reset the microcontroller.
• nFAULT is asserted
• WD_EN bit is cleared
• Report that the watchdog had expired through SPI bit WD_FAULT
• TI recommends that if the watchdog function is being used, the MCU software routine reads the status
registers as part of its recovery or power-up routine in order to know whether a WD_FAULT had previously
occurred.
Note that the fault results in clearing of the WD_EN bit and it will have to be set again to resume watchdog
functionality.
7.3.12 Pin Control Functions
7.3.12.1 EN_GATE
EN_GATE low is used to put the gate driver into standby mode. Note that EN_GATE has no effect on the LDO
voltage regulator. When EN_GATE is low, the device will always put the MOSFET output stage to high
impedance as long as PVDD is still present. EN_GATE is also used to reset the IC.
It is not possible to enter SLEEP mode without taking EN_GATE low and entering STANDBY mode first.
TI recommends to take EN_GATE for at least greater than 25 µs when it is asserted low to go into standby
mode.
7.3.12.2 SPI Pins
SDO pin has to be tri-state, so a data bus line can be connected to multiple SPI slave devices. SCS pin is active
low. When SCS is high, SDO is at high-impendence mode.
Ensure that SDO pin is always configured in the system as an output from DRV8305.
SDO pin must never be driven to ensure correct operation of DRV8305. SDO is referrenced to the VREG
voltage.
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Table 5. Fault / Warning Device Status
CLASS
OUTPUTS
PD – PULL
DOWN
O – OPERATING
PVDD undervoltage (VPVDD_UVLO1)
falling
None
PD
SD
SD
SD
PVDD undervoltage (VPVDD_UVLO2)
falling
Latched
PD
SD
O
O
PVDD undervoltage (VPVDD_UVFL)
falling
Warning
O
O
O
O
PVDD overvoltage (VPVDD_OVFL) rising
Warning
O
O
O
O
Charge pump undervoltage
(VVCPH_UVFL) falling
Warning
O
O
O
O
Charge pump undervoltage
(VVCPH_UVLO / VVCP_LSD_UVLO)
Latched
PD
SD
O
O
Charge pump overvoltage
(VVCPH_OVLO, VVCPH_OVLO_ABS)
Latched
PD
SD
O
O
AVDD undervoltage
Latched
PD
SD
SD
O
TEMP FLAG 1/2/3/4
Real time
O
O
O
O
OT warning (OTW)
Warning
O
O
O
O
OT shutdown (OTS)
Latched
PD
SD
O
O
VDS event – latch mode (FETxx_VDS)
CONDITION
CHARGE PUMP
AVDD / DVDD
O – OPERATING O – OPERATING
SD – SHUTDOWN SD – SHUTDOWN
VOLTAGE
REGULATOR
O – OPERATING
SD – SHUTDOWN
Latched
PD
O
O
O
VDS event – report mode
(FETxx_VDS)
Report only
O
O
O
O
VDS event – disable mode
(FETxx_VDS)
Not reported
O
O
O
O
SNS OCP
Latched
PD
O
O
O
Gate driver fault VGS event
Latched
PD
SD
O
O
MCU watchdog
Latched +
PWRGD
PD
O
O
O
VREG_UV
Latched +
PWRGD
PD
O
O
O
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7.3.13 Fault / Warning Classes and Recovery
7.3.13.1 Reg 09h CLR_FLTS
When CLR_FLTS bit is set to 1, all expired faults (latch/warn) will be cleared from the SPI status register. Also,
the nFAULT pin will be released on the event of an expired Latched fault. CLR_FLTS provides a software reset
option to DRV8305. The effect on nFAULT pin and SPI status registers is the same as pulling EN_GATE pin low
and taking it HIGH.
CLR_FLTS bit self clears to 0 after SPI status register is reset and nFAULT pin is released.
Table 6. Fault / Warning Reporting and Handling
CLASS
nFAULT
PWRGD
SPI REPORT
DEVICE RECOVERY SEQUENCE
SPI REPORT
RECOVERY
Latched
Low
No action
Yes
Toggle EN_GATE (Faults clear on
rising edge of EN_GATE)
OR
Write Reg 09h CLR_FLTS bit set 1
Bit clears only on
successful fault
recovery
Warning
Toggles with 64µs period
No action
Yes
Read SPI status register 0x01 to
acknowledge warning (otherwise
nFAULT will continue to toggle)
Bit clears on register
read only if condition
has passed
Report only (VDS
mode)
Toggles with 64µs period
No action
Yes
Read SPI status register 0x01 to
acknowledge warning (otherwise
nFAULT will continue to toggle)
Bit clears on register
read only if condition
has passed
Real time
No action
No action
Yes
Read SPI register to capture real
time status
Bit clears after
condition has passed
Not reported
No action
No action
No
None
None
Latched +
PWRGD
Low
Low for minimum
of 64 µs
Yes
Toggle EN_GATE (Faults clear on
rising edge of EN_GATE)
OR
Write Reg 09h CLR_FLTS bit set 1
Bit clears only on
successful fault
recovery
7.4 Device Functional Modes
7.4.1 Power-Up and Operating States Hardware Configuration for VREG/VREF
Hardware configuration is not required. Voltage regulator voltage (3.3 or 5 V or disabled) is based on orderable
part number.
7.4.1.1 POWER Up
During power-up, all internal circuits are enabled. The VREG will also be enabled based on the hardware
configuration (see Voltage Regulator Control (address = 0xB) section). All gate drive outputs are held low and
the nFAULT pin is taken low by the IC while power up is being executed.
7.4.1.2 STANDBY State
After the startup sequence is completed and the PVDD voltage is above VPVDD_UVLO2, the DRV8305 will indicate
successful and fault-free power up of all circuits by releasing the nFAULT pin.
The device will also enter STANDBY state any time that EN_GATE is taken low or a latched fault occurs.
Gate driver always has control of the power FETs even in STANDBY state.
TI recommends to set up the device control registers through SPI in the STANDBY state.
7.4.1.3 OPERATING State
Normal operation of the gate driver and current shunt amplifiers can be initiated by taking EN_GATE from a low
state to a high state. In this state the charge pump is powered up and the driver is ready for operation.
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Device Functional Modes (continued)
7.4.1.4
SLEEP State
The SLEEP state is invoked by issuing a SLEEP command through SPI. After the SLEEP command is received,
the VREG and the gate driver safely power down internally after a programmable delay.
The DRV8305 can then only be enabled through the WAKE pin which is a high-voltage-tolerant input pin.
For the DRV8305 to be brought out of SLEEP, the WAKE pin must be at a voltage greater than 3 V. This allows
the WAKE to be driven, for example, directly by the battery through a switch, through the inhibit pin (INH) on
standard LIN interface or through standard digital logic. The WAKE pin will only react to a wake-up command if
PVDD > VPVDD_UVLO2.
After the DRV8305 is out of SLEEP mode, all activity on the WAKE pin is ignored.
SLEEP state erases the values in the SPI control registers. TI does not recommend to write through SPI in
SLEEP state.
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7.5 Programming
7.5.1 SPI Communication
7.5.1.1 SPI
SPI is used to set device configuration, operating parameters, and read out diagnostic information. The
DRV8305 SPI operates in slave mode.
The SPI input data (SDI) word consists of a 16-bit word with 11-bit data and 5-bit (MSB) command. The SPI
output data (SDO) word consists of 11-bit register data. (The first 5 bits (MSB) are to be ignored.)
A
•
•
•
valid frame must meet following conditions:
Clock must be low when nSCS goes low.
It should have 16 full clock cycles.
Clock must be low when nSCS goes high.
Data is always shifted out on the rising edge of the clock in the same frame following the 5-bit MSB.
Data is always sampled on the falling edge of the clock in the same frame following the 5-bit MSB.
When SCS is asserted high, any signals at the SCLK and SDI pins are ignored, and SDO is forced into a highimpedance state. When SCS transitions from HIGH to LOW, SDO is enabled and the SPI response word loads
into the shift register based on 5-bit command.
The SCLK pin must be low when SCS transitions low. While SCS is low, at each rising edge of the clock, the
response bit is serially shifted out on the SDO pin with MSB shifted out first.
While SCS is low, at each falling edge of the clock, the new control bit is sampled on the SDI pin. The SPI
command bits are decoded to determine the register address and access type (read or write). The MSB will be
shifted in first. If the word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error and
the data will not be written into the destination address. If it is a write command, the data will be ignored.
For a write command, the existing data in the register being written to is shifted out on SDO following the 5-bit
MSB.
SCS should be taken high for at least 500 ns between frames.
7.5.1.2 SPI Format
SPI input data control word is 16-bit long, consisting of:
• 1 read or write bit W [15]
• 4 address bits A [14:11]
• 11 data bits D [10:0]
SPI output data response word is 11-bit long (first 5 bits are ignored) and its content is the content of the register
being accessed
For a Write transaction: The response word is the data currently in the register being written to.
For a Read Command: The response word is the data currently in the register being read.
Table 7. SPI Input Data Control Word Format
R/W
ADDRESS
DATA
Word Bit
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Command
W0
A3
A2
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 8. SPI Output Data Response Word Format
DATA
Word Bit
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Command
X
X
X
X
X
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
30
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7.6 Register Maps
Table 9. Register Map
ADDRESS
NAME
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0x1
Warning & Watch
Dog
FAULT
Reserved
TEMP_FLAG4
PVDD_UVFL
PVDD_OVFL
VDS_STATUS
VCPH_UVFL
TEMP_FLAG1
TEMP_FLAG2
TEMP_FLAG3
OTW
0x2
OV/VDS Faults
FETHA_VDS
FETLA_VDS
FETHB_VDS
FETLB_VDS
FETHC_VDS
FETLC_VDS
Reserved
Reserved
SNS_C_OCP
SNS_B_OCP
SNS_A_OCP
0x3
IC Faults
PVDD_UVLO2
WD_FAULT
OTS
Reserved
VREG_UV
AVDD_UVLO
VCP_LSD_UVLO
Reserved
VCPH_UVLO
VCPH_OVLO
VCPH_OVLO_A
BS
0x4
Gate drvier VGS
Faults
FETHA_VGS
FETLA_VGS
FETHB_VGS
FETLB_VGS
FETHC_VGS
FETLC_VGS
Reserved
Reserved
Reserved
Reserved
Reserved
0x5
HS Gate Driver
Control
Reserved
TDRIVEN[1]
TDRIVEN[0]
IDRIVEN_HS[3]
IDRIVEN_HS[2]
IDRIVEN_HS[1]
IDRIVEN_HS[0]
IDRIVEP_HS[3]
IDRIVEP_HS[2]
IDRIVEP_HS[1]
IDRIVEP_HS[0]
0x6
LS Gate Driver
Control
Reserved
TDRIVEP[1]
TDRIVE[0]
IDRIVEN_LS[3]
IDRIVEN_LS[2]
IDRIVEN_LS[1]
IDRIVEN_LS[0]
IDRIVEP_LS[3]
IDRIVEP_LS[2]
IDRIVEP_LS[1]
IDRIVEP_LS[0]
0x7
Gate Drive
Control
Reserved
COMM_OPTION
PWM_MODE[1]
PWM_MODE[0]
DEAD_TIME[2]
DEAD_TIME[1]
DEAD_TIME[0]
TBLANK[1]
TBLANK[0]
TVDS[1]
TVDS[0]
0x8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DIS_GDRV
FAULT
EN_SNS_CLAM
P
WD_DLY[1]
WD_DLY[0]
DIS_SNS_OCP
WD_EN
SLEEP
CLR_FLTS
SET_VCPH_UV
0x9
IC Operation
FLIP_OTS
DISABLE
VPVDD_UVLO2
0xA
Shunt Amplifier
Control
DC_CAL_CH3
DC_CAL_CH2
DC_CAL_CH1
CS_BLANK[1]
CS_BLANK[0]
GAIN_CS3[1]
GAIN_CS3[0]
GAIN_CS2[1]
GAIN_CS2[0]
GAIN_CS1[1]
GAIN_CS1[0]
0xB
Voltage
Regulator Control
Reserved
VREF_SCALE[1]
VREF_SCALE[0]
Reserved
Reserved
Reserved
SLEEP_DLY[1]
SLEEP_DLY[0]
DIS_VREG_PW
RGD
VREG_UV_LEVE
L[1]
VREG_UV_LEVE
L[0]
0xC
VDS Sense
Control
Reserved
Reserved
Reserved
VDS_LEVEL[4]
VDS_LEVEL[3]
VDS_LEVEL[2]
VDS_LEVEL[1]
VDS_LEVEL[0]
VDS_MODE[2]
VDS_MODE[1]
VDS_MODE[0]
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7.6.1 Read / Write Bit
The MSB bit of SDI word (W0) is read/write bit. When W0 = 0, input data is a write command; when W0 = 1,
input data is a read command, and the register value will send out on the same word cycle from SDO from D10
to D0.
7.6.2 Status Registers
Status registers are used to report warning, fault conditions and provide a means to prevent timing out of the
watchdog timer. Status registers are read only registers.
7.6.3 0x1 Warning and Watchdog Reset
Table 10. Warning and Watchdog Reset Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R
FAULT
0x0
0 - Warning,
1 - Latched fault
9
R
Reserved
0x0
8
R
TEMP_Flag4
0x0
Temperature flag setting for about 175°C
7
R
PVDD_UVFL
0x0
PVDD undervoltage flag warning
6
R
PVDD_OVFL
0x0
PVDD overvoltage flag warning
5
R
VDS_STATUS
0x0
Real time or of all VDS sensors (0x2[D10:5])
4
R
VCHP_UVFL
0x0
Charge pump undervoltage flag warning
3
R
TEMP_Flag1
0x0
Temperature flag setting for about 105°C
2
R
TEMP_Flag2
0x0
Temperature flag setting for about 125°C
1
R
TEMP_Flag3
0x0
Temperature flag setting for about 135°C
0
R
OTW
0x0
Overtemperature warning
7.6.4 0x2 OV/VDS Faults
Table 11. OV/VDS Faults Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R
FETHA_VDS
0x0
VDS monitor fault for high-side FET A
9
R
FETLA_VDS
0x0
VDS monitor fault for low-side FET A
8
R
FETHB_VDS
0x0
VDS monitor fault for high-side FET B
7
R
FETLB_VDS
0x0
VDS monitor fault for low-side FET B
6
R
FETHC_VDS
0x0
VDS monitor fault for high-side FET C
5
R
FETLC_VDS
0x0
VDS monitor fault for low-side FET C
4:3
R
Reserved
0x0
2
R
SNS_C_OCP
0x0
Sense C overcurrent protection flag
1
R
SNS_B_OCP
0x0
Sense B overcurrent protection flag
0
R
SNS_A_OCP
0x0
Sense A overcurrent protection flag
32
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7.6.5 0x3 IC Faults
Table 12. IC Faults Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R
PVDD_UVLO2
0x0
PVDD undervoltage 2 fault
9
R
WD_FAULT
0x0
Watchdog fault
8
R
OTS
0x0
Overtemperature fault
7
R
Reserved
0x0
6
R
VREG_UV
0x0
VREG undervoltage fault
5
R
AVDD_UVLO
0x0
AVDD undervoltage fault
4
R
VCP_LSD_UVLO
0x0
Charge pump low-side gate driver fault
3
R
Reserved
0x0
2
R
VCPH_UVLO
0x0
Charge pump high-side undervoltage 2 fault
1
R
VCPH_OVLO
0x0
Charge pump high-side overvoltage fault
0
R
VCPH_OVLO_ABS
0x0
Charge pump high-side overvoltage ABS fault
7.6.6 0x4 Gate Driver VGS Faults
Table 13. Gate Driver VGS Faults Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R
FETHA_VGS
0x0
VGS monitor fault for high-side FET A
9
R
FETLA_VGS
0x0
VGS monitor fault for low-side FET A
8
R
FETHB_VGS
0x0
VGS monitor fault for high-side FET B
7
R
FETLB_VGS
0x0
VGS monitor fault for low-side FET B
6
R
FETHC_VGS
0x0
VGS monitor fault for high-side FET C
5
R
FETLC_VGS
0x0
VGS monitor fault for low-side FET C
4:0
R
Reserved
0x0
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7.6.7 Control Registers
Control registers are used to set the user parameter for DRV8305. The default values are shown in bold.
• Control registers may be read and do not clear on read or EN_GATE resets
• Control registers are cleared to default values on power up
• Control registers are cleared to default values when the device enters SLEEP mode
7.6.7.1
HS Gate Driver Control (address = 0x5)
Table 14. HS Gate Driver Control Register Description
BIT
R/W
NAME
DEFAULT
10
R/W
Reserved
0x0
DESCRIPTION
9:8
R/W
TDRIVEN
0x3
High-side gate driver peak source time
b'00 - 250 ns
b'01 - 500 ns
b'10 - 1000 ns
b'11 - 2000 ns
7:4
R/W
IDRIVEN_HS
0x4
High-side gate driver peak sink current
b'0000 - 20 mA
b'0100 - 60 mA
b'1000 - 0.50 A
b'1100 - 60 mA
3:0
R/W
IDRIVEP_HS
0x4
- 30 mA
- 70 mA
- 0.75 A
- 60 mA
b'0010
b'0110
b'1010
b'1110
- 40 mA
- 80 mA
- 1.00 A
- 60 mA
b'0011
b'0111
b'1011
b'1111
- 50 mA
- 0.25 A
- 1.25 A
- 60 mA
- 30 mA
- 70 mA
- 0.75 A
- 50 mA
b'0011
b'0111
b'1011
b'1111
- 40 mA
- 0.125 A
- 1.00 A
- 50 mA
- 40 mA
- 80 mA
- 1.00 A
- 60 mA
b'0011
b'0111
b'1011
b'1111
- 50 mA
- 0.25 A
- 1.25 A
- 60 mA
- 30 mA
- 70 mA
- 0.75 A
- 50 mA
b'0011
b'0111
b'1011
b'1111
- 40 mA
- 0.125 A
- 1.00 A
- 50 mA
High-side gate driver peak source current
b'0000 - 10 mA
b'0100 - 50 mA
b'1000 - 0.25 A
b'1100 - 50 mA
7.6.7.2
b'0001
b'0101
b'1001
b'1101
b'0001
b'0101
b'1001
b'1101
- 20 mA
- 60 mA
- 0.50 A
- 50 mA
b'0010
b'0110
b'1010
b'1110
LS Gate Driver Control (address = 0x6)
Table 15. LS Gate Driver Control Register Description
BIT
R/W
NAME
DEFAULT
10
R/W
Reserved
0x0
DESCRIPTION
9:8
R/W
TDRIVEP
0x3
Low-side gate driver peak source time
b'00 - 250 ns
b'01 - 500 ns
b'10 - 1000 ns
b'11 - 2000 ns
7:4
R/W
IDRIVEN_LS
0x4
Low-side gate driver peak sink current
b'0000 - 20 mA
b'0100 - 60 mA
b'1000 - 0.50 A
b'1100 - 60 mA
3:0
R/W
IDRIVEP_LS
0x4
- 30 mA
- 70 mA
- 0.75 A
- 60 mA
b'0010
b'0110
b'1010
b'1110
Low-side gate driver peak source current
b'0000 - 10 mA
b'0100 - 50 mA
b'1000 - 0.25 A
b'1100 - 50 mA
34
b'0001
b'0101
b'1001
b'1101
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b'0001
b'0101
b'1001
b'1101
- 20 mA
- 60 mA
- 0.50 A
- 50 mA
b'0010
b'0110
b'1010
b'1110
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Gate Drive Control (address = 0x7)
Table 16. Gate Drive Control Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
Reserved
0x0
9
R/W
COMM_OPTION
0x1
Rectification control (PWM_MODE = b'10 only)
b'0 - diode freewheeling
b'1 - active freewheeling
8:7
R/W
PWM_MODE
0x0
PWM Mode
b'00 - PWM with 6 independent inputs
b'01 - PWM with 3 independent inputs
b'10 - PWM with one input
b'11 - PWM with 6 independent inputs
6:4
R/W
DEAD_TIME
0x1
Dead time
b'000 - 40 ns
b'011 - 500 ns
b'110 - 4000 ns
3:2
R/W
TBLANK
0x1
VDS sense blanking
b'00 - 0 µs
b'01 - 2 µs
b'10 - 4 µs
b'11 - 8 µs
1:0
R/W
TVDS
0x2
VDS sense deglitch
b'00 - 0 µs
b'01 - 2 µs
b'10 - 4 µs
b'11 - 8 µs
b'001 - 60 ns
b'100 - 1000 ns
b'111 - 6000 ns
b'010 - 100 ns
b'101 - 2000 ns
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IC Operation (address = 0x9)
Table 17. IC Operation Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
Flip_OTS
0x0
Enable OTS
b'0 - Disable OTS
b'1 - Enable OTS
9
R/W
DIS_VPVDD_UVLO2
0x0
Disable PVDD_UVLO2 fault and reporting
b'0 - PVDD_UVLO2 enabled
b'1 - PVDD_UVLO2 disabled
8
R/W
DIS_GDRV_FAULT
0x0
Disable gate driver fault and reporting
b'0 - Gate driver fault enabled
b'1 - Gate driver fault disabled
7
R/W
EN_SNS_CLAMP
0x0
Enable sense amplifier clamp
b'0 - sense amplifier clamp is not enabled
b'1 - sense amplifier clamp is enabled limiting output to about
3.3 V
6:5
R/W
WD_DLY
0x1
Watch dog delay
b'00 - 10 ms
b'01 - 20 ms
b'10 - 50 ms
b'11 - 100 ms
4
R/W
DIS_SNS_OCP
0x0
Disable SNS overcurrent protection fault and reporting
b'0 - SNS OCP enabled
b'1 - SNS OCP disabled
3
R/W
WD_EN
0x0
Watch dog enable
b'0 - Watch dog disabled
b'1 - Watch dog enabled
2
R/W
SLEEP
0x0
Put device into sleep mode
b'0 - Device awake
b'1 - Device asleep
1
R/W
CLR_FLTS
0x0
Clear faults
b'0 - Normal operation
b'1 - Clear fault bits
0
R/W
SET_VCPH_UV
0x0
Set charge pump undervoltage threshold level
b'0 - 4.9 V
b'1 - 4.6 V
36
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7.6.7.5
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Shunt Amplifier Control (address = 0xA)
Table 18. Shunt Amplifier Control Register Description
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
DC_CAL_CH3
0x0
DC Calibration of CS amplifier 3
b'0 - Normal operation
b'1 - DC calibration mode
9
R/W
DC_CAL_CH2
0x0
DC Calibration of CS amplifier 2
b'0 - Normal operation
b'1 - DC calibration mode
8
R/W
DC_CAL_CH1
0x0
DC Calibration of CS amplifier 1
b'0 - Normal operation
b'1 - DC calibration mode
7:6
R/W
CS_BLANK
0x0
Current shunt amplifier blanking time
b'00 - 0 ns
b'01 - 500 ns
b'10 - 2.5 µs
b'11 - 10 µs
5:4
R/W
GAIN_CS3
0x0
Gain of CS amplifier 3
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
3:2
R/W
GAIN_CS2
0x0
Gain of CS amplifier 2
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
1:0
R/W
GAIN_CS1
0x0
Gain of CS amplifier 1
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
7.6.7.6
Voltage Regulator Control (address = 0xB)
Table 19. Voltage Regulator Control Register Description
BIT
R/W
NAME
DEFAULT
10
R/W
Reserved
0x0
9:8
R/W
VREF_SCALING
0x1
7:5
R/W
Reserved
0x0
4:3
R/W
SLEEP_DLY
0x1
2
R/W
DIS_VREG_PWRGD
0x0
0:1
R/W
VREG_UV_LEVEL
0x2
DESCRIPTION
VREF Scaling
b'00 - RSVD
b'01 - k = 2
b'10 - k = 4
b'11 - RSVD
Delay to power down VREG after SLEEP
b'00 - 0 µs
b'01 - 10 µs
b'10 - 50 µs
b'11 - 1 ms
VREG undervoltage set point
b'00 - VSET-10%
b'01 - VSET-20%
b'10 - VSET-30%
b'11 - VSET-30%
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VDS Sense Control (address = 0xC)
Table 20. VDS Sense Control Register Description
BIT
R/W
NAME
DEFAULT
10:8
R/W
Reserved
0x0
7:3
R/W
VDS_LEVEL
0x19
DESCRIPTION
VDS comparator threshold
b'00000
V
b'00100
V
b'01000
V
b'01100
V
b'10000
V
b'10100
V
b'11000
V
b'11100
V
2:0
38
R/W
VDS_MODE
0x0
- 0.060
- 0.097
- 0.155
- 0.250
- 0.403
- 0.648
- 1.043
- 1.679
b'00001 - 0.068
V
b'00101 - 0.109
V
b'01001 - 0.175
V
b'01101 - 0.282
V
b'10001 - 0.454
V
b'10101 - 0.730
V
b'11001 - 1.175
V
b'11101 - 1.892
V
b'00010
V
b'00110
V
b'01010
0.197V
b'01110
V
b'10010
V
b'10110
V
b'11010
V
b'11110
V
- 0.076
- 0.123
- 0.317
- 0.511
- 0.822
- 1.324
- 2.131
b'00011
V
b'00111
V
b'01011
V
b'01111
V
b'10011
V
b'10111
V
b'11011
V
b'11111
V
- 0.086
- 0.138
- 0.222
- 0.358
- 0.576
- 0.926
- 1.491
- 2.131
VDS mode
b'000 - Latched shut down when over-current detected
b'001 - Report only when over current detected
b'010 - VDS protection disabled (no overcurrent sensing or reporting)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8305 is a gate driver IC designed to drive a 3-phase BLDC motor in combination with external power
MOSFETs. The device provides a high level of integration with three half-bridge gate drivers, three current shunt
amplifiers, adjustable slew rate control, logic LDO, and a suite of protection features.
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8.2 Typical Application
The following design is a common application of the DRV8305.
PVDD
4.7µF
PVDD
1 µF
2.2 µF
1 µF
PVDD
24
23
22
21
13
10 k
27
26
25
1 µF
SH_C
GL_A
GL_B
34.8 k
SL_A
GL_B
34.8 k
GL_A
GL_C
SL_A
SN1
GH_C
1000 pF
SH_C
SP1
SL_B
SN2
1000 pF
SP2
SL_C
SN3
1000 pF
0.1 µF
SH_B
GH_B
4.99 k
SL_B
CSENSE
28
VCC
SH_B
5m
29
SH_A
0.1 µF
30
SH_A
4.99 k
31
GH_C
VCC
34.8 k
32
GH_B
VCC
BSENSE
GL_C
33
1 µF
1 µF
SCLK
34
GH_A
GH_A
SP3
SL_C
GL_B
SP1
SL_C
SN1
SH_C
SDO
SP2
SDI
SN2
GH_C
SP3
nSCS
35
4.99 k
GH_B
36
5m
nFAULT
VCC
PVDD
PVDD
37
VCP_LSD
38
39
CP2H
VCPH
41
40
CP2L
PVDD
42
CP1L
CP1H
43
44
VDRAIN
46
45
GND
DVDD
SH_B
PWRGD
12
INLC
20
11
SL_B
DRV8305
SN3
10
SPI
INHC
SO3
9
GL_B
19
GPIO
INLB
SO2
8
SL_A
GL_A
18
7
10 k
PWR_PAD (0) - GND
INHB
17
6
INLA
SO1
5
VCC
GH_A
SH_A
AVDD
4
INHA
16
3
PWM
EN_GATE
GND
2
15
1
GPIO
WAKE
48
VREG
POWER
47
1 µF
VCC
14
MCU
5m
0.1 µF
0.1 µF
0.1 µF
ASENSE
100
VCC
PVDD
VCC
34.8 k
0.01 µF
0.1 µF
+
470 µF
+
470 µF
SP1
SP2
SN1
SP3
SN2
1 µF
SN3
GPIO
4.99 k
ADC
ASENSE
0.1 µF
PVDDSENSE
PVDDSENSE
BSENSE
CSENSE
Figure 11. Typical Application Schematic
40
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8.2.1 Design Requirements
Table 21. Design Parameters
DESIGN PARAMETER
Supply voltage
REFERENCE
VALUE
PVDD
12 V
MR
0.5 Ω
Motor winding inductance
ML
0.28 mH
Motor poles
MP
16 poles
Motor rated RPM
MRPM
2000 RPM
Number of MOSFETs switching
NSW
6
Switching frequency
fSW
45 kHz
IDRIVEP
IDRIVEP
50 mA
IDRIVEN
Motor winding resistance
IDRIVEN
60 mA
MOSFET QG
Qg
36 nC
MOSFET QGD
QGD
9 nC
RDS(on)
4.1 mΩ
MOSFET RDS(on)
Target full-scale current
IMAX
30 A
Sense resistor
RSENSE
0.005 Ω
VDS trip level
VDS_LVL
0.197 V
Amplifier bias
VBIAS
1.65 V
Amplifier gain
Gain
10 V/V
8.2.2 Detailed Design Procedure
8.2.2.1 Gate Drive Average Current
The gate drive supply (VCP) of the DRV8305 is capable of delivering up to 30 mA (RMS) of current to the
external power MOSFETs. The charge pump directly supplies the high-side N-channel MOSFETs and a 10-V
LDO powered from VCP supplies the low-side N-channel MOSFETs. The designer can determine the
approximate RMS load on the gate drive supply through the following equation.
Gate Drive RMS Current = MOSFET Qg × Number of Switching MOSFETs × Switching Frequency
(2)
Example: 36 nC (QG) × 6 (NSW) × 45 kHz (fSW) = 9.72 mA
Note that this is only a first-order approximation.
8.2.2.2 MOSFET Slew Rates
The rise and fall times of the external power MOSFET can be adjusted through the use of the DRV8305 IDRIVE
setting. A higher IDRIVE setting will charge the MOSFET gate more rapidly where a lower IDRIVE setting will
charge the MOSFET gate more slowly. System testing requires fine tuning to the desired slew rate, but a rough
first-order approximation can be calculated as shown in the following.
MOSFET Slew Rate = MOSFET QGD / IDRIVE Setting
(3)
Example: 9 nC (QGD) / 50 mA (IDRIVEP) = 180 ns
8.2.2.3 Overcurrent Protection
The DRV8305 provides overcurrent protection for the external power MOSFETs through the use of VDS
monitors for both the high-side and low-side MOSFETs. These are intended for protecting the MOSFET in
overcurrent conditions and are not for precise current regulation.
The overcurrent protection works by monitoring the VDS voltage drop of the external MOSFETs and comparing it
against the internal VDS_LEVEL set through the SPI registers. The high-side VDS is measured across the
VDRAIN and SH_X pins. The low-side VDS is measured across the SH_X and SL_X pins. If the VDS voltage
exceeds the VDS_LEVEL value, the DRV8305 will take action according to the VDS_MODE register.
The overcurrent trip level can be determined with the MOSFET RDS(on) and the VDS_LEVEL setting.
Overcurrent Trip = VDS Level (VDS_LVL) / MOSFET RDS(on) (RDS(on))
(4)
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Example: 0.197 V (VDS_LVL) / 4.1 mΩ (RDS(ON)) = 48 A
8.2.2.4 Current Sense Amplifiers
The DRV8305 provides three bidirectional low-side current shunt amplifiers. These can be used to sense the
current flowing through each half-bridge. If individual half-bridge sensing is not required, a single current shunt
amplifier can be used to measure the sum of the half-bridge current. Use this simple procedure to correctly
configure the current shunt amplifiers.
1. Determine the peak current that the motor will demand (IMAX). This demand depends on the motor
parameters and the application requirements. IMAX in this example is 14 A.
2. Determine the available voltage output range for the current shunt amplifiers. This will be the ± voltage
around the amplifier bias voltage (VBIAS). In this case VBIAS = 1.65 V and a valid output voltage is 0 to 3.3
V. This gives an output range of ±1.65 V.
3. Determine the sense resistor value and amplifier gain settings. The sense resistor value and amplifier gain
have common tradeoffs. The larger the sense resistor value, the better the resolution of the half-bridge
current. This comes at the cost of additional power dissipated from the sense resistor. A larger gain value
allows for the use of a smaller resolution, but at the cost of increased noise in the output signal and a longer
settling time. This example uses a 5-mΩ sense resistor and the minimum gain setting of the DRV8305 (10
V/V). These values allow the current shunt amplifiers to measure ±33 A across the sense resistor.
42
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8.2.3 Application Curves
Figure 12. Gate Drive 20% Duty Cycle
Figure 13. Gate Drive 80% Duty Cycle
Figure 14. Motor Spinning 1000 RPM
Figure 15. Motor Spinning 2000 RPM
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9 Power Supply Recommendations
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including the:
• Highest current required by the motor system
• Power supply’s capacitance and ability to source or sink current
• Amount of parasitic inductance between the power supply and motor system
• Acceptable voltage ripple
• Type of motor used (brushed DC, brushless DC, stepper)
• Motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate-sized bulk capacitor.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
±
+
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 16. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
44
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10 Layout
10.1 Layout Guidelines
Use the following layout recommendations when designing a PCB for the DRV8305.
• The DVDD and AVDD 1-μF bypass capacitors should connect directly to the adjacent GND pin to minimize
loop impedance for the bypass capacitor.
• The CP1 and CP2 0.047-μF flying capacitors should be placed directly next to the DRV8305 charge pump
pins.
• The VCPH 2.2-μF and VCP_LSD 1-μF bypass capacitors should be placed close to their corresponding pins
with a direct path back to the DRV8305 GND net.
• The PVDD 4.7-μF bypass capacitor should be placed as close as possible to the DRV8305 PVDD supply pin.
• Use the proper footprint as shown in the Mechanical, Packaging, and Orderable Information section.
• Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the DRV8305
GH_X to the power MOSFET and returns through SH_X. The low-side loop is from the DRV8305 GL_X to the
power MOSFET and returns through SL_X.
10.2 Layout Example
Figure 17. Layout Recommendation
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
46
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV83053PHP
ACTIVE
HTQFP
PHP
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83053
DRV83053PHPR
ACTIVE
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83053
DRV83055PHP
ACTIVE
HTQFP
PHP
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83055
DRV83055PHPR
ACTIVE
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83055
DRV8305NPHP
ACTIVE
HTQFP
PHP
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8305N
DRV8305NPHPR
ACTIVE
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8305N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Sep-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DRV8305 :
• Automotive: DRV8305-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DRV83053PHPR
HTQFP
PHP
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
DRV83055PHPR
HTQFP
PHP
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
DRV8305NPHPR
HTQFP
PHP
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV83053PHPR
HTQFP
PHP
48
1000
367.0
367.0
38.0
DRV83055PHPR
HTQFP
PHP
48
1000
367.0
367.0
38.0
DRV8305NPHPR
HTQFP
PHP
48
1000
367.0
367.0
38.0
Pack Materials-Page 2
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