LMH6702QML LMH6702QML 1.7 GHz, Ultra Low Distortion, Wideband Op Amp Literature Number: SNOSAQ2D LMH6702QML 1.7 GHz, Ultra Low Distortion, Wideband Op Amp General Description Features The LMH6702 is a very wideband, DC coupled monolithic operational amplifier designed specifically for wide dynamic range systems requiring exceptional signal fidelity. Benefiting from National's current feedback architecture, the LMH6702 offers unity gain stability at exceptional speed without need for external compensation. With its 720MHz bandwidth (AV = 2V/V, VO = 2VPP), 10-bit indistortion levels through 60MHz (RL = 100Ω), 1.83nV/ put referred noise and 12.5mA supply current, the LMH6702 is the ideal driver or buffer for high-speed flash A/D and D/A converters. Wide dynamic range systems such as radar and communication receivers, requiring a wideband amplifier offering exceptional signal purity, will find the LMH6702's low input referred noise and low harmonic and intermodulation distortion make it an attractive high speed solution. The LMH6702 is constructed using National's VIP10™ complimentary bipolar process and National's proven current feedback architecture. VS = ±5V, TA = 25°C, AV = +2V/V, RL = 100Ω, VOUT = 2VPP, Typical unless Noted: ■ Available with radiation guarantee 300 krad(Si) — High Dose Rate 300 krad(Si) — ELDRS Free 720 MHz ■ −3dB Bandwidth (VOUT = 0.2 VPP) 1.83nV/ ■ Low noise 13.4ns ■ Fast settling to 0.1% 3100V/μs ■ Fast slew rate 12.5mA ■ Supply current 80mA ■ Output current −67dBc ■ Low Intermodulation Distortion (75MHz) ■ Improved Replacement for CLC409 and CLC449 Applications ■ ■ ■ ■ ■ ■ Flash A/D driver D/A transimpedance buffer Wide dynamic range IF amp Radar/communication receivers Line driver High resolution video Ordering Information NS PART NUMBER SMD PART NUMBER LMH6702J-QMLV 5962–0254601VPA NS PACKAGE NUMBER J08A LMH6702WG-QMLV 5962–0254601VZA WG10A PACKAGE DISCRIPTION 8LD CERDIP 10LD CERAMIC SOIC LMH6702JFQMLV 5962F0254601VPA 300 krad(Si) J08A 8LD CERDIP LMH6702JFLQMLV ELDRS FREE 5962F0254602VPA 300 krad(Si) J08A 8LD CERDIP LMH6702WGFQMLV 5962F0254601VZA 300 krad(Si) WG10A 10LD CERAMIC SOIC LMH6702WGFLQMLV ELDRS FREE 5962F0254602VZA 300 krad(Si) WG10A 10LD CERAMIC SOIC Connection Diagrams 8 Lead Cerdip (J) 10 Lead Ceramic SOIC (WG) 20151631 Top View See NS Package Number J08A 20151632 Top View See NS Package Number WG10A VIP10™ is a trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation 201516 www.national.com LMH6702QML 1.7 GHz, LMH6702QML Ultra Low Distortion, Wideband Op Amp October 5, 2011 LMH6702QML Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) Common Mode Input Voltage (VCM) Power Dissipation (PD) (Note 2) Junction Temperature (TJ) Lead Temperature (soldering, 10 seconds) Storage Temperature Range ±6.75VDC V- to V+ 1W +175°C +300°C -65°C ≤ TA ≤ +150°C Thermal Resistance θJA Cerdip (Still Air) Cerdip (500LF/Min Air Flow) Ceramic SOIC (Still Air) Ceramic SOIC (500LF/Min Air Flow) 170°C/W 100°C/W 220°C/W 150°C/W θJC Cerdip Ceramic SOIC Package Weight (Typical) Cerdip Ceramic SOIC ESD Tolerance (Note 3) 35°C/W 37°C/W 1078mg 227mg 1000V Recommended Operating Conditions Supply Voltage (VCC) Gain Range Ambient Operating Temperature Range (TA) ±5VDC to ±6VDC ±1 to ±10 -55°C to +125°C Quality Conformance Inspection MIL-STD-883, Method 5005, Group A www.national.com Subgroup Description Temp ( C) 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 2 LMH6702QML LMH6702 Electrical Characteristics DC Parameters (Note 4), (Note 5) The following conditions apply, unless otherwise specified. RL = 100Ω, VCC = ±5VDC, AV = +2 feedback resistor (RF) = 250Ω, gain resistor (RG) = 250Ω Symbol Parameter IBN Input Bias Current, Noninverting IBI Conditions Notes Input Bias Current, Iverting VIO Input Offset Voltage ICC Supply Current, no load RL = ∞ PSSR Power Supply Rejection Ratio -VCC = -4.5V to -5.0V, +VCC = +4.5V to +5.0V Min Max Unit Subgroups -15 +15 μA 1, 2 -21 +21 μA 3 -30 +30 μA 1, 2 -34 +34 μA 3 -4.5 +4.5 mV 1, 3 -6.0 +6.0 mV 2 15 mA 1, 2, 3 dB 1, 2, 3 Max Unit Subgroups 45 AC Parameters (Note 4), (Note 6) The following conditions apply, unless otherwise specified. RL = 100Ω, VCC = ±5VDC, AV = +2 feedback resistor (RF) = 250Ω, gain resistor (RG) = 250Ω Symbol Parameter Conditions Notes Min HD3 3rd Harmonic Distortion 2VPP at 20MHz -62 dBc 4 GFPL Gain Flatness Peaking 0.1MHz to 75MHz, VO < 0.5VPP 0.4 dB 4 GFPH Gain Flatness Peaking > 75MHz, VO < 0.5VPP 2.0 dB 4 GFRH Gain Flatness Rolloff 75MHz to 125MHz, VO<0.5VPP 0.2 dB 4 HD2 2nd Harmonic Distortion 2VPP at 20MHz -52 dBc 4 Drift Values Parameters (Note 4) The following conditions apply, unless otherwise specified. RL = 100Ω, VCC = ±5VDC, AV = +2 feedback resistor (RF) = 250Ω, gain resistor (RG) = 250Ω "Delta not required on B level product. Delta required for S-level product at Group B5 only, or as specified on the Internal Processing Instruction (IPI)." Min Max Unit Subgroups Input Bias Current Noninverting -0.3 +0.3 μA 1 IBI Input Bias Current Inverting -3.0 +3.0 μA 1 VIO Input Offset Voltage -0.3 +0.3 mV 1 Symbol Parameter IBN Conditions Notes Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: Human body model, 1.5kΩ in series with 100pF. Note 4: The algebraic convention, whereby the most negative value is a minimum and most positive is a maximum, is used in this table. Negative cur rent shall be defined as convential current flow out of a device terminal. Note 5: Pre and Post irradiation limits are identical to those listed under the DC parameter tables above. Post irradiation testing is conducted at room temperature, +25°C, only. Testing is performed as specified in MIL-STD-883 Test Method 1019 Condition A. The ELDRS-Free part is also tested per Test Method 1019 Conditions D. Note 6: These parameters are not post irradiation tested. 3 www.national.com LMH6702QML Inverting Frequency Response 20151602 www.national.com 4 (TA = 25°C, VS = ±5V, RL = 100Ω, RF = 237Ω; Unless Specified). Non-Inverting Frequency Response Inverting Frequency Response 20151601 20151602 Small Signal Bandwidth Frequency Response for Various RL’s, AV = +2 20151630 20151618 Frequency Response for Various RL’s, AV = +4 Step Response, 2VPP 20151617 20151605 5 www.national.com LMH6702QML Typical Performance Characteristics LMH6702QML Step Response, 6VPP Percent Settling vs. Time 20151620 20151606 RS and Settling Time vs. CL Input Offset for 3 Representative Units 20151614 20151613 Inverting Input Bias for 3 Representative Units Non-Inverting Input Bias for 3 Representative Units 20151615 www.national.com 20151616 6 LMH6702QML Noise CMRR, PSRR, ROUT 20151619 20151612 Transimpedance DG/DP (NTSC) 20151611 20151604 DG/DP (PAL) 20151603 7 www.national.com LMH6702QML Application Section arate from the ground connections to sensitive input circuitry (such as RG, RT, and RIN ground connections). Splitting the ground plane in this fashion and separately routing the high frequency current spikes on the decoupling caps back to the power supply (similar to "Star Connection" layout technique) ensures minimum coupling back to the input circuitry and results in best harmonic distortion response (especially 2nd order distortion). If this lay out technique has not been observed on a particular application board, designer may actually find that supply decoupling caps could adversely affect HD2 performance by increasing the coupling phenomenon already mentioned. Figure 3 below shows actual HD2 data on a board where the ground plane is "shared" between the supply decoupling capacitors and the rest of the circuit. Once these capacitors are removed, the HD2 distortion levels reduce significantly, especially between 10MHz-20MHz, as shown in Figure 3 below: FEEDBACK RESISTOR 20151628 FIGURE 1. Recommended Non-Inverting Gain Circuit 20151622 FIGURE 3. Decoupling Current Adverse Effect on a Board with Shared Ground Plane At these extremely low distortion levels, the high frequency behavior of decoupling capacitors themselves could be significant. In general, lower value decoupling caps tend to have higher resonance frequencies making them more effective for higher frequency regions. A particular application board which has been laid out correctly with ground returns "split" to minimize coupling, would benefit the most by having low value and higher value capacitors paralleled to take advantage of the effective bandwidth of each and extend low distortion frequency range. 20151627 FIGURE 2. Recommended Inverting Gain Circuit The LMH6702 achieves its excellent pulse and distortion performance by using the current feedback topology. The loop gain for a current feedback op amp, and hence the frequency response, is predominantly set by the feedback resistor value. The LMH6702 is optimized for use with a 237Ω feedback resistor. Using lower values can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth. Application Note OA-13 discusses this in detail along with the occasions where a different RF might be advantageous. CAPACITIVE LOAD DRIVE Figure 4 shows a typical application using the LMH6702 to drive an ADC. HARMONIC DISTORTION The LMH6702 has been optimized for exceptionally low harmonic distortion while driving very demanding resistive or capacitive loads. Generally, when used as the input amplifier to very high speed flash ADCs, the distortions introduced by the converter will dominate over the low LMH6702 distortions. The capacitor CSS, shown across the supplies in Figure 1 and Figure 2, is critical to achieving the lowest 2nd harmonic distortion. For absolute minimum distortion levels, it is also advisable to keep the supply decoupling currents (ground connections to CPOS, and CNEG in Figure 1 and Figure 2) sepwww.national.com 8 DC ACCURACY AND NOISE Example below shows the output offset computation equation for the non-inverting configuration using the typical bias current and offset specifications for AV = + 2: Output Offset : VO = (±IBN · RIN ± VIO) (1 + RF/RG) ± IBI · RF Where RIN is the equivalent input impedance on the non-inverting input. Example computation for AV = +2, RF = 237Ω, RIN = 25Ω: VO = (±6μA · 25Ω ± 1mV) (1 + 237/237) ± 8μA · 237 = ±4.20mV A good design, however, should include a worst case calculation using Min/Max numbers in the data sheet tables, in order to ensure "worst case" operation. Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in Application Note OA-7. The two input bias currents are physically unrelated in both magnitude and polarity for the current feedback topology. It is not possible, therefore, to cancel their effects by matching the source impedance for the two inputs (as is commonly done for matched input bias current devices). The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage and the two input noise currents, the output noise is developed through the same gain equations for each term but combined as the square root of the sum of squared contributing elements. See Application Note OA-12 for a full discussion of noise calculations for current feedback amplifiers. 20151629 FIGURE 4. Input Amplifier to ADC The series resistor, RS, between the amplifier output and the ADC input is critical to achieving best system performance. This load capacitance, if applied directly to the output pin, can quickly lead to unacceptable levels of ringing in the pulse response. The plot of "RS and Settling Time vs. CL" in the Typical Performance Characteristics section is an excellent starting point for selecting RS. The value derived in that plot minimizes the step settling time into a fixed discrete capacitive load with the output driving a very light resistive load (1kΩ). Sensitivity to capacitive loading is greatly reduced once the output is loaded more heavily. Therefore, for cases where the output is heavily loaded, RS value may be reduced. The exact value may best be determined experimentally for these cases. In applications where the LMH6702 is replacing the CLC409, care must be taken when the device is lightly loaded and some capacitance is present at the output. Due to the much higher frequency response of the LMH6702 compared to the CLC409, there could be increased susceptibility to low value output capacitance (parasitic or inherent to the board layout or otherwise being part of the output load). As already mentioned, this susceptibility is most noticeable when the LMH6702's resistive load is light. Parasitic capacitance can be minimized by careful lay out. Addition of an output snubber R-C network will also help by increasing the high frequency resistive loading. Referring back to Figure 4, it must be noted that several additional constraints should be considered in driving the capacitive input of an ADC. There is an option to increase RS, band-limiting at the ADC input for either noise or Nyquist Device Package Evaluation Board Part Number LMH6702QMLMF SOT23-5 CLC730216 LMH6702QMLMA Plastic SOIC CLC730227 PRINTED CIRCUIT LAYOUT Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations (see Application Note OA-15 for more information). National Semiconductor suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization: These free evaluation boards are shipped when a device sample request is placed with National Semiconductor. 9 www.national.com LMH6702QML band-limiting purposes. Increasing RS too much, however, can induce an unacceptably large input glitch due to switching transients coupling through from the "convert" signal. Also, CIN is oftentimes a voltage dependent capacitance. This input impedance non-linearity will induce distortion terms that will increase as RS is increased. Only slight adjustments up or down from the recommended RS value should therefore be attempted in optimizing system performance. LMH6702QML Revision History Date Released Revision Section Originator Changes 07/12/05 A New Corporate format Release R. Malone 1 MDS data sheet converted in corporate data sheet format. Added reference to QMLV products and Drift Table. MDS MNLMH6702–X, Rev. 1A0 will be archived. 09/28/05 B Features, Ordering Information Table R. Malone and Notes Added radiation reference to Features, Rad NSID & SMD to Ordering Table and Note 5 to AC & DC Electrical tables. Note 5 to note section. 11/07/05 C Update AC electrical's and Notes R. Malone Added note 6 to AC electrical's and note section. LMH6702QML Revision B data sheet will be archived. 07/26/2011 D Update Features, Ordering Information and Footnotes Larry M. Added 'High Dose Rate' 300 krad(Si) and ELDRS Free 300 krad(Si). Deleted NS Part numbers LMH6702J-QML and LMH6702WG-QML. Added NS Part number LMH6702WGFLQMLV.Modified footnote 5. LMH6702QML Revision C data sheet will be archived. 10/05/2011 E Update Ordering Information, and Footnotes Kirby K.. Added NS Part number LMH6702JFLQMLV 300 krad(Si) .Modified footnote 5 and footnote 6. Revision D data sheet will be archived. www.national.com 10 LMH6702QML Physical Dimensions inches (millimeters) unless otherwise noted 8 Lead Cerdip (J) NS Package Number J08A 10 Lead Ceramic SOIC NS Package Number WG10A 11 www.national.com LMH6702QML 1.7 GHz, LMH6702QML Ultra Low Distortion, Wideband Op Amp Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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