Fujitsu MB95166DPMC1 8-bit microcontroller Datasheet

FUJITSU MICROELECTRONICS
DATA SHEET
DS07-12618-2E
8-bit Microcontroller
CMOS
F2MC-8FX MB95160 Series
MB95F166D/166D/FV100D-101
■ DESCRIPTION
The MB95160 series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
• Timer
• 8/16-bit compound timer × 2 channels
Can be used to interval timer, PWC timer, PWM timer and input capture.
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 1 channel
• Timebase timer × 1 channel
• Watch prescaler × 1 channel
• LIN-UART × 1 channel
• LIN function, clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.3
MB95160 Series
(Continued)
• UART/SIO × 1 channel
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
•
• I2C × 1 channel
Built-in wake-up function
• External interrupt × 8 channels
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter × 8 channels
8-bit or 10-bit resolution can be selected.
• LCD controller (LCDC)
• 32 SEG × 4 COM (Max 128 pixels) (Built-in internal division resistance product)
• With blinking function
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
• I/O port
• The number of maximum ports : Max 53
• Port configuration
- General-purpose I/O ports (N-ch open drain) : 2 ports
- General-purpose I/O ports (CMOS)
: 51 ports
• Programmable input voltage levels of port
CMOS input level/hysteresis input level
• Flash memory security function (Flash memory device only)
Protects the content of Flash memory
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MB95160 Series
■ PRODUCT LINEUP
Part number
Parameter
Type
MB95F166D
MB95166D
Flash memory product
Mask ROM product
32 Kbytes
RAM capacity
1 Kbyte
Reset output
No
Option*
ROM capacity
Clock system
Dual clock
Low voltage
detection reset
CPU functions
No
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Peripheral functions
Interrupt processing time
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 61.5 ns (at machine clock frequency
16.25 MHz)
: 0.6 μs (at machine clock frequency
16.25 MHz)
Ports (Max 53 ports)
General-purpose I/O port (N-ch open drain) : 2 ports
General-purpose I/O port (CMOS)
: 51 ports
Programmable input voltage levels of port.
CMOS input level/hysteresis input level.
Timebase timer
(1 channel)
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog timer
Reset generated cycle
At main oscillation clock 10 MHz
: Min 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Wild register
Capable of replacing 3 bytes of ROM data
IC
(1 channel)
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
UART/SIO
(1 channel)
Data transfer capable in UART/SIO
Full duplex double buffer,
variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock synchronous (SIO) or clock asynchronous (UART) serial data transfer capable
LIN-UART
(1 channel)
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Capable of serial data transfer synchronous or asynchronous to clock signal.
LIN functions available as the LIN master or LIN slave.
2
(Continued)
DS07-12618-2E
3
MB95160 Series
(Continued)
Part number
Peripheral functions
Parameter
MB95F166D
MB95166D
8/10-bit
A/D converter
(8 channels)
8-bit or 10-bit resolution can be selected.
LCD controller
(LCDC)
COM output
: 4 (Max)
SEG output
: 32 (Max)
LCD drive power supply (bias) pin
:4
32 SEG × 4 COM : 128 pixels can be displayed. (Built-in internal division resistance
product)
Duty LCD mode
Operable in LCD standby mode
Built-in internal division resistance
With blinking function
8/16-bit compound
timer (2 channels)
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer ×
1 channel”.
Built-in timer function, PWC function, PWM function, capture function, and square
wave form output
Count clock : 7 internal clocks and external clock can be selected.
16-bit PPG
(1 channel)
PWM mode or one-shot mode can be selected.
Counter operating clock : Eight selectable clock sources
Support for external trigger start
8/16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG ×
1 channel”.
Counter operating clock : Eight selectable clock sources
Watch counter
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when
selecting clock source 1 second and setting counter value to 60)
Watch prescaler
(1 channel)
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
External interrupt
(8 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Flash memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Min) : 10000 times
Data retention time : 20 years
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
Standby mode
Sleep, stop, watch, and timebase timer
* : For details of option, refer to “■ MASK OPTION”.
Note : Part number of the evaluation product in MB95160 series is MB95FV100D-101 (internal division resistance
included) . When using it, the MCU board (MB2146-301A) is required.
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MB95160 Series
■ OSCILLATION STABILIZATION WAIT TIME
For the MASK ROM product, you can set the mask option when ordering MASK ROM to select the initial value
of main clock oscillation stabilization wait time from among the following four values.
Note that the evaluation and Flash memory products are fixed their initial value of main clock oscillation stabilization wait time at the maximum value.
Select of oscillation stabilization wait time
Remarks
(2 − 2) /FCH
0.5 μs (at main oscillation clock 4 MHz)
(212 − 2) /FCH
Approx. 1.02 ms (at main oscillation clock 4 MHz)
(213 − 2) /FCH
Approx. 2.05 ms (at main oscillation clock 4 MHz)
(2 − 2) /FCH
Approx. 4.10 ms (at main oscillation clock 4 MHz)
2
14
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
Package
MB95F166D
MB95FV100D-101
MB95166D
FPT-64P-M23
FPT-64P-M24
BGA-224P-M08
: Available
: Unavailable
DS07-12618-2E
5
MB95160 Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The evaluation product has not only the functions of the MB95160 series but also those of other products to
support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for
peripheral resources not used by the MB95160 series are therefore access-barred. Read/write access to these
access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in
unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or written unexpectedly).
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the
Flash memory products and Mask ROM products, do not use these values in the program.
The functions corresponding to certain bits in single-byte registers may not be supported on some Flash memory
products and Mask ROM products. However, reading or writing to these bits will not cause malfunction of the
hardware. Also, as the evaluation, Flash memory products and Mask ROM products are designed to have
identical software operation, no particular precautions are required.
• Difference of Memory Spaces
If the amount of memory on the evaluation product is different from that of the Flash memory products and Mask
ROM products, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS”
and “■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage is different among the evaluation, Flash memory products and Mask ROM products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”
• Difference MOD pins
A pull-down resistor is provided for the MOD pin of the Mask ROM product.
6
DS07-12618-2E
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVCC
AVR
P14/PPG0
P13/ADTG/TRG0
P12/UCK0
P11/UO0
P10/UI0
P24/SDA0/EC0
P23/SCL0/TO01
P22/TO00
P21/PPG01
P20/PPG00
MOD
X0
X1
VSS
DS07-12618-2E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PG0
X1A
X0A
RST
P90/V3
P91/V2
P92/V1
P93/V0
P94
P95
PA0/COM0
PA1/COM1
PA2/COM2
PA3/COM3
PB0/SEG00
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P00/INT00/AN00/SEG31
P01/INT01/AN01/SEG30
P02/INT02/AN02/SEG29
P03/INT03/AN03/SEG28
P04/INT04/AN04/SEG27
P05/INT05/AN05/SEG26
P06/INT06/AN06/SEG25
P07/INT07/AN07/SEG24
P67/SEG23/SIN
P66/SEG22/SOT
P65/SEG21/SCK
P64/SEG20/EC1
P63/SEG19/TO11
P62/SEG18/TO10
P61/SEG17/PPG11
AVSS
MB95160 Series
■ PIN ASSIGNMENT
(TOP VIEW)
LQFP-64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P60/SEG16/PPG10
PC7/SEG15
PC6/SEG14
PC5/SEG13
PC4/SEG12
PC3/SEG11
PC2/SEG10
PC1/SEG09
PC0/SEG08
PB7/SEG07
PB6/SEG06
PB5/SEG05
PB4/SEG04
PB3/SEG03
PB2/SEG02
PB1/SEG01
(FPT-64P-M23,FPT-64P-M24)
7
MB95160 Series
■ PIN DESCRIPTION
Pin no.
Pin name
I/O circuit
type*
1
AVCC
⎯
A/D converter power supply pin.
2
AVR
⎯
A/D converter reference input pin.
3
P14/PPG0
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 output.
4
P13/TRG0/
ADTG
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and
A/D trigger input (ADTG) .
5
P12/UCK0
6
P11/UO0
7
P10/UI0
8
P24/EC0/
SDA0
H
Function
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 clock I/O.
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data output.
G
I
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data input.
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 clock input
(EC0) and I2C ch.0 data I/O (SDA0) .
9
P23/TO01/
SCL0
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 output (TO01)
and I2C ch.0 clock I/O (SCL0) .
10
P22/TO00
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 output.
11
P21/PPG01
12
P20/PPG00
13
MOD
14
X0
15
X1
16
H
General-purpose I/O port.
The pin is shared with 8/16-bit PPG ch.0 output.
General-purpose I/O port.
The pin is shared with 8/16-bit PPG ch.0 output.
B
Operating mode designation pin.
A
Main clock oscillation pins.
VSS
⎯
Power supply pin (GND).
17
VCC
⎯
Power supply pin.
18
PG0
H
General-purpose I/O port.
19
X1A
20
X0A
A
Sub clock oscillation pins (32 kHz).
21
RST
B’
Reset pin.
22
P90/V3
23
P91/V2
24
P92/V1
R
General-purpose I/O ports.
The pins are shared with power supply pin for LCDC drive.
25
P93/V0
(Continued)
8
DS07-12618-2E
MB95160 Series
Pin no.
Pin name
26
P94
27
P95
28
PA0/COM0
29
PA1/COM1
30
PA2/COM2
31
PA3/COM3
32
PB0/SEG00
33
PB1/SEG01
34
PB2/SEG02
35
PB3/SEG03
36
PB4/SEG04
37
PB5/SEG05
38
PB6/SEG06
39
PB7/SEG07
40
PC0/SEG08
41
PC1/SEG09
42
PC2/SEG10
43
PC3/SEG11
44
PC4/SEG12
45
PC5/SEG13
46
PC6/SEG14
47
PC7/SEG15
48
P60/SEG16/
PPG10
49
P61/SEG17/
PPG11
50
P62/SEG18/
TO10
I/O circuit
type*
Function
S
General-purpose I/O ports.
M
General-purpose I/O ports.
The pins are shared with LCDC COM output (COM0 to COM3).
M
General-purpose I/O ports.
The pins are shared with LCDC SEG output (SEG00 to SEG07).
M
General-purpose I/O ports.
The pins are shared with LCDC SEG output (SEG08 to SEG15).
M
General-purpose I/O ports.
The pins are shared with LCDC SEG output (SEG16, SEG17) and
8/16-bit PPG ch.1 output (PPG10, PPG11) .
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG18) and 8/16-bit
compound timer ch.1 output (TO10) .
(Continued)
DS07-12618-2E
9
MB95160 Series
(Continued)
I/O circuit
type*
Pin name
51
P63/SEG19/
TO11
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG19) and 8/16-bit
compound timer ch.1 output (TO11) .
52
P64/SEG20/
EC1
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG20) and 8/16-bit
compound timer ch.1 clock input (EC1) .
M
*:
10
Function
Pin no.
53
P65/SEG21/
SCK
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG21) and LIN-UART
clock I/O (SCK) .
54
P66/SEG22/
SOT
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG22) and LIN-UART
data output (SOT) .
55
P67/SEG23/
SIN
56
P07/INT07/
AN07/SEG24
57
P06/INT06/
AN06/SEG25
58
P05/INT05/
AN05/SEG26
59
P04/INT04/
AN04/SEG27
60
P03/INT03/
AN03/SEG28
61
P02/INT02/
AN02/SEG29
62
P01/INT01/
AN01/SEG30
63
P00/INT00/
AN00/SEG31
64
AVSS
N
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG23) and LIN-UART
data input (SIN) .
F
General-purpose I/O port.
The pins are shared with external interrupt input (INT00 to INT07) ,
A/D analog input (AN00 to AN07) and LCDC SEG output (SEG24 to
SEG31) .
⎯
Power supply pin (GND) of A/D converter
For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
DS07-12618-2E
MB95160 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1 (X1A)
Clock input
X0 (X0A)
N-ch
Standby control
B
Mode input
R
B’
• Oscillation circuit
• High-speed side
Feedback resistance : approx. 1 MΩ
• Low-speed side
- Feedback resistance : approx. 24 MΩ
(Evaluation product : approx. 10 MΩ)
- Dumping resistance : approx.144 kΩ
(Evaluation product : without dumping
resistance)
• Only for input
• Hysteresis input only for Mask ROM product
• Pull-down resistor only for MODE pin of
Mask ROM product
Hysteresis input
Reset input
F
P-ch
N-ch
Digital output
Digital output
•
•
•
•
CMOS output
LCD output
Hysteresis input
Analog input
•
•
•
•
CMOS output
CMOS input
Hysteresis input
With pull-up control
Analog input
LCD output
A/D control
LCD control
Standby control
Hysteresis input
External interrupt
control
G
R
P-ch
Pull-up control
P-ch
N-ch
Digital output
Digital output
CMOS input
Standby control
Hysteresis input
(Continued)
DS07-12618-2E
11
MB95160 Series
Type
Circuit
Remarks
H
Pull-up control
R
P-ch
P-ch
N-ch
• CMOS output
• Hysteresis input
• With pull-up control
Digital output
Digital output
Hysteresis input
Standby control
I
N-ch
Digital output
• N-ch open drain output
• CMOS input
• Hysteresis input
CMOS input
Hysteresis input
Standby control
M
P-ch
Digital output
• CMOS output
• LCD output
• Hysteresis input
Digital output
N-ch
LCD output
LCD control
Standby control
Hysteresis input
N
P-ch
N-ch
Digital output
Digital output
•
•
•
•
CMOS output
LCD output
CMOS input
Hysteresis input
LCD output
CMOS input
Hysteresis input
LCD control
Standby control
R
P-ch
N-ch
Digital output
• CMOS output
• LCD power supply
• Hysteresis input
Digital output
LCD built-in division
resistance I/O
Standby control
LCD control
Hysteresis input
(Continued)
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MB95160 Series
(Continued)
Type
Circuit
Remarks
S
P-ch
N-ch
Standby control
DS07-12618-2E
Digital output
• CMOS output
• Hysteresis input
Digital output
Hysteresis input
13
MB95160 Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the Vcc power-supply voltage.
For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range
(50/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
• Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of
receiving wrong data due to the noise.
PIN CONNECTION
• Treatment of Unused Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused
input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused
input pins. If there is unused output pin, make it to open.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS pins
near this device.
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the MOD pin to VCC or VSS and to provide a low-impedance connection.
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MB95160 Series
• Analog Power Supply
Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00
to AN07 pins.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 μF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
DS07-12618-2E
15
MB95160 Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
FPT-64P-M23
TEF110-95F168HPMC
FPT-64P-M24
TEF110-95F168HPMC1
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
Flash memory
CPU address
8000H
Programmer address*
18000H
FFFFH
1FFFFH
32 Kbytes
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
• Programming Method
1) Set the type code of the parallel programmer to “17222”.
2) Load program data to programmer addresses 18000H to 1FFFFH.
3) Programmed by parallel programmer
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MB95160 Series
■ BLOCK DIAGRAM
F2MC-8FX CPU
RST
X0, X1
X0A, X1A
Reset control
ROM
RAM
Clock control
Interrupt control
Watch prescaler
PG0
P00/INT00 to
P07/INT07
Wild register
Watch counter
External interrupt
8/16-bit PPG ch.1
P10/UI0
P11/UO0
UART/SIO
8/16-bit
compound timer ch.1
P13/TRG0/ADTG
P14/PPG0
P20/PPG00
P21/PPG01
16-bit PPG
8/16-bit PPG ch.0
Internal bus
P12/UCK0
P24/EC0/SDA0
P61/SEG17/PPG11
P62/SEG18/TO10
P63/SEG19/TO11
P64/SEG20/EC1
P65/SEG21/SCK
LIN-UART
P66/SEG22/SOT
P67/SEG23/SIN
P90/V3 to P93/V0
P22/TO00
P23/TO01/SCL0
P60/SEG16/PPG10
8/16-bit
compound timer ch.0
LCDC
PA0/COM0 to PA3/COM3
PB0/SEG00 to PB7/SEG07
PC0/SEG08 to PC7/SEG15
I2C
(P00/SEG31 to P07/SEG24)
(P00/AN00 to
P07/AN07)
AVCC
AVSS
8/10-bit
A/D converter
P94, P95
AVR
Port
Port
Other pins
MOD, VSS, VCC
DS07-12618-2E
17
MB95160 Series
■ CPU CORE
1. Memory space
Memory space of the MB95160 series is 64 Kbytes and consists of I/O area, data area, and program area. The
memory space includes special-purpose areas such as the general-purpose registers and vector table.
• Memory Map
MB95F166D
MB95FV100D-101
0000H
0000H
I/O
0080H
RAM 1 Kbyte
0100H Register
0200H
MB95166D
0000H
I/O
I/O
0080H
RAM 3.75 Kbytes
0100H Register
0200H
0480H
0080H
RAM 1 Kbyte
0100H Register
0200H
0480H
Access
prohibited
Access
prohibited
0F80H
0F80H
0F80H
Exterded I/O
Extended I/O
1000H
1000H
Extended I/O
1000H
Access
prohibited
Access
prohibited
8000H
8000H
Flash memory
60 Kbytes
Flash memory
32 Kbytes
FFFFH
18
Mask ROM
32 Kbytes
FFFFH
FFFFH
DS07-12618-2E
MB95160 Series
2. Register
The MB95160 series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored.
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1 byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1 byte is used.
Index register (IX)
: A 16-bit register for index modification.
Extra pointer (EP)
: A 16-bit pointer to point to a memory address.
Stack pointer (SP)
: A 16-bit register to indicate a stack area.
Program status (PS)
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register.
Initial Value
16-bit
PC
: Program counter
FFFDH
AH
AL
: Accumulator
0000H
TH
TL
: Temporary accumulator
0000H
IX
: Index register
0000H
EP
: Extra pointer
0000H
SP
: Stack pointer
0000H
PS
: Program status
0030H
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR) .
• Structure of the Program Status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
PS
R4
R3
R2
RP
DS07-12618-2E
R1
R0
DP2
DP1
DP
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DP0
H
I
IL1
IL0
N
Z
V
C
CCR
19
MB95160 Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
"0"
"0"
"0"
"0"
"0"
"0"
"0"
"1"
R4
Generated address A15 A14 A13 A12 A11 A10 A9
A8
A7
R3
A6
R2
A5
R1
A4
OP code lower
R0
A3
b2
b1
A2
b0
A1
A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
XXXB (no effect to mapping)
0000H to 007FH
0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH (without mapping)
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0080H to 00FFH
100B
0200H to 027FH
0280H to 02FFH
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is set to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
IL0
Interrupt level
Priority
0
0
0
High
0
1
1
1
0
2
1
1
3
N flag
Z flag
V flag
C flag
20
Low (no interruption)
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
: Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
DS07-12618-2E
MB95160 Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains
8-register. Up to a total of 32 banks can be used on the MB95160 series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
Address 100H
R0
R0
R0
R1
R2
R3
R4
R5
107H
R6
R1
R2
R3
R4
R5
R6
R1
R2
R3
R4
R5
R6
1FFH
R7
R7
R7
Bank 0
Memory area
DS07-12618-2E
Bank 31
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
21
MB95160 Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
⎯
(Disabled)
⎯
⎯
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
1010X011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset factor register
R/W
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
⎯
(Disabled)
⎯
⎯
000EH
PDR2
Port 2 data register
R/W
00000000B
000FH
DDR2
Port 2 direction register
R/W
00000000B
0010H
to
0015H
⎯
(Disabled)
⎯
⎯
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
001BH
⎯
(Disabled)
⎯
⎯
001CH
PDR9
Port 9 data register
R/W
00000000B
001DH
DDR9
Port 9 direction register
R/W
00000000B
001EH
PDRA
Port A data register
R/W
00000000B
001FH
DDRA
Port A direction register
R/W
00000000B
0020H
PDRB
Port B data register
R/W
00000000B
0021H
DDRB
Port B direction register
R/W
00000000B
0022H
PDRC
Port C data register
R/W
00000000B
0023H
DDRC
Port C direction register
R/W
00000000B
0024H
to
0029H
⎯
(Disabled)
⎯
⎯
(Continued)
22
DS07-12618-2E
MB95160 Series
Address
Register
abbreviation
Register name
R/W
Initial value
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
⎯
(Disabled)
⎯
⎯
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
PUL2
Port 2 pull-up register
R/W
00000000B
002FH
to
0034H
⎯
(Disabled)
⎯
⎯
0035H
PULG
Port G pull-up control register
R/W
00000000B
0036H
T01CR1
8/16-bit compound timer 01 control status register 1 ch.0
R/W
00000000B
0037H
T00CR1
8/16-bit compound timer 00 control status register 1 ch.0
R/W
00000000B
0038H
T11CR1
8/16-bit compound timer 11 control status register 1 ch.1
R/W
00000000B
0039H
T10CR1
8/16-bit compound timer 10 control status register 1 ch.1
R/W
00000000B
003AH
PC01
8/16-bit PPG1 control register ch.0
R/W
00000000B
003BH
PC00
8/16-bit PPG0 control register ch.0
R/W
00000000B
003CH
PC11
8/16-bit PPG1 control register ch.1
R/W
00000000B
003DH
PC10
8/16-bit PPG0 control register ch.1
R/W
00000000B
003EH
to
0041H
⎯
(Disabled)
⎯
⎯
0042H
PCNTH0
16-bit PPG status control register (upper byte) ch.0
R/W
00000000B
0043H
PCNTL0
16-bit PPG status control register (lower byte) ch.0
R/W
00000000B
0044H
to
0047H
⎯
(Disabled)
⎯
⎯
0048H
EIC00
External interrupt circuit control register ch.0/ch.1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch.2/ch.3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch.4/ch.5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch.6/ch.7
R/W
00000000B
004CH
to
004FH
⎯
(Disabled)
⎯
⎯
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART reception/transmission data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
(Continued)
DS07-12618-2E
23
MB95160 Series
Address
Register
abbreviation
Register name
R/W
Initial value
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch.0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch.0
R/W
00100000B
0058H
SSR0
UART/SIO serial status register ch.0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch. 0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch.0
R
00000000B
005BH
to
005FH
⎯
(Disabled)
⎯
⎯
0060H
IBCR00
I2C bus control register 0 ch.0
R/W
00000000B
R/W
00000000B
0061H
IBCR10
2
I C bus control register 1 ch.0
2
0062H
IBSR0
I C bus status register ch.0
R
00000000B
0063H
IDDR0
I2C data register ch.0
R/W
00000000B
0064H
IAAR0
I2C address register ch.0
R/W
00000000B
2
0065H
ICCR0
I C clock control register ch.0
R/W
00000000B
0066H
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (upper byte)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (lower byte)
R/W
00000000B
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
⎯
(Disabled)
⎯
⎯
0072H
FSR*
Flash memory status register
R/W
000X0000B
0073H
⎯
(Disabled)
⎯
⎯
0074H
⎯
(Disabled)
⎯
⎯
0075H
⎯
(Disabled)
⎯
⎯
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
⎯
Register bank pointer (RP) ,
Mirror of direct bank pointer (DP)
⎯
⎯
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
(Continued)
24
DS07-12618-2E
MB95160 Series
Address
Register
abbreviation
Register name
R/W
Initial value
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
⎯
(Disabled)
⎯
⎯
0F80H
WRARH0
Wild register address setting register (upper byte) ch.0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower byte) ch.0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch.0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper byte) ch.1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower byte) ch.1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch.1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper byte) ch.2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower byte) ch.2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch.2
R/W
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch.0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch.0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch.0
R/W
00000000B
0F95H
T00DR
8/16-bit compound timer 00 data register ch.0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control
register ch.0
R/W
00000000B
0F97H
T11CR0
8/16-bit compound timer 11 control status register 0 ch.1
R/W
00000000B
0F98H
T10CR0
8/16-bit compound timer 10 control status register 0 ch.1
R/W
00000000B
0F99H
T11DR
8/16-bit compound timer 11 data register ch.1
R/W
00000000B
0F9AH
T10DR
8/16-bit compound timer 10 data register ch.1
R/W
00000000B
0F9BH
TMCR1
8/16-bit compound timer 10/11 timer mode control
register ch.1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG1 cycle setting buffer register ch.0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG0 cycle setting buffer register ch.0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG1 duty setting buffer register ch.0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG0 duty setting buffer register ch.0
R/W
11111111B
0FA0H
PPS11
8/16-bit PPG1 cycle setting buffer register ch.1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG0 cycle setting buffer register ch.1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG1 duty setting buffer register ch.1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG0 duty setting buffer register ch.1
R/W
11111111B
0FA4H
PPGS
8/16-bit PPG start register
R/W
00000000B
(Continued)
DS07-12618-2E
25
MB95160 Series
Address
Register
abbreviation
Register name
R/W
Initial value
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
0FA6H
to
0FA9H
⎯
(Disabled)
⎯
⎯
0FAAH
PDCRH0
16-bit PPG down counter register (upper byte) ch.0
R
00000000B
0FABH
PDCRL0
16-bit PPG down counter register (lower byte) ch.0
R
00000000B
0FACH
PCSRH0
16-bit PPG cycle setting buffer register (upper byte) ch.0
R/W
11111111B
0FADH
PCSRL0
16-bit PPG cycle setting buffer register (lower byte) ch.0
R/W
11111111B
0FAEH
PDUTH0
16-bit PPG duty setting buffer register (upper byte) ch.0
R/W
11111111B
0FAFH
PDUTL0
16-bit PPG duty setting buffer register (lower byte) ch.0
R/W
11111111B
0FB0H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO dedicated baud rate generator prescaler selecting
register ch.0
R/W
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator setting register ch.0
R/W
00000000B
0FC0H
to
0FC2H
⎯
(Disabled)
⎯
⎯
0FC3H
AIDRL
A/D input disable register (lower byte)
R/W
00000000B
0FC4H
LCDCC
LCDC control register
R/W
00010000B
0FC5H
LCDCE1
LCDC enable register 1
R/W
00110000B
0FC6H
LCDCE2
LCDC enable register 2
R/W
00000000B
0FC7H
LCDCE3
LCDC enable register 3
R/W
00000000B
0FC8H
LCDCE4
LCDC enable register 4
R/W
00000000B
0FC9H
LCDCE5
LCDC enable register 5
R/W
00000000B
0FCAH
⎯
(Disabled)
⎯
⎯
0FCBH
LCDCB1
LCDC blinking setting register 1
R/W
00000000B
0FCCH
LCDCB2
LCDC blinking setting register 2
R/W
00000000B
0FCDH
to
0FDCH
LCDRAM
LCDC display RAM
R/W
00000000B
0FDDH
to
0FE2H
⎯
(Disabled)
⎯
⎯
0FE3H
WCDR
Watch counter data register
R/W
00111111B
(Continued)
26
DS07-12618-2E
MB95160 Series
(Continued)
Address
Register
abbreviation
Register name
R/W
Initial value
0FE4H
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
ILSR
Input level selecting register
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable/Writable
R
: Read only
W
: Write only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
* : Only for Flash product
DS07-12618-2E
27
MB95160 Series
■ INTERRUPT SOURCE TABLE
Interrupt source
Interrupt
request
number
Vector table address
Same level
Bit name of
priority order
interrupt level
(at simultaneous
setting register
occurrence)
Upper
Lower
IRQ0
FFFAH
FFFBH
L00 [1 : 0]
IRQ1
FFF8H
FFF9H
L01 [1 : 0]
IRQ2
FFF6H
FFF7H
L02 [1 : 0]
IRQ3
FFF4H
FFF5H
L03 [1 : 0]
UART/SIO ch.0
IRQ4
FFF2H
FFF3H
L04 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
IRQ5
FFF0H
FFF1H
L05 [1 : 0]
8/16-bit compound timer ch.0 (Upper)
IRQ6
FFEEH
FFEFH
L06 [1 : 0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1 : 0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1 : 0]
8/16-bit PPG ch.1 (Lower)
IRQ9
FFE8H
FFE9H
L09 [1 : 0]
8/16-bit PPG ch.1 (Upper)
IRQ10
FFE6H
FFE7H
L10 [1 : 0]
(Unused)
IRQ11
FFE4H
FFE5H
L11 [1 : 0]
8/16-bit PPG ch.0 (Upper)
IRQ12
FFE2H
FFE3H
L12 [1 : 0]
8/16-bit PPG ch.0 (Lower)
IRQ13
FFE0H
FFE1H
L13 [1 : 0]
8/16-bit compound timer ch.1 (Upper)
IRQ14
FFDEH
FFDFH
L14 [1 : 0]
16-bit PPG ch.0
IRQ15
FFDCH
FFDDH
L15 [1 : 0]
I2C ch.0
IRQ16
FFDAH
FFDBH
L16 [1 : 0]
(Unused)
IRQ17
FFD8H
FFD9H
L17 [1 : 0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1 : 0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1 : 0]
Watch prescaler/Watch counter
IRQ20
FFD2H
FFD3H
L20 [1 : 0]
(Unused)
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
8/16-bit compound timer ch.1 (Lower)
IRQ22
FFCEH
FFCFH
L22 [1 : 0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1 : 0]
External interrupt ch.0
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
28
High
Low
DS07-12618-2E
MB95160 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*
Rating
Symbol
1
Power supply voltage for
LCD
Unit
Remarks
Min
Max
VCC,
AVCC
Vss − 0.3
Vss + 4.0
AVR
Vss − 0.3
Vss + 4.0
V0 to V3
VSS − 0.3
VSS + 4.0
V
*3
Vss − 0.3
Vss + 6.0
V
P23, P24*4
Vss − 0.3
Vss + 4.0
V
Other than P23, P24*4
*4
V
*2
*2
Input voltage*1
VI
Output voltage*1
VO
Vss − 0.3
Vss + 4.0
V
ICLAMP
− 2.0
+ 2.0
mA
Applicable to pins*5
Σ|ICLAMP|
⎯
20
mA
Applicable to pins*5
IOL
⎯
15
mA
Applicable to pins*5
Applicable to pins*5
Average output current =
operating current × operating ratio
(1 pin)
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
“L” level average
current
IOLAV
⎯
4
mA
“L” level total maximum
output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
Total average output current =
operating current × operating ratio
(Total of pins)
IOH
⎯
− 15
mA
Applicable to pins*5
Applicable to pins*5
Average output current =
operating current × operating ratio
(1 pin)
“L” level total average
output current
“H” level maximum
output current
“H” level average
current
IOHAV
⎯
−4
mA
“H” level total maximum
output current
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Power consumption
Pd
⎯
320
mW
Operating temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 150
°C
“H” level total average
output current
Storage temperature
Total average output current =
operating current × operating ratio
(Total of pins)
*1 : The parameter is based on VSS = 0.0 V.
*2 : Apply equal potential to AVCC and VCC. AVR should not exceed AVCC + 0.3 V.
(Continued)
DS07-12618-2E
29
MB95160 Series
(Continued)
*3 : V0 to V3 should not exceed VCC + 0.3 V.
*4 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current
to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*5 : Applicable to pins :
P00 to P07, P10 to P14, P20 to P22,P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7
• Use within recommended operating conditions.
• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept
+ B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
+ B input (0 V to 16 V)
Vcc
Limiting
resistance
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
30
DS07-12618-2E
MB95160 Series
2. Recommended Operating Conditions
(Vss = 0.0 V)
Parameter
Power supply
voltage
Symbol
Conditions
VCC,
AVCC
Value
Unit
Typ
Max
1.8*
⎯
3.3
At normal operating,
TA = − 10 °C to + 85 °C
2.0*
⎯
3.3
At normal operating,
TA = − 40 °C to + 85 °C
V
2.6
⎯
3.6
MB95FV100D-101,
TA = + 5 °C to + 35 °C
1.5
⎯
3.3
Retain status of stop mode
operation
⎯
Power supply
voltage for LCD
V0 to V3
VSS
⎯
VCC
V
A/D converter
reference input
voltage
AVR
1.8
⎯
AVCC
V
TA
− 40
⎯
+ 85
°C
Operating
temperature
Remarks
Min
The optimal value depends
on liquid crystal display
elements used.
* : The values vary with the operating frequency, machine clock or analog guarantee range.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
DS07-12618-2E
31
MB95160 Series
3. DC Characteristics
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Typ
Max
Unit
Remarks
When selecting
CMOS input level
VIH1
P10, P67
⎯
0.7 VCC
⎯
VCC + 0.3
V
VIH2
P23, P24
⎯
0.7 VCC
⎯
VSS + 6.0
V
VIHS1
P00 to P07,
P10 to P14,
P20 to P22,
P60 to P67,
P90 to P95,
PA0 to PA3,
PB0 to PB7,
PC0 to PC7
⎯
0.8 VCC
⎯
VCC + 0.3
V
⎯
0.8 VCC
⎯
VSS + 5.5
V
0.7 VCC
⎯
VCC + 0.3
V
CMOS input
(Flash Memory
product)
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
(Mask ROM
product)
“H” level input
voltage
VIHS2 P23, P24
VIHM RST, MOD
⎯
Hysteresis input
VIL
P10,P23,
P24,P67
⎯
VSS − 0.3
⎯
0.3 VCC
V
When selecting
CMOS input level
VILS
P00 to P07,
P10 to P14,
P20 to P24,
P60 to P67,
P90 to P95,
PA0 to PA3,
PB0 to PB7,
PC0 to PC7
⎯
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
(Mask ROM
product)
VSS − 0.3
⎯
0.3 VCC
V
CMOS input
(Flash Memory
product)
“L” level input
voltage
VILM RST, MOD
⎯
“H” level
output voltage
VOH
Output pins
other than
P23, P24
IOH = 4.0 mA
2.4
⎯
⎯
V
“L” level output
voltage
VOL
Output pins
other than RST
IOL = 4.0 mA
⎯
⎯
0.4
V
Input leakage
current (Hi-Z
output leakage
current)
ILI
Ports other than
P23, P24
0.0 V < VI < VCC
−5
⎯
+5
μA
When the pull-up
prohibition setting
(Continued)
32
DS07-12618-2E
MB95160 Series
Parameter
Open-drain
output leakage
current
Symbol
ILIOD P23, P24
Pull-up resistor RPULL
Pull-down resistor
Input
capacitance
Pin name
P10 to P14,
P20 to P22
RMOD MOD
CIN
Other than AVCC,
AVSS, AVR,
VCC, VSS
(Vcc = 3.3 V,Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Conditions
Unit
Remarks
Min Typ Max
0.0 V < VI <
VSS + 5.5 V
⎯
⎯
5
μA
VI = 0.0 V
25
50
100
kΩ
VI = Vcc
25
50
100
kΩ Mask ROM product
f = 1 MHz
⎯
5
15
pF
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
ICC
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
VCC
(External clock
operation)
When the pull-up
permission setting
⎯
11.0
14.0
MB95F166D
At other than Flash
mA
memory writing
and erasing
⎯
30.0
35.0
MB95F166D
mA At Flash memory
writing and erasing
⎯
7.3
10.0
mA MB95166D
⎯
17.6
22.4
MB95F166D
At other than Flash
mA
memory writing
and erasing
⎯
38.1
44.9
MB95F166D
mA At Flash memory
writing and erasing
⎯
11.7
16.0
mA MB95166D
FCH = 20 MHz
FMP = 10 MHz
Main Sleep mode
(divided by 2)
⎯
4.5
6.0
mA
FCH = 32 MHz
FMP = 16 MHz
Main Sleep mode
(divided by 2)
⎯
7.2
9.6
mA
ICCL
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2)
⎯
25
35
μA
ICCLS
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2)
⎯
7
15
μA
Power supply
current*
ICCS
(Continued)
DS07-12618-2E
33
MB95160 Series
(Continued)
Parameter
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
Remarks
10
μA
Flash memory
product
1
5
μA
MASK ROM
product
⎯
10
14
mA
Flash memory
product
⎯
6.7
10
mA
MASK ROM
product
⎯
16.0
22.4
mA
Flash memory
product
⎯
10.8
16.0
mA
MASK ROM
product
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
⎯
190
250
μA
ICTS
FCH = 10 MHz
Timebase timer mode
TA = + 25 °C
⎯
0.4
0.5
mA
ICCH
Sub stop mode
TA = + 25 °C
⎯
1
5
μA
FCH = 16 MHz
At operating of A/D
conversion
⎯
1.3
2.2
mA
FCH = 16 MHz
At stopping of A/D
conversion
TA = + 25 °C
⎯
1
5
μA
Between V3 and VSS
⎯
300
⎯
kΩ
⎯
⎯
5
kΩ
⎯
⎯
7
kΩ
−1
⎯
+1
μA
ICCMPLL
VCC
(External clock
operation)
Power supply
current*
Value
Unit
ICCT
ICCSPLL
IA
AVCC
IAH
LCD internal
division resistance
RLCD
⎯
COM0 to COM3
output impedance
RVCOM
COM0 to COM3
SEG00 to SEG31
output impedance
RVSEG SEG00 to SEG31
LCD leak current
ILCDL
Conditions
Min
Typ
Max
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
⎯
2
⎯
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
V1 to V3 = 5.0 V
V0 to V3,
COM0 to COM3
SEG00 to SEG31
⎯
* : • The power-supply current is determined by the external clock.
• Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
34
DS07-12618-2E
MB95160 Series
4. AC Characteristics
(1) Clock Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
SymPin name Conditions
bol
FCH
X0, X1
Clock frequency
FCL
X0A, X1A
⎯
tHCYL
X0, X1
Clock cycle time
Input clock pulse
width
Input clock rise time
and fall time
DS07-12618-2E
Value
Unit
Remarks
16.25
MHz
When using main
oscillation circuit
⎯
32.50
MHz When using external clock
3.00
⎯
10.00
MHz Main PLL multiplied by 1
3.00
⎯
8.13
MHz Main PLL multiplied by 2
3.00
⎯
6.50
MHz Main PLL multiplied by 2.5
3.00
⎯
4.06
MHz Main PLL multiplied by 4
⎯
32.768
⎯
kHz
When using sub
oscillation circuit
⎯
32.768
⎯
kHz
When using sub PLL
61.5
⎯
1000
ns
When using oscillation
circuit
30.8
⎯
1000
ns
When using external clock
Min
Typ
Max
1.00
⎯
1.00
tLCYL
X0A, X1A
⎯
30.5
⎯
μs
When using sub clock,
When using external clock
tWH1
tWL1
X0
61.5
⎯
⎯
ns
tWH2
tWL2
X0A
⎯
15.2
⎯
μs
When using external clock
Duty ratio is about 30% to
70%.
tCR
tCF
X0, X0A
⎯
⎯
5
ns
When using external clock
35
MB95160 Series
• Input wave form at external clock use (main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of Main Clock Input Port External Connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
FCH
C1
C2
• Input wave form at external clock use (sub clock)
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Figure of Sub clock Input Port External Connection
When using a crystal or
ceramic oscillator
Microcontroller
X0A
X1A
When using external clock
Microcontroller
X0A
FCL
X1A
Open
FCL
C1
36
C2
DS07-12618-2E
MB95160 Series
(2) Source Clock/Machine Clock
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Source clock
cycle time*1
(Clock before
setting division)
Source clock
frequency
Machine clock
cycle time*2
(Minimum
instruction
execution time)
Machine clock
frequency
Symbol
Conditions
Value
Min
Typ
Max
Unit
Remarks
61.5
⎯
2000
ns
When using main clock
Min : FCH = 8.125 MHz,
PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2
7.6
⎯
61.0
μs
When using sub clock
Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
0.50
⎯
16.25
MHz When using main clock
16.384
⎯
131.072
kHz When using sub clock
61.5
⎯
32000
ns
When using main clock
Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
7.6
⎯
976.5
μs
When using sub clock
Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
FMP
0.031
⎯
16.250
MHz When using main clock
FMPL
1.024
⎯
131.072
kHz When using sub clock
tSCLK
FSP
FSPL
⎯
tMCLK
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
DS07-12618-2E
37
MB95160 Series
• Outline of clock generation block
FCH
(main oscillation)
Divided by 2
Main PLL
×1
×2
× 2.5
×4
SCLK
( source clock )
FCL
(sub oscillation)
Divided by 2
Sub PLL
×2
×3
×4
38
Division
circuit
×1
× 1/4
× 1/8
× 1/16
MCLK
( machine clock )
Clock mode select bit
( SYCC : SCS1, SCS0 )
DS07-12618-2E
MB95160 Series
• Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C)
• MB95166D
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.6
2.3
1.8
16.384 kHz
32 kHz
131.072 kHz
Operating voltage (V)
Operating voltage (V)
3.6
2.7
1.8
0.5 MHz 3 MHz 5 MHz
PLL operation guarantee range
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSP)
• MB95F166D
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
2.3
1.8
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Source clock frequency (FSP)
DS07-12618-2E
Operating voltage (V)
Operating voltage (V)
3.3
3.3
2.7
1.8
0.5 MHz 3 MHz 5 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
39
MB95160 Series
• Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C)
• MB95166D
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.6
2.3
1.8
16.384 kHz
32 kHz
131.072 kHz
Operating voltage (V)
Operating voltage (V)
3.6
2.7
1.8
0.5 MHz 3 MHz
PLL operation guarantee range
7.5 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSP)
• MB95F166D
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
2.3
2.0
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Source clock frequency (FSP)
40
Operating voltage (V)
Operating voltage (V)
3.3
3.3
2.7
2.0
0.5 MHz 3 MHz
7.5 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
DS07-12618-2E
MB95160 Series
• Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C)
• MB95FV100D-101
Main clock mode and main PLL mode
operation guarantee range
Operating voltage (V)
Operating voltage (V)
Sub PLL , Sub clock mode and
watch mode operation guarantee range
3.6
2.6
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Source clock frequency (FSP)
DS07-12618-2E
3.6
3.3
2.6
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
41
MB95160 Series
• Main PLL operation frequency
[MHz]
16.25
16
15
×4
12
Source clock frequency (FSP)
× 2.5
10
×1
×2
7.5
6
5
3
0
3
4
4.062
5
6.4
6.5
8
8.125
10 [MHz]
Machine clock frequency (FMP)
42
DS07-12618-2E
MB95160 Series
(3) External Reset
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
RST “L” level
pulse width
tRSTL
Pin
name
Value
Conditions
RST
⎯
Min
Max
2 tMCLK*1
⎯
Oscillation time of oscillator*2
+ 100
⎯
Unit
Remarks
ns
At normal operating
μs
At stop mode, sub
clock mode,
sub sleep mode,
and watch mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation
time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of
μs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
RST
tRSTL
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
2 tMCLK
Oscillation time Oscillation stabilization wait time
of oscillator
Execute instruction
Internal reset
DS07-12618-2E
43
MB95160 Series
(4) Power-on Reset
(Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Power supply
rising time
tR
Power supply
cutoff time
tOFF
Pin
name
Value
Conditions
Unit
Min
Max
⎯
36
ms
1
⎯
ms
⎯
VCC
tR
Remarks
Waiting time until
power-on
tOFF
1.5 V
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 20 mV/ms as shown below.
VCC
Limiting the slope of rising within
20 mV/ms is recommended.
1.5 V
Hold condition in stop mode
VSS
44
DS07-12618-2E
MB95160 Series
(5) Peripheral Input Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Peripheral input
“H” pulse width
tILIH
Peripheral input
“L” pulse width
tIHIL
Pin name
INT00 to INT07,
EC0, EC1, TRG0/ADTG
Conditions
Value
Unit
Min
Max
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
EC0, EC1,
TRG0/ADTG
DS07-12618-2E
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
45
MB95160 Series
(6) UART/SIO, Serial I/O Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
Serial clock “H” pulse width
tSHSL
UCK0
Serial clock “L” pulse width
tSLSH
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
Value
Conditions
Internal clock
operation
output pin : CL = 80 pF
+ 1TTL.
External clock
operation
output pin : CL = 80 pF
+ 1TTL.
Unit
Min
Max
4 tMCLK*
⎯
ns
− 190
+ 190
ns
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
4 tMCLK*
⎯
ns
4 tMCLK*
⎯
ns
⎯
190
ns
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
UCK0
2.4 V
0.8 V
0.8 V
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC 0.8 VCC
UCK0
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
46
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
DS07-12618-2E
MB95160 Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Serial clock cycle time
SymPin name
bol
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
Value
Conditions
Max
5 tMCLK*3
⎯
ns
+ 95
ns
⎯
ns
⎯
ns
3 tMCLK*3 − tR
⎯
ns
* + 95
⎯
ns
SCK
Internal clock
SCK, SOT
−95
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL. tMCLK*3 + 190
SCK, SIN
0
SCK
SCK
Unit
Min
t
MCLK 3
⎯
* + 95
SCK ↓ → SOT delay time
tSLOVE SCK, SOT
Valid SIN → SCK ↑
tIVSHE
SCK, SIN
SCK ↑ → valid SIN hold time
tSHIXE
SCK, SIN
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
External clock
operation output pin :
CL = 80 pF + 1 TTL.
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
DS07-12618-2E
47
MB95160 Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
tSLSH
SCK
0.8 VCC
0.2 VCC
tF
SOT
0.8 VCC
0.2 VCC
tR
tSLOVE
2.4 V
0.8 V
tIVSHE
SIN
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
48
DS07-12618-2E
MB95160 Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Conditions
Internal clock
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
* + 190
Valid SIN → SCK ↓
tIVSLI
SCK ↓ → valid SIN hold time
tSLIXI
Serial clock “H” pulse width
tSHSL
SCK
3 tMCLK*3 − tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3 + 95
⎯
ns
SCK, SOT
⎯
SCK ↑ → SOT delay time
tSHOVE
Valid SIN → SCK ↓
tIVSLE
SCK ↓ → valid SIN hold time
tSLIXE
External clock
SCK, SIN operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
t
MCLK 3
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of
the serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
DS07-12618-2E
49
MB95160 Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
SCK
0.8 VCC
tSLSH
0.8 VCC
0.2 VCC
tR
SOT
0.2 VCC
0.2 VCC
tF
tSHOVE
2.4 V
0.8 V
tIVSLE
SIN
tSLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
50
DS07-12618-2E
MB95160 Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Conditions
Valid SIN → SCK ↓
tIVSLI
SCK, SIN
SCK ↓ → valid SIN hold time
tSLIXI
SCK, SIN
SOT → SCK ↓ delay time
tSOVLI
SCK, SOT
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
* + 190
MCLK 3
t
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of
the serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
SIN
DS07-12618-2E
0.8 V
tSHOVI
tSOVLI
0.8 VCC
0.2 VCC
tSLIXI
0.8 VCC
0.2 VCC
51
MB95160 Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Parameter
Value
Conditions
Unit
Min
Max
SCK
5 tMCLK*3
⎯
ns
SCK, SOT
−95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Internal clock
SCK, SIN operation output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
SOT → SCK ↑ delay time
tSOVHI
SCK, SOT
t
* + 190
MCLK 3
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSHI
SIN
52
tSLOVI
0.8 VCC
0.2 VCC
tSHIXI
0.8 VCC
0.2 VCC
DS07-12618-2E
MB95160 Series
(8) I2C Timing
(VCC = 3.3 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
SCL clock frequency
Pin
name
Conditions Standard-mode
Fast-mode
Min
Max
Min
Max
Unit
fSCL
SCL0
0
100
0
400
kHz
tHD;STA
SCL0
SDA0
4.0
⎯
0.6
⎯
μs
SCL clock “L” width
tLOW
SCL0
4.7
⎯
1.3
⎯
μs
SCL clock “H” width
tHIGH
SCL0
4.0
⎯
0.6
⎯
μs
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
tSU;STA
SCL0
SDA0
4.7
⎯
0.6
⎯
μs
Data hold time SCL ↓ → SDA ↓ ↑
tHD;DAT
SCL0
SDA0
0
3.45*2
0
0.9*3
μs
Data setup time SDA ↓ ↑ → SCL ↑
tSU;DAT
SCL0
SDA0
0.25*4
⎯
0.1*4
⎯
μs
Stop condition setup time SCL ↑ →
SDA ↑
tSU;STO
SCL0
SDA0
4.0
⎯
0.6
⎯
μs
tBUF
SCL0
SDA0
4.7
⎯
1.3
⎯
μs
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
Bus free time between stop
condition and start condition
R = 1.7 kΩ,
C = 50 pF*1
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.
*4 : Refer to “ • Note of SDA and SCL set-up time”.
• Note of SDA and SCL set-up time
0.7 VCC
SDA0
Input data set-up time
SCL0
6 tcp
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on
the load capacitance or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be
satisfied.
DS07-12618-2E
53
MB95160 Series
tWAKEUP
SDA0
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL0
tHD;STA
54
tSU;DAT
tSU;STA
tSU;STO
DS07-12618-2E
MB95160 Series
(VCC = 3.3 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Sym- Pin
bol name
Conditions
Value*2
Min
Max
Unit
Remarks
SCL clock
“L” width
tLOW
SCL0
(2 + nm / 2) tMCLK − 20
⎯
ns
Master mode
SCL clock
“H” width
tHIGH
SCL0
(nm / 2) tMCLK − 20
(nm / 2 ) tMCLK + 20
ns
Master mode
Start condition
SCL0
tHD;STA
hold time
SDA0
(−1 + nm / 2) tMCLK − 20
(−1 + nm) tMCLK + 20
ns
Master mode
Maximum value is
applied when m,
n = 1, 8.
Otherwise, the
minimum value is
applied.
Stop condition
SCL0
tSU;STO
setup time
SDA0
(1 + nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Master mode
Start condition
SCL0
tSU;STA
setup time
SDA0
(1 + nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Master mode
SCL0
SDA0
(2 nm + 4) tMCLK − 20
⎯
ns
SCL0
SDA0
3 tMCLK − 20
⎯
ns
Master mode
ns
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
applied to first bit
of continuous
data.
Otherwise,
the maximum
value is applied.
Bus free time
between stop
condition and
start condition
tBUF
Data hold time tHD;DAT
R = 1.7 kΩ,
C = 50 pF*1
Data setup
time
Setup time
between
clearing
interrupt and
SCL rising
tSU;DAT
SCL0
SDA0
tSU;INT SCL0
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20
(nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Minimum value is
applied to interrupt
at 9th SCL↓.
Maximum value is
applied to interrupt
at 8th SCL↓.
SCL clock “L”
width
tLOW
SCL0
4 tMCLK − 20
⎯
ns
At reception
SCL clock “H”
width
tHIGH
SCL0
4 tMCLK − 20
⎯
ns
At reception
SCL0
Start condition
tHD;STA
SDA0
detection
2 tMCLK − 20
⎯
ns
Undetected when
1 tMCLK is used at
reception
(Continued)
DS07-12618-2E
55
MB95160 Series
(Continued)
(VCC = 3.3 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin
name
Stop condition
detection
tSU;STO
Restart condition
detection condition
Parameter
Conditions
Value*2
Unit
Remarks
Min
Max
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1
tMCLK is used at
reception
tSU;STA
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1
tMCLK is used at
reception
Bus free time
tBUF
SCL0
SDA0
2 tMCLK − 20
⎯
ns
At reception
Data hold time
tHD;DAT
2 tMCLK − 20
⎯
ns
At slave transmission
mode
Data setup time
tSU;DAT
SCL0
SDA0 R = 1.7 kΩ,
1
SCL0 C = 50 pF*
tLOW − 3 tMCLK − 20
⎯
ns
At slave transmission
mode
Data hold time
tHD;DAT
SCL0
SDA0
0
⎯
ns
At reception
Data setup time
tSU;DAT
SCL0
SDA0
tMCLK − 20
⎯
ns
At reception
tWAKEUP
SCL0
SDA0
Oscillation
stabilization
wait time +
2 tMCLK − 20
⎯
ns
SDA ↓ → SCL ↑
(at wakeup function)
SDA0
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : •
•
•
•
Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
m is CS4 bit and CS3 bit (bit 4 and bit 3) of I2C clock control register (ICCR) .
n is CS2 bit to CS0 bit (bit 2 to bit 0) of I2C clock control register (ICCR) .
Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
• Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK ≤ 10 MHz
• Fast-mode :
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22) , (5, 4)
: 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
56
DS07-12618-2E
MB95160 Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 1.8 V to 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Sym- Condibol
tions
Value
Unit
Min
Typ
Max
Resolution
⎯
⎯
10
bit
Total error
− 3.0
⎯
+ 3.0
LSB
− 2.5
⎯
+ 2.5
LSB
− 1.9
⎯
+ 1.9
LSB
Linearity error
⎯
Differential
linear error
Zero transition
voltage
VOT
Full-scale
transition
voltage
VFST
Compare time
⎯
⎯
Sampling time
Remarks
AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
V
2.7 V ≤ AVCC ≤ 3.3 V
AVSS − 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB
V
1.8 V ≤ AVCC < 2.7 V
AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB
V
2.7 V ≤ AVCC ≤ 3.3 V
AVR − 2.5 LSB AVR − 0.5 LSB AVR + 1.5 LSB
V
1.8 V ≤ AVCC < 2.7 V
0.6
⎯
140
μs
2.7 V ≤ AVcc ≤ 3.3 V
20
⎯
140
μs
1.8 V ≤ AVcc < 2.7 V
0.4
⎯
∞
μs
2.7 V ≤ AVcc ≤ 3.3 V,
At external
impedance < 1.8 kΩ
30
⎯
∞
μs
1.8 V ≤ AVcc < 2.7 V,
At external
impedance < 14.8 kΩ
⎯
Analog input
current
IAIN
−0.3
⎯
+0.3
μA
Analog input
voltage
VAIN
AVSS
⎯
AVR
V
Reference
voltage
⎯
AVSS + 1.8
⎯
AVCC
V
AVR pin
Reference
voltage supply
current
IR
⎯
400
600
μA
AVR pin,
During A/D operation
IRH
⎯
⎯
5
μA
AVR pin,
At stop mode
DS07-12618-2E
57
MB95160 Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
R
1.7 kΩ (Max)
84 kΩ (Max)
2.7 V ≤ VCC ≤ 3.6 V
1.8 V ≤ VCC < 2.7 V
C
14.5 pF (Max)
25.2 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
AVcc ≥ 2.7 V
External impedance [kΩ]
External impedance [kΩ]
AVcc ≥ 2.7 V
100
90
80
70
60
50
40
30
20
10
0
AVcc ≥ 1.8 V
0
5
10
15
20
25
30
35
Minimum sampling time [μs]
40
20
18
16
14
12
10
8
6
4
2
0
0
1
2
3
4
Minimum sampling time [μs]
• About errors
As |VCC − VSS| becomes smaller, values of relative errors grow larger.
58
DS07-12618-2E
MB95160 Series
(3) Definition of A/D Converter Terms
• Resolution
The analog quantity to be monitored by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FEH
1.5 LSB
3FDH
004H
003H
002H
VOT
Digital output
Digital output
3FEH
3FDH
Actual conversion
characteristic
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
1 LSB
VNT
Actual conversion
characteristic
Ideal characteristics
001H
001H
0.5 LSB
VSS
Analog input
1 LSB =
VCC − Vss
1024
(V)
VCC
VSS
VCC
Analog input
Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
[LSB]
digital output N
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) H to NH
(Continued)
DS07-12618-2E
59
MB95160 Series
(Continued)
Full-scale transition error
Zero transition error
Ideal characteristics
004H
3FFH
Digital output
Digital output
Actual conversion
characteristic
003H
Ideal
characteristics
002H
Actual conversion
characteristic
Actual conversion
characteristic
3FEH
VFST
(measurement
value)
3FDH
Actual conversion
characteristic
001H
VOT (measurement value)
VSS
3FCH
VCC
VSS
Analog input
Differential linear error
Linearity error
Actual conversion
characteristic
3FFH
Ideal characteristics
(N+1)H
3FEH
{1 LSB × N + VOT}
3FDH
VFST
(measurement
value)
VNT
004H
Actual conversion
characteristic
003H
Digital output
Digital output
VCC
Analog input
Actual conversion
characteristic
V (N+1)T
NH
(N-1)H
VNT
Actual conversion
characteristic
Ideal characteristics
002H
(N-2)H
001H
VOT (measurement value)
VSS
Analog input
Linearity error in = VNT − {1 LSB × N + VOT}
1 LSB
digital output N
VCC
VSS
Analog input
Differential linear error =
in digital output N
V (N + 1) T − VNT
1 LSB
VCC
−1
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) H to NH
VOT (Ideal value) = VSS + 0.5 LSB [V]
VFST (Ideal value) = VCC − 1.5 LSB [V]
60
DS07-12618-2E
MB95160 Series
6. Flash Memory Program/Erase Characteristics
Value
Unit
Remarks
15*2
s
Excludes 00H programming prior erasure.
32
3600*2
μs
Excludes system-level overhead.
10000
⎯
⎯
cycle
Power supply voltage at erase/
program
2.7
⎯
3.3
V
Flash memory data retention
time
20*3
⎯
⎯
year
Parameter
Min
Typ
Max
Chip erase time
⎯
1*1
Byte programming time
⎯
Erase/program cycle
Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 3.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 2.7 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
DS07-12618-2E
61
MB95160 Series
■ MASK OPTION
Part number
MB95F166D
MB95FV100D-101
MB95166D
Specifying procedure
Setting disabled
Setting disabled
Specifying when
ordering MASK
1
Clock mode select
• Single-system clock mode
• Dual-system clock mode
Dual-system clock
mode
Changing by the
switch on
MCU board
Dual-system clock
mode
2
Low voltage detection reset*
• With low voltage detection reset
• Without low voltage detection
reset
No
No
No
3
Clock supervisor*
• With clock supervisor
• Without clock supervisor
No
No
No
4
Selection of oscillation stabilizaFixed to oscillation sta- Fixed to oscillation station wait time
bilization wait time of bilization wait time of
• Selectable the initial value of
main clock oscillation stabilization (214 − 2) /FCH
(214 − 2) /FCH
wait time
No.
Selectable:
1 : (22 − 2) / FCH
2 : (212 − 2) / FCH
3 : (213 − 2) / FCH
4 : (214 − 2) / FCH
* : Low voltage detection reset and clock supervisor are options of 5-V products.
62
DS07-12618-2E
MB95160 Series
■ ORDERING INFORMATION
Part number
Package
MB95F166DPMC/MB95166DPMC
64-pin plastic LQFP
(FPT-64P-M23)
MB95F166DPMC1/MB95166DPMC1
64-pin plastic LQFP
(FPT-64P-M24)
MB2146-301A
(MB95FV100D-101PBT)
DS07-12618-2E
(
MCU board
224-ball plastic PFBGA
(BGA-224P-M08)
)
63
MB95160 Series
■ PACKAGE DIMENSIONS
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.0 × 12.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LFQFP64-12×12-0.65
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.25(.010)
INDEX
0~8˚
64
17
1
"A"
16
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
M
©2003-2008
FUJITSU
LIMITED F64034S-c-1-2
C
2003 FUJITSU
LIMITEDMICROELECTRONICS
F64034S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
64
DS07-12618-2E
MB95160 Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
* 10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
49
32
Details of "A" part
0.08(.003)
+0.20
1.50 –0.10
+.008
.059 –.004
INDEX
64
0˚~8˚
17
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
16
0.50(.020)
0.20±0.05
(.008±.002)
0.08(.003)
M
©2005-2008
FUJITSU MICROELECTRONICS LIMITED F64036S-c-1-2
C
2005 FUJITSU LIMITED F64036S-c-1-1
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-12618-2E
65
MB95160 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Changed as follows.
(• Flash memory security function →
• Flash memory security function (Flash memory device only) )
■ PRODUCT LINEUP
Added the row of MB95166D.
Changed the Reset output.
(Yes → No)
3
5
Added the part number;
(MB95166D)
■ FEATURE
2
3, 4
Change Results
■ OSCILLATION STABILIZATION
WAIT TIME
Changed the “■ OSCILLATION STABILIZATION WAIT TIME”
■ PACKAGES AND CORRESPOND- Added the row of MB95166D.
ING PRODUCTS
6
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING
PRODUCTS
11
■ I/O CIRCUIT TYPE
•
•
•
•
Changed the Notes on Using Evaluation Products
Changed the Difference of Memory Spaces
Changed the Operating voltage
Added the Difference MOD pins
Changed the Type B
Changed the Type S ( • LCD power supply was deleted)
13
14
■ HANDLING DEVICES
Added the item of “• Serial Communication”.
17
■ CPU CORE
Added the MB95166D in “• Memory Map”.
23
■ I/O MAP
Changed the Address 0073H, 0074H.
28
■ ELECTRICAL CHARACTERISTICS Changed the Remarks of “Power supply voltage for LCD”
1. Absolute Maximum Ratings
(Products with LCD internal division resistance*3 → *3)
31
3. DC Characteristics
Added the row of Pull-down resistor (RMOD).
32
32, 33
Changed the Power supply current.
4. AC Characteristics
38, 39 (2) Source Clock/Machine Clock
61
62
Changed the row of Symbol VIHM and VILM.
• Changed the Operating voltage - Operating frequency
(When TA = −10 °C to +85 °C)
(• Added the graph of MB95166D )
■ MASK OPTION
Added the row of MB95166D.
■ ORDERING INFORMATION
Changed the part numbers.
(MB95F166DPMC → MB95F166DPMC/MB95166DPMC)
(MB95F166DPMC1 → MB95F166DPMC1/MB95166DPMC1)
The vertical lines marked in the left side of the page show the changes.
66
DS07-12618-2E
MB95160 Series
MEMO
DS07-12618-2E
67
MB95160 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department