ON NCP500 150 ma cmos low noise low-dropout voltage regulator Datasheet

NCP500
150 mA CMOS Low Noise
Low−Dropout Voltage
Regulator
The NCP500 series of fixed output low dropout linear regulators are
designed for portable battery powered applications which require low
noise operation, fast enable response time, and low dropout. The
device achieves its low noise performance without the need of an
external noise bypass capacitor. Each device contains a voltage
reference unit, an error amplifier, a PMOS power transistor, and
resistors for setting output voltage, and current limit and temperature
limit protection circuits.
The NCP500 has been designed to be used with low cost ceramic
capacitors and requires a minimum output capacitor of 1.0 F.
Features
•
•
•
•
•
•
•
TSOP−5
SN SUFFIX
CASE 483
5
1
QFN 2x2
SQL SUFFIX
CASE 488
1
Ultra−Low Dropout Voltage of 170 mV at 150 mA
Fast Enable Turn−On Time of 20 sec
Wide Operating Voltage Range of 1.8 V to 6.0 V
Excellent Line and Load Regulation
High Accuracy Output Voltage of 2.5%
Enable Can Be Driven Directly by 1.0 V Logic
Typical RMS Noise Voltage 50 V with No Bypass Capacitor
(BW = 10 Hz to 100 kHz)
Very Small QFN 2x2 Package
Pb−Free Package May be Available.* The G−Suffix Denotes a
Pb−Free Lead Finish
6
PIN CONNECTIONS AND
MARKING DIAGRAMS
TSOP−5
Vin
1
GND
2
Enable
3
Typical Applications
•
•
•
•
Vout
4
N/C
6
N/C
5
GND
4
Vout
(Top View)
Noise Sensitive Circuits − VCO’s, RF Stages, etc.
SMPS Post−Regulation
Hand−Held Instrumentation
Camcorders and Cameras
Vin
1 (3)
QFN 2x2
Vout
5 (4)
Thermal
Shutdown
5
xxxYW
•
•
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Driver w/
Current
Limit
Enable
Enable
1
GND
2
Vin
3
xxM
(Top View)
xxx, xx
Y
W
M
= Version
= Year
= Work Week
= Date Code
ORDERING INFORMATION
ON 3 (1)
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
OFF
GND
2 (2, 5)
NOTE: Pin numbers in parenthesis indicate QFN package.
Figure 1. Simplified Block Diagram
 Semiconductor Components Industries, LLC, 2004
January, 2004 − Rev. 16
1
*For additional information on our Pb−Free strategy
and soldering details, please download the ON
Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Publication Order Number:
NCP500/D
NCP500
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PIN FUNCTION DESCRIPTION
TSOP−5
Pin No.
QFN 2x2
Pin No.
Pin Name
1
3
Vin
2
2, 5
GND
3
1
Enable
4
6
N/C
No internal connection.
5
4
Vout
Regulated output voltage.
Description
Positive power supply input voltage.
Power supply ground.
This input is used to place the device into low−power standby. When this input is pulled to a logic
low, the device is disabled. If this function is not used, Enable should be connected to Vin.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Vin
0 to 6.0
V
Enable Voltage
Von/off
−0.3 to Vin +0.3
V
Output Voltage
Vout
−0.3 to Vin +0.3
V
−
Infinite
−
Input Voltage
Output Short Circuit Duration
Thermal Resistance, Junction−to−Ambient
TSOP−5
QFN (Note 3)
°C/W
RJA
250
225
Operating Junction Temperature
TJ
+125
°C
Storage Temperature
Tstg
−65 to +150
°C
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL−STD−883, Method 3015
Machine Model Method 200 V
Latch up capability (85°C) 100 mA.
2. Device is internally limited to 160°C by thermal shutdown.
3. For more information, refer to application note, AND8080/D.
ELECTRICAL CHARACTERISTICS (Vin = 2.35 V, Cin = 1.0 F, Cout = 1.0 F, for typical value TA = 25°C, for min and
max values TA = −40°C to 85°C, Tjmax = 125°C, unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Vout
1.755
1.8
1.845
V
Line Regulation (Vin = 2.3 V to 6.0 V, Iout = 1.0 mA)
Regline
−
1.0
10
mV
Load Regulation (Iout = 1.0 mA to 150 mA)
Regload
−
15
45
mV
Dropout Voltage (Measured at Vout −2.0%, TA = −40°C to 85°C)
(Iout = 1.0 mA)
(Iout = 75 mA)
(Iout = 150 mA)
Vin−Vout
−
−
−
2.0
140
270
10
200
350
Output Short Circuit Current
Iout(max)
200
540
700
mA
RR
−
62
−
dB
−
−
−
0.01
175
175
1.0
300
300
0.9
−
−
−
−
0.15
Characteristic
−1.8 V
Output Voltage (TA = −40°C to 85°C, Iout = 1.0 mA to 150 mA)
Ripple Rejection
(Vin = Vout (nom.) + 1.0 V + 0.5 Vpp, f = 1.0 kHz, Io = 60 mA)
Quiescent Current
(Enable Input = 0 V)
(Enable Input = 0.9 V, Iout = 1.0 mA)
(Enable Input = 0.9 V, Iout = 150 mA)
mV
A
IQ
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(EN)
Enable Input Bias Current
IIB(EN)
−
3.0
100
nA
−
−
20
100
s
Output Turn On Time (Enable Input = 0 V to Vin)
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2
V
NCP500
ELECTRICAL CHARACTERISTICS (continued) (Vin = 2.35 V, Cin = 1.0 F, Cout = 1.0 F, for typical value TA = 25°C, for min and
max values TA = −40°C to 85°C, Tjmax = 125°C, unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Vout
1.804
1.85
1.896
V
Line Regulation (Vin = 2.3 V to 6.0 V, Iout = 1.0 mA)
Regline
−
1.0
10
mV
Load Regulation (Iout = 1.0 mA to 150 mA)
Regload
−
15
45
mV
Dropout Voltage (Measured at Vout −2.0%, TA = −40°C to 85°C)
(Iout = 1.0 mA)
(Iout = 75 mA)
(Iout = 150 mA)
Vin−Vout
−
−
−
2.0
−
−
10
−
−
Output Short Circuit Current
Iout(max)
200
540
700
mA
RR
−
62
−
dB
−
−
−
0.01
175
175
1.0
300
300
0.9
−
−
−
−
0.15
Characteristic
−1.85 V
Output Voltage (TA = −40°C to 85°C, Iout = 1.0 mA to 150 mA)
Ripple Rejection
(Vin = Vout (nom.) + 1.0 V + 0.5 Vpp, f = 1.0 kHz, Io = 60 mA)
Quiescent Current
(Enable Input = 0 V)
(Enable Input = 0.9 V, Iout = 1.0 mA)
(Enable Input = 0.9 V, Iout = 150 mA)
mV
A
IQ
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(EN)
Enable Input Bias Current
IIB(EN)
−
3.0
100
nA
−
−
20
100
s
Output Turn On Time (Enable Input = 0 V to Vin)
V
ELECTRICAL CHARACTERISTICS (continued) (Vin = 3.0 V, Cin = 1.0 F, Cout = 1.0 F, for typical value TA = 25°C, for min and max
values TA = −40°C to 85°C, Tjmax = 125°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
2.438
2.5
2.563
Unit
−2.5 V
Vout
Output Voltage
(TA =−40°C to 85°C, Iout = 1.0 mA to 150 mA)
V
Line Regulation (Vin = 3.0 V to 6.0 V, Iout = 1.0 mA)
Regline
−
1.0
10
mV
Load Regulation (Iout = 1.0 mA to 150 mA)
Regload
−
15
45
mV
Dropout Voltage (Measured at Vout −2.0%, TA = −40°C to 85°C)
(Iout = 1.0 mA)
(Iout = 75 mA)
(Iout = 150 mA)
Vin−Vout
−
−
−
2.0
100
190
10
170
270
Output Short Circuit Current
Iout(max)
200
540
700
mA
RR
−
62
−
dB
−
−
−
0.01
180
180
1.0
300
300
0.9
−
−
−
−
0.15
Ripple Rejection
(Vin = Vout (nom.) + 1.0 V + 0.5 Vpp, f = 1.0 kHz, Io = 60 mA)
Quiescent Current
(Enable Input = 0 V)
(Enable Input = 0.9 V, Iout = 1.0 mA)
(Enable Input = 0.9 V, Iout = 150 mA)
mV
A
IQ
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(EN)
Enable Input Bias Current
IIB(EN)
−
3.0
100
nA
−
−
20
100
s
Output Turn On Time (Enable Input = 0 V to Vin)
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3
V
NCP500
ELECTRICAL CHARACTERISTICS (Vin = 3.1 V, Cin = 1.0 F, Cout = 1.0 F, for typical value TA = 25°C, for min and max
values TA = −40°C to 85°C, Tjmax = 125°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
2.535
2.6
2.665
Unit
−2.6 V
Output Voltage
(TA =−40°C to 85°C, Iout = 1.0 mA to 150 mA)
Vout
V
Line Regulation (Vin = 3.0 V to 6.0 V, Iout = 1.0 mA)
Regline
−
1.0
10
mV
Load Regulation (Iout = 1.0 mA to 150 mA)
Regload
−
15
45
mV
Dropout Voltage (Measured at Vout −2.0%, TA = −40°C to 85°C)
(Iout = 1.0 mA)
(Iout = 75 mA)
(Iout = 150 mA)
Vin−Vout
−
−
−
2.0
−
−
10
−
−
Output Short Circuit Current
Iout(max)
200
540
700
mA
RR
−
62
−
dB
−
−
−
0.01
180
180
1.0
300
300
0.9
−
−
−
−
0.15
Ripple Rejection
(Vin = Vout (nom.) + 1.0 V + 0.5 Vpp, f = 1.0 kHz, Io = 60 mA)
Quiescent Current
(Enable Input = 0 V)
(Enable Input = 0.9 V, Iout = 1.0 mA)
(Enable Input = 0.9 V, Iout = 150 mA)
mV
A
IQ
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(EN)
Enable Input Bias Current
IIB(EN)
−
3.0
100
nA
−
−
20
100
s
Output Turn On Time (Enable Input = 0 V to Vin)
V
ELECTRICAL CHARACTERISTICS (Vin = 3.2 V, Cin = 1.0 F, Cout = 1.0 F, for typical value TA = 25°C, for min and max
values TA = −40°C to 85°C, Tjmax = 125°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
2.633
2.7
2.768
Unit
−2.7 V
Vout
Output Voltage
(TA =−40°C to 85°C, Iout = 1.0 mA to 150 mA)
V
Line Regulation (Vin = 3.2 V to 6.0 V, Iout = 1.0 mA)
Regline
−
1.0
10
mV
Load Regulation (Iout = 1.0 mA to 150 mA)
Regload
−
15
45
mV
Dropout Voltage (Measured at Vout −2.0%, TA = −40°C to 85°C)
(Iout = 1.0 mA)
(Iout = 75 mA)
(Iout = 150 mA)
Vin−Vout
−
−
−
2.0
90
180
10
160
260
Output Short Circuit Current
Iout(max)
200
540
700
mA
RR
−
62
−
dB
−
−
−
0.01
185
185
1.0
300
300
0.9
−
−
−
−
0.15
Ripple Rejection
(Vin = Vout (nom.) + 1.0 V + 0.5 Vpp, f = 1.0 kHz, Io = 60 mA)
Quiescent Current
(Enable Input = 0 V)
(Enable Input = 0.9 V, Iout = 1.0 mA)
(Enable Input = 0.9 V, Iout = 150 mA)
mV
A
IQ
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(EN)
Enable Input Bias Current
IIB(EN)
−
3.0
100
nA
−
−
20
100
s
Output Turn On Time (Enable Input = 0 V to Vin)
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4
V
NCP500
ELECTRICAL CHARACTERISTICS (Vin = 3.3 V, Cin = 1.0 F, Cout = 1.0 F, for typical value TA = 25°C, for min and max
values TA = −40°C to 85°C, Tjmax = 125°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
2.730
2.8
2.870
Unit
−2.8 V
Output Voltage
(TA =−40°C to 85°C, Iout = 1.0 mA to 150 mA)
Vout
V
Line Regulation (Vin = 3.3 V to 6.0 V, Iout = 1.0 mA)
Regline
−
1.0
10
mV
Load Regulation (Iout = 1.0 mA to 150 mA)
Regload
−
15
45
mV
Dropout Voltage (Measured at Vout −2.0%, TA = −40°C to 85°C)
(Iout = 1.0 mA)
(Iout = 75 mA)
(Iout = 150 mA)
Vin−Vout
−
−
−
2.0
90
170
10
150
250
Output Short Circuit Current
Iout(max)
200
540
700
mA
RR
−
62
−
dB
−
−
−
0.01
185
185
1.0
300
300
0.9
−
−
−
−
0.15
Ripple Rejection
(Vin = Vout (nom.) + 1.0 V + 0.5 Vpp, f = 1.0 kHz, Io = 60 mA)
Quiescent Current
(Enable Input = 0 V)
(Enable Input = 0.9 V, Iout = 1.0 mA)
(Enable Input = 0.9 V, Iout = 150 mA)
mV
A
IQ
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(EN)
Enable Input Bias Current
IIB(EN)
−
3.0
100
nA
−
−
20
100
s
Output Turn On Time (Enable Input = 0 V to Vin)
V
ELECTRICAL CHARACTERISTICS (Vin = 3.5 V, Cin = 1.0 F, Cout = 1.0 F, for typical value TA = 25°C, for min and max
values TA = −40°C to 85°C, Tjmax = 125°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
2.925
3.0
3.075
Unit
−3.0 V
Vout
Output Voltage
(TA =−40°C to 85°C, Iout = 1.0 mA to 150 mA)
V
Line Regulation (Vin = 3.5 V to 6.0 V, Iout = 1.0 mA)
Regline
−
1.0
10
mV
Load Regulation (Iout = 1.0 mA to 150 mA)
Regload
−
15
45
mV
Dropout Voltage (Measured at Vout −2.0%, TA = −40°C to 85°C)
(Iout = 1.0 mA)
(Iout = 75 mA)
(Iout = 150 mA)
Vin−Vout
−
−
−
2.0
85
165
10
130
240
Output Short Circuit Current
Iout(max)
200
540
700
mA
RR
−
62
−
dB
−
−
−
0.01
190
190
1.0
300
300
0.9
−
−
−
−
0.15
Ripple Rejection
(Vin = Vout (nom.) + 1.0 V + 0.5 Vpp, f = 1.0 kHz, Io = 60 mA)
Quiescent Current
(Enable Input = 0 V)
(Enable Input = 0.9 V, Iout = 1.0 mA)
(Enable Input = 0.9 V, Iout = 150 mA)
mV
A
IQ
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(EN)
Enable Input Bias Current
IIB(EN)
−
3.0
100
nA
−
−
20
100
s
Output Turn On Time (Enable Input = 0 V to Vin)
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5
V
NCP500
ELECTRICAL CHARACTERISTICS (Vin = 3.8 V, Cin = 1.0 F, Cout = 1.0 F, for typical value TA = 25°C, for min and max
values TA = −40°C to 85°C, Tjmax = 125°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
3.218
3.3
3.383
Unit
−3.3 V
Output Voltage
(TA =−40°C to 85°C, Iout = 1.0 mA to 150 mA)
Vout
V
Line Regulation (Vin = 3.8 V to 6.0 V, Iout = 1.0 mA)
Regline
−
1.0
10
mV
Load Regulation (Iout = 1.0 mA to 150 mA)
Regload
−
15
45
mV
Dropout Voltage (Measured at Vout −2.0%, TA = −40°C to 85°C)
(Iout = 1.0 mA)
(Iout = 75 mA)
(Iout = 150 mA)
Vin−Vout
−
−
−
2.0
80
150
10
110
230
Output Short Circuit Current
Iout(max)
200
540
700
mA
RR
−
62
−
dB
−
−
−
0.01
195
195
1.0
300
300
0.9
−
−
−
−
0.15
Ripple Rejection
(Vin = Vout (nom.) + 1.0 V + 0.5 Vpp, f = 1.0 kHz, Io = 60 mA)
Quiescent Current
(Enable Input = 0 V)
(Enable Input = 0.9 V, Iout = 1.0 mA)
(Enable Input = 0.9 V, Iout = 150 mA)
mV
A
IQ
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(EN)
Enable Input Bias Current
IIB(EN)
−
3.0
100
nA
−
−
20
100
s
Output Turn On Time (Enable Input = 0 V to Vin)
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6
V
NCP500
ELECTRICAL CHARACTERISTICS (Vin = 5.5 V, Cin = 1.0 F, Cout = 1.0 F, for typical value TA = 25°C, for min and max
values TA = −40°C to 85°C, Tjmax = 125°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
4.875
5.0
5.125
Unit
−5.0 V
Output Voltage
(TA =−40°C to 85°C, Iout = 1.0 mA to 150 mA)
Vout
V
Line Regulation (Vin = 5.5 V to 6.0 V, Iout = 1.0 mA)
Regline
−
1.0
10
mV
Load Regulation (Iout = 1.0 mA to 150 mA)
Regload
−
15
45
mV
Dropout Voltage (Measured at Vout −2.0%, TA = −40°C to 85°C)
(Iout = 1.0 mA)
(Iout = 75 mA)
(Iout = 150 mA)
Vin−Vout
−
−
−
2.0
60
120
10
100
180
Output Short Circuit Current
Iout(max)
200
540
700
mA
RR
−
62
−
dB
−
−
−
0.01
210
210
1.0
300
300
0.9
−
−
−
−
0.15
Ripple Rejection
(Vin = Vout (nom.) + 1.0 V + 0.5 Vpp, f = 1.0 kHz, Io = 60 mA)
Quiescent Current
(Enable Input = 0 V)
(Enable Input = 0.9 V, Iout = 1.0 mA)
(Enable Input = 0.9 V, Iout = 150 mA)
mV
A
IQ
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(EN)
Enable Input Bias Current
IIB(EN)
−
3.0
100
nA
−
−
20
100
s
Output Turn On Time (Enable Input = 0 V to Vin)
V
4. Maximum package power dissipation limits must be observed.
T
TA
PD J(max)
RJA
5. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
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7
NCP500
200
Vout(nom.) = 3.3 V
Vin − Vout, Dropout Voltage (mV)
Vin − Vout, Dropout Voltage (mV)
70
60
50
50 mA Load
40
30
20
10 mA Load
10
0
−50
1.0 mA Load
−25
0
25
50
75
100
120
100 mA Load
100
−25
0
25
50
75
100
Figure 3. Dropout Voltage vs. Temperature
125
220
Vout(nom.) = 2.8 V
Vin − Vout, Dropout Voltage (mV)
Vin − Vout, Dropout Voltage (mV)
120 mA Load
Figure 2. Dropout Voltage vs. Temperature
50 mA Load
40
30
20
10 mA Load
10
1.0 mA Load
−25
25
0
50
75
100
Vout(nom.) = 2.8 V
200
180
150 mA Load
160
140
120 mA Load
120
100 mA Load
100
80
−50
125
−25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 4. Dropout Voltage vs. Temperature
Figure 5. Dropout Voltage vs. Temperature
125
350
120
Vout(nom.) = 1.8 V
Vin − Vout, Dropout Voltage (mV)
Vin − Vout, Dropout Voltage (mV)
150 mA Load
140
Temperature (°C)
50
100
50 mA Load
80
60
40
10 mA Load
20
1.0 mA Load
0
−50
160
Temperature (°C)
60
0
−50
180
80
−50
125
80
70
Vout(nom.) = 3.3 V
−25
0
25
50
75
100
330
290
150 mA Load
270
250
230
120 mA Load
210
190
170
150
−50
125
Vout(nom.) = 1.8 V
310
100 mA Load
−25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 6. Dropout Voltage vs. Temperature
Figure 7. Dropout Voltage vs. Temperature
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125
NCP500
2.804
3.308
Vin = Vout(nom.) +0.5 V
Vout(nom.) = 3.3 V
IO = 1.0 mA
3.304
3.302
3.300
3.298
3.296
2.8
2.798
2.796
2.794
2.792
3.294
3.292
−50
−25
0
25
50
75
100
125
2.790
−50
25
50
75
100
Figure 8. Output Voltage vs. Temperature
Figure 9. Output Voltage vs. Temperature
125
210
IQ, Quiescent Current (A)
1.803
1.8025
1.802
Vin = Vout(nom.) + 0.5 V
Vout(nom.) = 1.8 V
IO = 1.0 mA
1.8015
1.801
1.8005
−50
−25
0
25
50
75
100
Vout(nom.) = 3.3 V
190
180
Vout(nom.) = 1.8 V
170
160
−25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 10. Output Voltage vs. Temperature
Figure 11. Quiescent Current vs. Temperature
225
225
200
200
175
150
125
100
75
50
Vout(nom.) = 1.8 V
Iout = 0 mA
TA = 25°C
25
0
Vin = Vout(nom.) = + 0.5 V
IO = 0 mA
200
150
−50
125
IQ, Quiescent Current (A)
Vout, Output Voltage (V)
0
Temperature (°C)
1.8035
IQ, Quiescent Current (A)
−25
Temperature (°C)
1.804
0
Vin = Vout(nom.) + 0.5 V
Vout(nom.) = 2.8 V
IO = 1.0 mA
2.802
Vout, Output Voltage (V)
Vout, Output Voltage (V)
3.306
1.0
2.0
3.0
4.0
5.0
175
150
125
100
75
Vout(nom.) = 3.3 V
Iout = 0 mA
TA = 25°C
50
25
6.0
0
0
1.0
2.0
3.0
4.0
5.0
6.0
Input Voltage (V)
Input Voltage (V)
Figure 12. Quiescent Current vs. Input Voltage
Figure 13. Quiescent Current vs. Input Voltage
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225
225
200
200
Ground Pin Current (A)
Ground Pin Current (A)
NCP500
175
150
125
100
75
50
Vout(nom.) = 1.8 V
Iout = 50 mA
TA = 25°C
25
1.0
2.0
3.0
4.0
5.0
125
100
75
50
Vout(nom.) = 3.3 V
Iout = 50 mA
TA = 25°C
0
0
6.0
1.0
2.0
3.0
4.0
5.0
6.0
Input Voltage (V)
Input Voltage (V)
Figure 14. Ground Pin Current vs. Input Voltage
Figure 15. Ground Pin Current vs. Input Voltage
600
100
500
80
400
300
200
100
Vout(nom.) = 3.3 V
1.0
2.0
3.0
4.0
5.0
10 mA
60 mA
60
10 mA
40
Vout = 1.8 V
Vin = 2.8 VDC + 0.5 Vp−p
Cout = 1 F
20
0
0.1
6.0
1.0
10
f, Frequency (kHz)
Figure 16. Current Limit vs. Input Voltage
Figure 17. Ripple Rejection vs. Frequency
1000
Vout = 1.8 V
Vin = 2.8 V
Iout = 1 mA
Cout = 1 F
800
600
5.0
4.0
3.0
200
Vin = 3.8 V to 4.8 V
Vout = 3.3 V
Cout = 1.0 F
Iout = 1.0 mA
150
Output Voltage
Deviation (mV)
400
200
0
0.01
100
Input Voltage (V)
Vin, Input Voltage (V)
0
0
Vout, Output Voltage Noise (nV/HZ)
150
25
RR, Ripple Rejection (dB)
Current Limit (mA)
0
0
175
0.1
1.0
10
100
1000
100
50
0
−50
0
20
40
60
80
100
120
140
f, Frequency (kHz)
Time (s)
Figure 18. Output Noise Density
Figure 19. Line Transient Response
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10
160
5.0
Iout, Output
Current (mA)
Vin, Input
Voltage (V)
NCP500
4.0
3.0
100
50
0
−50
20
40
60
80
100
120
140
Iout, Output
Current (mA)
0
100
0
−100
−200
0
10
20
30
40
50
Time (s)
Time (s)
Figure 20. Line Transient Response
Figure 21. Load Transient Response
225
Vin = 3.8 V
Vout = 3.3 V
Cout = 10 F
Cin = 1 F
150
75
0
50
60
3.0
Vin = 3.8 V
Vout = 3.3 V
TA = 25°C
RL = 3.3 k
Cin = 1 F
2.0
1.0
0
4.0
Output Voltage (V)
Output Voltage
Deviation (mV)
75
−300
160
Enable Voltage (V)
0
Vin = 3.8 V
Vout = 3.3 V
Cout = 1.0 F
Cin = 1 F
150
200
Vin = 3.8 V to 4.8 V
Vout = 3.3 V
Cout = 1.0 F
Iout = 10 mA
150
Output Voltage
Deviation (mV)
Output Voltage
Deviation (mV)
200
225
25
0
−25
−50
0
10
20
30
40
50
60
70
80
90
3.0
2.0
Cout = 10 F
1.0
Cout = 1.0 F
0
0
20
40
60
80
100
Time (s)
Time (ms)
Figure 22. Load Transient Response
Figure 23. Turn−off Response
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120
NCP500
2
3
2.5
Vout, Output Voltage (V)
1.6
1.4
1.2
1
0.8
Cin = 1 F
Cout = 1 F
TA = 25°C
VEnable = Vin
0.6
0.4
0.2
0
2
1.5
Cin = 1 F
Cout = 1 F
TA = 25°C
VEnable = Vin
1
0.5
0
0
1
2
3
5
4
6
0
1
2
3
4
5
Vin, Input Voltage (V)
Vin, Input Voltage (V)
Figure 24. Output Voltage vs. Input Voltage
Figure 25. Output Voltage vs. Input Voltage
3.5
3
Vout, Output Voltage (V)
Vout, Output Voltage (V)
1.8
2.5
2
1.5
Cin = 1 F
Cout = 1 F
TA = 25°C
VEnable = Vin
1
0.5
0
0
1
2
3
4
5
6
Vin, Input Voltage (V)
Figure 26. Output Voltage vs. Input Voltage
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7
6
NCP500
DEFINITIONS
Load Regulation
Line Regulation
The change in output voltage for a change in output load
current at a constant temperature.
The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse technique such that the average
chip temperature is not significantly affected.
Dropout Voltage
The input/output differential at which the regulator output
no longer maintains regulation against further reductions in
input voltage. Measured when the output drops 2% below its
nominal. The junction temperature, load current, and
minimum input supply requirements affect the dropout level.
Line Transient Response
Typical over and undershoot response when input voltage
is excited with a given slope.
Thermal Protection
are expressed in VRMS or nV Hz.
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 160°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Quiescent Current
Maximum Package Power Dissipation
Output Noise Voltage
This is the integrated value of the output noise over a
specified frequency range. Input voltage and output load
current are kept constant during the measurement. Results
The power dissipation level at which the junction
temperature reaches its maximum operating value, i.e.
125°C.
The current which flows through the ground pin when the
regulator operates without a load on its output: internal IC
operation, bias, etc. When the LDO becomes loaded, this
term is called the Ground current. It is actually the difference
between the input current (measured through the LDO input
pin) and the output current.
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13
NCP500
APPLICATIONS INFORMATION
The NCP500 series regulators are protected with internal
thermal shutdown and internal current limit. A typical
application circuit is shown in Figure 27.
If TJ is not recommended to exceed 125°C, then the
NCP500 can dissipate up to 400 mW @ 25°C.
The power dissipated by the NCP500 can be calculated
from the following equation:
Input Decoupling (C1)
Ptot [Vin * Ignd (Iout)] [Vin Vout] * Iout
A 1.0 F capacitor either ceramic or tantalum is
recommended and should be connected close to the NCP500
package. Higher values and lower ESR will improve the
overall line transient response.
or
P Vout * Iout
VinMAX tot
Ignd Iout
Output Decoupling (C2)
If a 150 mA output current is needed the ground current
is extracted from the data sheet curves: 200 A @ 150 mA.
For a NCP500SN18T1 (1.8 V), the maximum input voltage
will then be 4.4 V, good for a 1 Cell Li−ion battery.
The NCP500 is a stable component and does not require
a minimum Equivalent Series Resistance (ESR) or a
minimum output current. The minimum decoupling value is
1.0 F and can be augmented to fulfill stringent load
transient requirements. The regulator accepts ceramic chip
capacitors as well as tantalum devices. Larger values
improve noise rejection and load regulation transient
response. Figure 29 shows the stability region for a range of
operating conditions and ESR values.
Hints
Please be sure the Vin and GND lines are sufficiently wide.
When the impedance of these lines is high, there is a chance
to pick up noise or cause the regulator to malfunction.
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads as short
as possible.
Noise Decoupling
The NCP500 is a low noise regulator without the need of
an external bypass capacitor. It typically reaches a noise level
of 50 VRMS overall noise between 10 Hz and 100 kHz. The
classical bypass capacitor impacts the start up phase of
standard LDOs. However, thanks to its low noise
architecture, the NCP500 operates without a bypass element
and thus offers a typical 20 s start up phase.
Package Placement
QFN packages can be placed using standard pick and
place equipment with an accuracy of 0.05 mm.
Component pick and place systems are composed of a vision
system that recognizes and positions the component and a
mechanical system which physically performs the pick and
place operation. Two commonly used types of vision
systems are: (1) a vision system that locates a package
silhouette and (2) a vision system that locates individual
bumps on the interconnect pattern. The latter type renders
more accurate place but tends to be more expensive and time
consuming. Both methods are acceptable since the parts
align due to a self−centering feature of the QFN solder joint
during solder re−flow.
Enable Operation
The enable pin will turn on or off the regulator. These
limits of threshold are covered in the electrical specification
section of this data sheet. The turn−on/turn−off transient
voltage being supplied to the enable pin should exceed a
slew rate of 10 mV/s to ensure correct operation. If the
enable is not to be used then the pin should be connected
to Vin.
Solder Paste
Thermal
Type 3 or Type 4 solder paste is acceptable.
As power across the NCP500 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
effect the rate of junction temperature rise for the part. This
is stating that when the NCP500 has good thermal
conductivity through the PCB, the junction temperature will
be relatively low with high power dissipation applications.
The maximum dissipation the package can handle is
given by:
Re−flow and Cleaning
The QFN may be assembled using standard IR/IR
convection SMT re−flow processes without any special
considerations. As with other packages, the thermal profile
for specific board locations must be determined. Nitrogen
purge is recommended during solder for no−clean fluxes.
The QFN is qualified for up to three re−flow cycles at 235°C
peak (J−STD−020). The actual temperature of the QFN is a
function of:
• Component density
• Component location on the board
• Size of surrounding components
T
TA
PD J(max)
RJA
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NCP500
ON
OFF
Battery or
Unregulated
Voltage
C1
1
+
5
+
2
ON
3
1
6
2
5
3
4
Vout
Battery or
Unregulated
Voltage
C2
4
Vout
+
C2
+
C1
OFF
Figure 27. Typical Application Circuit
Figure 28. Typical Application Circuit
10
Cout = 1 F to 10 F
TA = 40°C to 125°C
Vin = up to 6.0 V
Output Capacitor ESR ()
UNSTABLE
1
STABLE
0.1
0.01
0
25
50
75
100
125
150
IO, Output Current (mA)
Figure 29. Stability
Input
Input
Q1
R1
Q1
R2
R
Output
1
1.0 F
R3
5
Output
1
1.0 F
2
3
Q2
1.0 F
4
5
1.0 F
2
3
4
Figure 30. Current Boost Regulator
Figure 31. Current Boost Regulator with Short
Circuit Limit
The NCP500 series can be current boosted with a PNP transistor. Resistor R in conjunction with VBE of the PNP determines
when the pass transistor begins conducting; this circuit is not
short circuit proof. Input/Output differential voltage minimum is
increased by VBE of the pass resistor.
Short circuit current limit is essentially set by the VBE of Q2 and
R1. ISC = ((VBEQ2 − ib * R2) / R1) + IO(max) Regulator
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Input
Output
1
5
1.0 F
1.0 F
2
Enable
Output
5
1
1.0 F
1.0 F
2
3
R
4
3
4
C
TA = 25°C
Vin = 3.4 V
Vout = 2.8 V
2
1
0
4
Vout, Output Voltage (V)
3
Enable Voltage (V)
NCP500
3
2.5
No Delay
2
1.5
R = 1.0 M
C = 1.0 F
R = 1.0 M
C = 0.1 F
1
0.5
0
10
0
20
30
40
50
60
70
80
90 100 110
Time (ms)
Figure 32. Delayed Turn−on
Figure 33. Delayed Turn−on
If a delayed turn−on is needed during power up of several voltages then the above schematic can be used. Resistor R, and
capacitor C, will delay the turn−on of the bottom regulator. A
few values were chosen and the resulting delay can be seen in
Figure 33.
The graph shows the delay between the enable signal and
output turn−on for various resistor and capacitor values.
Input
Output
Q1
R
1
1.0 F
5
1.0 F
2
3
4
5.6 V
Figure 34. Input Voltages Greater than 6.0 V
A regulated output can be achieved with input voltages that exceed the 6.0 V maximum rating of the NCP500 series with the
addition of a simple pre−regulator circuit. Care must be taken
to prevent Q1 from overheating when the regulated output
(Vout) is shorted to Gnd.
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16
NCP500
ORDERING INFORMATION
Nominal
Output Voltage
Marking
Package
Shipping†
NCP500SN18T1
NCP500SN185T1
NCP500SN25T1
NCP500SN25T1G
NCP500SN26T1
NCP500SN27T1
NCP500SN28T1
NCP500SN28T1G
NCP500SN30T1
NCP500SN33T1
NCP500SN33T1G
NCP500SN50T1
1.8
1.85
2.5
2.5
2.6
2.7
2.8
2.8
3.0
3.3
3.3
5.0
LCS
LFL
LCT
LCT
LFM
LCU
LCV
LCV
LCW
LCX
LCX
LCY
TSOP−5
3000 Units/
7″ Tape & Reel
NCP500SQL18T1
NCP500SQL25T1
NCP500SQL27T1
NCP500SQL28T1
NCP500SQL30T1
NCP500SQL33T1
NCP500SQL50T1
1.8
2.5
2.7
2.8
3.0
3.3
5.0
LD
LE
LF
LG
LH
LJ
LK
QFN 2x2
3000 Units/
7″ Tape & Reel
Device
For availability of other output voltages, please contact your local ON Semiconductor Sales Representative.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
NCP500
PACKAGE DIMENSIONS
TSOP−5
SN SUFFIX
PLASTIC PACKAGE
CASE 483−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
D
S
5
4
1
2
3
B
L
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
2.90
3.10 0.1142 0.1220
B
1.30
1.70 0.0512 0.0669
C
0.90
1.10 0.0354 0.0433
D
0.25
0.50 0.0098 0.0197
G
0.85
1.05 0.0335 0.0413
H 0.013 0.100 0.0005 0.0040
J
0.10
0.26 0.0040 0.0102
K
0.20
0.60 0.0079 0.0236
L
1.25
1.55 0.0493 0.0610
M
0_
10 _
0_
10 _
S
2.50
3.00 0.0985 0.1181
G
A
J
C
0.05 (0.002)
H
M
K
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
THIN SOT23−5/TSOP−5/SC59−5
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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18
NCP500
PACKAGE DIMENSIONS
QFN 2x2.2
SQL SUFFIX
PLASTIC PACKAGE
CASE 488−03
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. 488−01 OBSOLETE. NEW STANDARD IS 488−02.
TOP VIEW
A
J
H
PIN 1
C
S
G
L
D
U
BOTTOM VIEW
B
SIDE VIEW
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DIM
A
B
C
D
G
H
J
L
S
MILLIMETERS
MIN
MAX
2.18
2.23
1.98
2.03
0.88
0.93
0.23
0.28
0.650 BSC
0.35
0.40
0.05
0.10
1.28
1.33
0.33
0.38
INCHES
MIN
MAX
0.086
0.088
0.078
0.080
0.035
0.037
0.009
0.011
0.026 BSC
0.014
0.016
0.002
0.004
0.050
0.052
0.013
0.015
NCP500
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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