ON NBC12439FN 3.3 v/5 v programmable pll synthesized clock generator Datasheet

NBC12439
3.3 V/5 VProgrammable
PLL Synthesized Clock
Generator
50 MHz to 800 MHz
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The NBC12439 is a general purpose, PLL based synthesized clock
source. The VCO will operate over a frequency range of 400 MHz to
800 MHz. The VCO frequency is sent to the N-output divider, where
it can be configured to provide division ratios of 1, 2, 4 or 8. The VCO
and output frequency can be programmed using the parallel or serial
interfaces to the configuration logic. The PLL loop filter is fully
integrated and does not require any external components.
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Best-in-Class Output Jitter Performance, ±20 ps Peak-to-Peak
50 MHz to 800 MHz Programmable Differential PECL Outputs
Fully Integrated Phase-Lock-Loop with Internal Loop Filter
MARKING
DIAGRAMS
1 28
NBC12439
AWLYYWW
PLCC-28
FN SUFFIX
CASE 776
Parallel Interface for Programming Counter and Output Dividers
During Power-Up
Minimal Frequency Overshoot
Serial 3-Wire Programming Interface
NBC12439
Crystal Oscillator Interface
LQFP-32
FA SUFFIX
CASE 873A
Operating Range: VCC = 3.135 V to 5.25 V
CMOS and TTL Compatible Control Inputs
AWLYYWW
32
Pin Compatible with Motorola MC12439
1
Power-Down of PECL Outputs (16)
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2003
May, 2003 - Rev. 2
1
Package
Shipping
NBC12439FN
PLCC-28
37 Units/Rail
NBC12439FNR2
PLCC-28
500 Tape & Reel
NBC12439FA
LQFP-32
250 Units/Tray
NBC12439FAR2
LQFP-32
2000 Tape & Reel
Publication Order Number:
NBC12439/D
NBC12439
PWR_DOWN
+3.3 or 5.0 V
2
2
FREF
1
PLL_VCC
POWER
DOWN
PHASE
DETECTOR
+3.3 or 5.0 V
15
XTAL_SEL
VCO
3
FREF_EXT
4
10-20MHz
XTAL1
7-BIT M
COUNTER
2
20
XTAL2
LATCH
LATCH
6
OE
21, 25
24
23
N
(1, 2, 4, 8)
400-800
MHz
OSC
5
VCC
28
S_LOAD
LATCH
7
P_LOAD
0
1
0
27
S_DATA
1
2- BIT SR
7- BIT SR
3- BIT SR
26
S_CLOCK
8 → 14
17, 18
2
M[6:0]
N[1:0]
Table 1. Output Division
N [1:0]
Output Division
00
01
10
11
2
4
8
1
22, 19
7
Table 2. XTAL_SEL and OE
Input
PWR_DOWN
XTAL_SEL
OE
0
FOUT
FREF_EXT
Disabled
Figure 1. NBC12439 Block Diagram (28-Lead PLCC)
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2
1
FOUT 16
XTAL
Enabled
FOUT
FOUT
TEST
VCC
FOUT
FOUT
GND
VCC
TEST
GND
NBC12439
25
24
23
22
21
20
19
S_CLOCK
26
18
N[1]
S_DATA
27
17
N[0]
S_LOAD
28
16
NC
PLL_VCC
1
15
XTAL_SEL
PWR_DOWN
2
14
M[6]
FREF_EXT
3
13
M[5]
XTAL1
4
12
M[4]
11
M[3]
10
M[2]
9
M[1]
8
M[0]
OE
7
P_LOAD
6
XTAL2
5
VCC
FOUT
FOUT
GND
VCC
VCC
TEST
GND
Figure 2. 28-Lead PLCC (Top View)
32
31
30
29
28
27
26
25
3
22
N[0]
PLL_VCC
4
21
NC
PLL_VCC
5
20
XTAL_SEL
PWR_DOWN
6
19
M[6]
FREF_EXT
7
18
M[5]
XTAL1
8
17
M[4]
XTAL2
9
10
11
12
13
14
15
16
N/C
S_LOAD
M[3]
N[1]
M[2]
23
M[1]
N/C
2
M[0]
24
S_DATA
P_LOAD
1
OE
S_CLOCK
Figure 3. 32-Lead LQFP (Top View)
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3
NBC12439
The following gives a brief description of the functionality of the NBC12439 Inputs and Outputs. Unless explicitly stated,
all inputs are CMOS/TTL compatible with either pull-up or pulldown resistors. The PECL outputs are capable of driving two
series terminated 50 transmission lines on the incident edge.
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PIN FUNCTION DESCRIPTION
Pin Name
Function
Description
INPUTS
XTAL1, XTAL2
Crystal Inputs
These pins form an oscillator when connected to an external series-resonant
crystal.
S_LOAD*
CMOS/TTL Serial Latch Input
(Internal Pulldown Resistor)
This pin loads the configuration latches with the contents of the shift registers. The
latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH-to-LOW transition of S_LOAD for proper operation.
S_DATA*
CMOS/TTL Serial Data Input
(Internal Pulldown Resistor)
This pin acts as the data input to the serial configuration shift registers.
S_CLOCK*
CMOS/TTL Serial Clock Input
(Internal Pulldown Resistor)
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
P_LOAD**
CMOS/TTL Parallel Latch Input
(Internal Pullup Resistor)
This pin loads the configuration latches with the contents of the parallel inputs
.The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW-to-HIGH transition of P_LOAD for proper operation.
M[6:0]**
CMOS/TTL PLL Loop Divider
Inputs (Internal Pullup Resistor)
These pins are used to configure the PLL loop divider. They are sampled on the
LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.
N[1:0]**
CMOS/TTL Output Divider Inputs
(Internal Pullup Resistor)
These pins are used to configure the output divider modulus. They are sampled
on the LOW-to-HIGH transition of P_LOAD.
OE**
CMOS/TTL Output Enable Input
(Internal Pullup Resistor)
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the FOUT output.
FREF_EXT*
CMOS/TTL Input
(Internal Pulldown Resistor)
This pin can be used as the PLL Reference
XTAL_SEL**
CMOS/TTL Input
(Internal Pullup Resistor)
This pin selects between the crystal and the FREF_EXT source for the PLL reference signal. A HIGH selects the crystal input.
PWR_DOWN
CMOS/TTL Input
(Internal Pulldown Resistor)
PWR_DOWN forces the FOUT outputs to synchronously reduce frequency by a
factor of 16.
FOUT, FOUT
PECL Differential Outputs
These differential, positive-referenced ECL signals (PECL) are the outputs of the
synthesizer.
TEST
CMOS/TTL Output
The function of this output is determined by the serial configuration bits T[2:0].
VCC
Positive Supply for the Logic
The positive supply for the internal logic and output buffer of the chip, and is connected to +3.3 V or +5.0 V.
PLL_VCC
Positive Supply for the PLL
This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
GND
Negative Power Supply
These pins are the negative supply for the chip and are normally all connected to
ground.
OUTPUTS
POWER
* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.
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NBC12439
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
37.5 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
> 2 kV
> 150 V
> 1 kV
PLCC
LQFP
Flammability Rating
Oxygen Index: 28 to 34
Level 1
Level 2
UL 94 V-0 @ 0.125 in
Transistor Count
2269
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Rating
Units
VCC
Positive Supply
Parameter
GND = 0 V
-
6
V
VI
Input Voltage
GND = 0 V
VI VCC
6
V
Iout
Output Current
Continuous
Surge
-
50
100
mA
mA
TA
Operating Temperature Range
-
-
0 to +70
°C
Tstg
Storage Temperature Range
-
-
-65 to +150
°C
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
°C/W
°C/W
JC
Thermal Resistance (Junction to Case)
std bd
28 PLCC
22 to 26
°C/W
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction to Case)
std bd
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
< 3 sec @ 248°C
-
265
°C
Symbol
Condition 1
2. Maximum Ratings are those values beyond which device damage may occur.
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Condition 2
NBC12439
DC CHARACTERISTICS (VCC = 3.3 V ± 5%)
0°C
Symbol
Characteristic
25°C
70°C
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VIH
LVCMOS/
LVTTL
Input HIGH Voltage
VCC = 3.3 V
2.0
-
-
2.0
-
-
2.0
-
-
V
VIL
LVCMOS/
LVTTL
Input LOW Voltage
VCC = 3.3 V
-
-
0.8
-
-
0.8
-
-
0.8
V
IIN
Input Current
-
-
1.0
-
-
1.0
-
-
1.0
mA
VOH
Output HIGH Voltage
TEST
IOH = -0.8 mA
2.5
-
-
2.5
-
-
2.5
-
-
V
VOL
Output LOW Voltage
TEST
IOL = 0.8 mA
-
-
0.4
-
-
0.4
-
-
0.4
V
VOH
PECL
Output HIGH Voltage
FOUT
FOUT
VCC = 3.3 V
(Notes 3, 4)
2.155
-
2.405
2.155
-
2.405
2.155
-
2.405
V
VOL
PECL
Output LOW Voltage
FOUT
FOUT
VCC = 3.3 V
(Notes 3, 4)
1.355
-
1.675
1.355
-
1.675
1.355
-
1.675
V
ICC
Power Supply Current
VCC
PLL_VCC
44
19
56
23
80
28
44
19
58
23
80
28
44
19
61
23
80
28
mA
mA
3. FOUT/FOUT output levels will vary 1:1 with VCC variation.
4. FOUT/FOUT outputs are terminated through a 50 resistor to VCC - 2.0 volts.
DC CHARACTERISTICS (VCC = 5.0 V ± 5%)
0°C
25°C
70°C
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VIH
CMOS/
TTL
Input HIGH Voltage
VCC = 5.0 V
2.0
-
-
2.0
-
-
2.0
-
-
V
VIL
CMOS/
TTL
Input LOW Voltage
VCC = 5.0 V
-
-
0.8
-
-
0.8
-
-
0.8
V
IIN
Input Current
-
-
1.0
-
-
1.0
-
-
1.0
mA
VOH
Output HIGH Voltage
TEST
IOH = -0.8 mA
2.5
-
-
2.5
-
-
2.5
-
-
V
VOL
Output LOW Voltage
TEST
IOL = 0.8 mA
-
-
0.4
-
-
0.4
-
-
0.4
V
VOH
PECL
Output HIGH Voltage
FOUT
FOUT
VCC = 5.0 V
(Notes 5, 6)
3.855
-
4.105
3.855
-
4.105
3.855
-
4.105
V
VOL
PECL
Output LOW Voltage
FOUT
FOUT
VCC = 5.0 V
(Notes 5, 6)
3.055
-
3.305
3.055
-
3.305
3.055
-
3.305
V
ICC
Power Supply Current
VCC
PLL_VCC
47
19
58
24
85
28
47
19
60
24
85
28
47
19
64
24
85
28
mA
mA
Symbol
Characteristic
5. FOUT/FOUT output levels will vary 1:1 with VCC variation.
6. FOUT/FOUT outputs are terminated through a 50 resistor to VCC - 2.0 volts.
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6
NBC12439
AC CHARACTERISTICS (VCC = 3.135 V to 5.25 V ± 5%; TA = 0° to 70°C) (Note 8)
Characteristic
Symbol
Condition
FMAXI
Maximum Input Frequency
S_CLOCK
Xtal Oscillator
FREF_EXT
FMAXO
Maximum Output Frequency
VCO (Internal)
FOUT
tLOCK
Maximum PLL Lock Time
tjitter
Cycle-to-Cycle Jitter (Peak-to-Peak)
ts
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
th
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
tpwMIN
Minimum Pulse Width
S_LOAD
P_LOAD
DCO
Output Duty Cycle
tr, tf
Output Rise/Fall
(Note 7)
(Note 10)
1000 Cycles
FOUT
20%-80%
Min
Max
Unit
10
10
10
20
Note 9
MHz
400
50
800
800
MHz
-
10
ms
-
20
ps
20
20
20
-
ns
20
20
20
-
ns
50
50
-
ns
47.5
52.5
%
175
425
ps
7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as
a test clock in TEST_MODE 6.
8. FOUT/FOUT outputs are terminated through a 50 resistor to VCC - 2.0 V.
9. Maximum frequency on FREF_EXT is a function of setting the appropriate M counter value, 25 MHz M 50 MHz, for the VCO to operate
within the valid range of 400 MHz fVCO 800 MHz. The internal phase detector can handle up to 100 MHz on its input.
10. See applications information section.
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NBC12439
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as
the basis of its frequency reference. The output of the
reference oscillator is divided by 16 before being sent to the
phase detector. With a 2 MHz crystal, this provides a
reference frequency of 8 MHz. Although this data sheet
illustrates functionality only for a 16 MHz crystal, Table 3,
any crystal in the 10-20 MHz range can be used, Table 5.
The VCO within the PLL operates over a range of 400 to
800 MHz. Its output is scaled by a divider, M divider, that is
configured by either the serial or parallel interfaces. The
output of this loop divider is also applied to the phase
detector.
The phase detector and the loop filter force the VCO
output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some
values of M (either too high or too low), the PLL will not
achieve loop lock.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. This
N output divider is configured through either the serial or the
parallel interfaces and can provide one of four division ratios
(1, 2, 4, or 8). This divider extends the performance of the
part while providing a 50% duty cycle.
The output driver is driven differentially from the output
divider and is capable of driving a pair of transmission lines
terminated into 50 to VCC-2.0 V. The positive reference
for the output driver and the internal logic is separated from
the power supply for the phase-locked loop to minimize
noise induced jitter.
The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the M[6:0]
and N[1:0] inputs to configure the internal counters.
Normally upon system reset, the P_LOAD input is held
LOW until sometime after power becomes valid. On the
LOW-to-HIGH transition of P_LOAD, the parallel inputs
are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the
M[6:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial interface logic is implemented with a fourteen
bit shift register scheme. The register shifts once per rising
edge of the S_CLOCK input. The serial input S_DATA must
meet setup and hold timing as specified in the AC
Characteristics section of this document. With P_LOAD
held high, the configuration latches will capture the value of
the shift register on the HIGH-to-LOW edge of the
S_LOAD input. See the programming section for more
information.
The TEST output reflects various internal node values and
is controlled by the T[2:0] bits in the serial data stream. See
the programming section for more information.
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Table 3. Programming VCO Frequency Function Table with 16 MHz Crystal
64
32
16
8
4
2
1
M Count
M6
M5
M4
M3
M2
M1
M0
25
0
0
1
1
0
0
1
416
26
0
0
1
1
0
1
0
432
27
0
0
1
1
0
1
1
448
28
0
0
1
1
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
752
47
0
1
0
1
1
1
1
768
48
0
1
1
0
0
0
0
784
49
0
1
1
0
0
0
1
800
50
0
1
1
0
0
1
0
VCO
Frequency (MHz)
400
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8
NBC12439
PROGRAMMING INTERFACE
The input frequency and the selection of the feedback
divider M is limited by the VCO frequency range and
fXTAL. M must be configured to match the VCO frequency
range of 400 to 800 MHz in order to achieve stable PLL
operation.
Programming the NBC12439 is accomplished by
properly configuring the internal dividers to produce the
desired frequency at the outputs. The output frequency can
by represented by this formula:
FOUT (FXTAL 2) 2M N
(eq. 1)
This can be simplified to:
FOUT FXTALxM N
(eq. 2)
where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it
is possible to select values of M such that the PLL is unable
to achieve loop lock. To avoid this, always make sure that M
is selected to be 25 ≤ M ≤ 50 for a 16 MHz input reference.
See Table 5.
Assuming that a 16 MHz reference frequency is used the
above equation reduces to:
FOUT 16M N
(eq. 3)
Substituting the four values for N (1, 2, 4, 8) yields:
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ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Table 4. Programmable Output Divider Function Table
N1
N0
N Divider
FOUT
Output Frequency
Range (MHz)*
1
1
1
M 16
400-800
0
0
2
M8
200-400
0
1
4
M4
100-200
1
0
8
M2
50-100
*For crystal frequency of 16 MHz.
The user can identify the proper M and N values for the
desired frequency from the above equations. The four output
frequency ranges established by N are 400- 800 MHz,
200- 400 MHz, 100- 200 MHz and 50- 100 MHz, respectively.
From these ranges, the user will establish the value of N
required. The value of M can then be calculated based on
equation 1. For example, if an output frequency of 384 MHz
was desired, the following steps would be taken to identify the
appropriate M and N values. 384 MHz falls within the
frequency range set by an N value of 2; thus, N [1:0] = 00.
For N = 2, FOUT = 8M and M = FOUT 8. Therefore,
M = 384 8 = 48, so M[6:0] = 0110000. Following this same
procedure, a user can generate a selected frequency. The size
of the programmable frequency steps of FOUT will be equal
to FXTAL ÷ N.
For input reference frequencies other than 16 MHz, see
Table 5, which shows the usable VCO frequency and M
divider range.
(eq. 4)
M max fVCOmax FXTAL
(eq. 5)
The value for M falls within the constraints set for PLL
stability. If the value for M fell outside of the valid range, a
different N value would be selected to move M in the
appropriate direction.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is
controlled via the P_LOAD signal such that a LOW to HIGH
transition will latch the information present on the M[6:0]
and N[1:0] inputs into the M and N counters. When the
P_LOAD signal is LOW, the input latches will be
transparent and any changes on the M[6:0] and N[1:0] inputs
will affect the FOUT output pair. To use the serial port, the
S_CLOCK signal samples the information on the S_DATA
line and loads it into a 12 bit shift register. Note that the
P_LOAD signal must be HIGH for the serial load operation
to function. The Test register is loaded with the first three
bits, the N register with the next two, and the M register with
the final nine bits of the data stream on the S_DATA input.
For each register, the most significant bit is loaded first (T2,
N1, and M6). The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters. A
pulse on the S_LOAD pin after the shift register is fully
loaded will transfer the divide values into the counters.
Figures 4 and 5 illustrate the timing diagram for both a
parallel and a serial load of the NBC12439 synthesizer.
M[6:0] and N[1:0] are normally specified after power-up
through the parallel interface, and then possibly, fine tuned
again through the serial interface. This approach allows the
application to ramp up at one frequency and then change or
fine-tune the clock as the ability to control the serial
interface becomes available.
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. The T2, T1, and T0 control bits are preset
to ‘000’ when P_LOAD is LOW so that the PECL FOUT
outputs are as jitter-free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter
of the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select one
of the alternate functions for this pin.
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M min fVCOmin FXTAL and
NBC12439
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
Table 5. NBC12439 Frequency Operating Range
M
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VCO Frequency (MHz) Range for a Crystal Frequency (MHz) of:
M[6:0]
10
12
14
16
0010100
0010101
0010110
0010111
0011000
0011001
400
0011010
416
0011011
432
0011100
448
0011101
406
464
0011110
420
480
0011111
434
496
0100000
448
512
0100001
462
528
0100010
408
476
544
0100011
420
490
560
0100100
432
504
576
0100101
444
518
592
0100110
456
532
608
0100111
468
546
624
0101000
400
480
560
640
0101001
410
492
574
656
0101010
420
504
588
672
0101011
430
516
602
688
0101100
440
528
616
704
0101101
450
540
630
720
0101110
460
552
644
736
0101111
470
564
658
752
0110000
480
576
672
768
0110001
490
588
686
784
0110010
500
600
700
800
0110011
510
612
714
0110100
520
624
728
0110101
530
636
742
0110110
540
648
756
0110111
550
660
770
0111000
560
672
784
0111001
570
684
798
0111010
580
696
0111011
590
708
0111100
600
720
0111101
610
732
0111110
620
744
0111111
630
756
1000000
640
768
1000001
650
780
1000010
660
792
1000011
670
1000100
680
1000101
690
1000110
700
1000111
710
1001000
720
1001001
730
1001010
740
1001011
750
1001100
760
1001101
770
1001110
780
1001111
790
1010000
800
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10
18
414
432
450
468
486
504
522
540
558
576
594
612
630
648
666
684
702
720
738
756
774
792
20
400
420
440
460
480
500
520
540
560
580
600
620
640
660
680
700
720
740
760
780
800
Output Frequency (MHz) for
fXTAL = 16 MHz and for N =
1
2
4
8
400
416
432
448
464
480
496
512
528
544
560
576
592
608
624
640
656
672
688
704
720
736
752
768
784
800
200
208
216
224
232
240
248
256
264
272
280
288
296
304
312
320
328
336
344
352
360
368
376
384
392
400
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
184
188
192
196
200
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
NBC12439
Most of the signals available on the TEST output pin are
useful only for performance verification of the NBC12439
itself. However, the PLL bypass mode may be of interest at
the board level for functional debug. When T[2:0] is set to
110, the NBC12439 is placed in PLL bypass mode. In this
mode the S_CLOCK input is fed directly into the M and N
dividers. The N divider drives the FOUT differential pair
and the M counter drives the TEST output pin. In this mode
the S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
FOUT directly gives the user more control on the test clocks
sent through the clock tree. Figure 6 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK is a
CMOS level the input frequency is limited to 250 MHz or
less. This means the fastest the FOUT pin can be toggled via
the S_CLOCK is 250 MHz as the minimum divide ratio of
the N counter is 1. Note that the M counter output on the
TEST output will not be a 50% duty cycle due to the way the
divider is implemented.
T2
T1
T0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TEST OUTPUT
SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT
FOUT
LOW
PLL BYPASS
FOUT 4
M[8:0]
N[1:0]
M, N
P_LOAD
Figure 4. Parallel Interface Timing Diagram
S_CLOCK
T2 T1
S_DATA
T0
N1
N0
M6
M5
M4
M3
M2
M1
M0
First
Bit
S_LOAD
Last
Bit
Figure 5. Serial Interface Timing Diagram
FREF_EXT
MCNT
VCO_CLK
PLL 12439
0
N
(1, 2, 4, 8)
1
SCLOCK
FOUT
(VIA ENABLE GATE)
SEL_CLK
M COUNTER
LATCH
Reset
SDATA
SHIFT
REG
T0
12- BIT
T1
T2
SLOAD
PLOAD
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
7
TEST
MUX
0
DECODE
•
•
T2=T1=1, T0=0: Test Mode
SCLOCK is selected, MCNT is on TEST output, SCLOCK N is on FOUT pin.
PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.
Figure 6. Serial Test Clock Block Diagram
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TEST
NBC12439
APPLICATIONS INFORMATION
Using the On-Board Crystal Oscillator
Power Supply Filtering
The NBC12439 features a fully integrated on-board
crystal oscillator to minimize system implementation costs.
The oscillator is a series resonant, multivibrator type design
as opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability
and eliminates the need for large on chip capacitors. The
oscillator is totally self contained so that the only external
component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs, the user is
advised to mount the crystal as close to the NBC12439 as
possible to avoid any board level parasitics. To facilitate
co-location, surface mount crystals are recommended, but
not required. Because the series resonant design is affected
by capacitive loading on the crystal terminals, loading
variation introduced by crystals from different vendors
could be a potential issue. For crystals with a higher shunt
capacitance, it may be required to place a resistance across
the terminals to suppress the third harmonic. Although
typically not required, it is a good idea to layout the PCB
with the provision of adding this external resistor. The
resistor value will typically be between 500 and 1 K.
The oscillator circuit is a series resonant circuit and thus,
for optimum performance, a series resonant crystal should
be used. Unfortunately, most crystals are characterized in a
parallel resonant mode. Fortunately, there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result, a parallel resonant crystal can be
used with the NBC12439 with only a minor error in the
desired frequency. A parallel resonant mode crystal used in
a series resonant circuit will exhibit a frequency of
oscillation a few hundred ppm lower than specified (a few
hundred ppm translates to kHz inaccuracy). Table 6 below
specifies the performance requirements of the crystals to be
used with the NBC12439.
The NBC12439 is a mixed analog/digital product and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NBC12439 provides
separate power supplies for the digital circuitry (VCC) and
the internal PLL (PLL_VCC) of the device. The purpose of
this design technique is to try and isolate the high switching
noise of the digital outputs from the relatively sensitive
internal analog phase-locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on
the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply
filter on the PLL_VCC pin for the NBC12439.
Figure 7 illustrates a typical power supply filter scheme.
The NBC12439 is most susceptible to noise with spectral
content in the 1 KHz to 1 MHz range. Therefore, the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the
PLL_VCC pin of the NBC12439. From the data sheet, the
PLL_VCC current (the current sourced through the
PLL_VCC pin) is typically 23 mA (28 mA maximum).
Assuming that a minimum of 2.8 V must be maintained on
the PLL_VCC pin, very little DC voltage drop can be
tolerated when a 3.3 V VCC supply is used. The resistor
shown in Figure 7 must have a resistance of 10-15 to meet
the voltage drop criteria. The RC filter pictured will provide
a broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20 KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor, it’s overall impedance begins to look inductive
and thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL.
Table 6. Crystal Specifications
Parameter
Value
Crystal Cut
Fundamental AT Cut
Resonance
Series Resonance*
Frequency Tolerance
±75 ppm at 25°C
Frequency/Temperature Stability
±150 ppm 0 to 70°C
Operating Range
0 to 70°C
Shunt Capacitance
5-7 pF
Equivalent Series Resistance (ESR)
50 to 80 Correlation Drive Level
100 W
Aging
5 ppm/Yr
(First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
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NBC12439
3.3 V or
5.0 V
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.
The NBC12439 provides sub-nanosecond output edge
rates and therefore a good power supply bypassing scheme
is a must. Figure 8 shows a representative board layout for
the NBC12439. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 8 is the low impedance connections
between VCC and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective
capacitor resonances at frequencies adequate to supply the
instantaneous switching current for the NBC12439 outputs.
It is imperative that low inductance chip capacitors are used.
It is equally important that the board layout not introduce
any of the inductance saved by using the leadless capacitors.
Thin interconnect traces between the capacitor and the
power plane should be avoided and multiple large vias
should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.
3.3 V or
5.0 V
L=1000 H
R=15 RS = 10-15 PLL_VCC
22 F
NBC12439
0.01 F
VCC
0.01 F
Figure 7. Power Supply Filter
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. Figure 7
shows a 1000 H choke. This value choke will show a
significant impedance at 10 KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_VCC pin, a low DC resistance
inductor is required (less than 15 ). Generally, the
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
C1
ÉÉ
ÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
C1
R1
1
C3
C2
R1 = 10-15 C1 = 0.01 F
C2 = 22 F
C3 = 0.1 F
Xtal
ÉÉ
ÉÉ
= VCC
= GND
= Via
Figure 8. PCB Board Layout for NBC12439 (28 PLCC)
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.
Although the NBC12439 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL), there still
may be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise-related
problems in most designs.
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on-board oscillator. Note the provisions for
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13
NBC12439
Jitter Performance of the NBC12439
create a histogram of the edge placements and record
peak-to-peak as well as standard deviations of the jitter.
Care must be taken that the measured edge is the edge
immediately following the trigger edge. These scopes can
also store a finite number of period durations and
post-processing software can analyze the data to find the
maximum and minimum periods.
Recent hardware and software developments have
resulted in advanced jitter measurement techniques. The
Tektronix TDS-series oscilloscopes have superb jitter
analysis capabilities on non-contiguous clocks with their
histogram and statistics capabilities. The Tektronix
TDSJIT2/3 Jitter Analysis software provides many key
timing parameter measurements and will extend that
capability by making jitter measurements on contiguous
clock and data cycles from single-shot acquisitions.
M1 by Amherst was used as well and both test methods
correlated.
These test processes can be correlated to earlier test
methods and are more accurate. All of the jitter data reported
on the NBC12439 was collected in this manner. Figure 11
shows the RMS jitter performance as a function of the VCO
frequency range. The general trend is that as the VCO
frequency is increased, the RMS output jitter will decrease.
Figure 12 illustrates the RMS jitter performance versus
the output frequency. Note the jitter is a function of both the
output frequency as well as the VCO frequency. However,
the VCO frequency shows a much stronger dependence.
Long-Term Period Jitter is the maximum jitter
observed at the end of a period’s edge when compared to the
position of the perfect reference clock’s edge and is specified
by the number of cycles over which the jitter is measured.
The number of cycles used to look for the maximum jitter
varies by application but the JEDEC spec is 10,000 observed
cycles.
The NBC12439 exhibits long term and cycle-to-cycle
jitter, which rivals that of SAW based oscillators. This jitter
performance comes with the added flexibility associated
with a synthesizer over a fixed frequency oscillator. The
jitter data presented should provide users with enough
information to determine the effect on their overall timing
budget. The jitter performance meets the needs of most
system designs while adding the flexibility of frequency
margining and field upgrades. These features are not
available with a fixed frequency SAW oscillator.
Jitter is a common parameter associated with clock
generation and distribution. Clock jitter can be defined as the
deviation in a clock’s output transition from its ideal
position.
Cycle-to-Cycle Jitter (short-term) is the period
variation between adjacent periods over a defined number of
observed cycles. The number of cycles observed is
application dependent but the JEDEC specification is 1000
cycles. See Figure 9.
T0
T1
TJITTER(cycle- cycle) = T1 - T0
Figure 9. Cycle-to-Cycle Jitter
RMS
or one
Sigma
Jitter
Time*
*1,000 - 10,000 Cycles
Peak-to-Peak Jitter
Jitter Amplitude
Random Peak-to-Peak Jitter is the difference between
the highest and lowest acquired value and is represented as
the width of the Gaussian base. See Figure 10.
Typical
Gaussian
Distribution
Figure 10. Random Peak-to-Peak and RMS Jitter
There are different ways to measure jitter and often they
are confused with one another. An earlier method of
measuring jitter is to look at the timing signal with an
oscilloscope and observe the variations in period-to-period
or cycle-to-cycle. If the scope is set up to trigger on every
rising or falling edge, set to infinite persistence mode and
allowed to trace sufficient cycles, it is possible to determine
the maximum and minimum periods of the timing signal.
Digital scopes can accumulate a large number of cycles,
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14
25
25
20
20
RMS JITTER (ps)
RMS JITTER (ps)
NBC12439
15
10
N=8
N=4
15
10
5
5
N=1
N=2
0
400
0
500
600
700
800
100
VCO FREQUENCY (MHz)
200
300
400
500
600
700
OUTPUT FREQUENCY (MHz)
Figure 12. Cycle-to-Cycle RMS Jitter vs.
Output Frequency
Figure 11. Cycle-to-Cycle RMS Jitter vs.
VCO Frequency
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15
800
NBC12439
S_DATA
S_CLOCK
tHOLD
tSET- UP
Figure 13. Set-Up and Hold
S_DATA
S_LOAD
tHOLD
tSET- UP
Figure 14. Set-Up and Hold
M[8:0]
N[1:0]
P_LOAD
tHOLD
tSET- UP
Figure 15. Set-Up and Hold
FOUT
FOUT
Pulse Width
tPERIOD
Figure 16. Output Duty Cycle
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16
DCO pw
PERIOD
NBC12439
FOUT
D
Receiver
Device
Driver
Device
FOUT
D
50 50 V TT
V TT = V CC - 2.0 V
Figure 17. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
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NBC12439
PACKAGE DIMENSIONS
PLCC-28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776-02
ISSUE E
0.007 (0.180)
B
Y BRK
-N-
M
T L−M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
-M-
-L-
W
28
D
X
0.010 (0.250)
G1
T L−M
S
N
S
S
V
1
VIEW D-D
A
0.007 (0.180)
R
0.007 (0.180)
Z
C
M
M
T L−M
T L−M
S
S
N
N
S
0.007 (0.180)
H
0.004 (0.100)
J
0.010 (0.250)
S
-T-
T L−M
S
N
N
S
S
K
SEATING
PLANE
F
VIEW S
G1
T L−M
K1
E
G
M
S
S
VIEW S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−−
0.020
2
10
0.410
0.430
0.040
−−−
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18
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2
10
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
NBC12439
PACKAGE DIMENSIONS
A
32
A1
-T-, -U-, -Z-
LQFP-32
FA SUFFIX
PLASTIC LQFP PACKAGE
CASE 873A-02
ISSUE A
4X
25
0.20 (0.008) AB T−U Z
1
AE
-U-
-TB
P
V
17
8
BASE
METAL
DETAIL Y
V1
ÉÉ
ÉÉ
ÉÉ
ÉÉ
-Z9
S1
4X
0.20 (0.008) AC T−U Z
F
S
8X
M
J
R
D
DETAIL AD
G
SECTION AE-AE
-AB-
C E
-AC-
H
W
K
X
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED
AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
http://onsemi.com
19
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12 REF
0.090
0.160
0.400 BSC
1
5
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12 REF
0.004
0.006
0.016 BSC
1
5
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Q
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
M
N
9
0.20 (0.008)
DETAIL Y
AC T−U Z
AE
B1
NBC12439
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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20
NBC12439/D