Intersil CDP1822D 256-word x 4-bit lsi static ram Datasheet

CDP1822,
CDP1822C
256-Word x 4-Bit
LSI Static RAM
March 1997
Features
Description
• Low Operating Current
- VDD = 5V, Cycle Time 1µs . . . . . . . . . . . . . . . . . . 8mA
The CDP1822 and CDP1822C are 256-word by 4-bit static
random-access memories designed for use in memory systems where high speed, low operating current, and simplicity
in use are desirable. The CDP1822 features high speed and
a wide operating voltage range. Both types have separate
data inputs and outputs and utilize single power supplies of
4V to 6.5V for the CDP1822C and 4V to 10.5V for the
CDP1822.
• Industry Standard Pinout
• Two Chip-Select Inputs-Simple Memory Expansion
• Memory Retention for Standby Battery Voltage of 2V
Minimum
• Output-Disable for Common I/O Systems
• Three-State Data Output for Bus-Oriented Systems
• Separate Data Inputs and Outputs
Ordering Information
5V
CDP1822CE
10V
CDP1822E
CDP1822CEX CDP1822EX
CDP1822CD
CDP1822CDX
CDP1822D
-
PACKAGE
TEMP. RANGE
PDIP
-40oC to +85oC
E22.4
E22.4
Burn-In
SBDIP
PKG.
NO.
-40oC to +85oC
D22.4A
D22.4A
Burn-In
Two Chip-Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output systems. The Output Disable input allows these RAMs to be
used in common data Input/Output systems by forcing the
output into a high-impedance state during a write operation
independent of the Chip-Select input condition. The output
assumes a high-impedance state when the Output Disable is
at high level or when the chip is deselected by CS1 and/or
CS2.
The high noise immunity of the CMOS technology is preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
Pinout
CDP1822, CDP1822C
(PDIP, SBDIP)
TOP VIEW
A3 1
22 VDD
A2 2
21 A4
A1 3
20 R/W
A0 4
19 CS1
A5 5
18 O. D.
A6 6
17 CS2
A7 7
16 DO4
VSS 8
15 DI4
DI1 9
14 DO3
DO1 10
13 DI3
DI2 11
12 DO2
OPERATIONAL MODES
INPUTS
CHIP
SELECT
1
(CS1)
CHIP
SELECT
2
(CS2)
Read
0
1
0
1
Read
Write
0
1
0
0
Data In
Write
0
1
1
0
High
Impedance
Standby
1
X
X
X
High
Impedance
Standby
X
0
X
X
High
Impedance
Output
Disable
X
X
1
X
High
Impedance
MODE
OUTPUT READ/
DISABLE WRITE
(OD)
(R/W)
OUTPUT
NOTE:
Logic 1 = High, Logic 0 = Low, X = Don’t Care.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-11
File Number
1074.2
CDP1822, CDP1822C
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1822 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1822C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
75
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
80
21
Maximum Operating Temperature Range (TA)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC
TA = -40oC to +60oC (Package Type E) . . . . . . . . . . . . . . 500mW
TA = +60oC to +85oC (Package Type E) . . . . . . Derate Linearly at
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12mW/oC to 200mW
Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . . 300oC
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
LIMITS
CDP1822
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
VSS
VDD
VSS
VDD
V
DC Operating Voltage Range
Input Voltage Range
CDP1822C
At TA = -40oC to +85oC, Except as Noted
Static Electrical Specifications
CONDITIONS
LIMITS
CDP1822
CDP1822C
SYMBOL
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
Quiescent Device
Current
IDD
-
0, 5
5
-
-
500
-
-
500
µA
-
0, 10
10
-
-
1000
-
-
-
µA
Output Low (Sink)
Current
IOL
0.4
0, 5
5
2
4
-
2
4
-
mA
0.5
0, 10
10
4.5
9
-
-
-
-
mA
Output High (Source)
Current
IOH
4.6
0, 5
5
-1
-2
-
-1
-2
-
mA
9.5
0, 10
10
-2.2
-4.4
-
-
-
-
mA
Output Voltage
Low-Level
VOL
-
0, 5
5
-
0
0.1
-
0
0.1
V
-
0, 10
10
-
0
0.1
-
-
-
V
Output Voltage
High-Level
VOH
-
0, 5
5
4.9
5
-
4.9
5
-
V
-
0, 10
10
9.9
10
-
-
-
-
V
Input Low Voltage
VIL
0.5, 4.5
-
5
-
-
1.5
-
-
1.5
V
0.5, 9.5
-
10
-
-
3
-
-
-
V
0.5, 9.5
-
5
3.5
-
-
3.5
-
-
V
0.5, 9.5
-
10
7
-
-
-
-
-
V
-
0, 5
5
-
-
±5
-
-
±5
µA
-
0, 10
10
-
-
±10
-
-
-
µA
PARAMETER
Input High Voltage
Input Leakage Current
VIH
IIN
6-12
CDP1822, CDP1822C
At TA = -40oC to +85oC, Except as Noted (Continued)
Static Electrical Specifications
CONDITIONS
LIMITS
CDP1822
CDP1822C
SYMBOL
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
Operating Current
(Note 2)
IDD1
-
0, 5
5
-
4
8
-
4
8
mA
-
0, 10
10
-
8
16
-
-
-
mA
Three-State Output
Leakage Current
IOUT
0, 5
0, 5
5
-
-
±5
-
-
±5
µA
0, 10
0, 10
10
-
-
±10
-
-
-
µA
Input Capacitance
CIN
-
-
-
-
5
7.5
-
5
7.5
pF
COUT
-
-
-
-
10
15
-
10
15
pF
PARAMETER
Output Capacitance
NOTES:
1. Typical values are for TA = +25oC and nominal VDD.
2. Outputs open circuited; Cycle time = 1µs.
Dynamic Electrical Specifications
At TA + -40 to +85oC, VDD ±5%, Input t R, t F = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD ,
CL = 100 pF
TEST
CONDITIONS
LIMITS
CD1822
PARAMETER
CDP1822C
VDD
(V)
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
UNITS
5
450
-
-
450
-
-
ns
10
250
-
-
-
-
-
ns
5
-
250
450
-
250
450
ns
10
-
150
250
-
-
-
ns
5
-
250
450
-
250
450
ns
10
-
150
250
-
-
-
ns
5
-
250
450
-
250
450
ns
10
-
150
250
-
-
-
ns
5
-
-
200
-
-
200
ns
10
-
-
110
-
-
-
ns
5
20
-
-
20
-
-
ns
10
20
-
-
-
-
-
ns
5
20
-
-
20
-
-
ns
10
20
-
-
-
-
-
ns
5
20
-
-
20
-
-
ns
10
20
-
-
-
-
-
ns
Read Cycle Times (Figure 1)
Read Cycle
Access from Address
Output Valid from Chip-Select 1
Output Valid from Chip-Select 2
tRC
tAA
tDOA1
tDOA2
Output Valid from Output Disable tDOA3
Output Hold from Chip-Select 1
Output Hold from Chip-Select 2
tDOH1
tDOH2
Output Hold from Output Disable tDOH3
NOTES:
1. Time required by a limit device to allow for indicated function.
2. Typical values are for TA = 25oC and nominal VDD.
6-13
CDP1822, CDP1822C
tRC
A0 - A7
tDOA1
CHIP-SELECT 1
CHIP-SELECT 2
tDOH1
tDOH2
tDOA2
tDOA3
OUTPUT DISABLE
tDOH3
READ/WRITE
tAA
DATA OUT
VALID
DATA OUT
HIGH
IMPEDANCE
HIGH
IMPEDANCE
FIGURE 1. READ CYCLE TIMING WAVEFORMS
Dynamic Electrical Specifications
At TA + -40 to +85oC, VDD ±5%, Input t R, t F = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD ,
CL = 100 pF.
LIMITS
TEST
CONDITIONS
PARAMETER
CD1822
CDP1822C
VDD
(V)
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
UNITS
5
500
-
-
500
-
-
ns
10
300
-
-
-
-
-
ns
5
200
-
-
200
-
-
ns
10
110
-
-
-
-
-
ns
5
50
-
-
50
-
-
ns
10
40
-
-
-
-
-
ns
5
250
-
-
250
-
-
ns
10
150
-
-
-
-
-
ns
5
250
-
-
250
-
-
ns
10
150
-
-
-
-
-
ns
5
50
-
-
50
-
-
ns
10
40
-
-
-
-
-
ns
5
200
-
-
200
-
-
ns
10
110
-
-
-
-
-
ns
5
200
-
-
200
-
-
ns
10
110
-
-
-
-
-
ns
Read Cycle Times (Figure 2)
Write Cycle
Address Setup
Write Recovery
Write Width
Input Data Setup Time
Data Hold
Chip-Select 1 Setup
Chip-Select 2 Setup
tWC
tAS
tWR
tWRW
tDS
tDH
tCS1S
tCS2S
6-14
CDP1822, CDP1822C
Dynamic Electrical Specifications
At TA + -40 to +85oC, VDD ±5%, Input t R, t F = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD ,
CL = 100 pF. (Continued)
LIMITS
TEST
CONDITIONS
PARAMETER
Chip-Select 1 Hold
tCS1H
Chip-Select 2 Hold
tCS2H
Output Disable Set-Up
tODS
CD1822
CDP1822C
VDD
(V)
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
UNITS
5
0
-
-
0
-
-
ns
10
0
-
-
0
-
-
ns
5
0
-
-
0
-
-
ns
10
0
-
-
0
-
-
ns
5
200
-
-
200
-
-
ns
10
110
-
-
-
-
-
ns
NOTES:
1. Time required by a limit device to allow for indicated function.
2. Typical values are for TA = 25oC and nominal VDD.
tWC
tWR
A0-A7
tCSIS
tCSIH
CHIP-SELECT 1
CHIP-SELECT 2
tCS2S
OUTPUT DISABLE
tCS2H
(NOTE)
tODS
tDS
DI1-DI4
tDH
DATA IN STABLE
tWRW
READ/WRITE
tAS
DON’T CARE
NOTE: tODS is required for common I/O operation only. For separate I/O operations, output disable is don’t care.
FIGURE 2. WRITE CYCLE TIME WAVEFORMS
6-15
CDP1822, CDP1822C
At TA = -40 to +85oC, see Figure 3.
Data Retention Specifications
LIMITS
TEST CONDITIONS
PARAMETER
Min. Data Retention Voltage
VDR
Data Retention Quiescent
Current
IDD
Chip Deselect to Data Retention
Time
tCDR
Recovery to Normal Operation
Time
tRC
VDD to VDR Rise and Fall Time
tR, tF
CDP1822
CDP1822C
VDR
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
-
-
-
1.5
2
-
1.5
2
V
2
-
-
30
100
-
30
100
µA
-
5
600
-
-
600
-
-
ns
-
10
300
-
-
-
-
-
ns
-
5
600
-
-
600
-
-
ns
-
10
300
-
-
-
-
-
ns
2
5
1
-
-
1
-
-
µA
NOTE: Typical values are for TA = 25oC and nominal VDD.
VDD
DATA RETENTION
MODE
0.95 VDD
DATA IN
0.95 VDD
VDR
tCDR
CS2
VIH
VIL
tf
tr
VSS
tRC
READ
ADDRESS
DECODER
WRITE
ADDRESS
DECODER
VIH
DATA OUT
VDD
VIL
VDD
FIGURE 3. LOW VDD DATA RETENTION TIME WAVEFORMS
FIGURE 4. MEMORY CELL CONFIGURATION
6-16
CDP1822, CDP1822C
A0
A1
A2
A3
A4
DI1
DI2
DI3
DI4
A5
A6
A7
R/W
CSI
CS2
OD
†4
†3
†2
†1
† 21
(5)
INPUT
BUFFERS
AND
ALL ROWS
DESELECT
FUNCTION
(32)
ROW
22
DECODERS
(8 x 32)
STORAGE
ARRAY
†9
† 11
† 13
† 15
†5
†6
†7
†17
(8 x 32)
STORAGE
ARRAY
(8 x 32)
STORAGE
ARRAY
(4)
GATES
(4)
BITS
(1-4)
(3)
INPUT
BUFFERS
AND
ALL COLUMNS
DESELECT
FUNCTION
†20
†19
(8 x 32)
STORAGE
ARRAY
BIT (1)
BIT (2)
BIT (3)
(8)
(8)
(8)
(8)
COLUMN
DECODERS
COLUMN
DECODERS
COLUMN
DECODERS
COLUMN
DECODERS
BUFFER
DRIVERS
10
†††
VDD
††
D01
12 ††
D02
14 ††
D03
16 ††
D04
BIT (4)
CONTROL
B
8
CONTROL
C
CONTROL
A
†18
VDD
VDD
VSS
† INPUT PROTECTION
NETWORK
VDD
VSS
† † OUTPUT
VSS
† † † OVER VOLTAGE
PROTECTION
CIRCUIT
PROTECTION
CIRCUIT
FIGURE 5. FUNCTIONAL BLOCK DIAGRAM FOR CDP1822 AND CDP1822C
6-17
†††
VSS
CDP1822, CDP1822CS
C
CONTROL A
CS1 19
A
CHIP-SELECT
CONTROL
CS2 17
CONTROL B
B
CHIP-SELECT AND
R/W CONTROL
R/W 20
CONTROL C
C
OUTPUT
DISABLE
CONTROL
OUTPUT
18
DISABLE
FIGURE 6. LOGIC DIAGRAM OF CONTROLS FOR CDP1822 AND CDP1822C
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