Design Resources Online Documentation Product Overview Sample & Buy Discussion 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers AD7175-2 Data Sheet FEATURES GENERAL DESCRIPTION Fast and flexible output rate: 5 SPS to 250 kSPS Channel scan data rate of 50 kSPS/channel (20 µs settling) Performance specifications 17.2 noise free bits at 250 kSPS 20 noise free bits at 2.5 kSPS 24 noise free bits at 20 SPS INL: ±1 ppm of FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 2 fully differential channels or 4 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock Power supply: AVDD1 = 5 V, AVDD2 = IOVDD = 2 V to 5 V Split supply with AVDD1/AVSS at ±2.5 V ADC current: 8.4 mA Temperature range: −40°C to +105°C 3- or 4-wire serial digital interface (Schmitt trigger on SCLK) Serial port interface (SPI), QSPI, MICROWIRE, and DSP compatible The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SPS to 250 kSPS. APPLICATIONS The device operates with a 5 V AVDD1, or ±2.5 V AVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD supplies. The specified operating temperature range is −40°C to +105°C. The AD7175-2 is in a 24-lead TSSOP package. The AD7175-2 integrates key analog and digital signal conditioning blocks to allow users to configure an individual setup for each analog input channel in use. Each feature can be user selected on a per channel basis. Integrated true rail-to-rail buffers on the analog inputs and external reference inputs provide easy to drive high impedance inputs. The precision 2.5 V low drift (2 ppm/°C) band gap internal reference (with output reference buffer) adds embedded functionality to reduce external component count. The digital filter allows simultaneous 50 Hz/60 Hz rejection at 27.27 SPS output data rate. The user can switch between different filter options according to the demands of each channel in the application. The ADC automatically switches through each selected channel. Further digital processing functions include offset and gain calibration registers, configurable on a per channel basis. Process control: PLC/DCS modules Temperature and pressure measurement Medical and scientific multichannel instrumentation Chromatography Note that, throughout this data sheet, the dual function pin names are referenced by the relevant function only. FUNCTIONAL BLOCK DIAGRAM AVDD1 CROSSPOINT MULTIPLEXER AIN0 AVDD2 REGCAPA RAIL-TO-RAIL REFERENCE INPUT BUFFERS 1.8V LDO AVDD AIN1 REF– REF+ REFOUT IOVDD REGCAPD BUFFERED PRECISION REFERENCE 1.8V LDO INT REF RAIL-TO-RAIL ANALOG INPUT BUFFERS CS DIGITAL FILTER Σ-Δ ADC AIN2 SERIAL INTERFACE AND CONTROL SCLK DIN DOUT/RDY AIN3 GPIO AND MUX I/O CONTROL AVSS SYNC/ERROR XTAL AND INTERNAL CLOCK OSCILLATOR CIRCUITRY AD7175-2 TEMPERATURE SENSOR AVSS GPIO0 GPIO1 XTAL1 XTAL2/CLKIO DGND 12468-001 AIN4 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com Product Overview Design Resources Online Documentation AD7175-2 Discussion Sample & Buy Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 CRC Calculation......................................................................... 45 Applications ....................................................................................... 1 Integrated Functions ...................................................................... 47 General Description ......................................................................... 1 General-Purpose I/O ................................................................. 47 Functional Block Diagram .............................................................. 1 External Multiplexer Control ................................................... 47 Revision History ............................................................................... 3 Delay ............................................................................................ 47 Specifications..................................................................................... 4 16-Bit/24-Bit Conversions......................................................... 47 Timing Characteristics ................................................................ 7 DOUT_RESET ........................................................................... 47 Timing Diagrams.......................................................................... 8 Synchronization .......................................................................... 47 Absolute Maximum Ratings ............................................................ 9 Error Flags ................................................................................... 48 Thermal Resistance ...................................................................... 9 DATA_STAT ............................................................................... 49 ESD Caution .................................................................................. 9 IOSTRENGTH ........................................................................... 49 Pin Configuration and Function Descriptions ........................... 10 Internal Temperature Sensor .................................................... 49 Typical Performance Characteristics ........................................... 12 Grounding and Layout .................................................................. 50 Noise Performance and Resolution .............................................. 19 Register Summary .......................................................................... 51 Getting Started ................................................................................ 20 Register Details ............................................................................... 52 Power Supplies ............................................................................ 21 Communications Register......................................................... 52 Digital Communication............................................................. 21 Status Register ............................................................................. 53 AD7175-2 Reset .......................................................................... 22 ADC Mode Register ................................................................... 54 Configuration Overview ........................................................... 22 Interface Mode Register ............................................................ 55 Circuit Description ......................................................................... 28 Register Check ............................................................................ 56 Buffered Analog Input ............................................................... 28 Data Register ............................................................................... 56 Crosspoint Multiplexer .............................................................. 28 GPIO Configuration Register ................................................... 57 AD7175-2 Reference .................................................................. 29 ID Register................................................................................... 58 Buffered Reference Input ........................................................... 30 Channel Register 0 ..................................................................... 58 Clock Source ............................................................................... 30 Channel Register 1 to Channel Register 3 .............................. 59 Digital Filters ................................................................................... 32 Setup Configuration Register 0 ................................................ 60 Sinc5 + Sinc1 Filter..................................................................... 32 Sinc3 Filter ................................................................................... 32 Setup Configuration Register 1 to Setup Configuration Register 3 ..................................................................................... 60 Single Cycle Settling ................................................................... 33 Filter Configuration Register 0................................................. 61 Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 37 Filter Configuration Register 1 to Filter Configuration Register 3 ..................................................................................... 62 Operating Modes ............................................................................ 40 Continuous Conversion Mode ................................................. 40 Continuous Read Mode ............................................................. 41 Single Conversion Mode ........................................................... 42 Standby and Power-Down Modes............................................ 43 Calibration ................................................................................... 43 Digital Interface .............................................................................. 44 Offset Register 0 ......................................................................... 62 Offset Register 1 to Offset Register 3....................................... 62 Gain Register 0............................................................................ 62 Gain Register 1 to Gain Register 3 ........................................... 62 Outline Dimensions ....................................................................... 63 Ordering Guide .......................................................................... 63 Checksum Protection................................................................. 44 Rev. A | Page 2 of 63 Product Overview Design Resources Online Documentation Data Sheet Discussion Sample & Buy AD7175-2 REVISION HISTORY 9/14—Rev. 0 to Rev. A Changes to Ordering Guide ...........................................................60 7/14—Revision 0: Initial Version Rev. A | Page 3 of 63 Product Overview Design Resources Online Documentation Sample & Buy Discussion AD7175-2 Data Sheet SPECIFICATIONS AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, MCLK = internal master clock = 16 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted. Table 1. Parameter ADC SPEED AND PERFORMANCE Output Data Rate (ODR) No Missing Codes 1 Resolution Noise ACCURACY Integral Nonlinearity (INL) Offset Error 2 Offset Drift Gain Error2 Gain Drift REJECTION Power Supply Rejection Common-Mode Rejection At DC At 50 Hz, 60 Hz1 Normal Mode Rejection1 ANALOG INPUTS Differential Input Range Absolute Voltage Limits1 Input Buffers Disabled Input Buffers Enabled Analog Input Current Input Buffers Disabled Input Current Input Current Drift Input Buffers Enabled Input Current Input Current Drift Crosstalk INTERNAL REFERENCE Output Voltage Initial Accuracy 3 Temperature Coefficient 0°C to 105°C −40°C to +105°C Reference Load Current, ILOAD Power Supply Rejection Load Regulation Voltage Noise Test Conditions/Comments Excluding sinc3 filter ≥ 125 kSPS See Table 6 and Table 7 See Table 6 and Table 7 Min Typ 5 24 Analog input buffers enabled Analog input buffers disabled Internal short Internal short ±3.5 ±1 ±40 ±80 ±35 ±0.4 AVDD1, AVDD2, VIN = 1 V VIN = 0.1 V Max Unit 250,000 SPS Bits ±7.8 ±3.5 ppm of FSR ppm of FSR µV nV/°C ppm of FSR ppm/°C ±85 ±0.75 95 20 Hz output data rate (post filter), 50 Hz ± 1 Hz and 60 Hz ± 1 Hz 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) External clock, 20 SPS ODR (postfilter) 95 120 71 85 VREF = (REF+) − (REF−) dB dB 90 90 dB dB ±VREF V AVSS − 0.05 AVSS External clock Internal clock (±2.5% clock) AVDD1 − 0.2 V to AVSS + 0.2 V AVDD1 to AVSS 1 kHz input 100 nF external capacitor to AVSS REFOUT, with respect to AVSS REFOUT, TA = 25°C AVDD1 + 0.05 AVDD1 µA/V nA/V/°C nA/V/°C ±30 ±75 ±1 −120 nA pA/°C nA/°C dB 2.5 −0.12 +0.12 −10 Rev. A | Page 4 of 63 V V ±48 ±0.75 ±4 ±2 ±3 AVDD1, AVDD2, (line regulation) ∆VOUT/∆ILOAD eN, 0.1 Hz to 10 Hz, 2.5 V reference dB 90 32 4.5 ±5 ±10 +10 V % of V ppm/°C ppm/°C mA dB ppm/mA µV rms Product Overview Design Resources Online Documentation Sample & Buy Discussion Data Sheet Parameter Voltage Noise Density Turn-On Settling Time Short-Circuit Current, ISC EXTERNAL REFERENCE INPUTS Differential Input Range Absolute Voltage Limits1 Input Buffers Disabled Input Buffers Enabled REFIN Input Current Input Buffers Disabled Input Current Input Current Drift Input Buffers Enabled Input Current Input Current Drift Normal Mode Rejection1 Common-Mode Rejection TEMPERATURE SENSOR Accuracy Sensitivity BURNOUT CURRENTS Source/Sink Current GENERAL-PURPOSE I/O (GPIO0, GPIO1) Input Mode Leakage Current1 Floating State Output Capacitance Output High Voltage, VOH1 Output Low Voltage, VOL1 Input High Voltage, VIH1 Input Low Voltage, VIL1 CLOCK Internal Clock Frequency Accuracy Duty Cycle Output Low Voltage, VOL Output High Voltage, VOH Crystal Frequency Startup Time External Clock (CLKIO) Duty Cycle1 AD7175-2 Test Conditions/Comments eN, 1 kHz, 2.5 V reference 100 nF REFOUT capacitor Min Typ 215 200 25 Max Unit nV/√Hz µs mA VREF = (REF+) − (REF−) 1 2.5 AVDD1 V AVDD1 + 0.05 AVDD1 V V AVSS − 0.05 AVSS ±72 ±1.2 ±6 µA/V nA/V/°C nA/V/°C ±800 1.25 nA nA/°C 95 dB After user calibration at 25°C ±2 477 °C µV/K Analog input buffers must be enabled With respect to AVSS ±10 µA External clock Internal clock See the Rejection parameter −10 +10 5 ISOURCE = 200 µA ISINK = 800 µA AVSS + 4 AVSS + 0.4 AVSS + 3 AVSS + 0.7 16 −2.5% +2.5% 50 0.4 0.8 × IOVDD 14 30 Rev. A | Page 5 of 63 16 10 16 50 16.384 16.384 70 µA pF V V V V MHz % % V V MHz µs MHz % Product Overview Design Resources Online Documentation Sample & Buy Discussion AD7175-2 Parameter LOGIC INPUTS Input High Voltage, VINH1 Input Low Voltage, VINL1 Hysteresis1 Leakage Currents LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH1 Output Low Voltage, VOL1 Leakage Current Output Capacitance SYSTEM CALIBRATION1 Full-Scale (FS) Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS Power Supply Voltage AVDD1 to AVSS AVDD2 to AVSS AVSS to DGND IOVDD to DGND IOVDD to AVSS POWER SUPPLY CURRENTS 4 Full Operating Mode AVDD1 Current AVDD2 Current IOVDD Current Standby Mode (LDO On) Power-Down Mode Data Sheet Test Conditions/Comments Min 2 V ≤ IOVDD < 2.3 V 2.3 V ≤ IOVDD ≤ 5.5 V 2 V ≤ IOVDD < 2.3 V 2.3 V ≤ IOVDD ≤ 5.5 V IOVDD ≥ 2.7 V IOVDD < 2.7 V 0.65 × IOVDD 0.7 × IOVDD IOVDD ≥ 4.5 V, ISOURCE = 1 mA 2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 µA IOVDD < 2.7 V, ISOURCE = 200 µA IOVDD ≥ 4.5 V, ISINK = 2 mA 2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA IOVDD < 2.7 V, ISINK = 400 µA Floating state Floating state 0.8 × IOVDD 0.8 × IOVDD 0.8 × IOVDD Typ 0.08 0.04 −10 Max Unit 0.35 × IOVDD 0.7 0.25 0.2 +10 V V V V V V µA 0.4 0.4 0.4 +10 −10 10 1.05 × FS 2.1 × FS V V V 5.5 5.5 0 5.5 6.35 V V V V V 1.4 1.65 mA 1.75 2 mA 13 16 mA −1.05 × FS 0.8 × FS 4.5 2 −2.75 2 For AVSS < DGND All outputs unloaded, digital inputs connected to IOVDD or DGND Analog input and reference input buffers disabled, external reference Analog input and reference input buffers disabled, internal reference Analog input and reference input buffers enabled, external reference Each buffer: AIN+, AIN−, REF+, REF− External reference Internal reference External clock Internal clock External crystal Internal reference off, total current consumption Internal reference on, total current consumption Full power-down (including LDO and internal reference) Rev. A | Page 6 of 63 V V V V V V µA pF 2.9 4.5 4.75 2.5 2.75 3 25 5 5.2 2.8 3.1 425 5 mA mA mA mA mA mA µA µA 10 µA Design Resources Online Documentation Product Overview Sample & Buy Discussion Data Sheet AD7175-2 Parameter POWER DISSIPATION4 Full Operating Mode Test Conditions/Comments Min All buffers disabled, external clock and reference, AVDD2 = 2 V, IOVDD = 2 V All buffers disabled, external clock and reference, all supplies = 5 V All buffers disabled, external clock and reference, all supplies = 5.5 V All buffers enabled, internal clock and reference, AVDD2 = 2 V, IOVDD = 2 V All buffers enabled, internal clock and reference, all supplies = 5 V All buffers enabled, internal clock and reference, all supplies = 5.5 V Internal reference off, all supplies = 5 V Internal reference on, all supplies = 5 V Full power-down, all supplies = 5 V Standby Mode Power-Down Mode Typ Max Unit 21 mW 42 mW 52 mW 82 mW 105 mW 125 2.2 25 136 mW 50 µW mW µW Specification is not production tested but is supported by characterization data at initial product release. Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 3 This specification includes moisture sensitivity level (MSL) preconditioning effects. 4 This specification is with no load on the REFOUT and digital output pins. 1 2 TIMING CHARACTERISTICS IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted. Table 2. Parameter SCLK t3 t4 READ OPERATION t1 t2 3 t5 5 t6 t7 WRITE OPERATION t8 t9 t10 t11 Limit at TMIN, TMAX Unit Test Conditions/Comments 1, 2 25 25 ns min ns min SCLK high pulse width SCLK low pulse width 0 15 40 0 12.5 25 2.5 20 0 10 ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min CS falling edge to DOUT/RDY active time IOVDD = 4.75 V to 5.5 V IOVDD = 2 V to 3.6 V SCLK active edge to data valid delay 4 IOVDD = 4.75 V to 5.5 V IOVDD = 2 V to 3.6 V Bus relinquish time after CS inactive edge 0 8 8 5 ns min ns min ns min ns min CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high/low Sample tested during initial release to ensure compliance. See Figure 2 and Figure 3. 3 This parameter is defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 DOUT/RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while DOUT/RDY is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. 1 2 Rev. A | Page 7 of 63 Product Overview Design Resources Online Documentation Discussion AD7175-2 Sample & Buy Data Sheet TIMING DIAGRAMS CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 12468-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 2. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 3. Write Cycle Timing Diagram Rev. A | Page 8 of 63 12468-004 DIN (I) Product Overview Design Resources Online Documentation Discussion Sample & Buy Data Sheet AD7175-2 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for a device soldered on a JEDEC test board for surface-mount packages. Parameter AVDD1, AVDD2 to AVSS AVDD1 to DGND IOVDD to DGND IOVDD to AVSS AVSS to DGND Analog Input Voltage to AVSS Reference Input Voltage to AVSS Digital Input Voltage to DGND Digital Output Voltage to DGND Analog Input/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Soldering, Reflow Temperature ESD Rating (HBM) Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +7.5 V −3.25 V to +0.3 V −0.3 V to AVDD1 + 0.3 V −0.3 V to AVDD1 + 0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to IOVDD + 0.3 V 10 mA −40°C to +105°C −65°C to +150°C 150°C 260°C 4 kV Table 4. Thermal Resistance Package Type 24-Lead TSSOP JEDEC 1-Layer Board JEDEC 2-Layer Board ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 9 of 63 θJA Unit 149 81 °C/W °C/W Design Resources Online Documentation Product Overview Discussion AD7175-2 Sample & Buy Data Sheet AIN4 1 24 AIN3 REF– 2 23 AIN2 REF+ 3 22 AIN1 REFOUT 4 21 AIN0 REGCAPA 5 20 GPIO1 19 GPIO0 18 REGCAPD AVDD2 8 17 DGND XTAL1 9 16 IOVDD XTAL2/CLKIO 10 15 SYNC/ERROR DOUT/RDY 11 14 CS DIN 12 13 SCLK AD7175-2 AVSS 6 TOP VIEW (Not to Scale) AVDD1 7 12468-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 Mnemonic AIN4 REF− REF+ Type 1 AI AI AI 4 5 6 7 8 9 10 REFOUT REGCAPA AVSS AVDD1 AVDD2 XTAL1 XTAL2/CLKIO AO AO P P P AI AI/DI 11 DOUT/RDY DO 12 DIN DI 13 SCLK DI 14 CS DI Description Analog Input 4. Selectable through crosspoint multiplexer. Reference Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V. Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+ can span from AVSS + 1 V to AVDD1.The device functions with a reference magnitude from 1 V to AVDD1. Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF and a 0.1 µF capacitor. Negative Analog Supply. This supply ranges from −2.75 V to 0 V and is nominally set to 0 V. Analog Supply Voltage 1. This voltage is 5 V ± 10% with respect to AVSS. Analog Supply Voltage 2. This voltage ranges from 2 V to 5 V with respect to AVSS. Input 1 for Crystal. Input 2 for Crystal/Clock Input or Output. Based on the CLOCKSEL bits in the ADCMODE register. There are four options available for selecting the MCLK source: Internal oscillator: no output. Internal oscillator: output to XTAL2/CLKIO. Operates at IOVDD logic level. External clock: input to XTAL2/CLKIO. Input must be at IOVDD logic level. External crystal: connected between XTAL1 and XTAL2/CLKIO. Serial Data Output/Data Ready Output. DOUT/RDY is a dual purpose pin. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is three-stated. When CS is low, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register address (RA) bits of the communications register identifying the appropriate register. Data is clocked in on the rising edge of SCLK. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt triggered input, making the interface suitable for opto-isolated applications. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. When CS is high, the DOUT/RDY output is three-stated. Rev. A | Page 10 of 63 Online Documentation Product Overview Design Resources Discussion Sample & Buy Data Sheet AD7175-2 Pin No. 15 Mnemonic SYNC/ERROR Type 1 DI/O 16 IOVDD P 17 18 DGND REGCAPD P AO 19 20 21 22 23 24 GPIO0 GPIO1 AIN0 AIN1 AIN2 AIN3 DI/O DI/O AI AI AI AI 1 Description Synchronization Input/Error Input/Output. This pin can be switched between a logic input and a logic output in the GPIOCON register. When synchronization input (SYNC) is enabled, this pin allows synchronization of the digital filters and analog modulators when using multiple AD7175-2 devices. For more information, see the Synchronization section. When the synchronization input is disabled, this pin can be used in one of three modes: Active low error input mode: this mode sets the ADC_ERROR bit in the status register. Active low, open-drain error output mode: the status register error bits are mapped to the ERROR output. The SYNC/ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed. General-purpose output mode: the status of the pin is controlled by the ERR_DAT bit in the GPIOCON register. The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the GPIOx pins. The pin has an active pull-up in this case. Digital I/O Supply Voltage. The IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent of AVDD2. For example, IOVDD can be operated at 3 V when AVDD2 equals 5 V, or vice versa. If AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V. Digital Ground. Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using a 1 µF and a 0.1 µF capacitor. General-Purpose Input/Output 0. The pin is referenced between AVDD1 and AVSS levels. General-Purpose Input/Output 1. The pin is referenced between AVDD1 and AVSS levels. Analog Input 0. Selectable through the crosspoint multiplexer. Analog Input 1. Selectable through the crosspoint multiplexer. Analog Input 2. Selectable through the crosspoint multiplexer. Analog Input 3. Selectable through the crosspoint multiplexer. AI is analog input, AO is analog output, DI/O is bidirectional digital input/output, DO is digital output, DI is digital input, and P is power supply. Rev. A | Page 11 of 63 Product Overview Design Resources Online Documentation Discussion AD7175-2 Sample & Buy Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, TA = 25°C, unless otherwise noted. 1000 8390000 900 8389500 800 8389000 SAMPLE COUNT ADC CODE 700 8388500 8388000 8387500 600 500 400 300 8387000 200 8386500 100 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 12468-205 0 8388460 8388461 8388462 8388463 8388464 8388465 8388466 ADC CODE Figure 5. Noise (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 5 SPS) 12468-208 100 8386000 Figure 8. Histogram (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 5 SPS) 120 8388480 8388475 100 SAMPLE COUNT ADC CODE 8388470 8388465 8388460 80 60 40 8388455 100 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 ADC CODE Figure 6. Noise (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 10 kSPS) 12468-209 0 12468-206 8388445 8388450 8388451 8388452 8388453 8388454 8388455 8388456 8388457 8388458 8388459 8388460 8388461 8388462 8388463 8388464 8388465 8388466 8388467 8388468 8388469 8388470 8388471 8388472 8388473 8388474 8388475 8388476 8388477 20 8388450 Figure 9. Histogram (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 10 kSPS) 8388520 45 40 8388500 35 SAMPLE COUNT 8388460 8388440 30 25 20 15 10 8388420 100 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 ADC CODE Figure 7. Noise (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 250 kSPS) Figure 10. Histogram (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 250 kSPS) Rev. A | Page 12 of 63 12468-210 0 8388420 8388422 8388424 8388426 8388428 8388430 8388432 8388434 8388436 8388438 8388440 8388442 8388444 8388446 8388448 8388450 8388452 8388454 8388456 8388458 8388460 8388462 8388464 8388466 8388468 8388470 8388472 8388474 8388476 8388478 8388480 8388482 8388484 8388486 8388488 8388490 8388492 8388494 8388496 8388498 8388500 8388502 8388504 5 8388400 12468-207 ADC CODE 8388480 Product Overview Design Resources Online Documentation Discussion Data Sheet AD7175-2 8390000 1000 8389500 900 8389000 800 700 8388000 8387500 8387000 600 500 400 8386500 300 8386000 200 8385500 100 0 100 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 12468-211 8385000 8388490 8388491 8388492 8388493 8388494 8388495 8388496 ADC CODE 12468-214 SAMPLE COUNT 8388500 ADC CODE Sample & Buy Figure 14. Histogram (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 5 SPS) Figure 11. Noise (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 5 SPS) 100 8388520 90 8388515 80 8388510 SAMPLE COUNT ADC CODE 70 8388505 8388500 8388495 60 50 40 30 8388490 20 8388485 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 ADC CODE Figure 15. Histogram (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 10 kSPS) 35 8388560 30 8388540 25 8388520 8388500 20 15 8388480 10 8388460 5 8388440 100 200 300 400 500 600 700 SAMPLE NUMBER 800 900 1000 0 8388460 8388462 8388464 8388466 8388468 8388470 8388472 8388474 8388476 8388478 8388480 8388482 8388484 8388486 8388488 8388490 8388492 8388494 8388496 8388498 8388500 8388502 8388504 8388506 8388508 8388510 8388512 8388514 8388516 8388518 8388520 8388522 8388524 8388526 8388528 8388530 8388532 SAMPLE COUNT 8388580 12468-213 ADC CODE Figure 12. Noise (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 10 kSPS) 0 12468-215 200 ADC CODE Figure 13. Noise (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 250 kSPS) Figure 16. Histogram (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 250 kSPS) Rev. A | Page 13 of 63 12468-216 100 12468-212 0 8388480 8388481 8388482 8388483 8388484 8388485 8388486 8388487 8388488 8388489 8388490 8388491 8388492 8388493 8388494 8388495 8388496 8388497 8388498 8388499 8388500 8388501 8388502 8388503 8388504 8388505 8388506 8388507 8388508 8388509 8388510 8388511 8388512 8388513 8388514 10 8388480 Design Resources Online Documentation Product Overview Discussion Sample & Buy AD7175-2 0.000016 Data Sheet 0 BUFFER ON BUFFER OFF 0.000014 –20 0.000012 –40 CMRR (dB) NOISE (V) 0.000010 0.000008 0.000006 –60 –80 0.000004 –100 0 0.5 3.5 4.0 1.0 1.5 2.0 2.5 3.0 INPUT COMMON-MODE VOLTAGE (V) 5.0 4.5 –120 12468-217 0 1 100 1k 10k VIN FREQUENCY (Hz) 100k 1M Figure 20. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency (VIN = 0.1 V, Output Data Rate = 250 kSPS) Figure 17. Noise vs. Input Common-Mode Voltage, Analog Input Buffers On and Off –80 ANALOG INPUT BUFFERS OFF ANALOG INPUT BUFFERS ON 18 –90 14 –110 12 –120 CMRR (dB) 16 –100 10 8 –130 –140 6 –150 4 –160 2 –170 0 2 4 6 8 10 FREQUENCY (MHz) 12 14 16 –180 10 12468-218 0 Figure 18. Noise vs. External Master Clock Frequency, Analog Input Buffers On and Off 16800000 30 40 50 VIN FREQUENCY (Hz) 60 70 Figure 21. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency (VIN = 0.1 V, 10 Hz to 70 Hz, Output Data Rate = 20 SPS Enhanced Filter) CONTINUOUS CONVERSION—REFERENCE DISABLED STANDBY—REFERENCE DISABLED STANDBY—REFERENCE ENABLED 16780000 20 12468-227 20 NOISE (µV rms) 10 12468-226 0.000002 –60 AVDD1—EXTERNAL 2.5V REFERENCE AVDD1—INTERNAL 2.5V REFERENCE –70 16760000 PSRR (dB) 16740000 16720000 16700000 –90 –100 –110 16680000 16660000 1 10 100 SAMPLE NUMBER 1k 10k Figure 19. Internal Reference Settling Time –130 1 10 100 1k 10k 100k VIN FREQUENCY (Hz) 1M 10M 100M Figure 22. Power Supply Rejection Ratio (PSRR) vs. VIN Frequency Rev. A | Page 14 of 63 12468-228 –120 12468-225 OUTPUT CODE –80 Design Resources Online Documentation Product Overview Discussion Sample & Buy Data Sheet 20 30 INTERNAL 2.5V REF, ANALOG INPUT BUFFERS OFF INTERNAL 2.5V REF, ANALOG INPUT BUFFERS ON EXTERNAL 2.5V REF, ANALOG INPUT BUFFERS OFF EXTERNAL 2.5V REF, ANALOG INPUT BUFFERS ON EXTERNAL 5V REF, ANALOG INPUT BUFFERS OFF EXTERNAL 5V REF, ANALOG INPUT BUFFERS ON 10 5 25 SAMPLE COUNT 15 INL (ppm of FS) AD7175-2 0 –5 20 15 10 –10 5 –3 –4 –2 –1 0 1 2 3 4 5 VIN (V) Figure 23. Integral Nonlinearity (INL) vs. VIN (Differential Input) 0.5 30 30 25 25 20 20 15 10 1.5 2.0 2.5 3.0 3.5 INL ERROR (ppm) 4.0 4.5 5.0 15 10 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 INL ERROR (ppm) 0 12468-230 0 Figure 24. Integral Nonlinearity (INL) Distribution Histogram (Differential Input, Analog Input Buffers Enabled, VREF = 2.5 V External, 100 Units) 0.2 0.4 0.6 0.8 1.0 1.2 INL ERROR (ppm) 1.4 1.6 12468-233 5 5 Figure 27. Integral Nonlinearity (INL) Distribution Histogram (Analog Input Buffers Disabled, Differential Input, VREF = 5 V External, 100 Units) 30 5.0 BUFFER DISABLED BUFFER ENABLED 4.5 25 4.0 3.5 20 INL (ppm of FSR) SAMPLE COUNT 1.0 Figure 26. Integral Nonlinearity (INL) Distribution Histogram (Analog Input Buffers Enabled, Differential Input, VREF = 5 V External, 100 Units) SAMPLE COUNT SAMPLE COUNT 0 12468-229 –20 –5 12468-232 –15 15 10 3.0 2.5 2.0 1.5 1.0 5 0.4 0.6 0.8 1.0 1.2 1.4 INL ERROR (ppm) 1.6 1.8 2.0 Figure 25. Integral Nonlinearity (INL) Distribution Histogram (Differential Input, Analog Input Buffers Disabled, VREF = 2.5 V External, 100 Units) Rev. A | Page 15 of 63 0 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 Figure 28. Integral Nonlinearity (INL) vs. Temperature (Differential Input, VREF = 2.5 V External) 100 12468-234 0.2 12468-231 0.5 0 Product Overview Design Resources Online Documentation Discussion Sample & Buy Data Sheet 50 45 45 40 40 35 35 SAMPLE COUNT 50 30 25 20 25 20 15 10 10 5 5 15.99 16.00 16.01 16.02 16.03 FREQUENCY (MHz) 16.04 16.05 0 –40 –30 –20 –10 0 Figure 29. Internal Oscillator Frequency/Accuracy Distribution Histogram (100 Units) Figure 32. Offset Error Distribution Histogram (Internal Short) (248 Units) 16400000 35 16300000 30 16200000 SAMPLE COUNT 25 16100000 16000000 15900000 20 15 10 15800000 0 20 40 60 TEMPERATURE (°C) 80 100 0 12468-236 –20 12468-239 5 15700000 15600000 –40 10 20 30 40 50 60 70 80 90 OFFSET ERROR (µV) –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 15.98 12468-238 0 FREQUENCY (Hz) 30 15 12468-235 SAMPLE COUNT AD7175-2 OFFSET DRIFT ERROR (nV/°C) Figure 30. Internal Oscillator Frequency vs. Temperature Figure 33. Offset Error Drift Distribution Histogram (Internal Short) (248 Units) 0.0010 40 35 SAMPLE COUNT 30 0 –0.0005 25 20 15 10 –0.0010 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 Figure 31. Absolute Reference Error vs. Temperature 100 0 –4 –3 –2 –1 0 1 2 GAIN ERROR (ppm/FSR) 3 4 12468-240 5 12468-237 ERROR (V) 0.0005 Figure 34. Gain Error Distribution Histogram (Analog Input Buffers Enabled) (100 Units) Rev. A | Page 16 of 63 Design Resources Online Documentation Product Overview Discussion Sample & Buy Data Sheet AD7175-2 0.025 30 0.020 20 CURRENT (A) 15 0.015 0.010 10 0.005 5 34 35 36 37 38 39 40 GAIN ERROR (ppm/FSR) 41 42 43 0 –40 12468-241 0 Figure 35. Gain Error Distribution Histogram (Analog Input Buffers Disabled, 100 Units) BUFFERS DISABLED BUFFERS ENABLED –20 0 20 40 60 TEMPERATURE (°C) 80 100 12468-244 SAMPLE COUNT 25 Figure 38. Current Consumption vs. Temperature (Continuous Conversion Mode) 1.6 25 1.4 20 CURRENT (µA) SAMPLE COUNT 1.2 15 10 1.0 0.8 0.6 0.4 5 0 –40 0.30 GAIN ERROR DRIFT (ppm/FSR) 12468-242 0.28 0.26 0.24 0.22 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0 0.02 –0.02 0 Figure 36. Gain Error Drift Distribution Histogram (Analog Input Buffers Enabled, 100 Units) 0 20 40 60 TEMPERATURE (°C) 80 100 Figure 39. Current Consumption vs. Temperature (Power-Down Mode) 40 18 35 16 14 SAMPLE COUNT 30 25 20 15 10 12 10 8 6 4 5 0 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 GAIN ERROR DRIFT (ppm/FSR) 0.50 0.55 Figure 37. Gain Error Drift Distribution Histogram (Analog Input Buffers Disabled, 100 Units) 0 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 TEMPERATURE DELTA (°C) 0.6 0.8 1.0 Figure 40. Temperature Sensor Distribution Histogram (Uncalibrated, 100 Units) Rev. A | Page 17 of 63 12468-246 2 12468-243 SAMPLE COUNT –20 12468-245 0.2 Design Resources Online Documentation Product Overview Discussion Sample & Buy AD7175-2 Data Sheet 100 35 80 30 60 INPUT CURRENT (nA) SAMPLE COUNT 25 20 15 10 AIN+ = AVDD1 – 0.2V AIN– = AVSS + 0.2V AIN+ = AVDD1 AIN– = AVSS 40 20 0 –20 –40 –60 5 Figure 41. Burnout Current Distribution Histogram (100 Units) 100 40 20 0 –20 –40 –60 –80 –100 –5 –4 –3 –2 –1 0 1 2 INPUT VOLTAGE (V) 3 4 5 12468-248 INPUT CURRENT (nA) 60 –20 0 20 40 60 TEMPERATURE (°C) 80 Figure 43. Analog Input Current vs. Temperature –40°C, AIN+ –40°C, AIN– +25°C, AIN+ +25°C, AIN– +105°C, AIN+ +105°C, AIN– 80 –100 –40 Figure 42. Analog Input Current vs. Input Voltage (VCM = 2.5 V) Rev. A | Page 18 of 63 100 12468-249 9.60 9.65 9.70 9.75 9.80 9.85 9.90 9.95 10.00 10.05 10.10 CURRENT (µA) 12468-247 –80 0 Design Resources Online Documentation Product Overview Sample & Buy Discussion Data Sheet AD7175-2 NOISE PERFORMANCE AND RESOLUTION Table 6 and Table 7 show the rms noise, peak-to-peak noise, effective resolution and the noise free (peak-to-peak) resolution of the AD7175-2 for various output data rates and filters. The numbers given are for the bipolar input range with an external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. It is important to note that the peak-to-peak resolution is calculated based on the peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. Table 6. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate using Sinc5 + Sinc1 Filter (Default) 1 Output Data Rate (SPS) Input Buffers Disabled 250,000 62,500 10,000 1000 59.92 49.96 16.66 5 Input Buffers Enabled 250,000 62,500 10,000 1000 59.98 49.96 16.66 5 1 RMS Noise (µV rms) Effective Resolution (Bits) Peak-to-Peak Noise (µV p-p) Peak-to-Peak Resolution (Bits) 8.7 5.5 2.5 0.77 0.19 0.18 0.1 0.07 20.1 20.8 21.9 23.6 24 24 24 24 65 43 18.3 5.2 1.1 0.95 0.45 0.34 17.2 17.8 19.1 20.9 23.1 23.3 24 24 9.8 6.4 3 0.92 0.23 0.2 0.13 0.07 20 20.6 21.7 23.4 24 24 24 24 85 55 23 5.7 1.2 1 0.66 0.32 16.8 17.5 18.7 20.7 23.0 23.3 23.9 24 Selected rates only, 1000 samples. Table 7. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate using Sinc3 Filter 1 Output Data Rate (SPS) Input Buffers Disabled 250,000 62,500 10,000 1000 60 50 16.66 5 Input Buffers Enabled 250,000 62,500 10,000 1000 60 50 16.66 5 1 RMS Noise (µV rms) Effective Resolution (Bits) Peak-to-Peak Noise (µV p-p) Peak-to-Peak Resolution (Bits) 210 5.2 1.8 0.56 0.13 0.13 0.07 0.05 15.5 20.9 22.4 24 24 24 24 24 1600 40 14 3.9 0.8 0.7 0.37 0.21 12.6 17.9 19.4 21.3 23.6 23.8 24 24 210 5.8 2.1 0.71 0.17 0.15 0.12 0.08 15.5 20.7 22.2 23.7 24 24 24 24 1600 48 16 4.5 1.1 0.83 0.6 0.35 12.6 17.7 19.3 21.1 23.1 23.5 24 24 Selected rates only, 1000 samples. Rev. A | Page 19 of 63 Design Resources Online Documentation Product Overview Sample & Buy Discussion AD7175-2 Data Sheet GETTING STARTED The AD7175-2 includes a precision 2.5 V low drift (±2 ppm/°C) band gap internal reference. This reference can used for the ADC conversions, reducing the external component count. Alternatively, the reference can be output to the REFOUT pin to be used as a low noise biasing voltage for external circuitry. An example of this is using the REFOUT signal to set the input common mode for an external amplifier. The AD7175-2 offers the user a fast settling, high resolution, multiplexed ADC with high levels of configurability. • • • Two fully differential or four single-ended analog inputs. Crosspoint multiplexer selects any analog input combination as the input signals to be converted, routing them to the modulator positive or negative input. True rail-to-rail buffered analog and reference inputs. Fully differential input or single-ended input relative to any analog input. Per channel configurability—up to four different setups can be defined. A separate setup can be mapped to each of the channels. Each setup allows the user to configure whether the buffers are enabled or disabled, gain and offset correction, filter type, output data rate, and reference source selection (internal/external). The AD7175-2 includes two separate linear regulator blocks for both the analog and digital circuitry. The analog LDO regulates the AVDD2 supply to 1.8 V, supplying the ADC core. The user can tie the AVDD1 and AVDD2 supplies together for easiest connection. If there is already a clean analog supply rail in the system in the range of 2 V (minimum) to 5.5 V (maximum), the user can also choose to connect this to the AVDD2 input, allowing lower power dissipation. GENERAL-PURPOSE I/O 0 AND GENERAL-PURPOSE I/O 1 OUTPUT HIGH = AVDDx GPIO1 OUTPUT LOW = AVSS GPIO0 16MHz 19 20 GPIO0 GPIO1 CX2 CX1 OPTIONAL EXTERNAL CRYSTAL CIRCUITRY CAPACITORS XTAL1 9 21 AIN0 XTAL2/CLKI0 10 DOUT/RDY 11 DOUT/RDY 22 AIN1 DIN DIN 12 SCLK SCLK 13 23 AIN2 CS CS 14 SYNC/ERROR 15 24 AIN3 SYNC/ERROR AD7175-2 1 CLKIN OPTIONAL EXTERNAL CLOCK INPUT IOVDD IOVDD 16 AIN4 0.1µF DGND 17 VIN 1 2 4.7µF VIN 3 REGCAPD 18 NC 7 0.1µF 1µF 0.1µF ADR445BRZ 4 GND 5 AVDD1 7 VOUT 6 8 AVDD1 3 0.1µF 4.7µF 0.1µF REF+ AVDD2 0.1µF AVDD2 8 2.5V REFERENCE OUTPUT 2 REF– 4 REFOUT 0.1µF REGCAPA 5 0.1µF 0.1µF AVSS 1µF 6 0.1µF Figure 44. Typical Connection Diagram Rev. A | Page 20 of 63 12468-051 • • Design Resources Online Documentation Discussion Sample & Buy Data Sheet AD7175-2 The linear regulator for the digital IOVDD supply performs a similar function, regulating the input voltage applied at the IOVDD pin to 1.8 V for the internal digital filtering. The serial interface signals always operate from the IOVDD supply seen at the pin. This means that if 3.3 V is applied to the IOVDD pin, the interface logic inputs and outputs operate at this level. • • • • Fast scanning of analog input channels using the internal multiplexer Fast scanning of analog input channels using an external multiplexer with automatic control from the GPIOs. High resolution at lower speeds in either channel scanning or ADC per channel applications Single ADC per channel: the fast low latency output allows further application specific filtering in an external microcontroller, DSP, or FPGA POWER SUPPLIES The AD7175-2 has three independent power supply pins: AVDD1, AVDD2, and IOVDD. AVDD1 powers the crosspoint multiplexer and integrated analog and reference input buffers. AVDD1 is referenced to AVSS, and AVDD1 − AVSS = 5 V only. This can be a single 5 V supply or a ±2.5 V split supply. The split supply operation allows true bipolar inputs. When using split supplies, consider the absolute maximum ratings (see the Absolute Maximum Ratings section). AVDD2 powers the internal 1.8 V analog LDO regulator. This regulator powers the ADC core. AVDD2 is referenced to AVSS, and AVDD2 − AVSS can range from 5.5 V (maximum) to 2 V (minimum). IOVDD powers the internal 1.8 V digital LDO regulator. This regulator powers the digital logic of the ADC. IOVDD sets the voltage levels for the SPI interface of the ADC. IOVDD is referenced to DGND, and IOVDD − DGND can vary from 5.5 V (maximum) to 2 V (minimum). 12468-052 SAMPLE EDGE Figure 45. SPI Mode 3 SCLK Edges Accessing the ADC Register Map The communications register controls access to the full register map of the ADC. This register is an 8-bit write only register. On power-up or after a reset, the digital interface defaults to a state where it is expecting a write to the communications register; therefore, all communication begins by writing to the communications register. The data written to the communications register determines which register is being accessed and if the next operation is a read or write. The register address bits (RA[5:0]) determine the specific register to which the read or write operation applies. When the read or write operation to the selected register is complete, the interface returns to its default state, where it expects a write operation to the communications register. Figure 46 and Figure 47 illustrate writing to and reading from a register by first writing the 8-bit command to the communications register, followed by the data for that register. 8-BIT COMMAND 8 BITS, 16 BITS, OR 24 BITS OF DATA CMD DATA CS DIN SCLK 12468-053 The AD7175-2 can be used across a wide variety of applications, providing high resolution and accuracy. A sample of these scenarios is as follows: DRIVE EDGE Figure 46. Writing to a Register (8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits; Data Length on DIN Is Dependent on the Register Selected) 8-BIT COMMAND DIGITAL COMMUNICATION 8 BITS, 16 BITS, 24 BITS, OR 32 BITS OUTPUT CS The AD7175-2 has a 3- or 4-wire SPI interface that is compatible with QSPI™, MICROWIRE®, and DSPs. The interface operates in SPI Mode 3 and can be operated with CS tied low. In SPI Mode 3, the SCLK idles high, the falling edge of SCLK is the drive edge, and the rising edge of SCLK is the sample edge. This means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. DIN DOUT/RDY SCLK CMD DATA 12468-054 Product Overview Figure 47. Reading from a Register (8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits; Data Length on DOUT Is Dependent on the Register Selected) Rev. A | Page 21 of 63 Design Resources Online Documentation Product Overview Discussion Sample & Buy AD7175-2 Data Sheet Figure 48 shows an overview of the suggested flow for changing the ADC configuration, divided into the following three blocks: Reading the ID register is the recommended method for verifying correct communication with the device. The ID register is a read only register and contains the value 0x0CDX for the AD7175-2. The communications register and the ID register details are described in Table 8 and Table 9. • • • AD7175-2 RESET In situations where interface synchronization is lost, a write operation of at least 64 serial clock cycles with DIN high returns the ADC to its default state by resetting the entire device, including the register contents. Alternatively, if CS is being used with the digital interface, returning CS high sets the digital interface to its default state and halts any serial interface operation. Channel Configuration The AD7175-2 has four independent channels and four independent setups. The user can select any of the analog input pairs on any channel, as well as any of the four setups for any channel, giving the user full flexibility in the channel configuration. This also allows per channel configuration when using differential inputs and single-ended inputs because each channel can have its own dedicated setup. CONFIGURATION OVERVIEW After power-on or reset, the AD7175-2 default configuration is as follows: • • • • • Channel configuration (see Box A in Figure 48) Setup configuration (see Box B in Figure 48) ADC mode and interface mode configuration (see Box C in Figure 48) Channel Registers Channel configuration. CH0 is enabled, AIN0 is selected as the positive input, and AIN1 is selected as the negative input. Setup 0 is selected. Setup configuration. The internal reference and the analog input buffers are enabled. The reference input buffers are disabled. Filter configuration. The sinc5 + sinc 1 filter is selected and the maximum output data rate of 250 kSPS is selected. ADC mode. Continuous conversion mode and the internal oscillator are enabled. Interface mode. CRC and data + status output are disabled. The channel registers are used to select which of the five analog input pins (AIN0 to AIN4) are used as either the positive analog input (AIN+) or the negative analog input (AIN−) for that channel. This register also contains a channel enable/disable bit and the setup selection bits, which are used to pick which of the four available setups to use for this channel. When the AD7175-2 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order, from Channel 0 to Channel 3. If a channel is disabled, it is skipped by the sequencer. Details of the channel register for Channel 0 are shown in Table 10. A CHANNEL CONFIGURATION SELECT POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNEL SELECT ONE OF 4 SETUPS FOR ADC CHANNEL B SETUP CONFIGURATION 4 POSSIBLE ADC SETUPS SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE C ADC MODE AND INTERFACE MODE CONFIGURATION SELECT ADC OPERATING MODE, CLOCK SOURCE, ENABLE CRC, DATA + STATUS, AND MORE 12468-044 Note that only a few of the register setting options are shown; this list is just an example. For full register information, see the Register Details section. Figure 48. Suggested ADC Configuration Flow Table 8. Communications Register Reg. 0x00 Name COMMS Bits [7:0] Bit 7 WEN Bit 6 R/W Bit 5 Bits [15:8] [7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0x00 RW W Bit 2 Bit 1 Bit 0 Reset 0x0CDX RW R RA Table 9. ID Register Reg. 0x07 Name ID Bit 4 Bit 3 ID[15:8] ID[7:0] Rev. A | Page 22 of 63 Online Documentation Product Overview Design Resources Discussion Sample & Buy Data Sheet AD7175-2 Table 10. Channel 0 Register Reg. 0x10 Name CH0 Bits [15:8] [7:0] Bit 7 CH_EN0 Bit 6 Bit 5 Bit 4 Reserved SETUP_SEL[2:0] AINPOS0[2:0] Bit 3 Rev. A | Page 23 of 63 Bit 2 Reserved AINNEG0 Bit 1 Bit 0 AINPOS0[4:3] Reset 0x8001 RW RW Product Overview Design Resources Online Documentation Sample & Buy Discussion AD7175-2 Data Sheet ADC Setups Setup Configuration Registers The AD7175-2 has four independent setups. Each setup consists of the following four registers: The setup configuration registers allow the user to select the output coding of the ADC by selecting between bipolar and unipolar. In bipolar mode, the ADC accepts negative differential input voltages, and the output coding is offset binary. In unipolar mode, the ADC accepts only positive differential voltages, and the coding is straight binary. In either case, the input voltage must be within the AVDD1/ AVSS supply voltages. The user can select the reference source using this register. Three options are available: an internal 2.5 V reference, an external reference connected between the REF+ and REF− pins, or AVDD1 − AVSS. The analog input and reference input buffers can also be enabled or disabled using this register. Setup configuration register Filter configuration register Offset register Gain register For example, Setup 0 consists of Setup Configuration Register 0, Filter Configuration Register 0, Gain Register 0, and Offset Register 0. Figure 49 shows the grouping of these registers The setup is selectable from the channel registers (see the Channel Configuration section), which allows each channel to be assigned to one of four separate setups. Table 11 through Table 14 show the four registers that are associated with Setup 0. This structure is repeated for Setup 1 to Setup 3. SETUP CONFIG REGISTERS Filter Configuration Registers The filter configuration register selects which digital filter is used at the output of the ADC modulator. The order of the filter and the output data rate is selected by setting the bits in this register. For more information, see the Digital Filters section. FILTER CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 DATA OUTPUT CODING REFERENCE SOURCE INPUT BUFFERS SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) SINC5 + SINC1 SINC3 SINC3 MAP ENHANCED 50Hz AND 60Hz 12468-045 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL Figure 49. ADC Setup Register Grouping Table 11. Setup Configuration 0 Register Reg. 0x20 Name Bits Bit 7 Bit 6 SETUPCON0 [15:8] Reserved [7:0] BURNOUT_EN0 Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset BI_UNIPOLAR0 REFBUF0+ REFBUF0− AINBUF0+ AINBUF0− 0x1320 REF_SEL0 Reserved RW RW Table 12. Filter Configuration 0 Register Reg. 0x28 Name FILTCON0 Bits Bit 7 [15:8] SINC3_MAP0 [7:0] Reserved Bit 6 Bit 5 Bit 4 Reserved ORDER0 Bit 3 Bit 2 ENHFILTEN0 ODR0 Bit 1 Bit 0 ENHFILT0 Reset 0x0500 RW RW Table 13. Gain Configuration 0 Register Reg. 0x38 Name GAIN0 Bits [23:0] Bit[23:0] GAIN0[23:0] Reset RW 0x5XXXX0 RW Bit[23:0] OFFSET0[23:0] Reset RW 0x800000 RW Table 14. Offset Configuration 0 Register Reg. 0x30 Name OFFSET0 Bits [23:0] Rev. A | Page 24 of 63 Product Overview Design Resources Online Documentation Discussion Sample & Buy Data Sheet AD7175-2 Gain Registers ADC Mode and Interface Mode Configuration The gain register is a 24-bit register that holds the gain calibration coefficient for the ADC. The gain registers are read/write registers. These registers are configured at power-on with factory calibrated coefficients. Therefore, every device has different default coefficients. The default value is automatically overwritten if a system full-scale calibration is initiated by the user or if the gain register is written to by the user. For more information on calibration, see the Operating Modes section. The ADC mode register and the interface mode register configure the core peripherals for use by the AD7175-2 and the mode for the digital interface. ADC Mode Register The ADC mode register is used primarily to set the conversion mode of the ADC to either continuous or single conversion. The user can also select the standby and power-down modes, as well as any of the calibration modes. In addition, this register contains the clock source select bits and the internal reference enable bits. The reference select bits are contained in the setup configuration registers (see the ADC Setups section for more information). Offset Registers The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The offset register is a 24-bit read/write register. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user or if the offset register is written to by the user. Interface Mode Register The interface mode register configures the digital interface operation. This register allows the user to control data-word length, CRC enable, data plus status read, and continuous read mode. The details of both registers are shown in Table 15 and Table 16. For more information, see the Digital Interface section. Table 15. ADC Mode Register Reg. 0x01 Name ADCMODE Bits [15:8] [7:0] Bit 7 REF_EN Reserved Bit 6 HIDE_DELAY Bit 5 SING_CYC Mode Bit 4 Bit 3 Reserved Bit 2 CLOCKSEL Bit 1 Bit 0 Delay Reserved Reset 0x8000 RW RW Reset 0x0000 RW RW Table 16. Interface Mode Register Reg. 0x02 Name IFMODE Bits [15:8] [7:0] Bit 7 CONTREAD Bit 6 Reserved DATA_STAT Bit 5 REG_CHECK Bit 4 ALT_SYNC Reserved Bit 3 Bit 2 Bit 1 IOSTRENGTH Reserved CRC_EN Reserved Rev. A | Page 25 of 63 Bit 0 DOUT_RESET WL16 Design Resources Online Documentation Product Overview Sample & Buy Discussion AD7175-2 Data Sheet Understanding Configuration Flexibility The most straightforward implementation of the AD7175-2 is to use two differential inputs with adjacent analog inputs and run both of them with the same setup, gain correction, and offset correction register. In this case, the user selects the following differential inputs: AIN0/AIN1 and AIN2/AIN3. In Figure 50, the registers shown in black font must be programmed for such a configuration. The registers that are shown in gray font are redundant in this configuration. CHANNEL REGISTERS AIN0 CH0 AIN1 CH1 AIN2 CH2 AIN3 CH3 0x13 An alternative way to implement these two fully differential inputs is by taking advantage of the four available setups. Motivation for doing this includes having a different speed/noise requirement on each of the differential inputs, or there may be a specific offset or gain correction for each channel. Figure 51 shows how each of the differential inputs can use a separate setup, allowing full flexibility in the configuration of each channel. FILTER CONFIG REGISTERS GAIN REGISTERS* 0x10 SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x11 SETUPCON1 0x21 FILTCON1 0x29 0x12 SETUPCON2 0x22 FILTCON2 0x2A SETUPCON3 0x23 FILTCON3 0x2B SELECT ANALOG INPUT PAIRS ENABLE THE CHANNEL SELECT SETUP 0 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL DATA OUTPUT CODING REFERENCE SOURCE INPUT BUFFERS SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE OFFSET REGISTERS 0x38 OFFSET0 0x30 GAIN1 0x39 OFFSET1 0x31 GAIN2 0x3A OFFSET2 0x32 GAIN3 0x3B OFFSET3 0x33 GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) SINC5 + SINC1 SINC3 SINC3 MAP 12468-046 AIN4 SETUP CONFIG REGISTERS Programming the gain and offset registers is optional for any use case, as indicated by the dashed lines between the register blocks. ENHANCED 50Hz AND 60Hz Figure 50. Two Fully Differential Inputs, Both Using a Single Setup (SETUPCON0; FILTCON0; GAIN0; OFFSET0) SETUP CONFIG REGISTERS FILTER CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS AIN0 CH0 0x10 SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 AIN1 CH1 0x11 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 AIN2 CH2 0x12 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 AIN3 CH3 0x13 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 AIN4 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL DATA OUTPUT CODING REFERENCE SOURCE INPUT BUFFERS SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE SINC5 + SINC1 SINC3 SINC3 MAP GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) ENHANCED 50Hz AND 60Hz Figure 51. Two Fully Differential Inputs with a Setup per Channel Rev. A | Page 26 of 63 12468-047 CHANNEL REGISTERS Design Resources Online Documentation Product Overview Discussion Data Sheet AD7175-2 CHANNEL REGISTERS AIN0 CH0 AIN1 CH1 AIN2 CH2 AIN3 CH3 SETUP CONFIG REGISTERS required, and the FILTCON0 and FILTCON1 registers are also programmed as desired. Optional gain and offset correction can be employed on a per setup basis by programming the GAIN0 and GAIN1 registers and the OFFSET0 and OFFSET1 registers. In the example shown in Figure 52, the CH0 to CH2 registers are used. Setting the MSB in each of these registers, the CH_EN0 to CH_EN2 bits enable the three combinations via the crosspoint mux. When the AD7175-2 converts, the sequencer transitions in ascending sequential order from CH0 to CH1 to CH2 before looping back to CH0 to repeat the sequence. FILTER CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS 0x10 SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 0x11 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 0x12 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 0x13 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SELECT ANALOG INPUT PARTS ENABLE THE CHANNEL SELECT SETUP SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL DATA OUTPUT CODING REFERENCE SOURCE INPUT BUFFERS SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) SINC5 + SINC1 SINC3 SINC3 MAP ENHANCED 50Hz AND 60Hz Figure 52. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups Rev. A | Page 27 of 63 12468-048 Figure 52 shows an example of how the channel registers span between the analog input pins and the setup configurations downstream. In this example, one differential input and two singleended inputs are required. The single-ended inputs are the AIN2/AIN4 and AIN3/AIN4 combinations. The differential input pairs is AIN0/AIN1and uses Setup 0. The two single-ended input pairs are set up as diagnostics; therefore, use a separate setup from the differential input but share a setup between them, Setup 1. Given that two setups are selected for use, the SETUPCON0 and SETUPCON1 registers are programmed as AIN4 Sample & Buy Design Resources Online Documentation Product Overview Sample & Buy Discussion AD7175-2 Data Sheet CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT The AD7175-2 has true rail-to-rail, integrated, precision unity gain buffers on both ADC analog inputs. The buffers provide the benefit of giving the user high input impedance with only 30 nA typical input current, allowing high impedance sources to be connected directly to the analog inputs. The buffers fully drive the internal ADC switch capacitor sampling network, simplifying the analog front-end circuit requirements while consuming a very efficient 2.9 mA typical per buffer. Each analog input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the buffer. The 1/f noise profile of the ADC and buffer combined is shown in Figure 53. of the ADC. The simplified analog input circuit is shown in Figure 54. AVDD1 AIN0 AVSS AVDD1 Ø1 +IN AIN1 CS1 AVSS Ø2 AVDD1 Ø2 AIN2 CS2 AVSS 0 –IN AVDD1 Ø1 AIN3 –50 –100 AIN4 –150 12468-056 AMPLITUDE (dB) AVSS AVDD1 AVSS Figure 54. Simplified Analog Input Circuit –250 0.1 1 10 100 1k 10k FREQUENCY (Hz) 12468-259 –200 Figure 53. Shorted Input FFT (Analog Input Buffers Enabled) The analog input buffers do not suffer from linearity degradation when operating at the rails, unlike many discrete amplifiers. When operating at or close to the AVDD1 and AVSS supply rails, there is an increase in input current. This increase is most notable at higher temperatures. Figure 42 and Figure 43 show the input current for various conditions. With the analog input buffers disabled, the average input current to the AD7175-2 changes linearly with the differential input voltage at a rate of 48 µA/V. The CS1 and CS2 capacitors have a magnitude in the order of a number of picofarads each. This capacitance is the combination of both the sampling capacitance and the parasitic capacitance. Fully Differential Inputs Because the AIN0 to AIN4 analog inputs are connected to a crosspoint multiplexer, any combination of signals can be used to create an analog input pair. This (what does?) allows the user to select two fully differential inputs or four single-ended inputs. If two fully differential input paths are connected to the AD7175-2, using AIN0/AIN1 as one differential input pair and AIN2/AIN3 as the second differential input pair is recommended. This is due to the relative locations of these pins to each other. Decouple all analog inputs to AVSS. CROSSPOINT MULTIPLEXER Single-Ended Inputs There are five analog input pins: AIN0, AIN1, AIN2, AIN3, and AIN4. Each of these pins connects to the internal crosspoint multiplexer. The crosspoint multiplexer enables any of these inputs to be configured as an input pair, either single-ended or fully differential. The AD7175-2 can have up to four active channels. When more than one channel is enabled, the channels are automatically sequenced in order from the lowest enabled channel number to the highest enabled channel number. The output of the multiplexer is connected to the input of the integrated true rail-to-rail buffers. These can be bypassed and the multiplexer output can be directly connected to the switched-capacitor input The user can also choose to measure four different single-ended analog inputs. In this case, each of the analog inputs is converted as the difference between the single-ended input to be measured and a set analog input common pin. Because there is a crosspoint multiplexer, the user can set any of the analog inputs as the common pin. An example of such a scenario is to connect the AIN4 pin to AVSS or to the REFOUT voltage (that is, AVSS + 2.5 V) and select this input when configuring the crosspoint multiplexer. When using the AD7175-2 with single-ended inputs, the INL specification is degraded. Rev. A | Page 28 of 63 Design Resources Online Documentation Product Overview Discussion Sample & Buy Data Sheet AD7175-2 AD7175-2 REFERENCE output for stability purposes. The output is then connected to a 4.7 µF capacitor, which acts as a reservoir for any dynamic charge required by the ADC, and followed by a 0.1 µF decoupling capacitor at the REF+ input. This capacitor is placed as close as possible to the REF+ and REF− pins. The REF− pin is connected directly to the AVSS potential. On power-up of the AD7175-2, the internal reference is enabled by default and is output on the REFOUT pin. When an external reference is used instead of the internal reference to supply the AD7175-2, attention must be paid to the output of the REFOUT pin. If the internal reference is not being used elsewhere in the application, ensure that the REFOUT pin is not hardwired to AVSS because this draws a large current on power-up. On power-up, if the internal reference is not being used, write to the ADC mode register, disabling the internal reference. This is controlled by the REF_EN bit (Bit 15) in the ADC mode register, which is shown in Table 18. The AD7175-2 offers the user the option of either supplying an external reference to the REF+ and REF− pins of the device or allowing the use of the internal 2.5 V, low noise, low drift reference. Select the reference source to be used by the analog input by setting the REF_SELx bits (Bits[5:4]) in the setup configuration registers appropriately. The structure of the Setup Configuration 0 register is shown in Table 17. The AD7175-2 defaults on power-up to use the internal 2.5 V reference. External Reference The AD7175-2 has a fully differential reference input applied through the REF+ and REF− pins. Standard low noise, low drift voltage references, such as the ADR445, ADR444, and ADR441, are recommended for use. Apply the external reference to the AD7175-2 reference pins as shown in Figure 55. Decouple the output of any external reference to AVSS. As shown in Figure 55, the ADR445 output is decoupled with a 0.1 µF capacitor at its AD7175-2 5.5V TO 18V ADR4452 0.1µF 0.1µF 5V VREF 1 4.7µF 1 1 3 REF+ 2 REF– 0.1µF 1 1ALL DECOUPLING IS TO AVSS. 2ANY OF THE ADR44x FAMILY OF REFERENCES CAN BE USED. THE ADR444 AND ADR441 BOTH ENABLE REUSE OF THE 5V ANALOG SUPPLY NEEDED FOR AVDD1 TO POWER THE REFERENCE VIN. 12468-159 1 Figure 55. External Reference ADR445 Connected to AD7175-2 Reference Pins Table 17. Setup Configuration 0 Register Reg. 0x20 Name SETUPCON0 Bits [15:8] [7:0] Bit 7 Bit 6 Reserved BURNOUT_EN0 Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BI_UNIPOLAR0 REFBUF0+ REFBUF0− AINBUF0+ AINBUF0− REF_SEL0 Reserved Reset RW 0x1320 RW Table 18. ADC Mode Register Reg. 0x01 Name ADCMODE Bits [15:8] [7:0] Bit 7 REF_EN Reserved Bit 6 HIDE_DELAY Bit 5 SING_CYC Mode Bit 4 Bit 3 Reserved Rev. A | Page 29 of 63 Bit 2 CLOCKSEL Bit 1 Bit 0 Delay Reserved Reset 0x8000 RW RW Product Overview Design Resources Online Documentation Sample & Buy Discussion AD7175-2 Data Sheet Internal Reference Internal Oscillator The AD7175-2 includes its own low noise, low drift voltage reference. The internal reference has a 2.5 V output. The internal reference is output on the REFOUT pin after the REF_EN bit in the ADC mode register is set and is decoupled to AVSS with a 0.1 µF capacitor. The AD7175-2 internal reference is enabled by default on power-up and is selected as the reference source for the ADC. When using the internal reference, the INL performance is degraded as shown in Figure 23. The internal oscillator runs at 16 MHz and can be used as the ADC master clock. It is the default clock source for the AD7175-2 and is specified with an accuracy of ±2.5%. The REFOUT signal is buffered before being output to the pin. The signal can be used externally in the circuit as a common-mode source for external amplifier configurations. BUFFERED REFERENCE INPUT The AD7175-2 has true rail-to-rail, integrated, precision unity gain buffers on both ADC reference inputs. The buffers provide the benefit of giving the user high input impedance and allow high impedance external sources to be directly connected to the reference inputs. The integrated reference buffers can fully drive the internal reference switch capacitor sampling network, simplifying the reference circuit requirements while consuming a very efficient 2.9 mA typical per buffer. Each reference input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the buffer. When using an external reference, such as the ADR445, ADR444, and ADR441, these buffers are not required because these references, with proper decoupling, can drive the reference inputs directly. CLOCK SOURCE The AD7175-2 uses a nominal master clock of 16 MHz. The AD7175-2 can source its sampling clock from one of three sources: External Crystal If higher precision, lower jitter clock sources are required, the AD7175-2 can use an external crystal to generate the master clock. The crystal is connected to the XTAL1 and XTAL2/ CLKIO pins. A recommended crystal for use is the FA-20H—a 16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom—which is available in a surface-mount package. As shown in Figure 56, insert two capacitors from the traces connecting the crystal to the XTAL1 and XTAL2/CLKIO pins. These capacitors allow for circuit tuning. Connect these capacitors to the DGND pin. The value for these capacitors depends on the length and capacitance of the trace connections between the crystal and the XTAL1 and XTAL2/CLKIO pins. Therefore, the values of these capacitors differ depending on the printed circuit board (PCB) layout and the crystal employed. AD7175-2 Cx1 Internal oscillator External crystal External clock source * XTAL1 9 XTAL2/CLKIO 10 Cx2 All output data rates listed in the data sheet relate to a master clock rate of 16 MHz. Using a lower clock frequency from, for instance, an external source scales any listed data rate proportionally. To achieve the specified data rates, particularly rates for rejection of 50 Hz and 60 Hz, use a 16 MHz clock. The source of the master clock is selected by setting the CLOCKSEL bits (Bits[3:2]) in the ADC mode register as shown in Table 18. The default operation on power-up and reset of the AD7175-2 is to operate with the internal oscillator. It is possible to fine tune the output data rate and filter notch at low output data rates using the SINC3_MAPx bit. See the Sinc3 Filter section for more information. * *DECOUPLE TO DGND. 12468-160 • • • There is an option to allow the internal clock oscillator to be output on the XTAL2/CLKIO pin. The clock output is driven to the IOVDD logic level. Use of this option can affect the dc performance of the AD7175-2 due to the disturbance introduced by the output driver. The extent to which the performance is affected depends on the IOVDD voltage supply. Higher IOVDD voltages create a wider logic output swing from the driver and affect performance to a greater extent. This effect is further exaggerated if the IOSTRENGTH bit is set at higher IOVDD levels (see Table 28 for more information). Figure 56. External Crystal Connections The external crystal circuitry can be sensitive to the SCLK edges, depending on SCLK frequency, IOVDD voltage, crystal circuitry layout, and the crystal used. During crystal startup, any disturbances caused by the SLCK edges may cause double edges on the crystal input, resulting in invalid conversions until the crystal voltage has reached a high enough level such that any interference from the SCLK edges is insufficient to cause double clocking. This double clocking can be avoided by ensuring that the crystal circuitry has reached a sufficient voltage level after startup before applying any SCLK. Rev. A | Page 30 of 63 Product Overview Design Resources Online Documentation Data Sheet Discussion Sample & Buy AD7175-2 Due to the nature of the crystal circuitry, it is therefore recommended that empirical testing of the circuit b performed under the required conditions, with the final PCB layout and crystal, to ensure correct operation. External Clock The AD7175-2 can also use an externally supplied clock. In systems where this is desirable, the external clock is routed to the XTAL2/CLKIO pin. In this configuration, the XTAL2/CLKIO pin accepts the externally sourced clock and routes it to the modulator. The logic level of this clock input is defined by the voltage applied to the IOVDD pin. Rev. A | Page 31 of 63 Product Overview Design Resources Online Documentation Sample & Buy Discussion AD7175-2 Data Sheet DIGITAL FILTERS The AD7175-2 has three flexible filter options to allow optimization of noise, settling time, and rejection: The sinc3 filter achieves the best single-channel noise performance at lower rates and is, therefore, most suitable for single-channel applications. The sinc3 filter always has a settling time equal to Sinc5 + sinc1 filter Sinc3 filter Enhanced 50 Hz and 60 Hz rejection filters SINC1 Figure 59 shows the frequency domain filter response for the sinc3 filter. The sinc3 filter has good roll-off over frequency and has wide notches for good notch frequency rejection. 50Hz AND 60Hz POSTFILTER 0 12468-058 SINC5 tSETTLE = 3/Output Data Rate SINC3 –10 –20 Figure 57. Digital Filter Block Diagram The filter and output data rate are configured by setting the appropriate bits in the filter configuration register for the selected setup. Each channel can use a different setup and therefore, a different filter and output data rate. See the Register Details section for more information. FILTER GAIN (dB) –30 The sinc5 + sinc1 filter is targeted at multiplexed applications and achieves single cycle settling at output data rates of 10 kSPS and lower. The sinc5 block output is fixed at the maximum rate of 250 kSPS, and the sinc1 block output data rate can be varied to control the final ADC output data rate. Figure 58 shows the frequency domain response of the sinc5 + sinc1 filter at a 50 SPS output data rate. The sinc5 + sinc1 filter has a slow roll-off over frequency and narrow notches. 0 –20 FILTER GAIN (dB) –60 –70 –80 –90 SINC5 + SINC1 FILTER –40 –100 –110 –120 0 50 0 50 100 150 FREQUENCY (Hz) 12468-059 –100 Figure 58. Sinc5 + Sinc1 Filter Response at 50 SPS ODR The output data rates with the accompanying settling time and rms noise for the sinc5 + sinc1 filter are shown in Table 19 and Table 20. 150 Figure 59. Sinc3 Filter Response The output data rates with the accompanying settling time and rms noise for the sinc3 filter are shown in Table 21 and Table 22. It is possible to finely tune the output data rate for the sinc3 filter by setting the SINC3_MAPx bit in the filter configuration registers. If this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter. All other options are eliminated. The data rate when on a single channel can be calculated using the following equation: Output Data Rate –80 100 FREQUENCY (Hz) –60 –120 –40 –50 12468-060 SINC3 FILTER f MOD 32 FILTCONx[14:0] where: fMOD is the modulator rate (MCLK/2) and is 8 MHz for a 16 MHz MCLK. FILTCONx[14:0] are the contents on the filter configuration registers excluding the MSB. For example, an output data rate of 50 SPS can be achieved with SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a value of 5000. Rev. A | Page 32 of 63 Design Resources Online Documentation Product Overview Sample & Buy Discussion Data Sheet AD7175-2 The AD7175-2 can be configured by setting the SING_CYC bit in the ADC mode register so that only fully settled data is output, thus effectively putting the ADC into a single cycle settling mode. This mode achieves single cycle settling by reducing the output data rate to be equal to the settling time of the ADC for the selected output data rate. This bit has no effect with the sinc5 + sinc1 filter at output data rates of 10 kSPS and lower. Figure 61 shows the same step on the analog input but with single cycle settling enabled. The analog input requires at least a single cycle for the output to be fully settled. The output data rate, as indicated by the RDY signal, is now reduced to equal the settling time of the filter at the selected output data rate. ANALOG INPUT FULLY SETTLED ADC OUTPUT Figure 60 shows a step on the analog input with this mode disabled and the sinc3 filter selected. The analog input requires at least three cycles after the step change for the output to reach the final settled value. 12468-062 SINGLE CYCLE SETTLING tSETTLE Figure 61. Step Input with Single Cycle Settling ANALOG INPUT FULLY SETTLED 12468-061 ADC OUTPUT 1/ODR Figure 60. Step Input Without Single Cycle Settling Table 19. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Disabled Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 1 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 397.5 200 100 59.92 49.96 20 16.66 10 5 1 2 Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 50,000 41,667 31,250 27,778 20,833 17,857 12,500 10,000 5000 2500 1000 500.0 397.5 200.0 100 59.92 49.96 20.00 16.66 10.00 5.00 Settling Time1 20 µs 24 µs 32 µs 36 µs 48 µs 56 µs 80 µs 100 µs 200 µs 400 µs 1.0 ms 2.0 ms 2.516 ms 5.0 ms 10 ms 16.67 ms 20.016 ms 50.0 ms 60.02 ms 100 ms 200 ms Notch Frequency (Hz) 250,000 125,000 62,500 50,000 31,250 25,000 15,625 11,905 5435 2604 1016 504 400.00 200.64 100.16 59.98 50.00 20.01 16.66 10.00 5.00 Noise (µV rms) 8.7 7.2 5.5 5 4 3.6 2.9 2.5 1.7 1.2 0.77 0.57 0.5 0.36 0.25 0.19 0.18 0.11 0.1 0.08 0.07 Effective Resolution with 5 V Reference (Bits) 20.1 20.4 20.8 20.9 21.3 21.4 21.7 21.9 22.5 23.0 23.6 24 24 24 24 24 24 24 24 24 24 Noise (µV p-p) 2 65 60 43 41 32 29 22 18.3 12 8.2 5.2 3.2 3 2 1.3 1.1 0.95 0.6 0.45 0.4 0.34 Peak-to-Peak Resolution with 5 V Reference (Bits) 17.2 17.3 17.8 17.9 18.3 18.4 18.8 19.1 19.7 20.2 20.9 21.6 21.7 22.3 22.9 23.1 23.3 24 24 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. 1000 samples. Rev. A | Page 33 of 63 Product Overview Online Documentation Design Resources Discussion Sample & Buy AD7175-2 Data Sheet Table 20. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Enabled Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 1 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 397.5 200 100 59.92 49.96 20 16.66 10 5 1 2 Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 50,000 41,667 31,250 27,778 20,833 17,857 12,500 10,000 5000 2500 1000 500.0 397.5 200.0 100 59.92 49.96 20.00 16.66 10.00 5.00 Settling Time1 20 µs 24 µs 32 µs 36 µs 48 µs 56 µs 80 µs 100 µs 200 µs 400 µs 1.0 ms 2.0 ms 2.516 ms 5.0 ms 10 ms 16.67 ms 20.016 ms 50.0 ms 60.02 ms 100 ms 200 ms Notch Frequency (Hz) 250,000 125,000 62,500 50,000 31,250 25,000 15,625 11,905 5435 2604 1016 504 400.00 200.64 100.16 59.98 50.00 20.01 16.66 10.00 5.00 Noise (µV rms) 9.8 8.4 6.4 5.9 4.8 4.3 3.4 3 2.1 1.5 0.92 0.68 0.6 0.43 0.32 0.23 0.2 0.14 0.13 0.1 0.07 Effective Resolution with 5 V Reference (Bits) 20 20.2 20.6 20.7 21 21.1 21.5 21.7 22.2 22.7 23.4 23.8 24 24 24 24 24 24 24 24 24 Noise (µV p-p) 2 85 66 55 49 39 33 26 23 16 10 5.7 3.9 3.7 2.2 1.7 1.2 1 0.75 0.66 0.47 0.32 Peak-to-Peak Resolution with 5 V Reference (Bits) 16.8 17.2 17.5 17.6 18.0 18.2 18.6 18.7 19.3 19.9 20.7 21.3 21.4 22.1 22.5 23 23.3 23.7 23.9 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. 1000 samples. Rev. A | Page 34 of 63 Product Overview Online Documentation Design Resources Sample & Buy Discussion Data Sheet AD7175-2 Table 21. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Disabled Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 1 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 400 200 100 60 50 20 16.67 10 5 1 2 Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 83,333 41,667 20,833 16,667 10,417 8333 5208 3333 1667 833 333.3 166.7 133.3 66.7 33.33 19.99 16.67 6.67 5.56 3.33 1.67 Settling Time1 12 µs 24 µs 48 µs 60 µs 96 µs 120 µs 192 µs 300 µs 6 µs 1.2 ms 3 ms 6 ms 7.5 ms 15 ms 30 ms 50.02 ms 60 ms 150 ms 180 ms 300 ms 600 ms Notch Frequency (Hz) 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 400 200 100 59.98 50 20 16.67 10 5 Noise (µV rms) 210 28 5.2 4.2 3.2 2.9 2.2 1.8 1.3 0.91 0.56 0.44 0.4 0.25 0.2 0.13 0.13 0.08 0.07 0.06 0.05 Effective Resolution with 5 V Reference (Bits) 15.5 18.4 20.9 21.2 21.6 21.7 22.1 22.4 22.9 23.4 24 24 24 24 24 24 24 24 24 24 24 Noise (µV p-p) 2 1600 200 40 34 26 23 17 14 9.5 6 3.9 2.5 2.3 1.4 1 0.8 0.7 0.42 0.37 0.28 0.21 Peak-to-Peak Resolution with 5 V Reference (Bits) 12.6 15.6 17.9 18.2 18.6 18.7 19.2 19.4 20 20.7 21.3 21.9 22.1 22.8 23.3 23.6 23.8 24 24 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. 1000 samples. Rev. A | Page 35 of 63 Product Overview Online Documentation Design Resources Sample & Buy Discussion AD7175-2 Data Sheet Table 22. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Enabled Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 1 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 400 200 100 60 50 20 16.67 10 5 1 2 Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 83,333 41,667 20,833 16,667 10,417 8333 5208 3333 1667 833 333.3 166.7 133.3 66.7 33.33 19.99 16.67 6.67 5.56 3.33 1.67 Settling Time1 12 µs 24 µs 48 µs 60 µs 96 µs 120 µs 192 µs 300 µs 6 µs 1.2 ms 3 ms 6 ms 7.5 ms 15 ms 30 ms 50.02ms 60 ms 150 ms 180 ms 300 ms 600 ms Notch Frequency (Hz) 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 400 200 100 59.98 50 20 16.67 10 5 Noise (µV rms) 210 28 5.8 4.9 3.8 3.4 2.6 2.1 1.5 1.1 0.71 0.52 0.41 0.32 0.2 0.17 0.15 0.13 0.12 0.1 0.08 Effective Resolution with 5 V Reference (Bits) 15.5 18.4 20.7 21 21.3 21.5 21.9 22.2 22.7 23.1 23.7 24 24 24 24 24 24 24 24 24 24 Noise (µV p-p) 2 1600 210 48 41 30 26 18 16 11 7 4.5 3 2.7 1.8 1.2 1.1 0.83 0.61 0.6 0.55 0.35 Peak-to-Peak Resolution with 5 V Reference (Bits) 12.6 15.5 17.7 17.9 18.3 18.6 19.1 19.3 19.8 20.4 21.1 21.7 21.8 22.4 23 23.1 23.5 24 24 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. 1000 samples. Rev. A | Page 36 of 63 Design Resources Online Documentation Product Overview Sample & Buy Discussion Data Sheet AD7175-2 ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS The enhanced filters are designed to provide rejection of 50 Hz and 60 Hz simultaneously and to allow the user to trade off settling time and rejection. These filters can operate up to 27.27 SPS or can reject up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference. These filters are realized by postfiltering the output of the sinc5 + sinc1 filter. For this reason, the sinc5 + sinc1 filter must be selected when using the enhanced filters to achieve the specified settling time and noise performance. Table 23 shows the output data rates with the accompanying settling time, rejection, and rms noise. Figure 62 to Figure 69 show the frequency domain plots of the responses from the enhanced filters. Table 23. Enhanced Filters Output Data Rate, Noise, Settling Time, and Rejection Using the Enhanced Filters Output Data Rate (SPS) Input Buffers Disabled 27.27 25 20 16.667 Input Buffers Enabled 27.27 25 20 16.667 1 Settling Time (ms) Simultaneous Rejection of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz(dB) 1 Noise (µV rms) Peak-to-Peak Resolution (Bits) Comments 36.67 40.0 50.0 60.0 47 62 85 90 0.22 0.2 0.2 0.17 22.7 22.9 22.9 23 See Figure 62 and Figure 65 See Figure 63 and Figure 66 See Figure 64 and Figure 67 See Figure 68 and Figure 69 36.67 40.0 50.0 60.0 47 62 85 90 0.22 0.22 0.21 0.21 22.7 22.7 22.8 22.8 See Figure 62 and Figure 65 See Figure 63 and Figure 66 See Figure 64 and Figure 67 See Figure 68 and Figure 69 Master clock = 16.00 MHz. Rev. A | Page 37 of 63 Design Resources Online Documentation Product Overview Sample & Buy Discussion Data Sheet 0 0 –10 –10 –20 –30 –30 –40 –50 –60 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 200 300 400 500 600 FREQUENCY (Hz) –100 40 –10 –20 –20 –30 –30 FILTER GAIN (dB) –10 –40 –50 –60 –80 –90 –90 –100 –100 40 500 600 FREQUENCY (Hz) –10 –20 –20 –30 –30 FILTER GAIN (dB) –10 –40 –50 –60 –80 –90 –90 –100 500 FREQUENCY (Hz) 65 70 –60 –80 400 60 –50 –70 300 55 –40 –70 600 12468-067 FILTER GAIN (dB) 0 200 50 Figure 66. 25 SPS ODR, 40 ms Settling Time Figure 63. 25 SPS ODR, 40 ms Settling Time 100 45 FREQUENCY (Hz) 0 0 70 –60 –80 400 65 –50 –70 300 60 –40 –70 12468-065 FILTER GAIN (dB) 0 200 55 Figure 65. 27.27 SPS ODR, 36.67 ms Settling Time Figure 62. 27.27 SPS ODR, 36.67 ms Settling Time 100 50 FREQUENCY (Hz) 0 0 45 12468-066 100 –100 40 45 50 55 60 65 FREQUENCY (Hz) Figure 67. 20 SPS ODR, 50 ms Settling Time Figure 64. 20 SPS ODR, 50 ms Settling Time Rev. A | Page 38 of 63 70 12468-068 0 12468-064 FILTER GAIN (dB) –20 12468-063 FILTER GAIN (dB) AD7175-2 Design Resources Online Documentation Product Overview Sample & Buy Discussion AD7175-2 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 0 100 200 300 400 500 FREQUENCY (Hz) 600 Figure 68. 16.667 SPS ODR, 60 ms Settling Time –100 40 45 50 55 60 65 FREQUENCY (Hz) Figure 69. 16.667 SPS ODR, 60 ms Settling Time Rev. A | Page 39 of 63 70 12468-070 FILTER GAIN (dB) 0 12468-069 FILTER GAIN (dB) Data Sheet Product Overview Design Resources Online Documentation Sample & Buy Discussion AD7175-2 Data Sheet OPERATING MODES The AD7175-2 has a number of operating modes that can be set from the ADC mode register and interface mode register (see Table 27 and Table 28). These modes are as follows and are described in the following paragraphs: • • • • • • Continuous conversion mode Continuous read mode Single conversion mode Standby mode Power-down mode Calibration modes (three) CONTINUOUS CONVERSION MODE Continuous conversion is the default power-up mode. The AD7175-2 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the RDY output also goes low when a conversion is complete. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, the DOUT/RDY pin goes high. The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion; otherwise, the new conversion word is lost. When several channels are enabled, the ADC automatically sequences through the enabled channels, performing one conversion on each channel. When all channels have been converted, the sequence starts again with the first channel. The channels are converted in order from lowest enabled channel to highest enabled channel. The data register is updated as soon as each conversion is available. The RDY output pulses low each time a conversion is available. The user can then read the conversion while the ADC converts the next enabled channel. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion data, are output each time the data register is read. The status register indicates the channel to which the conversion corresponds. CS 0x44 0x44 DIN DATA DATA 12468-071 DOUT/RDY SCLK Figure 70. Continuous Conversion Mode Rev. A | Page 40 of 63 Design Resources Online Documentation Product Overview Discussion Data Sheet Sample & Buy AD7175-2 CONTINUOUS READ MODE To enable continuous read mode, set the CONTREAD bit in the interface mode register. When this bit is set, the only serial interface operations possible are reads from the data register. To exit continuous read mode, issue a dummy read of the ADC data register command (0x44) while the RDY output is low. Alternatively, apply a software reset, that is, 64 SCLKs with CS = 0 and DIN = 1. This resets the ADC and all register contents. These are the only commands that the interface recognizes after it is placed in continuous read mode. Hold DIN low in continuous read mode until an instruction is to be written to the device. In continuous read mode, it is not required to write to the communications register before reading ADC data; apply only the required number of SCLKs after RDY goes low to indicate the end of a conversion. When the conversion is read, RDY returns high until the next conversion is available. In this mode, the data can be read only once. The user must also ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7175-2 to read the data word, the serial output register is reset shortly before the next conversion is complete, and the new conversion is placed in the output serial register. The ADC must be configured for continuous conversion mode to use continuous read mode. If multiple ADC channels are enabled, each channel is output in turn, with the status bits being appended to the data if DATA_STAT is set in the interface mode register. The status register indicates the channel to which the conversion corresponds. CS 0x02 0x0080 DIN DATA DATA DATA 12468-072 DOUT/RDY SCLK Figure 71. Continuous Read Mode Rev. A | Page 41 of 63 Product Overview Design Resources Online Documentation Sample & Buy Discussion AD7175-2 Data Sheet SINGLE CONVERSION MODE In single conversion mode, the AD7175-2 performs a single conversion and is placed in standby mode after the conversion is complete. The RDY output goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/RDY pin goes high. The data register can be read several times, if required, even when DOUT/RDY pin has gone high. If several channels are enabled, the ADC automatically sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, the DOUT/RDY pin goes high and remains high until a valid conversion is available and CS is low. As soon as the conversion is available, the RDY output goes low. The ADC then selects the next channel and begins a conversion. The user can read the present conversion while the next conversion is being performed. As soon as the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to standby mode. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion, are output each time the data register is read. The two LSBs of the status register indicate the channel to which the conversion corresponds. CS 0x01 0x8010 0x44 DIN DATA 12468-073 DOUT/RDY SCLK Figure 72. Single Conversion Mode Rev. A | Page 42 of 63 Product Overview Design Resources Online Documentation Discussion Data Sheet AD7175-2 STANDBY AND POWER-DOWN MODES In standby mode, most blocks are powered down. The LDOs remain active so that registers maintain their contents. The internal reference remains active if enabled, and the crystal oscillator remains active if selected. To power down the reference in standby mode, set the REF_EN bit in the ADC mode regsiter to 0. To power down the clock in standby mode, set the CLOCKSEL bits in the ADC mode register to 00 (internal oscillator). In power-down mode, all blocks are powered down, including the LDOs. All registers lose their contents, and the GPIO outputs are placed in three-state. To prevent accidental entry to powerdown mode, the ADC must first be placed in standby mode. Exiting power-down mode requires 64 SCLKs with CS = 0 and DIN = 1, that is, a serial interface reset. A delay of 500 µs is recommended before issuing a subsequent serial interface command to allow the LDO to power up. Figure 19 shows the internal reference settling time after returning from standby mode (setting REF_EN = 0 and then 1) and returning from power down. CALIBRATION The AD7175-2 allows a two-point calibration to be performed to eliminate any offset and gain errors. Three calibration modes are used to eliminate these offset and gain errors on a per setup basis: • • • Sample & Buy Internal zero-scale calibration mode System zero-scale calibration mode System full-scale calibration mode There is no internal full-scale calibration mode bcause this is calibrated in the factory at the time of production. Only one channel can be active during calibration. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The default value of the offset register is 0x800000, and the nominal value of the gain register is 0x555555. The calibration range of the ADC gain is from 0.4 × VREF to 1.05 × VREF. The following equations show the calculations that are used. In unipolar mode, the ideal relationship—that is, not taking into account the ADC gain error and offset error—is as follows: Data = 0.75 × VIN Gain ×2 × 2 23 − (Offset − 0 x 800000 ) × 0 x 400000 VREF In bipolar mode, the ideal relationship—that is, not taking into account the ADC gain error and offset error—is as follows: Data = 0.75 × VIN Gain + × 223 − (Offset − 0 x 800000) × V 400000 0 x REF 0 x 800000 To start a calibration, write the relevant value to the mode bits in the ADC mode register. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration initiates. When the calibration is complete, the contents of the corresponding offset or gain register are updated, the RDY bit in the status register is reset and the RDY output pin returns low (if CS is low), and the AD7175-2 reverts to standby mode. During an internal offset calibration, the selected positive analog input pin is disconnected, and both modulator inputs are connected internally to the selected negative analog input pin. For this reason, it is necessary to ensure that the voltage on the selected negative analog input pin does not exceed the allowed limits and is free from excessive noise and interference. System calibrations, however, expect the system zero-scale (offset) and system full-scale (gain) voltages to be applied to the ADC pins before initiating the calibration modes. As a result, errors external to the ADC are removed. From an operational point of view, treat a calibration like another ADC conversion. An offset calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the RDY bit in the status register or the RDY output to determine the end of a calibration via a polling sequence or an interrupt-driven routine. All calibrations require a time equal to the settling time of the selected filter and output data rate to be completed. An internal offset calibration, system zero-scale calibration, and system full-scale calibration can be performed at any output data rate. Using lower output data rates results in better calibration accuracy and is accurate for all output data rates. A new offset calibration is required for a given channel if the reference source for that channel is changed. The offset error is typically ±40 µV and an offset calibration reduces the offset error to the order of the noise. The gain error is factory calibrated at ambient temperature. Following this calibration, the gain error is typically ±35 ppm of FSR. The AD7175-2 provides the user with access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and to write its own calibration coefficients. A read or write of the offset and gain registers can be performed at any time except during an internal or self calibration. Rev. A | Page 43 of 63 Product Overview Design Resources Online Documentation Sample & Buy Discussion AD7175-2 Data Sheet DIGITAL INTERFACE Figure 2 and Figure 3 show timing diagrams for interfacing to the AD7175-2 using CS to decode the device. Figure 2 shows the timing for a read operation from the AD7175-2, and Figure 3 shows the timing for a write operation to the AD7175-2. It is possible to read from the data register several times even though the RDY output returns high after the first read operation. However, care must be taken to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once. The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY pins are used to communicate with the AD7175-2. The end of the conversion can also be monitored using the RDY bit in the status register. The AD7175-2 can be reset by writing 64 SCLKs with CS = 0 and DIN = 1. A reset returns the interface to the state in which it expects a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, allow a period of 500 µs before addressing the serial interface. CHECKSUM PROTECTION The AD7175-2 has a checksum mode that can be used to improve interface robustness. Using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. If an error occurs during a register write, the CRC_ERROR bit is set in the status register. For CRC checksum calculations during a write operation, the following polynomial is always used: x8 + x2 + x + 1 During read operations, the user can select between this polynomial and a simpler XOR function. The XOR function requires less time to process on the host microcontroller than the polynomial-based checksum. The CRC_EN bits in the interface mode register enable and disable the checksum and allow the user to select between the polynomial check and the simple XOR check. The checksum is appended to the end of each read and write transaction. The checksum calculation for the write transaction is calculated using the 8-bit command word and the 8-bit to 24-bit data. For a read transaction, the checksum is calculated using the command word and the 8-bit to 32-bit data output. Figure 73 and Figure 74 show SPI write and read transactions, respectively. 8-BIT COMMAND UP TO 24-BIT INPUT 8-BIT CRC CS DATA CRC CS DIN 12468-074 The DOUT/RDY pin also functions as a data ready signal, with the output going low if CS is low when a new data-word is available in the data register. The RDY output is reset high when a read operation from the data register is complete. The RDY output also goes high before updating the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. Take care to avoid reading from the data register when the RDY output is about to go low. The best method to ensure that no data read occurs is to always monitor the RDY output; start reading the data register as soon as the RDY output goes low; and ensure a sufficient SCLK rate, such that the read is completed before the next conversion result. CS is used to select a device. It can be used to decode the AD7175-2 in systems where several components are connected to the serial bus. However, to ensure that the register write was successful, read back the register and verify the checksum. SCLK Figure 73. SPI Write Transaction with CRC 8-BIT COMMAND UP TO 32-BIT INPUT 8-BIT CRC CS DIN DOUT/ RDY CMD DATA CRC SCLK 12468-075 The programmable functions of the AD7175-2 are controlled via the SPI serial interface. The serial interface of the AD7175-2 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN input is used to transfer data into the on-chip registers, and DOUT output is used to access data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN input or on DOUT output) occur with respect to the SCLK signal. Figure 74. SPI Read Transaction with CRC If checksum protection is enabled when continuous read mode is active, an implied read data command of 0x44 before every data transmission must be accounted for when calculating the checksum value. This implied read data command ensures a nonzero checksum value even if the ADC data equals 0x000000. Rev. A | Page 44 of 63 Design Resources Online Documentation Product Overview Discussion Sample & Buy Data Sheet AD7175-2 CRC CALCULATION Polynomial The checksum, which is eight bits wide, is generated using the polynomial x8 + x2 + x + 1 To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned so that its MSB is adjacent to the leftmost Logic 1 of the data. An XOR (exclusive OR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process repeats until the original data is reduced to a value less than the polynomial. This is the 8-bit checksum. Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) An example of generating the 8-bit checksum using the polynomial based checksum is as follows: Initial value 011001010100001100100001 x +x +x+1 8 2 01100101010000110010000100000000 left shifted eight bits = polynomial 100000111 100100100000110010000100000000 100000111 XOR result polynomial 100011000110010000100000000 100000111 XOR result polynomial 11111110010000100000000 100000111 XOR result polynomial value 1111101110000100000000 100000111 XOR result polynomial value 111100000000100000000 100000111 XOR result polynomial value 11100111000100000000 100000111 XOR result polynomial value 1100100100100000000 100000111 XOR result polynomial value 100101010100000000 100000111 XOR result polynomial value 101101100000000 100000111 1101011000000 100000111 101010110000 100000111 1010001000 100000111 10000110 XOR result polynomial value XOR result polynomial value XOR result polynomial value XOR result polynomial value checksum = 0x86 Rev. A | Page 45 of 63 Online Documentation Product Overview Design Resources Discussion AD7175-2 Sample & Buy Data Sheet XOR Calculation The checksum, which is 8 bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes. Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) Using the previous example, divide into three bytes: 0x65, 0x43, and 0x21 01100101 0x65 01000011 0x43 00100110 XOR result 00100001 0x21 00000111 CRC Rev. A | Page 46 of 63 Product Overview Design Resources Online Documentation Discussion Data Sheet Sample & Buy AD7175-2 INTEGRATED FUNCTIONS The AD7175-2 has integrated functions that improve the usefulness of a number of applications as well as serve diagnostic purposes in safety conscious applications. GENERAL-PURPOSE I/O The AD7175-2 has two general-purpose digital input/output pins: GPIO0 and GPIO1. They are enabled using the IP_EN0/IP_EN1 bits or the OP_EN0/OP_EN1 bits in the GPIOCON register. When the GPIO0 or GPIO1 pin is enabled as an input, the logic level at the pin is contained in the GP_DATA0 or GP_DATA1 bit, respectively. When the GPIO0 or GPIO1 pin is enabled as an output, the GP_ DATA0 or GP_DATA1 bits, respectively, determine the logic level output at the pin. The logic levels for these pins are referenced to AVDD1 and AVSS; therefore, outputs have an amplitude of 5 V. The effect on the noise performance depends on the delay time compared to the conversion time. It is possible to absorb the delay only for output data rates less than 10 kSPS with the exception of the following four rates, which cannot absorb any delay: 397.5 SPS, 59.92 SPS, 49.96 SPS, and 16.66 SPS. 16-BIT/24-BIT CONVERSIONS By default, the AD7175-2 generates 24-bit conversions. However, the width of the conversions can be reduced to 16 bits. Setting the WL16 bit in the interface mode register to 1 rounds all data conversions to 16 bits. Clearing this bit sets the width of the data conversions to 24 bits. DOUT_RESET Both GPIOs and the SYNC/ERROR pin, when set as generalpurpose outputs, have an active pull-up. The serial interface uses a shared DOUT/RDY pin. By default, this pin outputs the RDY signal. During a data read, this pin outputs the data from the register being read. After the read is complete, the pin reverts to outputting the RDY signal after a short fixed period of time (t7). However, this time may be too short for some microcontrollers and can be extended until the CS pin is brought high by setting the DOUT_RESET bit in the interface mode register to 1. This means that CS must be used to frame each read operation and compete the serial interface transaction. EXTERNAL MULTIPLEXER CONTROL SYNCHRONIZATION If an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlled via the AD7175-2 GPIOx pins. With the MUX_IO bit, the GPIOx timing is controlled by the ADC; therefore, the channel change is synchronized with the ADC, eliminating any need for external synchronization. Normal Synchronization The SYNC/ERROR pin can also be used as a general-purpose output. When ERR_EN bits in the GPIOCON register are set to 11, the SYNC/ERROR pin operates as a general-purpose output. In this configuration, the ERR_DAT bit in the GPIOCON register determines the logic level output at the pin. The logic level for the pin is referenced to IOVDD and DGND. DELAY It is possible to insert a programmable delay before the AD7175-2 begins to take samples. This delay allows an external amplifier or multiplexer to settle and can also alleviate the specification requirements for the external amplifier or multiplexer. Eight programmable settings, ranging from 0 µs to 1 ms, can be set using the delay bits in the ADC mode register (Register 0x01, Bits[10:8]). If a delay greater than 0 µs is selected and the HIDE_DELAY bit in the ADC mode register is set to 0, this delay is added to the conversion time, regardless of selected output data rate. When using the sinc5 + sinc1 filter, it is possible to hide this delay such that the output data rate remains the same as the output data rate without the delay enabled. If the HIDE_DELAY bit is set to 1 and the selected delay is less than half of the conversion time, the delay can be absorbed by reducing the number of averages the digital filter performs, which keeps the conversion time the same but can affect the noise performance. When the SYNC_EN bit in the GPIOCON register is set to 1, the SYNC/ERROR pin functions as a synchronization input. The SYNC input lets the user reset the modulator and the digital filter without affecting any of the setup conditions on the device. This feature lets the user start to gather samples of the analog input from a known point, the rising edge of the SYNC input. The SYNC input must be low for at least one master clock cycle to ensure that synchronization occurs. If multiple AD7175-2 devices are operated from a common master clock, they can be synchronized so that their analog inputs are sampled simultaneously. This synchronization is normally done after each AD7175-2 device has performed its own calibration or has calibration coefficients loaded into its calibration registers. A falling edge on the SYNC input resets the digital filter and the analog modulator and places the AD7175-2 into a consistent known state. While the SYNC input is low, the AD7175-2 is maintained in this known state. On the SYNC input rising edge, the modulator and filter are taken out of this reset state, and on the next master clock edge, the device starts to gather input samples again. Rev. A | Page 47 of 63 Product Overview Design Resources Online Documentation Discussion AD7175-2 Sample & Buy Data Sheet The device is taken out of reset on the master clock falling edge following the SYNC input low to high transition. Therefore, when multiple devices are being synchronized, take the SYNC input high on the master clock rising edge to ensure that all devices are released on the master clock falling edge. If the SYNC input is not taken high in sufficient time, a difference of one master clock cycle between the devices is possible; that is, the instant at which conversions are available differs from device to device by a maximum of one master clock cycle. The SYNC input can also be used as a start conversion command for a single channel when in normal synchronization mode. In this mode, the rising edge of SYNC input starts a conversion, and the falling edge of the RDY output indicates when the conversion is complete. The settling time of the filter is required for each data register update. After the conversion is complete, bring the SYNC input low in preparation for the next conversion start signal. Alternate Synchronization In alternate synchronization mode, the SYNC input operates as a start conversion command when several channels of the AD7175-2 are enabled. Setting the ALT_SYNC bit in the interface mode register to 1 enables an alternate synchronization scheme. When the SYNC input is taken low, the ADC completes the conversion on the current channel, selects the next channel in the sequence, and then waits until the SYNC input is taken high to commence the conversion. The RDY output goes low when the conversion is complete on the current channel, and the data register is updated with the corresponding conversion. Therefore, the SYNC input does not interfere with the sampling on the currently selected channel but allows the user to control the instant at which the conversion begins on the next channel in the sequence. Alternate synchronization mode can be used only when several channels are enabled. It is not recommended to use this mode when a single channel is enabled. ERROR FLAGS The status register contains three error bits—ADC_ERROR, CRC_ERROR, and REG_ERROR—that flag errors with the ADC conversion, errors with the CRC check, and errors caused by changes in the registers, respectively. In addition, the ERROR output can indicate that an error has occurred. ADC_ERROR CRC_ERROR If the CRC value that accompanies a write operation does not correspond with the information sent, the CRC_ERROR flag is set. The flag is reset as soon as the status register is explicitly read. REG_ERROR The RE_ERROR flag is used in conjunction with the REG_CHECK bit in the interface mode register. When the REG_CHECK bit is set, the AD7175-2 monitors the values in the on-chip registers. If a bit changes, the REG_ERROR bit is set. Therefore, for writes to the on-chip registers, set REG_CHECK to 0. When the registers have been updated, the REG_CHECK bit can be set to 1. The AD7175-2 calculates a checksum of the on-chip registers. If one of the register values has changed, the REG_ERROR bit is set. If an error is flagged, the REG_CHECK bit must be set to 0 to clear the REG_ERROR bit in the status register. The register check function does not monitor the data register, status register, or interface mode register. ERROR Input/Output When the SYNC_EN bit in the GPIOCON register is set to 0, the SYNC/ERROR pin functions as an error input/output pin or a general-purpose output pin. The ERR_EN bits in the GPIOCON register determine the function of the pin. With ERR_EN is set to 10,the SYNC/ERROR pin functions as an open-drain error output, ERROR. The three error bits in the status register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are OR’ed, inverted, and mapped to the ERROR output. Therefore, the ERROR output indicates that an error has occurred. The status register must be read to identify the error source. When ERR_EN is set to 01, the SYNC/ERROR pin functions as an error input, ERROR. The error output of another component can be connected to the AD7175-2 ERROR input so that the AD7175-2 indicates when an error occurs on either itself or the external component. The value on the ERROR input is inverted and OR’ed with the errors from the ADC conversion, and the result is indicated via the ADC_ERROR bit in the status register. The value of the ERROR input is reflected in the ERR_DAT bit in the status register. The ERROR input/output is disabled when ERR_EN is set to 00. When the ERR_EN bits are set to 11, the SYNC/ERROR pin operates as a general-purpose output. The ADC_ERROR bit in the status register flags any errors that occur during the conversion process. The flag is set when an overrange or underrange result is output from the ADC. The ADC also outputs all 0s or all 1s when an undervoltage or overvoltage occurs. This flag is reset only when the overvoltage or undervoltage is removed. It is not reset by a read of the data register. Rev. A | Page 48 of 63 Product Overview Design Resources Online Documentation Discussion Sample & Buy Data Sheet AD7175-2 DATA_STAT The contents of the status register can be appended to each conversion on the AD7175-2. This function is useful if several channels are enabled. Each time a conversion is output, the contents of the status register are appended. The two LSBs of the status register indicate to which channel the conversion corresponds. In addition, the user can determine if any errors are being flagged by the error bits. IOSTRENGTH The serial interface can operate with a power supply as low as 2 V. However, at this low voltage, the DOUT/RDY pin may not have sufficient drive strength if there is moderate parasitic capacitance on the board or the SCLK frequency is high. The IOSTRENGTH bit in the interface mode register increases the drive strength of the DOUT/RDY pin. circuit needs to re-run a calibration routine to take into account a shift in operating temperature. The temperature sensor is selected using the crosspoint multiplexer and is selected the same as an analog input channel. The temperature sensor requires that the analog input buffers be enabled on both analog inputs. If the buffers are not enabled then selecting the temperature sensor as an input forces the buffers to be enabled during the conversion. To use the temperature sensor, the first step is to calibrate the device in a known temperature (25°C) and take a conversion as a reference point. The temperature sensor has a nominal sensitivity of 477 µV/K; the difference in this ideal slope and the slope measured can be used to calibrate the temperature sensor. The temperature sensor is specified with a ±2°C typical accuracy after calibration at 25°C. The temperature can be calculated as follows: INTERNAL TEMPERATURE SENSOR The AD7175-2 has an integrated temperature sensor. The temperature sensor can be used as a guide for the ambient temperature at which the part is operating. This can be used for diagnostic purposes or as an indicator of when the application Rev. A | Page 49 of 63 Conversion Result Temperature ( °C ) = 477 μV – 273.15 Product Overview Design Resources Online Documentation AD7175-2 Discussion Sample & Buy Data Sheet GROUNDING AND LAYOUT The analog inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are common-mode voltages. The high common-mode rejection of the device removes common-mode noise on these inputs. The analog and digital supplies to the AD7175-2 are independent and connected to separate pins to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency. possible to provide low impedance paths and reduce glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This technique reduces the effects of feed through on the board. A microstrip technique is by far the best but is not always possible with a double-sided board. The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD7175-2 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7175-2 is high and the noise levels from the converter are so low, take care with regard to grounding and layout. Good decoupling is important when using high resolution ADCs. The AD7175-2 has three power supply pins—AVDD1, AVDD2, and IOVDD. The AVDD1 and AVDD2 pins are referenced to AVSS, and the IOVDD pin is referenced to DGND. Decouple AVDD1 and AVDD2 with a 10 µF capacitor in parallel with a 0.1 µF capacitor to AVSS on each pin. Place the 0.1 µF capacitor as close as possible to the device on each supply, ideally right up against the device. Decouple IOVDD with a 10 µF capacitor in parallel with a 0.1 µF capacitor to DGND. Decouple all analog inputs to AVSS. If an external reference is used, decouple the REF+ and REF− pins to AVSS. The PCB that houses the ADC must be designed such that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it results in the best shielding. In any layout, the user must consider the flow of currents in the system, ensuring that the paths for all return currents are as close as possible to the paths the currents took to reach their destinations. Avoid running digital lines under the device because this couples noise onto the die and allow the analog ground plane to run under the AD7175-2 to prevent noise coupling. The power supply lines to the AD7175-2 must use as wide a trace as The AD7175-2 also has two on-board LDO regulators—one that regulates the AVDD2 supply and one that regulates the IOVDD supply. For the REGCAPA pin, it is recommended that 1 µF and 0.1 µF capacitors to AVSS be used. Similarly, for the REGCAPD pin, it is recommended that 1 µF and 0.1 µF capacitors to DGND be used. If using the AD7175-2 for split supply operation, a separate plane must be used for AVSS. Rev. A | Page 50 of 63 Design Resources Online Documentation Product Overview Sample & Buy Discussion Data Sheet AD7175-2 REGISTER SUMMARY Table 24. Register Summary Reg. Name Bits Bit 7 Bit 6 0x00 COMMS [7:0] WEN R/W 0x00 STATUS [7:0] RDY 0x01 ADCMODE [15:8] [7:0] [15:8] [7:0] REF_EN RESERVED 0x02 IFMODE 0x03 REGCHECK 0x04 DATA 0x06 GPIOCON 0x07 ID 0x10 CH0 0x11 CH1 0x12 CH2 0x13 CH3 0x20 SETUPCON0 0x21 SETUPCON1 0x22 SETUPCON2 0x23 SETUPCON3 0x28 0x29 0x2A 0x2B 0x30 0x31 0x32 0x33 0x38 0x39 0x3A 0x3B FILTCON0 FILTCON1 FILTCON2 FILTCON3 OFFSET0 OFFSET1 OFFSET2 OFFSET3 GAIN0 GAIN1 GAIN2 GAIN3 [23:16] [15:8] [7:0] [23:16] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] CONTREAD Bit 5 Bit 4 ADC_ERROR CRC_ERROR REG_ERROR HIDE_DELAY SING_CYC MODE RESERVED DATA_STAT RESERVED RESERVED CH_EN0 RESERVED AINPOS0[2:0] CH_EN1 RESERVED AINPOS1[2:0] CH_EN2 RESERVED AINPOS2[2:0] CH_EN3 RESERVED AINPOS3[2:0] RESERVED BURNOUT_EN0 RESERVED RESERVED BURNOUT_EN1 RESERVED RESERVED BURNOUT_EN2 RESERVED BURNOUT_EN3 SINC3_MAP0 RESERVED SINC3_MAP1 RESERVED SINC3_MAP2 RESERVED SINC3_MAP3 RESERVED RESERVED RESERVED Bit 2 RA RESERVED RESERVED ALT_SYNC RESERVED REG_CHECK IP_EN1 Bit 3 CLOCKSEL IOSTRENGTH CRC_EN Bit 1 Bit 0 CHANNEL RESERVED REFBUF3+ 0x80 R RW RW 0x000000 R 0x000000 R 0x0800 RW 0x0CDX R 0x8001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x1320 RW 0x1320 RW 0x1320 RW 0x1320 RW ENHFILT0 0x0500 RW ENHFILT1 0x0500 RW ENHFILT2 0x0500 RW ENHFILT3 0x0500 RW 0x800000 0x800000 0x800000 0x800000 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 RW RW RW RW RW RW RW RW REFBUF3− AINBUF3+ RESERVED ENHFILTEN0 ORDER0 RW W DELAY 0x8000 RESERVED RESERVED DOUT_RESET 0x0000 RESERVED WL16 REGISTER_CHECK[23:16] REGISTER_CHECK[15:8] REGISTER_CHECK[7:0] DATA[23:16] DATA[15:8] DATA[7:0] MUX_IO SYNC_EN ERR_EN ERR_DAT IP_EN0 OP_EN1 OP_EN0 GP_DATA1 GP_DATA0 ID[15:8] ID[7:0] SETUP_SEL0 RESERVED AINPOS0[4:3] AINNEG0 SETUP_SEL1 RESERVED AINPOS1[4:3] AINNEG1 SETUP_SEL2 RESERVED AINPOS2[4:3] AINNEG2 SETUP_SEL3 RESERVED AINPOS3[4:3] AINNEG3 BI_UNIPOLAR0 REFBUF0+ REFBUF0AINBUF0+ AINBUF0− REF_SEL0 RESERVED BI_UNIPOLAR1 REFBUF1+ REFBUF1− AINBUF1+ AINBUF1− REF_SEL1 RESERVED BI_UNIPOLAR2 REFBUF2+ REFBUF2− AINBUF2+ AINBUF2− REF_SEL2 RESERVED BI_UNIPOLAR3 REF_SEL3 Reset 0x00 AINBUF3− ODR0 RESERVED ENHFILTEN1 ORDER1 ODR1 RESERVED ENHFILTEN2 ORDER2 ODR2 RESERVED ENHFILTEN3 ORDER3 ODR3 OFFSET0[23:0] OFFSET1[23:0] OFFSET2[23:0] OFFSET3[23:0] GAIN0[23:0] GAIN1[23:0] GAIN2[23:0] GAIN3[23:0] Rev. A | Page 51 of 63 Online Documentation Product Overview Design Resources Discussion AD7175-2 Sample & Buy Data Sheet REGISTER DETAILS COMMUNICATIONS REGISTER Address: 0x00, Reset: 0x00, Name: COMMS All access to the on-chip registers must start with a write to the communications register. This write determines what register is next accessed and whether that operation is a write or a read. Table 25. Bit Descriptions for COMMS Bits 7 Bit Name WEN 6 R/W Settings 0 1 [5:0] RA 000000 000001 000010 000011 000100 000110 000111 010000 010001 010010 010011 100000 100001 100010 100011 101000 101001 101010 101011 110000 110001 110010 110011 111000 111001 111010 111011 Description This bit must be low to begin communications with the ADC. Reset 0x0 Access W This bit determines if the command is a read or write operation. Write command Read command The register address bits determine which register is to be read from or written to as part of the current communication. Status register ADC mode register Interface mode register Register checksum register Data register GPIO configuration register ID register Channel 0 register Channel 1 register Channel 2 register Channel 3 register Setup Configuration 0 register Setup Configuration 1 register Setup Configuration 2 register Setup Configuration 3 register Filter Configuration 0 register Filter Configuration 1 register Filter Configuration 2 register Filter Configuration 3 register Offset 0 register Offset 1 register Offset 2 register Offset 3 register Gain 0 register Gain 1 register Gain 2 register Gain 3 register 0x0 W 0x00 W Rev. A | Page 52 of 63 Online Documentation Product Overview Design Resources Discussion Sample & Buy Data Sheet AD7175-2 STATUS REGISTER Address: 0x00, Reset: 0x80, Name: STATUS The status register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the data register by setting the DATA_STAT bit in the interface mode register. Table 26. Bit Descriptions for STATUS Bits 7 Bit Name RDY Settings 0 1 6 ADC_ERROR 0 1 5 CRC_ERROR 0 1 4 REG_ERROR 0 1 [3:2] [1:0] RESERVED CHANNEL 00 01 10 11 Description The status of RDY is output to the DOUT/RDYpin whenever CS is low and a register is not being read. This bit goes low when the ADC has written a new result to the data register. In ADC calibration modes, this bit goes low when the ADC has written the calibration result. RDY is brought high automatically by a read of the data register. New data result available Awaiting new data result This bit by default indicates if an ADC overrange or underrange has occurred. The ADC result is clamped to 0xFFFFFF for overrange errors and 0x000000 for underrange errors. This bit is updated when the ADC result is written and is cleared at the next update after removing the overrange or underrange condition. No error Error This bit indicates if a CRC error has taken place during a register write. For register reads, the host microcontroller determines if a CRC error has occurred. This bit is cleared by a read of this register. No error CRC error This bit indicates if the content of one of the internal registers has changed from the value calculated when the register integrity check was activated. The check is activated by setting the REG_CHECK bit in the interface mode register. This bit is cleared by clearing the REG_CHECK bit. No error Error These bits are reserved. These bits indicate which channel was active for the ADC conversion whose result is currently in the data register. This may be different from the channel currently being converted. The mapping is a direct map from the channel register; therefore, Channel 0 results in 0x0 and Channel 3 results in 0x3. Channel 0 Channel 1 Channel 2 Channel 3 Rev. A | Page 53 of 63 Reset 0x1 Access R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R Online Documentation Product Overview Design Resources Discussion Sample & Buy AD7175-2 Data Sheet ADC MODE REGISTER Address: 0x01, Reset: 0x8000, Name: ADCMODE The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets the filter and the RDY bits and starts a new conversion or calibration. Table 27. Bit Descriptions for ADCMODE Bits 15 Bit Name REF_EN Settings 0 1 14 HIDE_DELAY 0 1 13 SING_CYC 0 1 [12:11] [10:8] RESERVED DELAY 000 001 010 011 100 101 110 111 7 [6:4] RESERVED MODE 000 001 010 011 100 110 111 [3:2] CLOCKSEL 00 01 10 11 [1:0] RESERVED Description Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin. Disabled Enabled If a programmable delay has been set using the DELAY bits, this bit allows the delay to be hidden by absorbing the delay into the conversion time for selected data rates with the sinc5 + sinc1 filter. See the Delay section for more information. Enabled Disabled This bit can be used when only a single channel is active to set the ADC to only output at the settled filter data rate. Disabled Enabled These bits are reserved; set these bits to 0. These bits allow a programmable delay to be added after a channel switch to allow settling of external circuitry before the ADC starts processing its input. 0 µs 4 µs 16 µs 40 µs 100 µs 200 µs 500 µs 1 ms This bit is reserved; set this bit to 0. These bits control the operating mode of the ADC. See the Operating Modes section for more information. Continuous conversion mode Single conversion mode Standby mode Power-down mode Internal offset calibration System offset calibration System gain calibration This bit is used to select the ADC clock source. Selecting internal oscillator also enables the internal oscillator. Internal oscillator Internal oscillator output on XTAL2/CLKIO pin External clock input on XTAL2/CLKIO pin External crystal on XTAL1 and XTAL2/CLKIO pins These bits are reserved; set these bits to 0. Rev. A | Page 54 of 63 Reset 0x1 Access RW 0x0 RW 0x0 RW 0x0 0x0 R RW 0x0 0x0 R RW 0x0 RW 0x0 R Online Documentation Product Overview Design Resources Discussion Sample & Buy Data Sheet AD7175-2 INTERFACE MODE REGISTER Address: 0x02, Reset: 0x0000, Name: IFMODE The interface mode register configures various serial interface options. Table 28. Bit Descriptions for IFMODE Bits [15:13] 12 Bit Name RESERVED ALT_SYNC Settings 0 1 11 IOSTRENGTH 0 1 [10:9] 8 RESERVED DOUT_RESET 0 1 7 CONTREAD 0 1 6 DATA_STAT 0 1 5 REG_CHECK 0 1 4 [3:2] RESERVED CRC_EN 00 01 10 1 RESERVED Description These bits are reserved; set these bits to 0. This bit enables a different behavior of the SYNC/ERROR pin to allow the use of SYNC/ERROR as a control for conversions when cycling channels (see the description of the SYNC_EN bit in the GPIO Configuration Register section for details). Disabled Enabled This bit controls the drive strength of the DOUT/RDY pin. Set this bit when reading from the serial interface at high speed with a low IOVDD supply and moderate capacitance. Disabled (default) Enabled These bits are reserved; set these bits to 0. See DOUT_RESET section for more information. Disabled Enabled This enables continuous read of the ADC data register. The ADC must be configured in continuous conversion mode to use continuous read. For more details, see the Operating Modes section. Disabled Enabled This enables the status register to be appended to the data register when read so that channel and status information are transmitted with the data. This is the only way to be sure that the channel bits read from the status register correspond to the data in the data register. Disabled Enabled This bit enables a register integrity checker, which can be used to monitor any change in the value of the user registers. To use this feature, configure all other registers as desired, with this bit cleared. Then write to this register to set the REG_CHECK bit to 1. If the contents of any of the registers change, the REG_ERROR bit is set in the status register. To clear the error, set the REG_CHECK bit to 0. Neither the interface mode register nor the ADC data or status registers are included in the registers that are checked. If a register must have a new value written, this bit must first be cleared; otherwise, an error is flagged when the new register contents are written. Disabled Enabled This bit is reserved; set this bit to 0. Enables CRC protection of register reads/writes. CRC increases the number of bytes in a serial interface transfer by one. See the CRC Calculation section for more details. Disabled XOR checksum enabled for register read transactions; register writes still use CRC with these bits set CRC checksum enabled for read and write transactions This bit is reserved; set this bit to 0. Rev. A | Page 55 of 63 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 0x0 R RW 0x0 RW 0x0 RW 0x0 RW 0x0 0x00 R RW 0x0 R Online Documentation Product Overview Design Resources Discussion Sample & Buy AD7175-2 Bits 0 Bit Name WL16 Data Sheet Settings 0 1 Description Changes the ADC data register to 16 bits. The ADC is not reset by a write to the interface mode register; therefore, the ADC result is not rounded to the correct word length immediately after writing to these bits. The first new ADC result is correct. 24-bit data 16-bit data Reset 0x0 Access RW REGISTER CHECK Address: 0x03, Reset: 0x000000, Name: REGCHECK The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit in the interface mode register must be set for this to operate; otherwise, the register reads 0. Table 29. Bit Descriptions for REGCHECK Bits [23:0] Bit Name REGISTER_CHECK Settings Description This register contains the 24-bit checksum of user registers when the REG_CHECK bit is set in the interface mode register. Reset 0x000000 Access R DATA REGISTER Address: 0x04, Reset: 0x000000, Name: DATA The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the BI_UNIPOLARx bit in the setup configuration registers. Reading the data register brings the RDY bit and the RDY output high if it had been low. The ADC result can be read multiple times; however, because the RDY output has been brought high, it is not possible to know if another ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the data register. Table 30. Bit Descriptions for DATA Bits [23:0] Bit Name DATA Settings Description This register contains the ADC conversion result. If DATA_STAT is set in the interface mode register, the status register is appended to this register when read, making this a 32-bit register. If WL16 is set in the interface mode register, this register is reduced to 16 bits. Rev. A | Page 56 of 63 Reset 0x000000 Access R Online Documentation Product Overview Design Resources Discussion Sample & Buy Data Sheet AD7175-2 GPIO CONFIGURATION REGISTER Address: 0x06, Reset: 0x0800, Name: GPIOCON The GPIO configuration register controls the general-purpose I/O pins of the ADC. Table 31. Bit Descriptions for GPIOCON Bits [15:13] 12 Bit Name RESERVED MUX_IO 11 SYNC_EN Settings 0 1 [10:9] ERR_EN 00 01 10 11 8 ERR_DAT [7:6] 5 RESERVED IP_EN1 0 1 4 IP_EN0 0 1 3 OP_EN1 0 1 2 OP_EN0 0 1 Description These bits are reserved; set these bits to 0. This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1 in sync with the internal channel sequencing. The analog input pins used for a channel can still be selected on a per channel basis. Therefore, it is possible to have a 4-channel multiplexer in front of AIN0/AIN1 and another in front of AIN2/AIN3, giving a total of eight differential channels with the AD7175-2. However, only four channels at a time can be automatically sequenced. A delay can be inserted after switching an external multiplexer (see the DELAY bits in the ADC Mode Register section). This bit enables the SYNC/ERROR pin as a sync input. When the pin is low, this holds the ADC and filter in reset until SYNC/ERROR pin goes high. An alternative operation of the SYNC/ERROR pin is available when the ALT_SYNC bit in the interface mode register is set. This mode only works when multiple channels are enabled. In this case, a low on the SYNC/ERROR pin does not immediately reset the filter/ modulator. Instead, if the SYNC/ERROR pin is low when the channel is due to be switched, the modulator and filter are prevented from starting a new conversion. Bringing SYNC/ERROR high begins the next conversion. This alternative sync mode allows SYNC/ERROR to be used while cycling through channels. Disabled. Enabled. These bits enable the SYNC/ERROR pin as an error input/output. Disabled. SYNC/ERROR is an error input. The (inverted) readback state is OR'ed with other error sources and is available in the ADC_ERROR bit in the status register. The SYNC / ERROR pin state can also be read from the ERR_DAT bit in this register. SYNC/ERROR is an open-drain error output. The status register error bits are OR'ed, inverted, and mapped to the SYNC/ERROR pin. The SYNC/ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed. SYNC/ERROR is a general-purpose output. The status of the pin is controlled by the ERR_DAT bit in this register. This output is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the general-purpose I/O pins. The SYNC/ERROR pin has an active pull-up in this case. Reset 0x0 0x0 Access R RW 0x1 RW 0x0 RW This bit determines the logic level at the SYNC/ERROR pin if the pin is enabled as a general-purpose output. This bit reflects the readback status of the pin if the pin is enabled as an input. These bits are reserved; set these bits to 0. This bit turns GPIO1 into an input. Inputs are referenced to AVDD1 or AVSS. Disabled. Enabled. This bit turns GPIO0 into an input. Inputs are referenced to AVDD1 or AVSS. Disabled. Enabled. This bit turns GPIO1 into an output. Outputs are referenced between AVDD1 and AVSS. Disabled. Enabled. This bit turns GPIO0 into an output. Outputs are referenced between AVDD1 and AVSS. Disabled. Enabled. 0x0 RW 0x0 0x0 R RW 0x0 RW 0x0 RW 0x0 RW Rev. A | Page 57 of 63 Online Documentation Product Overview Design Resources Discussion Sample & Buy AD7175-2 1 0 Data Sheet GP_DATA1 GP_DATA0 This bit is the readback or write data for GPIO1. This bit is the readback or write data for GPIO0. 0x0 0x0 RW RW ID REGISTER Address: 0x07, Reset: 0x0CDX, Name: ID The ID register returns a 16-bit ID. For the AD7175-2, this should be 0x0CDX. Table 32. Bit Descriptions for ID Bits [15:0] Bit Name ID Settings 0x0CDX Description The ID register returns a 16-bit ID code that is specific to the ADC. AD7175-2 Reset 0x0CDX Access R CHANNEL REGISTER 0 Address: 0x10, Reset: 0x8001, Name: CH0 The channel registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup is used to configure the ADC for that channel. Table 33. Bit Descriptions for CH0 Bits 15 Bit Name CH_EN0 Settings 0 1 14 [13:12] RESERVED SETUP_SEL0 00 01 10 11 [11:10] [9:5] RESERVED AINPOS0 00000 00001 00010 00011 00100 10001 10010 10011 10100 10101 10110 Description This bit enables Channel 0. If more than one channel is enabled, the ADC automatically sequences between them. Disabled Enabled (default) This bit is reserved; set this bit to 0. These bits identify which of the four setups are used to configure the ADC for this channel. A setup comprises a set of four registers: setup configuration register, filter configuration register, offset register, and gain register. All channels can use the same setup, in which case the same 2-bit value must be written to these bits on all active channels, or up to four channels can be configured differently. Setup 0 Setup 1 Setup 2 Setup 3 These bits are reserved; set these bits to 0. These bits select which input is connected to the positive input of the ADC for this channel. AIN0 (default) AIN1 AIN2 AIN3 AIN4 Temperature sensor+ Temperature sensor− ((AVDD1 − AVSS)/5)+ (analog input buffers must be enabled) ((AVDD1 − AVSS)/5)− (analog input buffers must be enabled) REF+ REF− Rev. A | Page 58 of 63 Reset 0x1 Access RW 0x0 0x0 R RW 0x0 0x0 R RW Design Resources Online Documentation Product Overview Sample & Buy Discussion Data Sheet Bits [4:0] AD7175-2 Bit Name AINNEG0 Settings 00000 00001 00010 00011 00100 10001 10010 10011 10100 10101 10110 Description These bits select which input is connected to the negative input of the ADC for this channel. AIN0 AIN1 (default) AIN2 AIN3 AIN4 Temperature sensor+ Temperature sensor− ((AVDD1 − AVSS)/5)+ ((AVDD1 − AVSS)/5)− REF+ REF− Reset 0x1 Access RW CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 Address: 0x11 to 0x13, Reset: 0x0001, Name: CH1 to CH3 The remaining three channel registers share the same layout as Channel Register 0. Table 34. CH1 to CH3 Register Map Reg. 0x11 Name CH1 Bits [15:8] Bit 7 CH_EN1 0x12 CH2 [15:8] [7:0] CH_EN2 RESERVED AINPOS2[2:0] SETUP_SEL2 0x13 CH3 [15:8] [7:0] CH_EN3 RESERVED AINPOS3[2:0] SETUP_SEL3 [7:0] Bit 6 RESERVED Bit 5 Bit 4 SETUP_SEL1 Bit 3 AINPOS1[2:0] Bit 2 RESERVED Bit 1 Bit 0 AINPOS1[4:3] Reset 0x0001 RW RW RESERVED AINNEG2 AINPOS2[4:3] 0x0001 RW RESERVED AINNEG3 AINPOS3[4:3] 0x0001 RW AINNEG1 Rev. A | Page 59 of 63 Online Documentation Product Overview Design Resources Discussion Sample & Buy AD7175-2 Data Sheet SETUP CONFIGURATION REGISTER 0 Address: 0x20, Reset: 0x1320, Name: SETUPCON0 The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC. Table 35. Bit Descriptions for SETUPCON0 Bits [15:13] 12 Bit Name RESERVED BI_UNIPOLAR0 Settings 0 1 11 REFBUF0+ 0 1 10 REFBUF0− 0 1 9 AINBUF0+ 0 1 8 AINBUF0− 0 1 7 BURNOUT_EN0 6 [5:4] RESERVED REF_SEL0 00 10 11 [3:0] RESERVED Description These bits are reserved; set these bits to 0. This bit sets the output coding of the ADC for Setup 0. Unipolar coded output Bipolar coded output (offset binary) This bit enables or disables the REF+ input buffer. REF+ buffer disabled REF+ buffer enabled This bit enables or disables the REF− input buffer. REF− buffer disabled REF− buffer enabled This bit enables or disables the AIN+ input buffer. AIN+ buffer disabled AIN+ buffer enabled This bit enables or disables the AIN− input buffer. AIN− buffer disabled AIN− buffer enabled This bit enables a 10 µA current source on the positive analog input selected and a 10 µA current sink on the negative analog input selected. The burnout currents are useful in diagnosis of an open wire, whereby the ADC result goes to full scale. Enabling the burnout currents during measurement results in an offset voltage on the ADC. This means the strategy for diagnosing an open wire operates best by turning on the burnout currents at intervals, before or after precision measurements. These bits are reserved; set these bits to 0. These bits allow you to select the reference source for ADC conversion on Setup 0. External Reference. Internal 2.5 V Reference. This must also be enabled in the ADC mode register. AVDD1 − AVSS. This can be used to as a diagnostic to validate other reference values. These bits are reserved; set these bits to 0. Reset 0x0 0x1 Access R RW 0x0 RW 0x0 RW 0x1 RW 0x1 RW 0x00 R 0x00 0x2 R RW 0x0 R SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 Address: 0x21 to 0x23, Reset: 0x1320, Name: SETUPCON1 to SETUPCON3 The remaining three setup configuration registers share the same layout as Setup Configuration Register 0. Table 36. SETUPCON1 to SETUPCON3 Register Map Reg. 0x21 Name SETUPCON1 0x22 SETUPCON2 0x23 SETUPCON3 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 7 BURNOUT_EN1 BURNOUT_EN2 BURNOUT_EN3 Bit 6 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Bit 5 Bit 4 BI_UNIPOLAR1 REF_SEL1 BI_UNIPOLAR2 REF_SEL2 BI_UNIPOLAR3 REF_SEL3 Rev. A | Page 60 of 63 Bit 3 REFBUF1+ REFBUF2+ REFBUF3+ Bit 2 Bit 1 REFBUF1− AINBUF1+ RESERVED REFBUF2− AINBUF2+ RESERVED REFBUF3− AINBUF3+ RESERVED Bit 0 AINBUF1− Reset 0x1320 RW RW AINBUF2− 0x1320 RW AINBUF3− 0x1320 RW Online Documentation Product Overview Design Resources Discussion Sample & Buy Data Sheet AD7175-2 FILTER CONFIGURATION REGISTER 0 Address: 0x28, Reset: 0x0500, Name: FILTCON0 The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence. Table 37. Bit Descriptions for FILTCON0 Bits 15 Bit Name SINC3_MAP0 [14:12] 11 RESERVED ENHFILTEN0 Settings 0 1 [10:8] ENHFILT0 010 011 101 110 7 [6:5] RESERVED ORDER0 00 11 [4:0] ODR0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 Description If this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter for Setup 0. All other options are eliminated. This allows fine tuning of the output data rate and filter notch for rejection of specific frequencies. The data rate when on a single channel equals fMOD/(32 × FILTCON0[14:0]). These bits are reserved; set these bits to 0. This bit enables various postfilters for enhanced 50 Hz/60 Hz rejection for Setup 0. The ORDER0 bits must be set to 00 to select the sinc5 + sinc1 filter for this to work. Disabled Enabled These bits select between various postfilters for enhanced 50 Hz/60 Hz rejection for Setup 0. 27 SPS, 47 dB rejection, 36.7 ms settling 25 SPS, 62 dB rejection, 40 ms settling 20 SPS, 86 dB rejection, 50 ms settling 16.67 SPS, 92 dB rejection, 60 ms settling This bit is reserved; set this bit to 0. These bits control the order of the digital filter that processes the modulator data for Setup 0. Sinc5 + sinc1 (default) Sinc3 These bits control the output data rate of the ADC and, therefore, the settling time and noise for Setup 0. Rates shown as for sinc5 + sinc 1 filter. See Table 19 to Table 22. 250,000 125,000 62,500 50,000 31,250 25,000 15,625 10,000 5000 2500 1000 500 397.5 200 100 59.92 49.96 20 16.66 10 5 Rev. A | Page 61 of 63 Reset 0x0 Access RW 0x0 0x0 R RW 0x5 RW 0x0 0x0 R RW 0x0 RW Design Resources Online Documentation Product Overview Discussion Sample & Buy AD7175-2 Data Sheet FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 Address: 0x29 to 0x2B, Reset: 0x0500, Name: FILTCON1 to FILTCON3 The remaining three filter configuration registers share the same layout as Filter Configuration Register 0. Table 38. FILTCON1 to FILTCON3 Register Map Reg. 0x29 Name FILTCON1 0x2A FILTCON2 0x2B FILTCON3 Bits [15:8] Bit 7 SINC3_MAP1 Bit 6 Bit 5 RESERVED Bit 4 Bit 3 ENHFILTEN1 [7:0] RESERVED ORDER1 [15:8] [7:0] SINC3_MAP2 RESERVED RESERVED ORDER2 ENHFILTEN2 [15:8] SINC3_MAP3 RESERVED ENHFILTEN3 [7:0] RESERVED Bit 2 Bit 1 ENHFILT1 Bit 0 Reset 0x0500 RW RW ENHFILT2 0x0500 RW ENHFILT3 0x0500 RW ODR1 ODR2 ORDER3 ODR3 OFFSET REGISTER 0 Address: 0x30, Reset: 0x800000, Name: OFFSET0 The offset (zero-scale) registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system. Table 39. Bit Descriptions for OFFSET0 Bits [23:0] Bit Name OFFSET0 Settings Description Offset calibration coefficient for Setup 0. Reset 0x800000 Access RW OFFSET REGISTER 1 TO OFFSET REGISTER 3 Address: 0x31 to 0x33, Reset: 0x800000, Name: OFFSET1 to OFFSET3 The remaining three offset registers share the same layout as Offset Register 0. Table 40. OFFSET1 to OFFSET3 Register Map Reg. 0x31 0x32 0x33 Name OFFSET1 OFFSET2 OFFSET3 Bits [23:0] [23:0] [23:0] OFFSET1[23:0] OFFSET2[23:0] OFFSET3[23:0] Reset 0x800000 0x800000 0x800000 RW RW RW RW GAIN REGISTER 0 Address: 0x38, Reset: 0x5XXXX0, Name: GAIN0 The gain (full-scale) registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system. Table 41. Bit Descriptions for GAIN0 Bits [23:0] Bit Name GAIN0 Settings Description Gain calibration coefficient for Setup 0. Reset 0x5XXXX0 Access RW GAIN REGISTER 1 TO GAIN REGISTER 3 Address: 0x39 to 0x3B, Reset: 0x5XXXX0, Name: GAIN1 to GAIN3 The remaining three gain registers share the same layout as Gain Register 0. Table 42. GAIN1 to GAIN3 Register Map Reg. 0x39 0x3A 0x3B Name GAIN1 GAIN2 GAIN3 Bits [23:0] [23:0] [23:0] GAIN1[23:0] GAIN2[23:0] GAIN3[23:0] Rev. A | Page 62 of 63 Reset 0x5XXXX0 0x5XXXX0 0x5XXXX0 RW RW RW RW Design Resources Online Documentation Product Overview Discussion Data Sheet Sample & Buy AD7175-2 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 75. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Models 1 AD7175-2BRUZ AD7175-2BRUZ-RL AD7175-2BRUZ-RL7 EVAL-AD7175-2SDZ EVAL-SDP-CB1Z 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation Board Evaluation Controller Board Z = RoHS Compliant Part. ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12468-0-9/14(A) Rev. A | Page 63 of 63 Package Option RU-24 RU-24 RU-24