LP38842-ADJ 1.5A Ultra Low Dropout Adjustable Linear Regulators Stable with Ceramic Output Capacitors General Description Features The LP38842-ADJ is a high current, fast response regulator which can maintain output voltage regulation with minimum input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: Vbias provides voltage to drive the gate of the N-MOS power transistor, while Vin is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low Vin voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. The fast transient response of these devices makes them suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The parts are available in the PSOP package. Dropout Voltage: 115 mV (typ) @ 1.5A load current. Quiescent Current: 30 mA (typ) at full load. Shutdown Current: 30 nA (typ) when S/D pin is low. Precision Reference Voltage: 1.5% room temperature accuracy. n n n n n n n n n n n Ideal for conversion from 1.8V or 1.5V inputs Designed for use with low ESR ceramic capacitors Ultra low dropout voltage (115mV @ 1.5A typ) 0.56V to 1.5V adjustable output range Load regulation of 0.1%/A (typ) 30nA quiescent current in shutdown (typ) Low ground pin current at all loads Over temperature/over current protection Available in 8 lead PSOP package −40˚C to +125˚C junction temperature range UVLO disables output when VBIAS < 3.8V Applications n ASIC Power Supplies In: - Desktops, Notebooks, and Graphics Cards, Servers - Gaming Set Top Boxes, Printers and Copiers n Server Core and I/O Supplies n DSP and FPGA Power Supplies n SMPS Post-Regulators Typical Application Circuit 20117601 * Minimum value required if Tantalum capacitor is used (see Application Hints). © 2005 National Semiconductor Corporation DS201176 www.national.com LP38842-ADJ 1.5A Ultra Low Dropout Linear Regulators Stable with Ceramic Output Capacitors February 2005 LP38842-ADJ Connection Diagram 20117635 PSOP-8, Top View Pin Description Pin Name BIAS OUTPUT Description The bias pin is used to provide the low current bias voltage to the chip which operates the internal circuitry and provides drive voltage for the N-FET. The regulated output voltage is connected to this pin. GND This is both the power and analog ground for the IC. Note that both pin three and the tab of the TO-220 and TO-263 packages are at ground potential. Pin three and the tab should be tied together using the PC board copper trace material and connected to circuit ground. INPUT The high current input voltage which is regulated down to the nominal output voltage must be connected to this pin. Because the bias voltage to operate the chip is provided seperately, the input voltage can be as low as a few hundered millivolts above the output voltage. SHUTDOWN ADJ This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if this function is not used. The adjust pin is used to set the regulated output voltage by connecting it to the external resistors R1 and R2 (see Typical Application Circuit). Ordering Information Order Number Package Type Package Drawing Supplied As LP38842MR-ADJ PSOP-8 MRA08A 95 Units Tape and Reel LP38842MRX-ADJ PSOP-8 MRA08A 2500 Units Tape and Reel Block Diagram 20117624 www.national.com 2 IOUT (Survival) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Output Voltage (Survival) Storage Temperature Range −40˚C to +150˚C Operating Ratings 260˚C VIN Supply Voltage ESD Rating Human Body Model (Note 3) Machine Model (Note 9) (VOUT + VDO) to 5.5V Shutdown Input Voltage 2 kV 200V 0 to +5.5V IOUT 1.5A VIN Supply Voltage (Survival) −0.3V to +6V Operating Junction Temperature Range VBIAS Supply Voltage (Survival) −0.3V to +7V VBIAS Supply Voltage Shutdown Input Voltage (Survival) −0.3V to +7V VOUT VADJ -0.3V to +6V Power Dissipation (Note 2) −0.3V to +6V Junction Temperature −65˚C to +150˚C Lead Temp. (Soldering, 5 seconds) Internally Limited Internally Limited −40˚C to +125˚C 4.5V to 5.5V 0.56V to 1.5V Electrical Characteristics Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = 10 µF CER, COUT = 22 µF CER, VS/D = VBIAS. Min/Max limits are guaranteed through testing, statistical correlation, or design. Symbol VADJ IADJ Parameter Adjust Pin Voltage Adjust Pin Bias Current Conditions 10 mA < IL < 1.5A VO(NOM) + 1V ≤ VIN ≤ 5.5V 4.5V ≤ VBIAS ≤ 5.5V Output Voltage Line Regulation VO(NOM) + 1V ≤ VIN ≤ 5.5V (Note 6) ∆VO/∆IL Output Voltage Load Regulation (Note 7) 10 mA < IL < 1.5A VDO Dropout Voltage (Note 8) IL = 1.5A IQ(VIN) Quiescent Current Drawn from VIN Supply 10 mA < IL < 1.5A V Quiescent Current Drawn from VBIAS Supply TYP (Note 4) MAX Units 0.552 0.543 0.56 0.568 0.577 V 10 mA < IL < 1.5A VO(NOM) + 1V ≤ VIN ≤ 5.5V 4.5V ≤ VBIAS ≤ 5.5V ∆VO/∆VIN IQ(VBIAS) MIN S/D ≤ 0.3V 10 mA < IL < 1.5A V S/D ≤ 0.3V UVLO VBIAS Voltage Where Regulator Output Is Enabled ISC Short-Circuit Current VOUT = 0V Output Turn-off Threshold Output = ON 1 µA 0.01 %/V 0.1 0.4 1.1 %/A 115 175 315 mV 30 35 40 mA 0.06 1 30 µA 2 4 6 mA 0.03 1 30 µA 3.8 V 4 A Shutdown Input VSDT 0.7 Output = OFF 0.3 0.7 Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15 IS/D S/D Input Current V S/D =1.3V 1 ≤ 0.3V −1 V θJ-A Junction to Ambient Thermal Resistance S/D PSOP-8 Package (Note 10) 3 43 1.3 V µs µA ˚C/W www.national.com LP38842-ADJ Absolute Maximum Ratings (Note 1) LP38842-ADJ Electrical Characteristics Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = 10 µF CER, COUT = 22 µF CER, VS/D = VBIAS. Min/Max limits are guaranteed through testing, statistical correlation, or design. (Continued) Symbol Parameter Conditions MIN TYP (Note 4) MAX Units AC Parameters PSRR (VIN) PSRR (VBIAS) en Ripple Rejection for VIN Input Voltage VIN = VOUT +1V, f = 120 Hz 80 VIN = VOUT + 1V, f = 1 kHz 65 Ripple Rejection for VBIAS Voltage VBIAS = VOUT + 3V, f = 120 Hz 58 VBIAS = VOUT + 3V, f = 1 kHz 58 Output Noise Density f = 120 Hz 1 Output Noise Voltage VOUT = 1.5V BW = 10 Hz − 100 kHz 150 BW = 300 Hz − 300 kHz 90 dB µV/root−Hz µV (rms) Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Note 4: Typical numbers represent the most likely parametric norm for 25˚C operation. Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. Note 9: The machine model is a 220 pF capacitor discharged directly into each pin. Note 10: For optimum heat dissipation, the ground pad must be soldered to a copper plane or connected using vias to an internal copper plane. www.national.com 4 VBIAS Transient Response Load Transient Response 20117636 20117637 Load Transient Response Dropout Voltage Over Temperature 20117638 20117639 VBIAS PSRR VBIAS PSRR 20117651 20117641 5 www.national.com LP38842-ADJ Typical Performance Characteristics Unless otherwise specified: TJ = 25˚C, CIN = 10 µF CER, COUT = 22 µF CER, CBIAS = 1 µF CER, S/D Pin is tied to VBIAS, VOUT = 1.2V, IL = 10mA, VBIAS = 5V, VIN = VOUT + 1V. LP38842-ADJ Typical Performance Characteristics Unless otherwise specified: TJ = 25˚C, CIN = 10 µF CER, COUT = 22 µF CER, CBIAS = 1 µF CER, S/D Pin is tied to VBIAS, VOUT = 1.2V, IL = 10mA, VBIAS = 5V, VIN = VOUT + 1V. (Continued) VIN PSRR Output Noise Voltage 20117643 20117642 VADJ / IADJ vs Temperature 20117660 www.national.com 6 SETTING THE OUTPUT VOLTAGE (Refer to Typical Application Circuit) The output voltage is set using the resistive divider R1 and R2. The output voltage is given by the formula: VOUT = VADJ x (1 + R1 / R2) As R1 reduces, the two equations come closer to being equal and the pole and zero begin to cancel each other out which removes the beneficial phase lead of the zero. The value of resistor R2 must be 10k or less for proper operation. EXTERNAL CAPACITORS BIAS CAPACITOR To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended). OUTPUT CAPACITOR BIAS VOLTAGE The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage must be in the range of 4.5 - 5.5V to assure proper operation of the part. An output capacitor is required on the LP3884X devices for loop stability. The minimum value of capacitance necessary depends on type of capacitor: if a solid Tantalum capacitor is used, the part is stable with capacitor values as low as 4.7µF. If a ceramic capacitor is used, a minimum of 22 µF of capacitance must be used (capacitance may be increased without limit). The reason a larger ceramic capacitor is required is that the output capacitor sets a pole which limits the loop bandwidth. The Tantalum capacitor has a higher ESR than the ceramic which provides more phase margin to the loop, thereby allowing the use of a smaller output capacitor because adequate phase margin can be maintained out to a higher crossover frequency. The tantalum capacitor will typically also provide faster settling time on the output after a fast changing load transient occurs, but the ceramic capacitor is superior for bypassing high frequency noise. The output capacitor must be located less than one centimeter from the output pin and returned to a clean analog ground. Care must be taken in choosing the output capacitor to ensure that sufficient capacitance is provided over the full operating temperature range. If ceramics are selected, only X7R or X5R types may be used because Z5U and Y5F types suffer severe loss of capacitance with temperature and applied voltage and may only provide 20% of their rated capacitance in operation. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage is below approximately 3.8V. SHUTDOWN OPERATION Pulling down the shutdown (S/D) pin will turn-off the regulator. The S/D pin must be actively terminated through a pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used. POWER DISSIPATION/HEATSINKING Heatsinking for the PSOP-8 package is accomplished by allowing heat to flow through the ground slug on the bottom of the package into the copper on the PC board. The heat slug must be soldered down to a copper plane to get good heat transfer. It can also be connected through vias to internal copper planes. Since the heat slug is at ground potential, traces must not be routed under it which are not at ground potential. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. INPUT CAPACITOR The input capacitor is also critical to loop stability because it provides a low source impedance for the regulator. The minimum required input capacitance is 10 µF ceramic (Tantalum not recommended). The value of CIN may be increased without limit. As stated above, X5R or X7R must be used to ensure sufficient capacitance is provided. The input capacitor must be located less than one centimeter from the input pin and returned to a clean analog ground. FEED FORWARD CAPACITOR (Refer to Typical Application Circuit) A capacitor placed across R1 can provide some additional phase margin and improve transient response. The capacitor CFF and R1 form a zero in the loop response given by the formula: 7 www.national.com LP38842-ADJ FZ = 1 / (2 x π x CFF x R1) For best effect, select CFF so the zero frequency is approximately 70 kHz. The phase lead provided by CFF drops as the output voltage gets closer to 0.56V (and R1 reduces in value). The reason is that CFF also forms a pole whose frequency is given by: FP = 1 / (2 x π x CFF x R1 // R2) Application Hints LP38842-ADJ 1.5A Ultra Low Dropout Linear Regulators Stable with Ceramic Output Capacitors Physical Dimensions inches (millimeters) unless otherwise noted PSOP-8 8-Lead Molded PSOP-2 NS Package Number MRA08B National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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