MOTOROLA MC68HC908JK8 Motorola reserves the right to make changes without further notice to any products herein Datasheet

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Freescale Semiconductor, Inc.
MC68HC908JL8
MC68HC908JK8
Technical Data
M68HC08
Microcontrollers
MC68HC908JL8/D
Rev. 2, 12/2002
MOTOROLA.COM/SEMICONDUCTORS
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MC68HC908JL8
MC68HC908JK8
Technical Data
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for
each customer application by customer's technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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digital dna is a trademark of Motorola, Inc.
MC68HC908JL8 — Rev. 2.0
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Technical Data
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Revision History
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documents on the World Wide Web will be the most current. Your printed
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The following revision history table summarizes changes contained in
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Revision History
Date
Revision
Level
Dec 2002
2
Description
First general release.
Technical Data
Page
Number(s)
—
MC68HC908JL8 — Rev. 2.0
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List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 27
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Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Section 3. Random-Access Memory (RAM) . . . . . . . . . . 47
Section 4. FLASH Memory (FLASH) . . . . . . . . . . . . . . . . 49
Section 5. Configuration and Mask Option Registers
(CONFIG & MOR). . . . . . . . . . . . . . . . . . . . . . 59
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 65
Section 7. System Integration Module (SIM) . . . . . . . . . 85
Section 8. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . 109
Section 9. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . 117
Section 10. Timer Interface Module (TIM) . . . . . . . . . . . 145
Section 11. Serial Communications Interface (SCI) . . . 169
Section 12. Analog-to-Digital Converter (ADC) . . . . . . 207
Section 13. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 217
Section 14. External Interrupt (IRQ) . . . . . . . . . . . . . . . 235
Section 15. Keyboard Interrupt Module (KBI). . . . . . . . 241
Section 16. Computer Operating Properly (COP) . . . . 249
Section 17. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . . 255
Section 18. Break Module (BREAK) . . . . . . . . . . . . . . . 259
Section 19. Electrical Specifications. . . . . . . . . . . . . . . 267
Section 20. Mechanical Specifications . . . . . . . . . . . . . 279
Section 21. Ordering Information . . . . . . . . . . . . . . . . . 285
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List of Sections
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List of Sections
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Technical Data – MC68HC908JL8
Table of Contents
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Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.6
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Section 2. Memory Map
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Section 3. Random-Access Memory (RAM)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Section 4. FLASH Memory (FLASH)
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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4.4
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.5
FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.6
FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.7
FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.8
FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.8.1
FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . .57
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Section 5. Configuration and Mask Option Registers
(CONFIG & MOR)
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.4
Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .61
5.5
Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .62
5.6
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Section 6. Central Processor Unit (CPU)
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
6.4.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.4.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.4.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.4.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Technical Data
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6.7
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.8
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.9
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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Section 7. System Integration Module (SIM)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 89
7.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.3.2
Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . . 89
7.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 89
7.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 90
7.4.1
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 91
7.4.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.4.2.2
Computer Operating Properly (COP) Reset. . . . . . . . . . . 93
7.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.4.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . 94
7.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 94
7.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . 94
7.5.3
SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .95
7.6
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.6.2
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.6.2.1
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 100
7.6.2.2
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . 100
7.6.2.3
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . 101
7.6.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.6.4
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
7.6.5
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 102
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7.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.8.1
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . 105
7.8.2
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . 106
7.8.3
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 108
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Section 8. Oscillator (OSC)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.3
Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.3.1
XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.3.2
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.4
Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.5.1
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . 114
8.5.2
Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6) . 115
8.5.3
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 115
8.5.4
XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . 115
8.5.5
RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . 115
8.5.6
Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . 115
8.5.7
Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.5.8
Internal Oscillator Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . 116
8.6
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
8.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.7
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . 116
Section 9. Monitor ROM (MON)
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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9.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.4.1
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.4.2
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.4.3
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9.4.4
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.4.5
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
9.4.6
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
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9.5
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.6
ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
9.6.1
PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.6.2
ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.6.3
LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.6.4
MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.6.5
MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.6.6
MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
9.6.7
EE_WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
9.6.8
EE_READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Section 10. Timer Interface Module (TIM)
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
10.5.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 152
10.5.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 153
10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 153
10.5.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 154
10.5.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 155
10.5.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
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10.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
10.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
10.8
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 158
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10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
10.9.1 TIM Clock Pin (ADC12/T2CLK) . . . . . . . . . . . . . . . . . . . . . 159
10.9.2 TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1,
PTE0/T2CH0, PTE1/T2CH1) . . . . . . . . . . . . . . . . . . . . 159
10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
10.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 160
10.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
10.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 163
10.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .164
10.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Section 11. Serial Communications Interface (SCI)
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
11.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
11.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
11.5.2.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.5.2.2
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.5.2.3
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.5.2.4
Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.5.2.5
Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . . 179
11.5.2.6
Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 179
11.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.5.3.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.5.3.2
Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
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11.5.3.3
11.5.3.4
11.5.3.5
11.5.3.6
11.5.3.7
11.5.3.8
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
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11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.7
SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 189
11.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
11.8.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
11.8.2 RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
11.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
11.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
11.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
11.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
11.9.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
11.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
11.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
11.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Section 12. Analog-to-Digital Converter (ADC)
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
12.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
12.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
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12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 212
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12.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
12.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 212
12.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
12.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 215
Section 13. Input/Output (I/O) Ports
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
13.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
13.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 220
13.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 221
13.3.3 Port A Input Pull-Up Enable Registers . . . . . . . . . . . . . . . . 223
13.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
13.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 224
13.4.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 225
13.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
13.5.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 227
13.5.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 228
13.5.3 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . . 230
13.6 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
13.6.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . 231
13.6.2 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . 232
Section 14. External Interrupt (IRQ)
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
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14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
14.4.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
14.5
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .239
14.6
IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 239
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Section 15. Keyboard Interrupt Module (KBI)
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
15.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
15.4
I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
15.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
15.5.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
15.6 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . 245
15.6.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 246
15.6.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 247
15.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
15.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
15.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
15.8
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .248
Section 16. Computer Operating Properly (COP)
16.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
16.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
16.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.4.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.4.4 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
16.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
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16.4.7
COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 252
16.5
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
16.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
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16.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .254
Section 17. Low Voltage Inhibit (LVI)
17.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
17.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
17.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
17.5
LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . 257
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Section 18. Break Module (BREAK)
18.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
18.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .262
18.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 262
18.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 262
18.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 262
18.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
18.5.1 Break Status and Control Register (BRKSCR) . . . . . . . . . 263
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18.5.2
18.5.3
18.5.4
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .264
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 266
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
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Section 19. Electrical Specifications
19.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
19.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .268
19.4
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 269
19.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
19.6
5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 270
19.7
5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
19.8
5V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 272
19.9
3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 273
19.10 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
19.11 3V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 275
19.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
19.13 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 277
19.14 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
19.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Section 20. Mechanical Specifications
20.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
20.3
20-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . . 280
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20.4
20-Pin Small Outline Integrated Circuit Package (SOIC) . . . . 280
20.5
28-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . . 281
20.6
28-Pin Small Outline Integrated Circuit Package (SOIC) . . . . 281
20.7
32-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . . 282
20.8
32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . 283
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Section 21. Ordering Information
21.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
21.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
21.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
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Technical Data – MC68HC908JL8
List of Figures
Freescale Semiconductor, Inc...
Figure
Title
1-1
1-2
1-3
1-4
1-5
MC68HC908JL8 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 30
32-Pin LQFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 31
32-Pin SDIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 31
28-Pin PDIP/SOIC Pin Assignment . . . . . . . . . . . . . . . . . . . . . 32
20-Pin PDIP/SOIC Pin Assignment . . . . . . . . . . . . . . . . . . . . . 32
2-1
2-2
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 38
4-1
4-2
4-3
4-4
FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 50
FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . . 51
FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 55
FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . . 57
5-1
5-2
5-3
5-4
CONFIG Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .61
Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .62
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6-1
6-2
6-3
6-4
6-5
6-6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 70
7-1
7-2
7-3
7-4
SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
MC68HC908JL8 — Rev. 2.0
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Freescale Semiconductor, Inc...
Figure
Title
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . 98
Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .100
Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .100
Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .101
Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 103
Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 103
Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 105
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . 105
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . 107
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . .108
8-1
8-2
8-3
8-4
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . 111
XTAL Oscillator External Connections . . . . . . . . . . . . . . . . . . 112
RC Oscillator External Connections . . . . . . . . . . . . . . . . . . . . 113
Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . . 122
Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Data Block Format for ROM-Resident Routines. . . . . . . . . . . 132
EE_WRITE FLASH Memory Usage . . . . . . . . . . . . . . . . . . . . 141
10-1
10-2
10-3
TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 154
Technical Data
20
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MC68HC908JL8 — Rev. 2.0
List of Figures
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Freescale Semiconductor, Inc.
List of Figures
Freescale Semiconductor, Inc...
Figure
Title
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 160
TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . . 162
TIM Counter Registers Low (TCNTL) . . . . . . . . . . . . . . . . . . . 163
TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .163
TIM Counter Modulo Register Low (TMODL) . . . . . . . . . . . . . 163
TIM Channel 0 Status and Control Register (TSC0) . . . . . . . 164
TIM Channel 1 Status and Control Register (TSC1) . . . . . . . 164
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . . 168
TIM Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . . . . . . 168
TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . . 168
TIM Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . . . . . . 168
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
11-16
SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 181
Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . . 191
SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . . 194
SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . . 197
SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . . 199
Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . 203
SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . . 204
12-1
12-2
12-3
12-4
12-5
ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .208
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 212
ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .215
13-1
I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 218
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Figure
Title
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .220
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 221
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . . . 223
PTA7 Input Pull-up Enable Register (PTA7PUE) . . . . . . . . . . 223
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .224
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 225
Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .227
Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 228
Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . 230
Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .231
Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 232
Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
14-1
14-2
14-3
14-4
IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .237
IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 237
IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 239
Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .240
15-1
15-2
15-3
15-4
KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . 243
Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 246
Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 247
16-1
16-2
16-3
COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .252
COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .253
17-1
17-2
17-3
LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .257
Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .257
18-1
18-2
18-3
Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 261
Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 261
Break Status and Control Register (BRKSCR). . . . . . . . . . . . 263
Technical Data
22
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18-4
18-5
18-6
18-7
Title
Page
Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . . 264
Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . 264
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . 264
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . .266
Freescale Semiconductor, Inc...
19-1 RC vs. Frequency (5V @25°C) . . . . . . . . . . . . . . . . . . . . . . . 272
19-2 RC vs. Frequency (3V @25°C) . . . . . . . . . . . . . . . . . . . . . . . 275
19-3 Internal Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . 276
19-4 Typical Operating IDD (XTAL osc),
with All Modules Turned On (25 °C) . . . . . . . . . . . . . . . . . 276
19-5 Typical Wait Mode IDD (XTAL osc),
with All Modules Turned Off (25 °C) . . . . . . . . . . . . . . . . . 276
20-1
20-2
20-3
20-4
20-5
20-6
20-Pin PDIP (Case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
20-Pin SOIC (Case #751D) . . . . . . . . . . . . . . . . . . . . . . . . . .280
28-Pin PDIP (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . . 281
32-Pin SDIP (Case #1376) . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
32-Pin LQFP (Case #873A) . . . . . . . . . . . . . . . . . . . . . . . . . .283
MC68HC908JL8 — Rev. 2.0
MOTOROLA
Technical Data
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List of Figures
Technical Data
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MC68HC908JL8 — Rev. 2.0
List of Figures
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Freescale Semiconductor, Inc.
Technical Data – MC68HC908JL8
List of Tables
Freescale Semiconductor, Inc...
Table
Title
1-1
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2-1
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6-1
6-2
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7-1
7-2
7-3
Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
Monitor Mode Entry Requirements and Options. . . . . . . . . . . 120
Monitor Mode Vector Differences . . . . . . . . . . . . . . . . . . . . . .123
Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 123
READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 126
WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 126
IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 127
IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 127
READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . .128
RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 128
Summary of ROM-Resident Routines . . . . . . . . . . . . . . . . . . 131
PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
ERARNGE Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
LDRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MON_PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MON_ERARNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
ICP_LDRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
EE_WRITE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
EE_READ Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
10-1
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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Table
Title
10-2
10-3
Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .166
11-1
11-2
11-3
11-4
11-5
11-7
11-6
11-8
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .193
SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . 206
12-1
12-2
MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
13-1
13-2
13-3
13-4
13-5
Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . . 219
Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
15-1
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
17-1
Trip Voltage Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .268
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
DC Electrical Characteristics (5V) . . . . . . . . . . . . . . . . . . . . . 270
Control Timing (5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Oscillator Specifications (5V) . . . . . . . . . . . . . . . . . . . . . . . . . 272
DC Electrical Characteristics (3V) . . . . . . . . . . . . . . . . . . . . . 273
Control Timing (3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Oscillator Specifications (3V) . . . . . . . . . . . . . . . . . . . . . . . . . 275
Timer Interface Module Characteristics (5V and 3V) . . . . . . . 277
ADC Characteristics (5V and 3V). . . . . . . . . . . . . . . . . . . . . .277
Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
21-1
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Technical Data
26
Page
MC68HC908JL8 — Rev. 2.0
List of Tables
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Freescale Semiconductor, Inc.
Technical Data – MC68HC908JL8
Section 1. General Description
Freescale Semiconductor, Inc...
1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.6
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2 Introduction
The MC68HC908JL8 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
MC68HC908JL8 — Rev. 2.0
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General Description
1.3 Features
Freescale Semiconductor, Inc...
Features of the MC68HC908JL8 include the following:
•
High-performance M68HC08 architecture,
•
Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
•
Low-power design; fully static with stop and wait modes
•
Maximum internal bus frequency:
– 8-MHz at 5V operating voltage
– 4-MHz at 3V operating voltage
•
Oscillator options:
– Crystal or resonator
– RC oscillator
•
8,192 bytes user program FLASH memory with security1 feature
•
256 bytes of on-chip RAM
•
Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2)
with selectable input capture, output compare, and PWM
capability on each channel; external clock input option on TIM2
•
13-channel, 8-bit analog-to-digital converter (ADC)
•
Serial communications interface module (SCI)
•
26 general-purpose input/output (I/O) ports:
– 8 keyboard interrupt with internal pull-up
– 11 LED drivers (sink)
– 2 × 25mA open-drain I/O with pull-up
•
Resident routines for in-circuit programming and EEPROM
emulation
•
System protection features:
– Optional computer operating properly (COP) reset, driven by
internal RC oscillator
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Technical Data
28
MC68HC908JL8 — Rev. 2.0
General Description
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General Description
Features
– Optional low-voltage detection with reset and selectable trip
points for 3V and 5V operation
– Illegal opcode detection with reset
Freescale Semiconductor, Inc...
– Illegal address detection with reset
•
Master reset pin with internal pull-up and power-on reset
•
IRQ with schmitt-trigger input and programmable pull-up
•
20-pin dual in-line package (PDIP), 20-pin small outline integrated
package (SOIC), 28-pin PDIP, 28-pin SOIC, 32-pin shrink dual inline package (SDIP), and 32-pin low-profile quad flat pack (LQFP)
•
Specific features of the MC68HC908JL8 in 28-pin packages are:
– 23 general-purpose I/Os only
– 7 keyboard interrupt with internal pull-up
– 10 LED drivers (sink)
– 12-channel ADC
– Timer I/O pins on TIM1 only
•
Specific features of the MC68HC908JL8 in 20-pin packages are:
– 15 general-purpose I/Os only
– 1 keyboard interrupt with internal pull-up
– 4 LED drivers (sink)
– 10-channel ADC
– Timer I/O pins on TIM1 only
Features of the CPU08 include the following:
•
Enhanced HC05 programming model
•
Extensive loop control functions
•
16 addressing modes (eight more than the HC05)
•
16-bit index register and stack pointer
•
Memory-to-memory data transfers
•
Fast 8 × 8 multiply instruction
•
Fast 16/8 divide instruction
•
Binary-coded decimal (BCD) instructions
•
Optimization for controller applications
•
Efficient C language support
MC68HC908JL8 — Rev. 2.0
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General Description
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General Description
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908JL8.
INTERNAL BUS
USER FLASH — 8,192 BYTES
PORTA
CONTROL AND STATUS REGISTERS — 64 BYTES
PTA7/KBI7**‡
PTA6/KBI6**¥
PTA5/KBI5**‡
PTA4/KBI4**‡
PTA3/KBI3**‡
PTA2/KBI2**‡
PTA1/KBI1**‡
PTA0/KBI0**‡
PTB7/ADC7
PTB6/ADC6
PTB5/ADC5
PTB4/ADC4
PTB3/ADC3
PTB2/ADC2
PTB1/ADC1
PTB0/ADC0
KEYBOARD INTERRUPT
MODULE
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
DDRA
ARITHMETIC/LOGIC
UNIT (ALU)
2-CHANNEL TIMER INTERFACE
MODULE 1
2-CHANNEL TIMER INTERFACE
MODULE 2
MONITOR ROM — 959 BYTES
BREAK
MODULE
USER FLASH VECTORS — 36 BYTES
RC OSCILLATOR
INTERNAL OSCILLATOR
POWER-ON RESET
MODULE
* RST
SYSTEM INTEGRATION
MODULE
LOW-VOLTAGE INHIBIT
MODULE
* IRQ
EXTERNAL INTERRUPT
MODULE
VDD
POWER
VSS
ADC REFERENCE
COMPUTER OPERATING
PROPERLY MODULE
PORTD
OSC2/RCCLK
ADC12/T2CLK
SERIAL COMMUNICATIONS
INTERFACE MODULE
PTE
¥
CRYSTAL OSCILLATOR
DDRD
OSC1
DDRB
USER RAM — 256 BYTES
DDRE
Freescale Semiconductor, Inc...
CPU
REGISTERS
PORTB
M68HC08 CPU
PTD7/RxD**†‡
PTD6/TxD**†‡
PTD5/T1CH1
PTD4/T1CH0
PTD3/ADC8‡
PTD2/ADC9‡
PTD1/ADC10
PTD0/ADC11
#
##
#
##
PTE1/T2CH1
#
PTE0/T2CH0
* Pin contains integrated pull-up device.
** Pin contains programmable pull-up device.
† 25mA open-drain if output pin.
‡ LED direct sink pin.
¥ Shared pin: OSC2/RCCLK/PTA6/KBI6.
# Pins available on 32-pin packages only.
## Pins available on 28-pin and 32-pin packages only.
Figure 1-1. MC68HC908JL8 Block Diagram
Technical Data
30
MC68HC908JL8 — Rev. 2.0
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General Description
Pin Assignments
IRQ
ADC12/T2CLK
PTA7/KBI7
RST
PTA5/KBI5
30
29
28
27
26
25 PTD4/T1CH0
PTA0/KBI0
24 PTD5/T1CH1
PTD3/ADC8
PTA2/KBI2
5
20
PTB0/ADC0
6
19
PTB1/ADC1
7
18
PTB7/ADC7
PTB5/ADC5 9
PTB6/ADC6 8
PTD1/ADC10
17 PTB2/ADC2
PTB3/ADC3 16
PTA3/KBI3
15
21
PTD0/ADC11
4
14
VDD
PTB4/ADC4
PTA4/KBI4
13
22
12
3
PTE1/T2CH1
PTA1/KBI1
PTE0/T2CH0
PTD2/ADC9
11
23
PTD6/TxD
2
10
OSC2/RCCLK/PTA6/KBI6
PTD7/RxD
Freescale Semiconductor, Inc...
OSC1 1
31
32 VSS
1.5 Pin Assignments
Figure 1-2. 32-Pin LQFP Pin Assignment
IRQ
1
32
ADC12/T2CLK
PTA0/KBI0
2
31
PTA7/KBI7
VSS
3
30
RST
OSC1
4
29
PTA5/KBI5
OSC2/RCCLK/PTA6/KBI6
5
28
PTD4/T1CH0
PTA1/KBI1
6
27
PTD5/T1CH1
VDD
7
26
PTD2/ADC9
PTA2/KBI2
8
25
PTA4/KBI4
PTA3/KBI3
9
24
PTD3/ADC8
PTB7/ADC7
10
23
PTB0/ADC0
PTB6/ADC6
11
22
PTB1/ADC1
PTB5/ADC5
12
21
PTD1/ADC10
PTD7/RxD
13
20
PTB2/ADC2
PTD6/TxD
14
19
PTB3/ADC3
PTE0/T2CH0
15
18
PTD0/ADC11
PTE1/T2CH1
16
17
PTB4/ADC4
Figure 1-3. 32-Pin SDIP Pin Assignment
MC68HC908JL8 — Rev. 2.0
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General Description
IRQ
1
28
RST
PTA0/KBI0
2
27
PTA5/KBI5
VSS
3
26
PTD4/T1CH0
OSC1
4
25
PTD5/T1CH1
OSC2/RCCLK/PTA6/KBI6
5
24
PTD2/ADC9
PTA1/KBI1
6
23
PTA4/KBI4
VDD
7
22
PTD3/ADC8
PTA2/KBI2
8
21
PTB0/ADC0
PTA3/KBI3
9
20
PTB1/ADC1
PTB7/ADC7
10
19
PTD1/ADC10
PTB6/ADC6
11
18
PTB2/ADC2
PTB5/ADC5
12
17
PTB3/ADC3
PTD7/RxD
13
16
PTD0/ADC11
PTD6/TxD
14
15
PTB4/ADC4
Pins not available on 28-pin packages
PTE0/T2CH0
PTE1/T2CH1
ADC12/T2CLK
PTA7/KBI7
Internal pads are unconnected.
Set these unused port I/Os to output low.
Figure 1-4. 28-Pin PDIP/SOIC Pin Assignment
IRQ
1
20
RST
VSS
2
19
PTD4/T1CH0
OSC1
3
18
PTD5/T1CH1
PTA0/KBI0
PTD0/ADC11
OSC2/RCCLK/PTA6/KBI6
4
17
PTD2/ADC9
PTA1/KBI1
PTD1/ADC10
PTA2/KBI2
VDD
5
16
PTD3/ADC8
PTB7/ADC7
6
15
PTB0/ADC0
PTB6/ADC6
7
14
PTB1/ADC1
PTB5/ADC5
8
13
PTB2/ADC2
PTD7/RxD
9
12
PTB3/ADC3
PTD6/TxD
10
11
PTB4/ADC4
Pins not available on 20-pin packages
PTA3/KBI3
PTE0/T2CH0
PTA4/KBI4
PTE1/T2CH1
PTA5/KBI5
ADC12/T2CLK
PTA7/KBI7
Internal pads are unconnected.
Set these unused port I/Os to output low.
The 20-pin MC68HC908JL8 is designated MC68HC908JK8.
Figure 1-5. 20-Pin PDIP/SOIC Pin Assignment
Technical Data
32
MC68HC908JL8 — Rev. 2.0
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General Description
Pin Functions
1.6 Pin Functions
Description of the pin functions are provided in Table 1-1.
Table 1-1. Pin Functions
IN/OUT
VOLTAGE
LEVEL
In
5V or 3V
Out
0V
In/Out
VDD
External IRQ pin; with programmable internal pull-up and
schmitt trigger input.
In
VDD
Used for monitor mode entry.
In
VDD to VTST
Crystal or RC oscillator input.
In
VDD
OSC2: crystal oscillator output; inverted OSC1 signal.
Out
VDD
RCCLK: RC oscillator clock output.
Out
VDD
In/Out
VDD
ADC12: channel-12 input of ADC.
In
VSS to VDD
T2CLK: external input clock for TIM2.
In
VDD
In/Out
VDD
Each pin has programmable internal pull-up when configured
as input.
In
VDD
Pins as keyboard interrupts, KBI0–KBI7.
In
VDD
PTA0–PTA5 and PTA7 have LED direct sink capability.
Out
VSS
PTA6 as OSC2/RCCLK.
Out
VDD
In/Out
VDD
In
VSS to VDD
Freescale Semiconductor, Inc...
PIN NAME
PIN DESCRIPTION
VDD
Power supply.
VSS
Power supply ground.
RST
Reset input, active low;
with internal pull-up and schmitt trigger input.
IRQ
OSC1
OSC2/RCCLK
Pin as PTA6/KBI6 (see PTA0–PTA7).
ADC12/T2CLK
8-bit general purpose I/O port.
PTA0–PTA7
8-bit general purpose I/O port.
PTB0–PTB7
Pins as ADC input channels, ADC0–ADC7.
MC68HC908JL8 — Rev. 2.0
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General Description
Table 1-1. Pin Functions (Continued)
IN/OUT
VOLTAGE
LEVEL
8-bit general purpose I/O port;
with programmable internal pull-ups on PTD6–PTD7.
In/Out
VDD
PTD0–PTD3 as ADC input channels, ADC11–ADC8.
Input
VSS to VDD
PTD2–PTD3 and PTD6–PTD7 have LED direct sink
capability
Out
VSS
PTD4 as T1CH0 of TIM1.
In/Out
VDD
PTD5 as T1CH1 of TIM1.
In/Out
VDD
PTD6–PTD7 have configurable 25mA open-drain output.
Out
VSS
PTD6 as TxD of SCI.
Out
VDD
PTD7 as RxD of SCI.
In
VDD
2-bit general purpose I/O port.
In/Out
VDD
PTE0 as T2CH0 of TIM2.
In/Out
VDD
PTE1 as T2CH1 of TIM2.
In/Out
VDD
PIN NAME
PIN DESCRIPTION
Freescale Semiconductor, Inc...
PTD0–PTD7
PTE0–PTE1
NOTE:
Devices in 28-pin packages, the following pins are not available:
PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK.
Devices in 20-pin packages, the following pins are not available:
PTA0/KBI0–PTA5/KBI5, PTD0/ADC11, PTD1/ADC10,
PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK.
Technical Data
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MC68HC908JL8 — Rev. 2.0
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Technical Data – MC68HC908JL8
Section 2. Memory Map
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2 Introduction
The CPU08 can address 64-kbytes of memory space. The memory map,
shown in Figure 2-1, includes:
•
8,192 bytes of user FLASH memory
•
36 bytes of user-defined vectors
•
959 bytes of monitor ROM
MC68HC908JL8 — Rev. 2.0
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Memory Map
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Memory Map
$0000
↓
$003F
I/O REGISTERS
64 BYTES
$0040
↓
$005F
RESERVED
32 BYTES
$0060
↓
$015F
RAM
256 BYTES
$0160
↓
$DBFF
UNIMPLEMENTED
55,968 BYTES
$DC00
↓
$FBFF
FLASH MEMORY
8,192 BYTES
$FC00
↓
$FDFF
MONITOR ROM
512 BYTES
$FE00
BREAK STATUS REGISTER (BSR)
$FE01
RESET STATUS REGISTER (RSR)
$FE02
RESERVED
$FE03
BREAK FLAG CONTROL REGISTER (BFCR)
$FE04
INTERRUPT STATUS REGISTER 1 (INT1)
$FE05
INTERRUPT STATUS REGISTER 2 (INT2)
$FE06
INTERRUPT STATUS REGISTER 3 (INT3)
$FE07
RESERVED
$FE08
FLASH CONTROL REGISTER (FLCR)
$FE09
↓
$FF0B
RESERVED
$FE0C
BREAK ADDRESS HIGH REGISTER (BRKH)
$FE0D
BREAK ADDRESS LOW REGISTER (BRKL)
$FE0E
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0F
RESERVED
$FE10
↓
$FFCE
MONITOR ROM
447 BYTES
$FFCF
FLASH BLOCK PROTECT REGISTER (FLBPR)
$FFD0
MASK OPTION REGISTER (MOR)
$FFD1
↓
$FFDB
RESERVED
11 BYTES
$FFDC
↓
$FFFF
USER FLASH VECTORS
36 BYTES
Figure 2-1. Memory Map
Technical Data
36
MC68HC908JL8 — Rev. 2.0
Memory Map
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Memory Map
I/O Section
2.3 I/O Section
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Addresses $0000–$003F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have the
following addresses:
•
$FE00; Break Status Register, BSR
•
$FE01; Reset Status Register, RSR
•
$FE02; Reserved
•
$FE03; Break Flag Control Register, BFCR
•
$FE04; Interrupt Status Register 1, INT1
•
$FE05; Interrupt Status Register 2, INT2
•
$FE06; Interrupt Status Register 3, INT3
•
$FE07; Reserved
•
$FE08; FLASH Control Register, FLCR
•
$FE09; Reserved
•
$FE0A; Reserved
•
$FE0B; Reserved
•
$FE0C; Break Address Register High, BRKH
•
$FE0D; Break Address Register Low, BRKL
•
$FE0E; Break Status and Control Register, BRKSCR
•
$FE0F; Reserved
•
$FFCF; FLASH Block Protect Register, FLBPR (FLASH register)
•
$FFD0; Mask Option Register, MOR (FLASH register)
•
$FFFF; COP Control Register, COPCTL
2.4 Monitor ROM
The 959 bytes at addresses $FC00–$FDFF and $FE10–$FFCE are
reserved ROM addresses that contain the instructions for the monitor
functions. (See Section 9. Monitor ROM (MON).)
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Memory Map
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Memory Map
Addr.
Register Name
$0000
Read:
Port A Data Register
Write:
(PTA)
Reset:
$0001
Read:
Port B Data Register
Write:
(PTB)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTD2
PTD1
PTD0
Unaffected by reset
PTB7
PTB6
PTB5
PTB4
PTB3
Unaffected by reset
Freescale Semiconductor, Inc...
Read:
$0002
Unimplemented Write:
$0003
Read:
Port D Data Register
Write:
(PTD)
Reset:
PTD7
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
Read:
DDRA7
Data Direction Register A
$0004
Write:
(DDRA)
Reset:
0
Read:
DDRB7
Data Direction Register B
$0005
Write:
(DDRB)
Reset:
0
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
PTE1
PTE0
Read:
Unimplemented Write:
$0006
Read:
DDRD7
Data Direction Register D
$0007
Write:
(DDRD)
Reset:
0
$0008
Read:
Port E Data Register
Write:
(PTE)
Reset:
Unaffected by reset
Read:
$0009
Unimplemented Write:
U = Unaffected
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
Technical Data
38
MC68HC908JL8 — Rev. 2.0
Memory Map
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Memory Map
Monitor ROM
Addr.
$000A
Register Name
Read:
Port D Control Register
Write:
(PDCR)
Reset:
Bit 7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
SLOWD7 SLOWD6 PTDPU7
0
0
Bit 0
PTDPU6
0
0
DDRE1
DDRE0
0
0
Read:
Freescale Semiconductor, Inc...
$000B
Unimplemented Write:
Read:
Data Direction Register E
Write:
$000C
(DDRE)
Reset:
Read:
PTA7 Input Pull-up
PTAPUE7
Enable Register Write:
(PTA7PUE)
Reset:
0
$000E
$0015
$0016
0
0
0
0
0
0
0
0
0
0
0
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
Read:
$000F
↓
$0012
$0014
0
Read:
Port A Input Pull-up
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Enable Register Write:
(PTAPUE)
Reset:
0
0
0
0
0
0
0
0
$000D
$0013
0
Unimplemented Write:
Read:
LOOPS
SCI Control Register 1
Write:
(SCC1)
Reset:
0
Read:
SCI Control Register 2
Write:
(SCC2)
Reset:
Read:
SCI Control Register 3
Write:
(SCC3)
Reset:
R8
U
U
0
0
0
0
0
0
Read:
SCI Status Register 1
Write:
(SCS1)
Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
= Unimplemented
R
U = Unaffected
X = Indeterminate
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)
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Addr.
Register Name
$0017
Read:
SCI Status Register 2
Write:
(SCS2)
Reset:
Freescale Semiconductor, Inc...
$0018
$0019
$001A
$001B
Bit 7
Read:
SCI Data Register
Write:
(SCDR)
Reset:
Read:
SCI Baud Rate Register
Write:
(SCBR)
Reset:
Read:
Keyboard Status and
Control Register Write:
(KBSCR)
Reset:
Read:
Keyboard Interrupt
Enable Register Write:
(KBIER)
Reset:
6
5
4
3
2
1
Bit 0
BKF
RPF
0
0
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Unaffected by reset
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
IMASKK
MODEK
0
0
0
0
0
0
0
0
0
0
KEYF
0
ACKK
0
0
0
0
0
0
0
0
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
0
0
0
0
IRQF
0
IMASK
MODE
Read:
$001C
$001D
$001E
$001F
Unimplemented Write:
Read:
IRQ Status and Control
Register Write:
(INTSCR)
Reset:
ACK
0
Read:
IRQPUD
Configuration Register 2
† Write:
(CONFIG2)
Reset:
0
Read:
COPRS
Configuration Register 1
Write:
(CONFIG1)†
Reset:
0
0
0
0
0
0
0
0
R
R
LVIT1
LVIT0
R
R
STOP_
ICLKDIS
0
0
0*
0*
0
0
0
R
R
LVID
R
SSREC
STOP
COPD
0
0
0
0
0
0
0
† One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.
U = Unaffected
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)
Technical Data
40
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Monitor ROM
Addr.
$0020
Freescale Semiconductor, Inc...
$0021
$0022
$0023
$0024
$0025
Register Name
6
5
TOIE
TSTOP
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
Read:
TIM1 Status and Control
Register Write:
(T1SC)
Reset:
TOF
0
0
1
0
0
0
0
0
Read:
TIM1 Counter Register
High Write:
(T1CNTH)
Reset:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
0
0
0
Read:
TIM1 Counter Register
Low Write:
(T1CNTL)
Reset:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
1
1
1
1
1
1
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
Read:
TIM Counter Modulo
Register High Write:
(TMODH)
Reset:
Read:
TIM1 Counter Modulo
Register Low Write:
(T1MODL)
Reset:
Read:
TIM1 Channel 0 Status
and Control Register Write:
(T1SC0)
Reset:
Read:
TIM1 Channel 0
Register High Write:
(T1CH0H)
Reset:
$0026
Read:
TIM1 Channel 0
Register Low Write:
(T1CH0L)
Reset:
$0027
$0028
Bit 7
Read:
TIM1 Channel 1 Status
and Control Register Write:
(T1SC1)
Reset:
$0029
Read:
TIM1 Channel 1
Register High Write:
(T1CH1H)
Reset:
U = Unaffected
0
CH0F
0
TRST
Indeterminate after reset
Bit7
Bit6
Bit5
Bit4
Bit3
Indeterminate after reset
CH1F
0
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Indeterminate after reset
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
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Addr.
Register Name
Read:
TIM1 Channel 1
Register Low Write:
(T1CH1L)
Reset:
Freescale Semiconductor, Inc...
$002A
Bit 7
6
5
4
3
2
1
Bit 0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PS2
PS1
PS0
Indeterminate after reset
Read:
$002B
↓
$002F
Unimplemented Write:
TOF
$0030
Read:
TIM2 Status and Control
Register Write:
(T2SC)
Reset:
$0031
$0032
$0033
$0034
$0035
0
0
TOIE
TSTOP
0
0
1
0
0
0
0
0
Read:
TIM2 Counter Register
High Write:
(T2CNTH)
Reset:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
0
0
0
Read:
TIM2 Counter Register
Low Write:
(T2CNTL)
Reset:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
1
1
1
1
1
1
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
Read:
TIM2 Counter Modulo
Register High Write:
(T2MODH)
Reset:
Read:
TIM2 Counter Modulo
Register Low Write:
(T2MODL)
Reset:
Read:
TIM2 Channel 0 Status
and Control Register Write:
(T2SC0)
Reset:
$0036
$0037
Read:
TIM2 Channel 0
Register High Write:
(T2CH0H)
Reset:
Read:
TIM2 Channel 0
Register Low Write:
(T2CH0L)
Reset:
U = Unaffected
0
CH0F
0
TRST
Indeterminate after reset
Bit7
Bit6
Bit5
Bit4
Bit3
Indeterminate after reset
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)
Technical Data
42
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Monitor ROM
Addr.
$0038
Register Name
Read:
TIM2 Channel 1 Status
and Control Register Write:
(T2SC1)
Reset:
Read:
TIM2 Channel 1
Register High Write:
(T2CH1H)
Reset:
$0039
Freescale Semiconductor, Inc...
Bit 7
Read:
TIM2 Channel 1
Register Low Write:
(T2CH1L)
Reset:
$003A
CH1F
0
6
CH1IE
5
0
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
Indeterminate after reset
Bit7
Bit6
Bit5
Bit4
Bit3
Indeterminate after reset
Read:
$003B
$003C
Unimplemented Write:
Read:
ADC Status and Control
Register Write:
(ADSCR)
Reset:
Read:
ADC Data Register
Write:
(ADR)
Reset:
$003D
Read:
ADC Input Clock Register
$003E
Write:
(ADICLK)
Reset:
COCO
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Indeterminate after reset
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
ADIV2
ADIV1
ADIV0
0
0
R
R
Read:
$003F
$FE00
Unimplemented Write:
Read:
Break Status Register
Write:
(BSR)
Reset:
SBSW
See note
R
0
Note: Writing a logic 0 clears SBSW.
U = Unaffected
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)
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Addr.
$FE01
Register Name
Read:
Reset Status Register
Write:
(RSR)
POR:
Freescale Semiconductor, Inc...
Read:
$FE02
Reserved Write:
$FE03
Read:
Break Flag Control
Register Write:
(BFCR)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
BCFE
R
R
R
R
R
R
R
0
Read:
Interrupt Status Register 1
$FE04
Write:
(INT1)
Reset:
IF6
IF5
IF4
IF3
0
IF1
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
Interrupt Status Register 2
$FE05
Write:
(INT2)
Reset:
IF14
IF13
IF12
IF11
0
0
IF8
IF7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
Interrupt Status Register 3
$FE06
Write:
(INT3)
Reset:
0
0
0
0
0
0
0
IF15
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
0
0
0
0
HVEN
MASS
ERASE
PGM
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
0
0
0
= Unimplemented
R
Read:
$FE07
Reserved Write:
$FE08
Read:
FLASH Control Register
Write:
(FLCR)
Reset:
Read:
$FE09
↓
$FE0B
Reserved Write:
$FE0C
Read:
Break Address High
Register Write:
(BRKH)
Reset:
U = Unaffected
X = Indeterminate
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)
Technical Data
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Monitor ROM
Addr.
Register Name
Read:
Break Address low
Register Write:
(BRKL)
Reset:
$FE0D
Freescale Semiconductor, Inc...
Read:
Break Status and Control
$FE0E
Register Write:
(BRKSCR)
Reset:
$FFCF
$FFD0
Read:
FLASH Block Protect
Register Write:
(FLBPR)#
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
R
R
Unaffected by reset; $FF when blank
Read:
OSCSEL
Mask Option Register
Write:
(MOR)#
Reset:
R
R
R
R
R
Unaffected by reset; $FF when blank
# Non-volatile FLASH registers; write by programming.
$FFFF
Read:
COP Control Register
Write:
(COPCTL)
Reset:
U = Unaffected
Low byte of reset vector
Writing clears COP counter (any value)
Unaffected by reset
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)
MC68HC908JL8 — Rev. 2.0
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Memory Map
.
Table 2-1. Vector Addresses
Vector Priority
Lowest
INT Flag
Address
—
$FFD0
↓
$FFDD
Not Used
$FFDE
ADC Conversion Complete Vector (High)
$FFDF
ADC Conversion Complete Vector (Low)
$FFE0
Keyboard Interrupt Vector (High)
$FFE1
Keyboard Interrupt Vector (Low)
$FFE2
SCI Transmit Vector (High)
$FFE3
SCI Transmit Vector (Low)
$FFE4
SCI Receive Vector (High)
$FFE5
SCI Receive Vector (Low)
$FFE6
SCI Error Vector (High)
$FFE7
SCI Error Vector (Low)
IF15
Freescale Semiconductor, Inc...
IF14
IF13
IF12
IF11
IF10
↓
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
—
Highest
—
—
Vector
Not Used
$FFEC
TIM2 Overflow Vector (High)
$FFED
TIM2 Overflow Vector (Low)
$FFEE
TIM2 Channel 1 Vector (High)
$FFEF
TIM2 Channel 1 Vector (Low)
$FFF0
TIM2 Channel 0 Vector (High)
$FFF1
TIM2 Channel 0 Vector (Low)
$FFF2
TIM1 Overflow Vector (High)
$FFF3
TIM1 Overflow Vector (Low)
$FFF4
TIM1 Channel 1 Vector (High)
$FFF5
TIM1 Channel 1 Vector (Low)
$FFF6
TIM1 Channel 0 Vector (High)
$FFF7
TIM1 Channel 0 Vector (Low)
—
Not Used
$FFFA
IRQ Vector (High)
$FFFB
IRQ Vector (Low)
$FFFC
SWI Vector (High)
$FFFD
SWI Vector (Low)
$FFFE
Reset Vector (High)
$FFFF
Reset Vector (Low)
Technical Data
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Technical Data – MC68HC908JL8
Section 3. Random-Access Memory (RAM)
Freescale Semiconductor, Inc...
3.1 Contents
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2 Introduction
This section describes the 256 bytes of RAM.
3.3 Functional Description
Addresses $0060 through $015F are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64-Kbyte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 160 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can
access efficiently all page zero RAM locations. Page zero RAM,
therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE:
For M6805 compatibility, the H register is not stacked.
MC68HC908JL8 — Rev. 2.0
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Random-Access Memory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
Freescale Semiconductor, Inc...
NOTE:
Technical Data
48
MC68HC908JL8 — Rev. 2.0
Random-Access Memory (RAM)
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Technical Data – MC68HC908JL8
Section 4. FLASH Memory (FLASH)
Freescale Semiconductor, Inc...
4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.5
FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.6
FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.7
FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.8
FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.8.1
FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . .57
4.2 Introduction
This section describes the operation of the embedded FLASH memory.
The FLASH memory can be read, programmed, and erased from a
single external supply. The program and erase operations are enabled
through the use of an internal charge pump.
MC68HC908JL8 — Rev. 2.0
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FLASH Memory (FLASH)
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FLASH Memory (FLASH)
Addr.
$FE08
$FFCF
Register Name
Bit 7
6
5
4
0
0
0
0
0
0
0
BPR7
BPR6
BPR5
Read:
FLASH Control Register
Write:
(FLCR)
Reset:
Read:
FLASH Block Protect
Register Write:
(FLBPR)#
Reset:
3
2
1
Bit 0
HVEN
MASS
ERASE
PGM
0
0
0
0
0
BPR4
BPR3
BPR2
BPR1
BPR0
Unaffected by reset; $FF when blank
Freescale Semiconductor, Inc...
# Non-volatile FLASH register; write by programming.
= Unimplemented
Figure 4-1. FLASH I/O Register Summary
4.3 Functional Description
The FLASH memory consists of an array of 8,192 bytes for user memory
plus a block of 36 bytes for user interrupt vectors. An erased bit reads as
logic 1 and a programmed bit reads as a logic 0. The FLASH memory
page size is defined as 64 bytes, and is the minimum size that can be
erased in a page erase operation. Program and erase operations are
facilitated through control bits in FLASH control register (FLCR). The
address ranges for the FLASH memory are:
•
$DC00–$FBFF; user memory; 12,288 bytes
•
$FFDC–$FFFF; user interrupt vectors; 36 bytes
Programming tools are available from Motorola. Contact your local
Motorola representative for more information.
NOTE:
A security feature prevents viewing of the FLASH contents.1
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Technical Data
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MC68HC908JL8 — Rev. 2.0
FLASH Memory (FLASH)
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FLASH Memory (FLASH)
FLASH Control Register
4.4 FLASH Control Register
The FLASH control register (FCLR) controls FLASH program and erase
operations.
Address:
Read:
$FE08
Bit 7
6
5
4
0
0
0
0
3
2
1
Bit 0
HVEN
MASS
ERASE
PGM
0
0
0
0
Write:
Freescale Semiconductor, Inc...
Reset:
0
0
0
0
Figure 4-2. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or
page erase operation when the ERASE bit is set.
1 = Mass erase operation selected
0 = Page erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation not selected
PGM — Program Control Bit
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
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FLASH Memory (FLASH)
4.5 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page
consists of 64 consecutive bytes starting from addresses $XX00,
$XX40, $XX80 or $XXC0. The 36-byte user interrupt vectors area also
forms a page. Any page within the 8,192 bytes user memory area
($DC00–$FBFF) can be erased alone. The 36-byte user interrupt
vectors cannot be erased by the page erase operation because of
security reasons. Mass erase is required to erase this page.
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1. Set the ERASE bit and clear the MASS bit in the FLASH control
register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address within the page address
range desired.
4. Wait for a time, tnvs (10µs).
5. Set the HVEN bit.
6. Wait for a time terase (4ms).
7. Clear the ERASE bit.
8. Wait for a time, tnvh (5µs).
9. Clear the HVEN bit.
10. After time, trcv (1µs), the memory can be accessed in read mode
again.
NOTE:
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
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FLASH Memory (FLASH)
FLASH Mass Erase Operation
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory:
1. Set both the ERASE bit and the MASS bit in the FLASH control
register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the FLASH memory
address range.
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4. Wait for a time, tnvs (10µs).
5. Set the HVEN bit.
6. Wait for a time tmerase (4ms).
7. Clear the ERASE bit.
8. Wait for a time, tnvh1 (100µs).
9. Clear the HVEN bit.
10. After time, trcv (1µs), the memory can be accessed in read mode
again.
NOTE:
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
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FLASH Memory (FLASH)
4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 32 consecutive bytes starting from addresses $XX00,
$XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this
step-by-step procedure to program a row of FLASH memory:
(Figure 4-3 shows a flowchart of the programming algorithm.)
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1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of
the row to be programmed.
4. Wait for a time, tnvs (10µs).
5. Set the HVEN bit.
6. Wait for a time, tpgs (5µs).
7. Write data to the FLASH address to be programmed.
8. Wait for time, tprog (30µs).
9. Repeat steps 7 and 8 until all bytes within the row are programmed.
10. Clear the PGM bit.
11. Wait for time, tnvh (5µs).
12. Clear the HVEN bit.
13. After time, trcv (1µs), the memory can be accessed in read mode
again.
This program sequence is repeated throughout the memory until all data
is programmed.
NOTE:
The time between each FLASH address change (step 7 to step 7), or the
time between the last FLASH addressed programmed to clearing the
PGM bit (step 7 to step 10), must not exceed the maximum programming
time, tprog max.
NOTE:
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.
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FLASH Memory (FLASH)
FLASH Program Operation
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Algorithm for programming
a row (32 bytes) of FLASH memory
1
Set PGM bit
2
Read the FLASH block protect register
3
Write any data to any FLASH location
within the address range of the row to
be programmed
4
Wait for a time, tnvs
5
Set HVEN bit
6
Wait for a time, tpgs
7
8
Write data to the FLASH address
to be programmed
Wait for a time, tprog
Completed
programming
this row?
Y
N
NOTE:
The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming
time, tprog max.
10
Clear PGM bit
11
Wait for a time, tnvh
12
Clear HVEN bit
13
Wait for a time, trcv
This row program algorithm assumes the row/s
to be programmed are initially erased.
End of programming
Figure 4-3. FLASH Programming Flowchart
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FLASH Memory (FLASH)
4.8 FLASH Block Protection
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Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made to protect
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by use of a FLASH block
protect register (FLBPR). The FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends to the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either erase or program operations.
NOTE:
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit
When the FLBPR is program with all 0’s, the entire memory is protected
from being programmed and erased. When all the bits are erased
(all 1’s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of
memory, address ranges as shown in 4.8.1 FLASH Block Protect
Register. Once the FLBPR is programmed with a value other than $FF,
any erase or program of the FLBPR or the protected block of FLASH
memory is prohibited. The FLBPR itself can be erased or programmed
only with an external voltage, VTST, present on the IRQ pin. This voltage
also allows entry from reset into the monitor mode.
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FLASH Memory (FLASH)
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FLASH Memory (FLASH)
FLASH Block Protection
4.8.1 FLASH Block Protect Register
The FLASH block protect register (FLBPR) is implemented as a byte
within the FLASH memory, and therefore can only be written during a
programming sequence of the FLASH memory. The value in this register
determines the starting location of the protected range within the FLASH
memory.
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Address:
$FFCF
Bit 7
6
5
4
3
2
1
Bit 0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
Read:
Write:
Reset:
Unaffected by reset; $FF when blank
Non-volatile FLASH register; write by programming.
Figure 4-4. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Block Protect Bits
BPR[7:0] represent bits [13:6] of a 16-bit memory address. Bits
[15:14] are logic 1’s and bits [5:0] are logic 0’s.
16-bit memory address
Start address of FLASH block protect
1 1
0 0 0 0 0 0
BPR[7:0]
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be XX00, XX40, XX80,
or XXC0 (at page boundaries — 64 bytes) within the FLASH memory.
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FLASH Memory (FLASH)
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Examples of protect start address:
BPR[7:0]
Start of Address of Protect Range (1)
$00–$70
The entire FLASH memory is protected.
$71
(0111 0001)
$DC40 (1101 1100 0100 0000)
$72
(0111 0010)
$DC80 (1101 1100 1000 0000)
$73
(0111 0011)
$DCC0 (1101 1100 1100 0000)
and so on...
$FD
(1111 1101)
$FF40 (1111 1111 0100 0000)
$FE
(1111 1110)
$FF80 (1111 1111 1000 0000)
$FF
The entire FLASH memory is not protected.
NOTES:
1. The end address of the protected range is always $FFFF.
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Technical Data – MC68HC908JL8
Section 5. Configuration and Mask Option Registers
(CONFIG & MOR)
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5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.4
Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .61
5.5
Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .62
5.6
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Introduction
This section describes the configuration registers, CONFIG1 and
CONFIG2; and the mask option register (MOR).
The configuration registers enable or disable these options:
•
Computer operating properly module (COP)
•
COP timeout period (213 –24 or 218 –24 ICLK cycles)
•
Internal oscillator during stop mode
•
Low voltage inhibit (LVI) module
•
LVI module voltage trip point selection
•
STOP instruction
•
Stop mode recovery time (32 or 4096 ICLK cycles)
•
Pull-up on IRQ pin
The mask option register selects the oscillator option:
•
Crystal or RC
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Configuration and Mask Option
Addr.
$001E
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$001F
$FFD0
Register Name
Bit 7
Read:
IRQPUD
Configuration Register 2
Write:
(CONFIG2)†
Reset:
0
Read:
COPRS
Configuration Register 1
† Write:
(CONFIG1)
Reset:
0
Read:
OSCSEL
Mask Option Register
Write:
(MOR)#
Reset:
6
5
4
3
2
1
Bit 0
R
R
LVIT1
LVIT0
R
R
STOP_
ICLKDIS
0
0
0*
0*
0
0
0
R
R
LVID
R
SSREC
STOP
COPD
0
0
0
0
0
0
0
R
R
R
R
R
R
R
Unaffected by reset; $FF when blank
† One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.
# Non-volatile FLASH register; write by programming.
R
= Reserved
Figure 5-1. CONFIG Registers Summary
5.3 Functional Description
The configuration registers are used in the initialization of various
options. The configuration registers can be written once after each reset.
All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that
these registers be written immediately after reset. The configuration
registers are located at $001E and $001F. The configuration registers
may be read at anytime.
NOTE:
The options except LVIT[1:0] are one-time writable by the user after
each reset. The LVIT[1:0] bits are one-time writable by the user only after
each POR (power-on reset). The CONFIG registers are not in the
FLASH memory but are special registers containing one-time writable
latches after each reset. Upon a reset, the CONFIG registers default to
predetermined settings as shown in Figure 5-2 and Figure 5-3.
The mask option register (MOR) is used to select the oscillator option for
the MCU: crystal oscillator or RC oscillator. The MOR is implemented as
a byte in FLASH memory. Hence, writing to the MOR requires
programming the byte.
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Configuration and Mask Option Registers (CONFIG & MOR)
Configuration Register 1 (CONFIG1)
5.4 Configuration Register 1 (CONFIG1)
Address:
$001F
Bit 7
6
5
4
3
2
1
Bit 0
COPRS
R
R
LVID
R
SSREC
STOP
COPD
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
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R
= Reserved
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select Bit
COPRS selects the COP time-out period. Reset clears COPRS.
(See Section 16. Computer Operating Properly (COP).)
1 = COP timeout period is (213 – 24) ICLK cycles
0 = COP timeout period is (218 – 24) ICLK cycles
LVID — Low Voltage Inhibit Disable Bit
LVID disables the LVI module. Reset clears LVID.
(See Section 17. Low Voltage Inhibit (LVI).)
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
32 ICLK cycles instead of a 4096 ICLK cycle delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
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Configuration and Mask Option
COPD — COP Disable Bit
COPD disables the COP module. Reset clears COPD.
(See Section 16. Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
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5.5 Configuration Register 2 (CONFIG2)
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
IRQPUD
R
R
LVIT1
LVIT0
R
R
STOP_
ICLKDIS
Reset:
0
0
0
Not affected
Not affected
0
0
0
POR:
0
0
0
0
0
0
0
0
Read:
Write:
R
= Reserved
Figure 5-3. Configuration Register 2 (CONFIG2)
IRQPUD — IRQ Pin Pull-Up Disable Bit
IRQPUD disconnects the internal pull-up on the IRQ pin.
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ pin and VDD
LVIT1, LVIT0 — LVI Trip Voltage Selection Bits
Detail description of trip voltage selection is given in Section 17. Low
Voltage Inhibit (LVI).
STOP_ICLKDIS — Internal Oscillator Stop Mode Disable Bit
Setting STOP_ICLKDIS disables the internal oscillator during stop
mode. When this bit is cleared, the internal oscillator continues to
operate in stop mode. Reset clears this bit.
1 = Internal oscillator disabled during stop mode
0 = Internal oscillator enabled during stop mode
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Configuration and Mask Option Registers (CONFIG & MOR)
Mask Option Register (MOR)
5.6 Mask Option Register (MOR)
The mask option register (MOR) is implemented as a byte within the
FLASH memory, and therefore can only be written during a
programming sequence of the FLASH memory. This register is read
after a power-on reset to determine the type of oscillator selected.
(See Section 8. Oscillator (OSC).)
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Address:
$FFD0
Bit 7
6
5
4
3
2
1
Bit 0
OSCSEL
R
R
R
R
R
R
R
1
1
1
1
1
1
1
1
Read:
Write:
Erased:
Reset:
Unaffected by reset
Non-volatile FLASH register; write by programming.
R
= Reserved
Figure 5-4. Mask Option Register (MOR)
OSCSEL — Oscillator Select Bit
OSCSEL selects the oscillator type for the MCU. The erased or
unprogrammed state of this bit is logic 1, selecting the crystal
oscillator option. This bit is unaffected by reset.
1 = Crystal oscillator
0 = RC oscillator
Bits 6–0 — Should be left as logic 1’s.
NOTE:
When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is
used as OSC2; other functions such as PTA6/KBI6 will not be available.
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Configuration and Mask Option
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Technical Data – MC68HC908JL8
Section 6. Central Processor Unit (CPU)
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6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
6.4.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.4.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.4.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.4.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.7
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.8
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.9
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Motorola document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
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Central Processor Unit (CPU)
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6.3 Features
•
Object code fully upward-compatible with M68HC05 Family
•
16-bit stack pointer with stack manipulation instructions
•
16-bit index register with x-register manipulation instructions
•
8-MHz CPU internal bus frequency
•
64-Kbyte program/data memory space
•
16 addressing modes
•
Memory-to-memory data moves without using accumulator
•
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
•
Enhanced binary-coded decimal (BCD) data handling
•
Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64 Kbytes
•
Low-power stop and wait modes
6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
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Central Processor Unit (CPU)
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Central Processor Unit (CPU)
CPU Registers
7
0
ACCUMULATOR (A)
15
0
H
X
INDEX REGISTER (H:X)
0
15
STACK POINTER (SP)
0
15
PROGRAM COUNTER (PC)
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7
0
V 1 1 H I N Z C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 6-2. Accumulator (A)
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Central Processor Unit (CPU)
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
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The index register can serve also as a temporary data storage location.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Read:
Write:
Reset:
X = Indeterminate
Figure 6-3. Index Register (H:X)
6.4.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
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Central Processor Unit (CPU)
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Central Processor Unit (CPU)
CPU Registers
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 6-4. Stack Pointer (SP)
Freescale Semiconductor, Inc...
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
6.4.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
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6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
5
4
3
2
1
Bit 0
V
1
1
H
I
N
Z
C
X
1
1
X
1
X
X
X
Read:
Freescale Semiconductor, Inc...
Write:
Reset:
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction
uses the states of the H and C flags to determine the appropriate
correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
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Central Processor Unit (CPU)
CPU Registers
NOTE:
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
Freescale Semiconductor, Inc...
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting
bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
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6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Freescale Semiconductor, Inc...
Refer to the CPU08 Reference Manual (Motorola document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
6.6.1 Wait Mode
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
6.6.2 Stop Mode
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
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CPU During Break Interrupts
6.7 CPU During Break Interrupts
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If a break module is present on the MCU, the CPU starts a break
interrupt by:
•
Loading the instruction register with the SWI instruction
•
Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
6.9 Opcode Map
The opcode map is provided in Table 6-2.
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V H I N Z C
Freescale Semiconductor, Inc...
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
A ← (A) + (M) + (C)
Add with Carry
↕ ↕
IMM
DIR
EXT
IX2
– ↕ ↕ ↕
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
IMM
DIR
EXT
IX2
– ↕ ↕ ↕
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry
AIS #opr
Add Immediate Value (Signed) to SP
SP ← (SP) + (16 « M)
– – – – – – IMM
AIX #opr
Add Immediate Value (Signed) to H:X
H:X ← (H:X) + (16 « M)
– – – – – – IMM
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
A ← (A) + (M)
A ← (A) & (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
C
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
C
Clear Bit n in M
b0
PC ← (PC) + 2 + rel ? (C) = 0
Mn ← 0
A7
ii
2
AF
ii
2
2
3
4
4
3
2
4
5
ii
dd
hh ll
ee ff
ff
DIR
INH
INH
– – ↕ ↕ ↕
IX1
IX
SP1
38
48
58
68
78
9E68
dd
DIR
INH
INH
– – ↕ ↕ ↕
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
4
1
1
4
3
5
– – – – – – REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – –
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
↕
↕
Technical Data
74
ff
ee ff
2
3
4
4
3
2
4
5
A4
B4
C4
D4
E4
F4
9EE4
9ED4
b0
b7
2
3
4
4
3
2
4
5
IMM
DIR
EXT
IX2
–
IX1
IX
SP1
SP2
0 – – ↕ ↕
0
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
BCLR n, opr
↕ ↕
ff
ee ff
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary
ff
ee ff
ff
ff
ff
4
1
1
4
3
5
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Opcode Map
Effect on
CCR
Freescale Semiconductor, Inc...
V H I N Z C
Cycles
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? (Z) = 1
– – – – – – REL
27
rr
3
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
– – – – – – REL
90
rr
3
BGT opr
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 +rel ? (Z) | (N ⊕ V)=0 – – – – – – REL
92
rr
3
BHCC rel
Branch if Half Carry Bit Clear
PC ← (PC) + 2 + rel ? (H) = 0
– – – – – – REL
28
rr
3
BHCS rel
Branch if Half Carry Bit Set
PC ← (PC) + 2 + rel ? (H) = 1
– – – – – – REL
29
rr
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
– – – – – – REL
22
rr
3
BHS rel
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
– – – – – – REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
– – – – – – REL
2E
rr
3
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
93
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
BLE opr
Branch if Less Than or Equal To
(Signed Operands)
BLO rel
Branch if Lower (Same as BCS)
BLS rel
(A) & (M)
0 – – ↕ ↕
IMM
DIR
EXT
IX2
–
IX1
IX
SP1
SP2
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V)=1 – – – – – – REL
A5
B5
C5
D5
E5
F5
9EE5
9ED5
3
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
– – – – – – REL
23
rr
3
BLT opr
Branch if Less Than (Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 1
– – – – – – REL
91
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? (I) = 0
– – – – – – REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? (N) = 1
– – – – – – REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? (I) = 1
– – – – – – REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
– – – – – – REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? (N) = 0
– – – – – – REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel
– – – – – – REL
20
rr
3
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Table 6-1. Instruction Set Summary
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
– – – – – – REL
21
rr
3
PC ← (PC) + 3 + rel ? (Mn) = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – –
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
– – – – – – REL
AD
rr
4
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
Description
V H I N Z C
Freescale Semiconductor, Inc...
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
PC ← (PC) + 2
Branch Never
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
BSR rel
PC ← (PC) + 3 + rel ? (Mn) = 0
Set Bit n in M
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
Compare and Branch if Equal
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
DIR
IMM
PC ← (PC) + 3 + rel ? (A) – (M) = $00
IMM
PC ← (PC) + 3 + rel ? (X) – (M) = $00
– – – – – –
IX1+
PC ← (PC) + 3 + rel ? (A) – (M) = $00
IX+
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
SP1
31
41
51
61
71
9E61
Cycles
Operand
Effect on
CCR
Opcode
Operation
Address
Mode
Source
Form
CLC
Clear Carry Bit
C←0
– – – – – 0 INH
98
1
CLI
Clear Interrupt Mask
I←0
– – 0 – – – INH
9A
2
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
0 – – 0 1 – INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Clear
Technical Data
76
dd
ff
ff
3
1
1
1
3
2
4
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Opcode Map
V H I N Z C
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CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Compare A with M
(A) – (M)
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (One’s Complement)
CPHX #opr
CPHX opr
Compare H:X with M
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M
DAA
Decimal Adjust A
(H:X) – (M:M + 1)
(X) – (M)
(A)10
DBNZ opr,rel
DBNZA rel
Decrement and Branch if Not Zero
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
DIV
Divide
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
↕
IMM
DIR
EXT
IX2
– – ↕ ↕ ↕
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
ii
dd
hh ll
ee ff
ff
DIR
INH
INH
1
IX1
IX
SP1
33
43
53
63
73
9E63
dd
0 – – ↕ ↕
– – ↕ ↕ ↕
↕
IMM
DIR
EXT
IX2
– – ↕ ↕ ↕
IX1
IX
SP1
SP2
U – – ↕ ↕ ↕ INH
A ← (A)–1 or M ← (M)–1 or X ← (X)–1
DIR
PC ← (PC) + 3 + rel ? (result) ≠ 0
INH
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
– – – – – – INH
IX1
PC ← (PC) + 3 + rel ? (result) ≠ 0
IX
PC ← (PC) + 2 + rel ? (result) ≠ 0
SP1
PC ← (PC) + 4 + rel ? (result) ≠ 0
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A ← (H:A)/(X)
H ← Remainder
↕
– – ↕ ↕
DIR
INH
INH
–
IX1
IX
SP1
– – – – ↕ ↕ INH
MC68HC908JL8 — Rev. 2.0
MOTOROLA
IMM
DIR
↕
ff
ee ff
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary
2
3
4
4
3
2
4
5
ff
4
1
1
4
3
5
65
75
ii ii+1
dd
3
4
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
ff
ff
ee ff
72
2
3B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff rr
rr
ff rr
3A
4A
5A
6A
7A
9E6A
dd
52
ff
ff
5
3
3
5
4
6
4
1
1
4
3
5
7
Technical Data
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V H I N Z C
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EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Load A from M
LDHX #opr
LDHX opr
Load H:X from M
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
– – ↕ ↕
DIR
INH
INH
–
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
ff
ee ff
ff
ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
PC ← Jump Address
dd
hh ll
ee ff
ff
2
3
4
3
2
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
DIR
EXT
– – – – – – IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ii jj
dd
3
4
2
3
4
4
3
2
4
5
A ← (M)
0 – – ↕ ↕
H:X ← (M:M + 1)
X ← (M)
C
0
b7
b0
IMM
DIR
EXT
IX2
–
IX1
IX
SP1
SP2
IMM
DIR
45
55
0 – – ↕ ↕
–
0 – – ↕ ↕
IMM
DIR
EXT
IX2
–
IX1
IX
SP1
SP2
AE
BE
CE
DE
EE
FE
9EEE
9EDE
ii
dd
hh ll
ee ff
ff
DIR
INH
INH
– – ↕ ↕ ↕
IX1
IX
SP1
38
48
58
68
78
9E68
dd
↕
Technical Data
78
ii
dd
hh ll
ee ff
ff
BC
CC
DC
EC
FC
Load X from M
Logical Shift Left
(Same as ASL)
↕
A8
B8
C8
D8
E8
F8
9EE8
9ED8
DIR
EXT
– – – – – – IX2
IX1
IX
Jump
Jump to Subroutine
0 – – ↕ ↕
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
Increment
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
A ← (A ⊕ M)
Exclusive OR M with A
IMM
DIR
EXT
IX2
–
IX1
IX
SP1
SP2
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary
ff
ee ff
ff
ff
4
1
1
4
3
5
MC68HC908JL8 — Rev. 2.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Opcode Map
V H I N Z C
Freescale Semiconductor, Inc...
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
0
Logical Shift Right
C
b7
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
MUL
Unsigned multiply
↕
b0
(M)Destination ← (M)Source
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
DIR
INH
INH
– – 0 ↕ ↕
IX1
IX
SP1
0 – – ↕ ↕
DD
DIX+
–
IMD
IX+D
– 0 – – – 0 INH
DIR
INH
INH
– – ↕ ↕ ↕
IX1
IX
SP1
34
44
54
64
74
9E64
4E
5E
6E
7E
dd
ff
4
1
1
4
3
5
dd dd
dd
ii dd
dd
5
4
4
4
ff
42
30
40
50
60
70
9E60
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary
5
dd
4
1
1
4
3
5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
Negate (Two’s Complement)
NOP
No Operation
None
– – – – – – INH
9D
1
NSA
Nibble Swap A
A ← (A[3:0]:A[7:4])
– – – – – – INH
62
3
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
↕
IMM
DIR
EXT
IX2
–
IX1
IX
SP1
SP2
ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
PSHA
Push A onto Stack
Push (A); SP ← (SP) – 1
– – – – – – INH
87
2
PSHH
Push H onto Stack
Push (H); SP ← (SP) – 1
– – – – – – INH
8B
2
PSHX
Push X onto Stack
Push (X); SP ← (SP) – 1
– – – – – – INH
89
2
PULA
Pull A from Stack
SP ← (SP + 1); Pull (A)
– – – – – – INH
86
2
PULH
Pull H from Stack
SP ← (SP + 1); Pull (H)
– – – – – – INH
8A
2
PULX
Pull X from Stack
SP ← (SP + 1); Pull (X)
– – – – – – INH
88
2
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
A ← (A) | (M)
Rotate Left through Carry
0 – – ↕ ↕
↕
C
b7
b0
DIR
INH
INH
– – ↕ ↕ ↕
IX1
IX
SP1
MC68HC908JL8 — Rev. 2.0
MOTOROLA
AA
BA
CA
DA
EA
FA
9EEA
9EDA
39
49
59
69
79
9E69
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
Technical Data
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
79
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Freescale Semiconductor, Inc...
V H I N Z C
36
46
56
66
76
9E66
dd
4
1
1
4
3
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry
RSP
Reset Stack Pointer
SP ← $FF
– – – – – – INH
9C
1
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕ ↕ INH
80
7
RTS
Return from Subroutine
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
– – – – – – INH
81
4
C
b7
↕
b0
DIR
INH
INH
– – ↕ ↕ ↕
IX1
IX
SP1
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary
IMM
DIR
EXT
IX2
– – ↕ ↕ ↕
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
ff
ff
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry
SEC
Set Carry Bit
C←1
– – – – – 1 INH
99
1
SEI
Set Interrupt Mask
I←1
– – 1 – – – INH
9B
2
A ← (A) – (M) – (C)
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
STHX opr
Store H:X in M
STOP
Enable IRQ Pin; Stop Oscillator
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (A)
(M:M + 1) ← (H:X)
I ← 0; Stop Oscillator
M ← (X)
↕
DIR
EXT
IX2
– IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
– DIR
35
– – 0 – – – INH
8E
0 – – ↕ ↕
0 – – ↕ ↕
0 – – ↕ ↕
Technical Data
80
DIR
EXT
IX2
– IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
dd
4
1
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
MC68HC908JL8 — Rev. 2.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Opcode Map
V H I N Z C
Freescale Semiconductor, Inc...
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
A ← (A) – (M)
Subtract
↕
IMM
DIR
EXT
IX2
– – ↕ ↕ ↕
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
ff
ee ff
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary
2
3
4
4
3
2
4
5
SWI
Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
Transfer A to CCR
CCR ← (A)
↕ ↕ ↕ ↕ ↕ ↕ INH
84
2
TAX
Transfer A to X
X ← (A)
– – – – – – INH
97
1
TPA
Transfer CCR to A
A ← (CCR)
– – – – – – INH
85
1
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero
TSX
Transfer SP to H:X
TXA
Transfer X to A
TXS
Transfer H:X to SP
(A) – $00 or (X) – $00 or (M) – $00
– – 1 – – – INH
83
9
0 – – ↕ ↕
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
H:X ← (SP) + 1
– – – – – – INH
95
2
A ← (X)
– – – – – – INH
9F
1
(SP) ← (H:X) – 1
– – – – – – INH
94
2
MC68HC908JL8 — Rev. 2.0
MOTOROLA
DIR
INH
INH
–
IX1
IX
SP1
Technical Data
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
81
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Freescale Semiconductor, Inc...
V H I N Z C
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
⊕
()
–( )
#
«
←
?
:
↕
—
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
Technical Data
82
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary
MC68HC908JL8 — Rev. 2.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
MOTOROLA
MC68HC908JL8 — Rev. 2.0
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
0
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
1
3
BRA
2 REL
3
BRN
2 REL
3
BHI
2 REL
3
BLS
2 REL
3
BCC
2 REL
3
BCS
2 REL
3
BNE
2 REL
3
BEQ
2 REL
3
BHCC
2 REL
3
BHCS
2 REL
3
BPL
2 REL
3
BMI
2 REL
3
BMC
2 REL
3
BMS
2 REL
3
BIL
2 REL
3
BIH
2 REL
2
Branch
REL
4
INH
1
NEGX
1 INH
4
CBEQX
3 IMM
7
DIV
1 INH
1
COMX
1 INH
1
LSRX
1 INH
4
LDHX
2 DIR
1
RORX
1 INH
1
ASRX
1 INH
1
LSLX
1 INH
1
ROLX
1 INH
1
DECX
1 INH
3
DBNZX
2 INH
1
INCX
1 INH
1
TSTX
1 INH
4
MOV
2 DIX+
1
CLRX
1 INH
5
4
NEG
2
IX1
5
CBEQ
3 IX1+
3
NSA
1 INH
4
COM
2 IX1
4
LSR
2 IX1
3
CPHX
3 IMM
4
ROR
2 IX1
4
ASR
2 IX1
4
LSL
2 IX1
4
ROL
2 IX1
4
DEC
2 IX1
5
DBNZ
3 IX1
4
INC
2 IX1
3
TST
2 IX1
4
MOV
3 IMD
3
CLR
2 IX1
6
7
IX
9
7
3
RTI
BGE
1 INH 2 REL
4
3
RTS
BLT
1 INH 2 REL
3
BGT
2 REL
9
3
SWI
BLE
1 INH 2 REL
2
2
TAP
TXS
1 INH 1 INH
1
2
TPA
TSX
1 INH 1 INH
2
PULA
1 INH
2
1
PSHA
TAX
1 INH 1 INH
2
1
PULX
CLC
1 INH 1 INH
2
1
PSHX
SEC
1 INH 1 INH
2
2
PULH
CLI
1 INH 1 INH
2
2
PSHH
SEI
1 INH 1 INH
1
1
CLRH
RSP
1 INH 1 INH
1
NOP
1 INH
1
STOP
*
1 INH
1
1
WAIT
TXA
1 INH 1 INH
8
Control
INH
INH
B
DIR
0
LSB
MSB
3
SUB
2 DIR
3
CMP
2 DIR
3
SBC
2 DIR
3
CPX
2 DIR
3
AND
2 DIR
3
BIT
2 DIR
3
LDA
2 DIR
3
STA
2 DIR
3
EOR
2 DIR
3
ADC
2 DIR
3
ORA
2 DIR
3
ADD
2 DIR
2
JMP
2 DIR
4
4
BSR
JSR
2 REL 2 DIR
2
3
LDX
LDX
2 IMM 2 DIR
2
3
AIX
STX
2 IMM 2 DIR
2
SUB
2 IMM
2
CMP
2 IMM
2
SBC
2 IMM
2
CPX
2 IMM
2
AND
2 IMM
2
BIT
2 IMM
2
LDA
2 IMM
2
AIS
2 IMM
2
EOR
2 IMM
2
ADC
2 IMM
2
ORA
2 IMM
2
ADD
2 IMM
A
IMM
Low Byte of Opcode in Hexadecimal
5
3
NEG
NEG
3 SP1 1 IX
6
4
CBEQ
CBEQ
4 SP1 2 IX+
2
DAA
1 INH
5
3
COM
COM
3 SP1 1 IX
5
3
LSR
LSR
3 SP1 1 IX
4
CPHX
2 DIR
5
3
ROR
ROR
3 SP1 1 IX
5
3
ASR
ASR
3 SP1 1 IX
5
3
LSL
LSL
3 SP1 1 IX
5
3
ROL
ROL
3 SP1 1 IX
5
3
DEC
DEC
3 SP1 1 IX
6
4
DBNZ
DBNZ
4 SP1 2 IX
5
3
INC
INC
3 SP1 1 IX
4
2
TST
TST
3 SP1 1 IX
4
MOV
2 IX+D
4
2
CLR
CLR
3 SP1 1 IX
9E6
SP1
Table 6-2. Opcode Map
Read-Modify-Write
INH
IX1
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
4
1
NEG
NEGA
2 DIR 1 INH
5
4
CBEQ CBEQA
3 DIR 3 IMM
5
MUL
1 INH
4
1
COM
COMA
2 DIR 1 INH
4
1
LSR
LSRA
2 DIR 1 INH
4
3
STHX
LDHX
2 DIR 3 IMM
4
1
ROR
RORA
2 DIR 1 INH
4
1
ASR
ASRA
2 DIR 1 INH
4
1
LSL
LSLA
2 DIR 1 INH
4
1
ROL
ROLA
2 DIR 1 INH
4
1
DEC
DECA
2 DIR 1 INH
5
3
DBNZ DBNZA
3 DIR 2 INH
4
1
INC
INCA
2 DIR 1 INH
3
1
TST
TSTA
2 DIR 1 INH
5
MOV
3 DD
3
1
CLR
CLRA
2 DIR 1 INH
3
DIR
INH Inherent
REL Relative
IMM Immediate
IX
Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct
IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
LSB
MSB
Bit Manipulation
DIR
DIR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
E
3
SUB
2 IX1
3
CMP
2 IX1
3
SBC
2 IX1
3
CPX
2 IX1
3
AND
2 IX1
3
BIT
2 IX1
3
LDA
2 IX1
3
STA
2 IX1
3
EOR
2 IX1
3
ADC
2 IX1
3
ORA
2 IX1
3
ADD
2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
SP2 2 IX1
5
3
STX
STX
SP2 2 IX1
5
SUB
SP2
5
CMP
SP2
5
SBC
SP2
5
CPX
SP2
5
AND
SP2
5
BIT
SP2
5
LDA
SP2
5
STA
SP2
5
EOR
SP2
5
ADC
SP2
5
ORA
SP2
5
ADD
SP2
9ED
IX1
F
IX
2
SUB
1 IX
2
CMP
1 IX
2
SBC
1 IX
2
CPX
1 IX
2
AND
1 IX
2
BIT
1 IX
2
LDA
1 IX
2
STA
1 IX
2
EOR
1 IX
2
ADC
1 IX
2
ORA
1 IX
2
ADD
1 IX
2
JMP
1 IX
4
JSR
1 IX
4
2
LDX
LDX
3 SP1 1 IX
4
2
STX
STX
3 SP1 1 IX
4
SUB
3 SP1
4
CMP
3 SP1
4
SBC
3 SP1
4
CPX
3 SP1
4
AND
3 SP1
4
BIT
3 SP1
4
LDA
3 SP1
4
STA
3 SP1
4
EOR
3 SP1
4
ADC
3 SP1
4
ORA
3 SP1
4
ADD
3 SP1
9EE
SP1
High Byte of Opcode in Hexadecimal
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
SUB
IX2
4
CMP
IX2
4
SBC
IX2
4
CPX
IX2
4
AND
IX2
4
BIT
IX2
4
LDA
IX2
4
STA
IX2
4
EOR
IX2
4
ADC
IX2
4
ORA
IX2
4
ADD
IX2
4
JMP
IX2
6
JSR
IX2
4
LDX
IX2
4
STX
IX2
D
Register/Memory
IX2
SP2
5
Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
0
4
SUB
3 EXT
4
CMP
3 EXT
4
SBC
3 EXT
4
CPX
3 EXT
4
AND
3 EXT
4
BIT
3 EXT
4
LDA
3 EXT
4
STA
3 EXT
4
EOR
3 EXT
4
ADC
3 EXT
4
ORA
3 EXT
4
ADD
3 EXT
3
JMP
3 EXT
5
JSR
3 EXT
4
LDX
3 EXT
4
STX
3 EXT
C
EXT
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Opcode Map
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Technical Data
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Technical Data – MC68HC908JL8
Section 7. System Integration Module (SIM)
7.1 Contents
Freescale Semiconductor, Inc...
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 89
7.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.3.2
Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . . 89
7.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 89
7.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 90
7.4.1
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 91
7.4.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.4.2.2
Computer Operating Properly (COP) Reset. . . . . . . . . . . 93
7.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.4.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . 94
7.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 94
7.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . 94
7.5.3
SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .95
7.6
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.6.2
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.6.2.1
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 100
7.6.2.2
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . 100
7.6.2.3
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . 101
7.6.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.6.4
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
7.6.5
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 102
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7.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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7.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.8.1
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . 105
7.8.2
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . 106
7.8.3
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 108
7.2 Introduction
This section describes the system integration module (SIM), which
supports up to 24 external and/or internal interrupts. Together with the
CPU, the SIM controls all MCU activities. A block diagram of the SIM is
shown in Figure 7-1. Figure 7-2 is a summary of the SIM I/O registers.
The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
•
Master reset control, including power-on reset (POR) and COP
timeout
•
Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
•
CPU enable/disable timing
•
Modular architecture expandable to 128 interrupt sources
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System Integration Module (SIM)
Introduction
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO OSCILLATOR)
SIM
COUNTER
COP CLOCK
ICLK (FROM OSCILLATOR)
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OSCOUT (FROM OSCILLATOR)
÷2
VDD
INTERNAL
PULL-UP
RESET
PIN LOGIC
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
MASTER
RESET
CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
USB RESET (FROM USB MODULE)
RESET
INTERRUPT SOURCES
INTERRUPT CONTROL
AND PRIORITY DECODE
CPU INTERFACE
Figure 7-1. SIM Block Diagram
Table 7-1. Signal Name Conventions
Signal Name
ICLK
OSCOUT
Description
Internal oscillator clock
The XTAL or RC frequency divided by two. This signal is again divided by two in the
SIM to generate the internal bus clocks. (Bus clock = OSCOUT ÷ 2)
IAB
Internal address bus
IDB
Internal data bus
PORRST
Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal
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Addr.
Register Name
Bit 7
6
5
4
3
2
R
R
R
R
R
R
Read:
$FE00
Break Status Register
Write:
(BSR)
Reset:
1
Bit 0
SBSW
R
NOTE
0
0
0
0
0
0
0
0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
BCFE
R
R
R
R
R
R
R
IF6
IF5
IF4
IF3
0
IF1
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
IF14
IF13
IF12
IF11
0
0
IF8
IF7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IF15
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Note: Writing a logic 0 clears SBSW.
Read:
Freescale Semiconductor, Inc...
$FE01
Reset Status Register
Write:
(RSR)
POR:
Read:
$FE02
Reserved Write:
Reset:
$FE03
Read:
Break Flag Control
Register Write:
(BFCR)
Reset:
Read:
$FE04
Interrupt Status Register 1
Write:
(INT1)
Reset:
Read:
$FE05
Interrupt Status Register 2
Write:
(INT2)
Reset:
Read:
$FE06
Interrupt Status Register 3
Write:
(INT3)
Reset:
0
= Unimplemented
R
= Reserved
Figure 7-2. SIM I/O Register Summary
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System Integration Module (SIM)
SIM Bus Clock Control and Generation
7.3 SIM Bus Clock Control and Generation
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The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 7-3.
From
OSCILLATOR
ICLK
From
OSCILLATOR
OSCOUT
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
OSCOUT is OSC frequency divided by 2
SIM
Figure 7-3. SIM Clock Signals
7.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
divided by four.
7.3.2 Clock Start-Up from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 ICLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this
entire period. The IBUS clocks start upon completion of the timeout.
7.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
ICLK to clock the SIM counter. The CPU and peripheral clocks do not
become active until after the stop delay time-out. This time-out is
selectable as 4096 or 32 ICLK cycles. (See 7.7.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
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7.4 Reset and System Initialization
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The MCU has these reset sources:
•
Power-on reset module (POR)
•
External reset pin (RST)
•
Computer operating properly module (COP)
•
Low-voltage inhibit module (LVI)
•
Illegal opcode
•
Illegal address
All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in
Monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 7.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the reset status register (RSR). (See 7.8 SIM Registers.)
7.4.1 External Pin Reset
The RST pin circuits include an internal pull-up device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the reset
status register (RSR) is set as long as RST is held low for a minimum of
67 ICLK cycles, assuming that the POR was not the source of the reset.
See Table 7-2 for details. Figure 7-4 shows the relative timing.
Table 7-2. PIN Bit Set Timing
Reset Type
Number of Cycles Required to Set PIN
POR
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
ICLK
RST
IAB
PC
VECT H VECT L
Figure 7-4. External Reset Timing
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Reset and System Initialization
7.4.2 Active Resets from Internal Sources
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All internal reset sources actively pull the RST pin low for 32 ICLK cycles
to allow resetting of external peripherals. The internal reset signal IRST
continues to be asserted for an additional 32 cycles (Figure 7-5). An
internal reset can be caused by an illegal address, illegal opcode, COP
time-out, or POR. (See Figure 7-6 . Sources of Internal Reset.) Note
that for POR resets, the SIM cycles through 4096 ICLK cycles during
which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 7-5.
IRST
RST
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
ICLK
IAB
VECTOR HIGH
Figure 7-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
INTERNAL RESET
LVI
Figure 7-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
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7.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and memories
are released from reset to allow the reset vector sequence to occur.
Freescale Semiconductor, Inc...
At power-on, the following events occur:
•
A POR pulse is generated.
•
The internal reset signal is asserted.
•
The SIM enables OSCOUT.
•
Internal clocks to the CPU and modules are held inactive for 4096
ICLK cycles to allow stabilization of the oscillator.
•
The RST pin is driven low during the oscillator stabilization time.
•
The POR bit of the reset status register (RSR) is set and all other
bits in the register are cleared.
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
ICLK
OSCOUT
RST
$FFFE
IAB
$FFFF
Figure 7-7. POR Recovery
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Reset and System Initialization
7.4.2.2 Computer Operating Properly (COP) Reset
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An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (RSR). The SIM actively pulls down the RST pin for
all internal reset sources.
To prevent a COP module time-out, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12 through
5 of the SIM counter. The SIM counter output, which occurs at least
every (212 – 24) ICLK cycles, drives the COP counter. The COP should
be serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first time-out.
The COP module is disabled if the RST pin or the IRQ pin is held at VTST
while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, VTST on the
RST pin disables the COP module.
7.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the reset status register (RSR) and
causes a reset.
If the stop enable bit, STOP, in the mask option register is logic zero, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
7.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a
reset. The SIM actively pulls down the RST pin for all internal reset
sources.
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7.4.2.5 Low-Voltage Inhibit (LVI) Reset
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The low-voltage inhibit module (LVI) asserts its output to the SIM when
the VDD voltage falls to the LVI trip voltage VTRIP. The LVI bit in the reset
status register (RSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 ICLK cycles. Sixty-four ICLK
cycles later, the CPU and memories are released from reset to allow the
reset vector sequence to occur. The SIM actively pulls down the RST pin
for all internal reset sources.
7.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter uses 12 stages for counting, followed by a 13th stage that
triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of ICLK.
7.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the oscillator to drive the bus clock state machine.
7.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic one, then the stop recovery is
reduced from the normal delay of 4096 ICLK cycles down to 32 ICLK
cycles. This is ideal for applications using canned oscillators that do not
require long start-up times from stop mode. External crystal applications
should use the full stop recovery time, that is, with SSREC cleared in the
configuration register 1 (CONFIG1).
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Exception Control
7.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 7.7.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. (See
7.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
Freescale Semiconductor, Inc...
7.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
•
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
•
Reset
•
Break interrupts
7.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. Figure 7-8 flow charts the handling of
system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
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FROM RESET
BREAK
INTERRUPT?
I BIT
SET?
YES
NO
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YES
I BIT SET?
NO
IRQ
INTERRUPT?
YES
NO
TIMER 1
INTERRUPT?
YES
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
(As many interrupts as exist on chip)
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS.
NO
EXECUTE INSTRUCTION.
Figure 7-8. Interrupt Processing
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Exception Control
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 7-9 shows interrupt entry timing.
Figure 7-10 shows interrupt recovery timing.
MODULE
INTERRUPT
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I BIT
IAB
IDB
DUMMY
SP
DUMMY
SP – 1
SP – 2
PC – 1[7:0] PC – 1[15:8]
SP – 3
X
SP – 4
A
VECT H
CCR
VECT L
V DATA H
START ADDR
V DATA L
OPCODE
R/W
Figure 7-9. Interrupt Entry
MODULE
INTERRUPT
I BIT
IAB
SP – 4
IDB
SP – 3
CCR
SP – 2
A
SP – 1
X
SP
PC
PC – 1[15:8] PC – 1[7:0]
PC + 1
OPCODE
OPERAND
R/W
Figure 7-10. Interrupt Recovery
7.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
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If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 7-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
CLI
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LDA #$FF
INT1
BACKGROUND ROUTINE
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 7-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
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Exception Control
7.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
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7.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 7-3 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 7-3. Interrupt Sources
Flag
Mask1(1)
INT Flag
Vector Address
Reset
—
—
—
$FFFE–$FFFF
SWI Instruction
—
—
—
$FFFC–$FFFD
IRQ Pin
IRQF
IMASK
IF1
$FFFA–$FFFB
Timer 1 Channel 0 Interrupt
CH0F
CH0IE
IF3
$FFF6–$FFF7
Timer 1 Channel 1 Interrupt
CH1F
CH1IE
IF4
$FFF4–$FFF5
TOF
TOIE
IF5
$FFF2–$FFF3
Timer 2 Channel 0 Interrupt
CH0F
CH0IE
IF6
$FFF0–$FFF1
Timer 2 Channel 1 Interrupt
CH1F
CH1IE
IF7
$FFEE–$FFEF
Timer 2 Overflow Interrupt
TOF
TOIE
IF8
$FFEC–$FFED
SCI Error
OR
NF
FE
PE
ORIE
NEIE
FEIE
PEIE
IF11
$FFE6–$FFE7
SCI Receive
SCRF
IDLE
SCRIE
ILIE
IF12
$FFE4–$FFE5
SCI Transmit
SCTE
TC
SCTIE
TCIE
IF13
$FFE2–$FFE3
Keyboard Interrupt
KEYF
IMASKK
IF14
$FFE0–$FFE1
ADC Conversion Complete Interrupt
COCO
AIEN
IF15
$FFDE–$FFDF
Priority
Highest
Source
Timer 1 Overflow Interrupt
Lowest
NOTES:
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
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7.6.2.1 Interrupt Status Register 1
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Address:
$FE04
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF6
IF5
IF4
IF3
0
IF1
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 7-12. Interrupt Status Register 1 (INT1)
IF1, IF3 to IF6 — Interrupt Flags
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, and 3 — Always read 0
7.6.2.2 Interrupt Status Register 2
Address:
$FE05
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF14
IF13
IF12
IF11
0
0
IF8
IF7
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 7-13. Interrupt Status Register 2 (INT2)
IF7, IF8, IF11 to F14 — Interrupt Flags
This flag indicates the presence of interrupt requests from the sources
shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 2 and 3 — Always read 0
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7.6.2.3 Interrupt Status Register 3
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Address:
$FE06
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
IF15
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 7-14. Interrupt Status Register 3 (INT3)
IF15 — Interrupt Flags
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 1 to 7 — Always read 0
7.6.3 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
7.6.4 Break Interrupts
The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. (See
Section 18. Break Module (BREAK).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
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7.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
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Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
7.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-powerconsumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
below. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
7.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 7-15 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
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Low-Power Modes
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic zero, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
WAIT ADDR
IAB
PREVIOUS DATA
IDB
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WAIT ADDR + 1
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 7-15. Wait Mode Entry Timing
Figure 7-16 and Figure 7-17 show the timing for WAIT recovery.
IAB
$6E0B
$A6
IDB
$A6
$6E0C
$A6
$01
$00FF
$0B
$00FE
$00FD
$00FC
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 7-16. Wait Recovery from Interrupt or Break
32
Cycles
IAB
IDB
32
Cycles
$6E0B
$A6
$A6
RST VCT H
RST VCTL
$A6
RST
ICLK
Figure 7-17. Wait Recovery from Internal Reset
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7.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
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The SIM disables the oscillator signals (OSCOUT) in stop mode,
stopping the CPU and peripherals. Stop recovery time is selectable
using the SSREC bit in the configuration register 1 (CONFIG1). If
SSREC is set, stop recovery is reduced from the normal delay of 4096
ICLK cycles down to 32. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode.
NOTE:
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the break status register (BSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 7-18 shows stop mode entry timing.
NOTE:
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 7-18. Stop Mode Entry Timing
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SIM Registers
STOP RECOVERY PERIOD
ICLK
INT/BREAK
IAB
STOP + 2
STOP +1
STOP + 2
SP
SP – 1
SP – 2
SP – 3
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Figure 7-19. Stop Mode Recovery from Interrupt or Break
7.8 SIM Registers
The SIM has three memory mapped registers.
•
Break Status Register (BSR)
•
Reset Status Register (RSR)
•
Break Flag Control Register (BFCR)
7.8.1 Break Status Register (BSR)
The break status register contains a flag to indicate that a break caused
an exit from stop or wait mode.
Address:
$FE00
Bit 7
6
5
4
3
2
R
R
R
R
R
R
Read:
1
Bit 0
SBSW
Write:
Note(1)
Reset:
0
R
= Reserved
R
1. Writing a logic zero clears SBSW.
Figure 7-20. Break Status Register (BSR)
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SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
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SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing zero to the SBSW bit clears
it.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE
EQU
5
LOBYTE
EQU
6
;
If not SBSW, do RTI
BRCLR
SBSW,BSR, RETURN
; See if wait mode or stop mode was exited
; by break.
TST
LOBYTE,SP
; If RETURNLO is not zero,
BNE
DOLO
; then just decrement low byte.
DEC
HIBYTE,SP
; Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN
PULH
RTI
; Restore H register.
7.8.2 Reset Status Register (RSR)
This register contains six flags that show the source of the last reset.
Clear the SIM reset status register by reading it. A power-on reset sets
the POR bit and clears all other bits in the register.
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SIM Registers
Address:
Read:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
Write:
POR:
= Unimplemented
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Figure 7-21. Reset Status Register (RSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of RSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of RSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of RSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of RSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of RSR
MODRST — Monitor Mode Entry Module Reset bit
1 = Last reset caused by monitor mode entry when vector locations
$FFFE and $FFFF are $FF after POR while IRQ = VDD
0 = POR or read of RSR
LVI — Low Voltage Inhibit Reset bit
1 = Last reset caused by LVI circuit
0 = POR or read of RSR
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7.8.3 Break Flag Control Register (BFCR)
The break control register contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
Read:
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Write:
Reset:
0
R
= Reserved
Figure 7-22. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
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Section 8. Oscillator (OSC)
8.1 Contents
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8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.3
Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.3.1
XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.3.2
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.4
Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.5.1
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . 114
8.5.2
Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6) . 115
8.5.3
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . 115
8.5.4
XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . 115
8.5.5
RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . 115
8.5.6
Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . 115
8.5.7
Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.5.8
Internal Oscillator Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . 116
8.6
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
8.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.7
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . 116
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Oscillator (OSC)
8.2 Introduction
The oscillator module provides the reference clocks for the MCU system
and bus. Two oscillators are running on the device:
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Selectable oscillator — for bus clock
•
Crystal oscillator (XTAL) — built-in oscillator that requires an
external crystal or ceramic-resonator. This option also allows an
external clock that can be driven directly into OSC1.
•
RC oscillator (RC) — built-in oscillator that requires an external
resistor-capacitor connection only.
The selected oscillator is used to drive the bus clock, the SIM, and other
modules on the MCU. The oscillator type is selected by programming a
bit FLASH memory. The RC and crystal oscillator cannot run
concurrently; one is disabled while the other is selected; because the RC
and XTAL circuits share the same OSC1 pin.
Non-selectable oscillator — for COP
•
Internal oscillator — built-in RC oscillator that requires no external
components.
This internal oscillator is used to drive the computer operating properly
(COP) module and the SIM. The internal oscillator runs continuously
after a POR or reset, and is always available.
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Oscillator (OSC)
Oscillator Selection
8.3 Oscillator Selection
The oscillator type is selected by programming a bit in a FLASH memory
location; the mask option register (MOR), at $FFD0.
(See 5.6 Mask Option Register (MOR).)
NOTE:
On the ROM device, the oscillator is selected by a ROM-mask layer at
factory.
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Address:
$FFD0
Bit 7
6
5
4
3
2
1
Bit 0
OSCSEL
R
R
R
R
R
R
R
1
1
1
1
1
1
1
1
Read:
Write:
Erased:
Reset:
Unaffected by reset
Non-volatile FLASH register; write by programming.
R
= Reserved
Figure 8-1. Mask Option Register (MOR)
OSCSEL — Oscillator Select Bit
OSCSEL selects the oscillator type for the MCU. The erased or
unprogrammed state of this bit is logic 1, selecting the crystal
oscillator option. This bit is unaffected by reset.
1 = Crystal oscillator
0 = RC oscillator
Bits 6–0 — Should be left as logic 1’s.
NOTE:
When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is
used as OSC2; other functions such as PTA6/KBI6 will not be available.
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Oscillator (OSC)
8.3.1 XTAL Oscillator
The XTAL oscillator circuit is designed for use with an external crystal or
ceramic resonator to provide accurate clock source.
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In its typical configuration, the XTAL oscillator is connected in a Pierce
oscillator configuration, as shown in Figure 8-2. This figure shows only
the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five
components:
•
Crystal, X1
•
Fixed capacitor, C1
•
Tuning capacitor, C2 (can also be a fixed capacitor)
•
Feedback resistor, RB
•
Series resistor, RS (optional)
To SIM
From SIM
2OSCOUT
XTALCLK
To SIM
OSCOUT
÷2
SIMOSCEN
MCU
OSC1
RB
OSC2
R S*
*RS can be zero (shorted) when used with higher-frequency crystals.
Refer to manufacturer’s data.
X1
See Section 19. for component value requirements.
C1
C2
Figure 8-2. XTAL Oscillator External Connections
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Oscillator (OSC)
Oscillator Selection
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.
8.3.2 RC Oscillator
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The RC oscillator circuit is designed for use with external resistor and
capacitor to provide a clock source with tolerance less than 10%.
In its typical configuration, the RC oscillator requires two external
components, one R and one C. Component values should have a
tolerance of 1% or less, to obtain a clock source with less than 10%
tolerance. The oscillator configuration uses two components:
•
CEXT
•
REXT
From SIM
To SIM
To SIM
2OSCOUT
SIMOSCEN
EN
EXT-RC
OSCILLATOR
OSCOUT
RCCLK
÷2
0
1
PTA6
I/O
PTA6
PTA6EN
MCU
OSC1
VDD
REXT
RCCLK/PTA6 (OSC2)
CEXT
See Section 19. for component value requirements.
Figure 8-3. RC Oscillator External Connections
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Oscillator (OSC)
8.4 Internal Oscillator
The internal oscillator clock (ICLK) is a free running 50-kHz clock that
requires no external components. It is used as the reference clock input
to the computer operating properly (COP) module and the SIM.
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The internal oscillator by default is always available and is free running
after POR or reset. It can be stopped in stop mode by setting the
STOP_ICLKDIS bit before executing the STOP instruction.
Figure 8-4 shows the logical representation of components of the
internal oscillator circuitry.
From SIM
To SIM and COP
SIMOSCEN
ICLK
CONFIG2
STOP_ICLKDIS
EN
INTERNAL
OSCILLATOR
Figure 8-4. Internal Oscillator
NOTE:
The internal oscillator is a free running oscillator and is available after
each POR or reset. It is turned-off in stop mode by setting the
STOP_ICLKDIS bit in CONFIG2 (see 5.5 Configuration Register 2
(CONFIG2)).
8.5 I/O Signals
The following paragraphs describe the oscillator I/O signals.
8.5.1 Crystal Amplifier Input Pin (OSC1)
OSC1 pin is an input to the crystal oscillator amplifier or the input to the
RC oscillator circuit.
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I/O Signals
8.5.2 Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6)
For the XTAL oscillator, OSC2 pin is the output of the crystal oscillator
inverting amplifier.
Freescale Semiconductor, Inc...
For the RC oscillator, OSC2 pin can be configured as a general purpose
I/O pin PTA6, or the output of the RC oscillator, RCCLK.
Oscillator
OSC2 pin function
XTAL
Inverting OSC1
RC
Controlled by PTA6EN bit in PTAPUE ($000D)
PTA6EN = 0: RCCLK output
PTA6EN = 1: PTA6/KBI6
8.5.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables/disables the XTAL oscillator circuit or the RC-oscillator.
8.5.4 XTAL Oscillator Clock (XTALCLK)
XTALCLK is the XTAL oscillator output signal. It runs at the full speed of
the crystal (fXCLK) and comes directly from the crystal oscillator circuit.
Figure 8-2 shows only the logical relation of XTALCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
XTALCLK is unknown and may depend on the crystal and other external
factors. Also, the frequency and amplitude of XTALCLK can be unstable
at start-up.
8.5.5 RC Oscillator Clock (RCCLK)
RCCLK is the RC oscillator output signal. Its frequency is directly
proportional to the time constant of the external R and C. Figure 8-3
shows only the logical relation of RCCLK to OSC1 and may not
represent the actual circuitry.
8.5.6 Oscillator Out 2 (2OSCOUT)
2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal
is driven to the SIM module.
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Oscillator (OSC)
8.5.7 Oscillator Out (OSCOUT)
The frequency of this signal is equal to half of the 2OSCOUT, this signal
is driven to the SIM for generation of the bus clocks used by the CPU
and other modules on the MCU. OSCOUT will be divided again in the
SIM and results in the internal bus frequency being one fourth of the
XTALCLK or RCCLK frequency.
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8.5.8 Internal Oscillator Clock (ICLK)
ICLK is the internal oscillator output signal (typically 50-kHz), for the
COP module and the SIM. Its frequency depends on the VDD voltage.
(See Section 19. Electrical Specifications for ICLK parameters.)
8.6 Low Power Modes
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
8.6.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. OSCOUT,
2OSCOUT, and ICLK continues to drive to the SIM module.
8.6.2 Stop Mode
The STOP instruction disables the XTALCLK or the RCCLK output,
hence, OSCOUT and 2OSCOUT are disabled.
The STOP instruction also turns off the ICLK input to the COP module if
the STOP_ICLKDIS bit is set in configuration register 2 (CONFIG2).
After reset, the STOP_ICLKDIS bit is clear by default and ICLK is
enabled during stop mode.
8.7 Oscillator During Break Mode
The OSCOUT, 2OSCOUT, and ICLK clocks continue to be driven out
when the device enters the break state.
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Technical Data – MC68HC908JL8
Section 9. Monitor ROM (MON)
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9.1 Contents
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.4.1
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.4.2
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.4.3
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9.4.4
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.4.5
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
9.4.6
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.5
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.6
ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
9.6.1
PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.6.2
ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.6.3
LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.6.4
MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.6.5
MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.6.6
MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
9.6.7
EE_WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
9.6.8
EE_READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.2 Introduction
This section describes the monitor ROM (MON) and the monitor mode
entry methods. The monitor ROM allows complete testing of the MCU
through a single-wire interface with a host computer. This mode is also
used for programming and erasing of FLASH memory in the MCU.
Monitor mode entry can be achieved without use of the higher test
voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank,
thus reducing the hardware requirements for in-circuit programming.
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9.3 Features
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Features of the monitor ROM include the following:
•
Normal user-mode pin functionality
•
One pin dedicated to serial communication between monitor ROM
and host computer
•
Standard mark/space non-return-to-zero (NRZ) communication
with host computer
•
Execution of code in RAM or FLASH
•
FLASH memory security feature1
•
FLASH memory programming interface
•
959 bytes monitor ROM code size
•
Monitor mode entry without high voltage, VTST, if reset vector is
blank ($FFFE and $FFFF contain $FF)
•
Standard monitor mode entry if high voltage, VTST, is applied to
IRQ
•
Resident routines for FLASH programming and EEPROM
emulation
9.4 Functional Description
The monitor ROM receives and executes commands from a host
computer. Figure 9-1 shows a example circuit used to enter monitor
mode and communicate with a host computer via a standard RS-232
interface.
Simple monitor commands can access any memory address. In monitor
mode, the MCU can execute host-computer code in RAM while most
MCU pins retain normal operating mode functions. All communication
between the host computer and the MCU is through the PTB0 pin. A
level-shifting and multiplexing interface is required between PTB0 and
the host computer. PTB0 is used in a wired-OR configuration and
requires a pull-up resistor.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
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Monitor ROM (MON)
Functional Description
RST
0.1 µF
HC908JL8
VDD
VDD
VDD
EXT OSC (50% DUTY)
0.1 µF
VSS
EXT OSC CONNECTION TO OSC1, WITH OSC2
UNCONNECTED, CAN REPLACE XTAL CIRCUIT.
9.8304MHz
OSC1
10M
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OSC1
20 pF
OSC2
20 pF
MAX232
1
1 µF
+
3
4
1 µF
C1+
VDD
VCC
C1–
GND
C2+
V+
16
+
XTAL CIRCUIT
1 µF
15
+
1 µF
A
VTST
2
VDD
+
5 C2–
V–
6
1 µF
7
10
3
8
9
5
B
VDD
10 k
10 k
74HC125
5
6
DB9
2
(SEE NOTE 1)
IRQ
8.5 V
+
SW1
1k
2
74HC125
3
PTB0
4
VDD
VDD
1
10 k
10 k
C
PTB1
SW2
PTB3
(SEE NOTE 2)
NOTES:
1. Monitor mode entry method:
SW1: Position A — High voltage entry (VTST)
Bus clock depends on SW2.
SW1: Position B — Reset vector must be blank ($FFFE = $FFFF = $FF)
Bus clock = OSC1 ÷ 4.
2. Affects high voltage entry to monitor mode only (SW1 at position A):
SW2: Position C — Bus clock = OSC1 ÷ 4
SW2: Position D — Bus clock = OSC1 ÷ 2
5. See Table 19-4 for VTST voltage level requirements.
D
10 k
PTB2
10 k
Figure 9-1. Monitor Mode Circuit
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9.4.1 Entering Monitor Mode
Table 9-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR.
Communication at 9600 baud will be established provided one of the
following sets of conditions is met:
1. If IRQ = VTST:
– PTB3 = low
2. If IRQ = VTST:
– Clock on OSC1 is 9.8304MHz
– PTB3 = high
3. If $FFFE and $FFFF are blank (contain $FF):
– Clock on OSC1 is 9.8304MHz
– IRQ = VDD
VTST(2)
X
0
0
VTST(1)
X
1
0
1
VDD
BLANK
(contain
$FF)
X
X
X
1
9.8304MHz
2.4576MHz
VDD
NOT
BLANK
X
X
X
X
X
OSC1 ÷ 4
PTB0
$FFFE
and
$FFFF
PTB1
IRQ
PTB2
Table 9-1. Monitor Mode Entry Requirements and Options
PTB3
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– Clock on OSC1 is 4.9125MHz
OSC1 Clock(1)
Bus
Frequency
Comments
1
1
4.9152MHz
2.4576MHz
1
9.8304MHz
2.4576MHz
High voltage entry to
monitor mode.
9600 baud communication
on PTB0. COP disabled.
Blank reset vector (lowvoltage) entry to monitor
mode.
9600 baud communication
on PTB0. COP disabled.
Enters User mode.
NOTES:
1. RC oscillator cannot be used for monitor mode; must use either external oscillator or XTAL oscillator circuit.
2. See Table 19-4 for VTST voltage level requirements.
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Monitor ROM (MON)
Functional Description
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If VTST is applied to IRQ and PTB3 is low upon monitor mode entry
(Table 9-1 condition set 1), the bus frequency is a divide-by-two of the
clock input to OSC1. If PTB3 is high with VTST applied to IRQ upon
monitor mode entry (Table 9-1 condition set 2), the bus frequency is a
divide-by-four of the clock input to OSC1. Holding the PTB3 pin low
when entering monitor mode causes a bypass of a divide-by-two stage
at the oscillator only if VTST is applied to IRQ. In this event, the OSCOUT
frequency is equal to the 2OSCOUT frequency, and OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Entering monitor mode with VTST on IRQ, the COP is disabled as long
as VTST is applied to either IRQ or RST. (See Section 7. System
Integration Module (SIM) for more information on modes of operation.)
If entering monitor mode without high voltage on IRQ and reset vector
being blank ($FFFE and $FFFF) (Table 9-1 condition set 3, where
applied voltage is VDD), then all port B pin requirements and conditions,
including the PTB3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ or the RST.
Figure 9-2. shows a simplified diagram of the monitor mode entry when
the reset vector is blank and IRQ = VDD. An OSC1 frequency of
9.8304MHz is required for a baud rate of 9600.
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POR RESET
IS VECTOR
BLANK?
NO
NORMAL USER
MODE
YES
MONITOR MODE
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EXECUTE
MONITOR
CODE
POR
TRIGGERED?
NO
YES
Figure 9-2. Low-Voltage Monitor Mode Entry Flowchart
Enter monitor mode with the pin configuration shown above by pulling
RST low and then high. The rising edge of RST latches monitor mode.
Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU waits for the host to send eight security
bytes. (See 9.5 Security.) After the security bytes, the MCU sends a
break signal (10 consecutive logic zeros) to the host, indicating that it is
ready to receive a command. The break signal also provides a timing
reference to allow the host to determine the necessary baud rate.
In monitor mode, the MCU uses different vectors for reset, SWI, and
break interrupt. The alternate vectors are in the $FE page instead of the
$FF page and allow code execution from the internal monitor firmware
instead of user code.
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Monitor ROM (MON)
Functional Description
Table 9-2 is a summary of the vector differences between user mode
and monitor mode.
Table 9-2. Monitor Mode Vector Differences
Functions
COP
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User
Enabled
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
Disabled(1)
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
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Modes
Notes:
1. If the high voltage (VTST) is removed from the IRQ pin or the RST pin, the SIM asserts
its COP enable output. The COP is a mask option enabled or disabled by the COPD bit
in the configuration register.
When the host computer has completed downloading code into the MCU
RAM, the host then sends a RUN command, which executes an RTI,
which sends control to the address on the stack pointer.
9.4.2 Baud Rate
The communication baud rate is dependant on oscillator frequency. The
state of PTB3 also affects baud rate if entry to monitor mode is by
IRQ = VTST. When PTB3 is high, the divide by ratio is 1024. If the PTB3
pin is at logic zero upon entry into monitor mode, the divide by ratio is
512.
Table 9-3. Monitor Baud Rate Selection
Monitor Mode
Entry By:
IRQ = VTST
Blank reset vector,
IRQ = VDD
OSC1 Clock
Frequency
PTB3
Baud Rate
4.9152 MHz
0
9600 bps
9.8304 MHz
1
9600 bps
4.9152 MHz
1
4800 bps
9.8304 MHz
X
9600 bps
4.9152 MHz
X
4800 bps
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9.4.3 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. (See Figure 9-3 and Figure 9-4.)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
STOP
BIT
BIT 7
NEXT
START
BIT
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Figure 9-3. Monitor Data Format
$A5
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BREAK
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
STOP
BIT
NEXT
START
BIT
NEXT
START
BIT
Figure 9-4. Sample Monitor Waveforms
The data transmit and receive rate can be anywhere from 4800 baud to
28.8k-baud. Transmit and receive baud rates must be identical.
9.4.4 Echoing
As shown in Figure 9-5, the monitor ROM immediately echoes each
received byte back to the PTB0 pin for error checking.
SENT TO
MONITOR
READ
READ
ADDR. HIGH ADDR. HIGH
ADDR. LOW
ECHO
ADDR. LOW
DATA
RESULT
Figure 9-5. Read Transaction
Any result of a command appears after the echo of the last byte of the
command.
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Functional Description
9.4.5 Break Signal
A start bit followed by nine low bits is a break signal. (See Figure 9-6.)
When the monitor receives a break signal, it drives the PTB0 pin high for
the duration of two bits before echoing the break signal.
MISSING STOP BIT
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TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 9-6. Break Transaction
9.4.6 Commands
The monitor ROM uses the following commands:
•
READ (read memory)
•
WRITE (write memory)
•
IREAD (indexed read)
•
IWRITE (indexed write)
•
READSP (read stack pointer)
•
RUN (run user program)
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Table 9-4. READ (Read Memory) Command
Description
Read byte from memory
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of specified address
Opcode
$4A
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Command Sequence
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
Table 9-5. WRITE (Write Memory) Command
Description
Write byte to memory
Operand
Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data Returned
None
Opcode
$49
Command Sequence
SENT TO
MONITOR
WRITE
WRITE
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
DATA
ECHO
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Functional Description
Table 9-6. IREAD (Indexed Read) Command
Description
Read next 2 bytes in memory from last address accessed
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of next two addresses
Opcode
$1A
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Command Sequence
SENT TO
MONITOR
IREAD
IREAD
DATA
DATA
RESULT
ECHO
Table 9-7. IWRITE (Indexed Write) Command
Description
Write to last address accessed + 1
Operand
Specifies single data byte
Data Returned
None
Opcode
$19
Command Sequence
SENT TO
MONITOR
IWRITE
IWRITE
DATA
DATA
ECHO
NOTE:
A sequence of IREAD or IWRITE commands can sequentially access a
block of memory over the full 64-Kbyte memory map.
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Table 9-8. READSP (Read Stack Pointer) Command
Description
Reads stack pointer
Operand
None
Data Returned
Returns stack pointer in high byte:low byte order
Opcode
$0C
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Command Sequence
SENT TO
MONITOR
READSP
READSP
SP HIGH
SP LOW
RESULT
ECHO
Table 9-9. RUN (Run User Program) Command
Description
Executes RTI instruction
Operand
None
Data Returned
None
Opcode
$28
Command Sequence
SENT TO
MONITOR
RUN
RUN
ECHO
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Security
9.5 Security
A security feature discourages unauthorized reading of FLASH locations
while in monitor mode. The host can bypass the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain userdefined data.
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NOTE:
Do not leave locations $FFF6–$FFFD blank. For security reasons,
program locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PTB0. If the received
bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code
from FLASH. Security remains bypassed until a power-on reset occurs.
If the reset was not a power-on reset, security remains bypassed and
security code entry is not required. (See Figure 9-7.)
VDD
4096 + 32 ICLK CYCLES
RST
COMMAND
BYTE 8
BYTE 2
BYTE 1
24 BUS CYCLES
FROM HOST
PTB0
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
4
1
COMMAND ECHO
2
BREAK
1
BYTE 8 ECHO
1
BYTE 2 ECHO
FROM MCU
4
BYTE 1 ECHO
1
Figure 9-7. Monitor Mode Entry Timing
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Upon power-on reset, if the received bytes of the security code do not
match the data at locations $FFF6–$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading a
FLASH location returns an invalid value and trying to execute code from
FLASH causes an illegal address reset. After receiving the eight security
bytes from the host, the MCU transmits a break character, signifying that
it is ready to receive a command.
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NOTE:
The MCU does not transmit a break character until after the host sends
the eight security bytes.
To determine whether the security code entered is correct, check to see
if bit 6 of RAM address $40 is set. If it is, then the correct security code
has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on
reset and brought up in monitor mode to attempt another entry. After
failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal
RAM. The mass erase operation clears the security code locations so
that all eight security bytes become $FF (blank).
9.6 ROM-Resident Routines
Eight routines stored in the monitor ROM area (thus ROM-resident) are
provided for FLASH memory manipulation. Six of the eight routines are
intended to simplify FLASH program, erase, and load operations. The
other two routines are intended to simplify the use of the FLASH memory
as EEPROM. Table 9-10 shows a summary of the ROM-resident
routines.
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ROM-Resident Routines
Table 9-10. Summary of ROM-Resident Routines
Routine Name
Call
Address
Stack Used(1)
(bytes)
PRGRNGE
Program a range of locations
$FC06
15
ERARNGE
Erase a page or the entire array
$FCBE
9
Loads data from a range of locations
$FF30
9
MON_PRGRNGE
Program a range of locations in monitor
mode
$FF28
17
MON_ERARNGE
Erase a page or the entire array in
monitor mode
$FF2C
11
Loads data from a range of locations in
monitor mode
$FF24
11
EE_WRITE
Emulated EEPROM write. Data size
ranges from 2 to 15 bytes at a time.
$FD3F
24
EE_READ
Emulated EEPROM read. Data size
ranges from 2 to 15 bytes at a time.
$FDD0
16
LDRNGE
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Routine Description
MON_LDRNGE
NOTES:
1. The listed stack size excludes the 2 bytes used by the calling instruction, JSR.
The routines are designed to be called as stand-alone subroutines in the
user program or monitor mode. The parameters that are passed to a
routine are in the form of a contiguous data block, stored in RAM. The
index register (H:X) is loaded with the address of the first byte of the data
block (acting as a pointer), and the subroutine is called (JSR). Using the
start address as a pointer, multiple data blocks can be used, any area of
RAM be used. A data block has the control and data bytes in a defined
order, as shown in Figure 9-8.
During the software execution, it does not consume any dedicated RAM
location, the run-time heap will extend the system stack, all other RAM
location will not be affected.
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Monitor ROM (MON)
R
FILE_PTR
$XXXX
ADDRESS AS POINTER
A
M
BUS SPEED (BUS_SPD)
DATA SIZE (DATASIZE)
START ADDRESS HIGH (ADDRH)
START ADDRESS LOW (ADDRL)
DATA 0
DATA
BLOCK
DATA 1
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DATA
ARRAY
DATA N
Figure 9-8. Data Block Format for ROM-Resident Routines
The control and data bytes are described below.
•
Bus speed — This one byte indicates the operating bus speed of
the MCU. The value of this byte should be equal to 4 times the bus
speed, and should not be set to less than 4 (i.e. minimum bus
speed is 1MHz).
•
Data size — This one byte indicates the number of bytes in the
data array that are to be manipulated. The maximum data array
size is 128. Routines EE_WRITE and EE_READ are restricted to
manipulate a data array between 2 to 15 bytes. Whereas routines
ERARNGE and MON_ERARNGE do not manipulate a data array,
thus, this data size byte has no meaning.
•
Start address — These two bytes, high byte followed by low byte,
indicate the start address of the FLASH memory to be
manipulated.
•
Data array — This data array contains data that are to be
manipulated. Data in this array are programmed to FLASH
memory by the programming routines: PRGRNGE,
MON_PRGRNGE, EE_WRITE. For the read routines: LDRNGE,
MON_LDRNGE, and EE_READ, data is read from FLASH and
stored in this array.
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ROM-Resident Routines
9.6.1 PRGRNGE
PRGRNGE is used to program a range of FLASH locations with data
loaded into the data array.
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Table 9-11. PRGRNGE Routine
Routine Name
PRGRNGE
Routine Description
Program a range of locations
Calling Address
$FC06
Stack Used
15 bytes
Data Block Format
Bus speed (BUS_SPD)
Data size (DATASIZE)
Start address high (ADDRH)
Start address (ADDRL)
Data 1 (DATA1)
:
Data N (DATAN)
The start location of the FLASH to be programmed is specified by the
address ADDRH:ADDRL and the number of bytes from this location is
specified by DATASIZE. The maximum number of bytes that can be
programmed in one routine call is 128 bytes (max. DATASIZE is 128).
ADDRH:ADDRL do not need to be at a page boundary, the routine
handles any boundary misalignment during programming. A check to
see that all bytes in the specified range are erased is not performed by
this routine prior programming. Nor does this routine do a verification
after programming, so there is no return confirmation that programming
was successful. User must assure that the range specified is first
erased.
The coding example below is to program 32 bytes of data starting at
FLASH location $EF00, with a bus speed of 4.9152 MHz. The coding
assumes the data block is already loaded in RAM, with the address
pointer, FILE_PTR, pointing to the first byte of the data block.
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ORG
RAM
:
FILE_PTR:
BUS_SPD
DATASIZE
START_ADDR
DATAARRAY
DS.B
DS.B
DS.W
DS.B
1
1
1
32
PRGRNGE
FLASH_START
EQU
EQU
$FC06
$EF00
;
;
;
;
Indicates 4x bus frequency
Data size to be programmed
FLASH start address
Reserved data array
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ORG
FLASH
INITIALISATION:
MOV
#20,
BUS_SPD
MOV
#32,
DATASIZE
LDHX
#FLASH_START
STHX
START_ADDR
RTS
MAIN:
BSR
INITIALISATION
:
:
LDHX
#FILE_PTR
JSR
PRGRNGE
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ROM-Resident Routines
9.6.2 ERARNGE
ERARNGE is used to erase a range of locations in FLASH.
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Table 9-12. ERARNGE Routine
Routine Name
ERARNGE
Routine Description
Erase a page or the entire array
Calling Address
$FCBE
Stack Used
9 bytes
Data Block Format
Bus speed (BUS_SPD)
Data size (DATASIZE)
Starting address (ADDRH)
Starting address (ADDRL)
There are two sizes of erase ranges: a page or the entire array. The
ERARNGE will erase the page (64 consecutive bytes) in FLASH
specified by the address ADDRH:ADDRL. This address can be any
address within the page. Calling ERARNGE with ADDRH:ADDRL equal
to $FFFF will erase the entire FLASH array (mass erase). Therefore,
care must be taken when calling this routine to prevent an accidental
mass erase. To avoid undesirable routine return addresses after a mass
erase, the ERARNGE routine should not be called from code executed
from FLASH memory. Load the code into an area of RAM before calling
the ERARNGE routine.
The ERARNGE routine do not use a data array. The DATASIZE byte is
a dummy byte that is also not used.
The coding example below is to perform a page erase, from
$EF00–$EF3F. The Initialization subroutine is the same as the coding
example for PRGRNGE (see 9.6.1 PRGRNGE).
ERARNGE
MAIN:
EQU
BSR
:
:
LDHX
JSR
:
$FCBE
INITIALISATION
#FILE_PTR
ERARNGE
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9.6.3 LDRNGE
LDRNGE is used to load the data array in RAM with data from a range
of FLASH locations.
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Table 9-13. LDRNGE Routine
Routine Name
LDRNGE
Routine Description
Loads data from a range of locations
Calling Address
$FF30
Stack Used
9 bytes
Data Block Format
Bus speed (BUS_SPD)
Data size (DATASIZE)
Starting address (ADDRH)
Starting address (ADDRL)
Data 1
:
Data N
The start location of FLASH from where data is retrieved is specified by
the address ADDRH:ADDRL and the number of bytes from this location
is specified by DATASIZE. The maximum number of bytes that can be
retrieved in one routine call is 128 bytes. The data retrieved from FLASH
is loaded into the data array in RAM. Previous data in the data array will
be overwritten. User can use this routine to retrieve data from FLASH
that was previously programmed.
The coding example below is to retrieve 32 bytes of data starting from
$EF00 in FLASH. The Initialization subroutine is the same as the coding
example for PRGRNGE (see 9.6.1 PRGRNGE).
LDRNGE
MAIN:
EQU
BSR
:
:
LDHX
JSR
:
$FF30
INITIALIZATION
#FILE_PTR
LDRNGE
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ROM-Resident Routines
9.6.4 MON_PRGRNGE
In monitor mode, MON_PRGRNGE is used to program a range of
FLASH locations with data loaded into the data array.
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Table 9-14. MON_PRGRNGE Routine
Routine Name
MON_PRGRNGE
Routine Description
Program a range of locations, in monitor mode
Calling Address
$FC28
Stack Used
17 bytes
Data Block Format
Bus speed
Data size
Starting address (high byte)
Starting address (low byte)
Data 1
:
Data N
The MON_PRGRNGE routine is designed to be used in monitor mode.
It performs the same function as the PRGRNGE routine (see 9.6.1
PRGRNGE), except that MON_PRGRNGE returns to the main program
via an SWI instruction. After a MON_PRGRNGE call, the SWI instruction
will return the control back to the monitor code.
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9.6.5 MON_ERARNGE
In monitor mode, ERARNGE is used to erase a range of locations in
FLASH.
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Table 9-15. MON_ERARNGE Routine
Routine Name
MON_ERARNGE
Routine Description
Erase a page or the entire array, in monitor mode
Calling Address
$FF2C
Stack Used
11 bytes
Data Block Format
Bus speed
Data size
Starting address (high byte)
Starting address (low byte)
The MON_ERARNGE routine is designed to be used in monitor mode.
It performs the same function as the ERARNGE routine (see 9.6.2
ERARNGE), except that MON_ERARNGE returns to the main program
via an SWI instruction. After a MON_ERARNGE call, the SWI instruction
will return the control back to the monitor code.
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ROM-Resident Routines
9.6.6 MON_LDRNGE
In monitor mode, LDRNGE is used to load the data array in RAM with
data from a range of FLASH locations.
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Table 9-16. ICP_LDRNGE Routine
Routine Name
MON_LDRNGE
Routine Description
Loads data from a range of locations, in monitor mode
Calling Address
$FF24
Stack Used
11 bytes
Data Block Format
Bus speed
Data size
Starting address (high byte)
Starting address (low byte)
Data 1
:
Data N
The MON_LDRNGE routine is designed to be used in monitor mode. It
performs the same function as the LDRNGE routine (see 9.6.3
LDRNGE), except that MON_LDRNGE returns to the main program via
an SWI instruction. After a MON_LDRNGE call, the SWI instruction will
return the control back to the monitor code.
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9.6.7 EE_WRITE
EE_WRITE is used to write a set of data from the data array to FLASH.
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Table 9-17. EE_WRITE Routine
Routine Name
EE_WRITE
Routine Description
Emulated EEPROM write. Data size ranges from 2 to 15
bytes at a time.
Calling Address
$FD3F
Stack Used
24 bytes
Data Block Format
Bus speed (BUS_SPD)
Data size (DATASIZE)(1)
Starting address (ADDRH)(2)
Starting address (ADDRL)(1)
Data 1
:
Data N
NOTES:
1. The minimum data size is 2 bytes. The maximum data size is 15 bytes.
2. The start address must be a page boundary start address: $xx00, $xx40, $xx80, or $00C0.
The start location of the FLASH to be programmed is specified by the
address ADDRH:ADDRL and the number of bytes in the data array is
specified by DATASIZE. The minimum number of bytes that can be
programmed in one routine call is 2 bytes, the maximum is 15 bytes.
ADDRH:ADDRL must always be the start of boundary address (the page
start address: $XX00, $XX40, $XX80, or $00C0) and DATASIZE must
be the same size when accessing the same page.
In some applications, the user may want to repeatedly store and read a
set of data from an area of non-volatile memory. This is easily possible
when using an EEPROM array. As the write and erase operations can
be executed on a byte basis. For FLASH memory, the minimum erase
size is the page — 64 bytes per page for MC68HC908JL8. If the data
array size is less than the page size, writing and erasing to the same
page cannot fully utilize the page. Unused locations in the page will be
wasted. The EE_WRITE routine is designed to emulate the properties
similar to the EEPROM. Allowing a more efficient use of the FLASH page
for data storage.
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ROM-Resident Routines
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When the user dedicates a page of FLASH for data storage, and the size
of the data array defined, each call of the EE_WRTIE routine will
automatically transfer the data in the data array (in RAM) to the next
blank block of locations in the FLASH page. Once a page is filled up, the
EE_WRITE routine automatically erases the page, and starts to reuse
the page again. In the 64-byte page, an 4-byte control block is used by
the routine to monitor the utilization of the page. In effect, only 60 bytes
are used for data storage. (see Figure 9-9). The page control operations
are transparent to the user.
F L A S H
PAGE BOUNDARY
CONTROL: 8 BYTES
$XX00, $XX40, $XX80, OR $XXC0
DATA ARRAY
DATA ARRAY
DATA ARRAY
ONE PAGE = 64 BYTES
PAGE BOUNDARY
Figure 9-9. EE_WRITE FLASH Memory Usage
When using this routine to store a 3-byte data array, the FLASH page
can be programmed 20 times before the an erase is required. In effect,
the write/erase endurance is increased by 20 times. When a 15-byte
data array is used, the write/erase endurance is increased by 5 times.
Due to the FLASH page size limitation, the data array is limited from 2
bytes to 15 bytes.
The coding example below uses the $EF00–$EE3F page for data
storage. The data array size is 15 bytes, and the bus speed is
4.9152 MHz. The coding assumes the data block is already loaded in
RAM, with the address pointer, FILE_PTR, pointing to the first byte of the
data block.
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ORG
RAM
:
FILE_PTR:
BUS_SPD
DATASIZE
START_ADDR
DATAARRAY
DS.B
DS.B
DS.W
DS.B
1
1
1
15
EE_WRITE
FLASH_START
EQU
EQU
$FD3F
$EF00
;
;
;
;
Indicates 4x bus frequency
Data size to be programmed
FLASH starting address
Reserved data array
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ORG
FLASH
INITIALISATION:
MOV
#20,
BUS_SPD
MOV
#15,
DATASIZE
LDHX
#FLASH_START
STHX
START_ADDR
RTS
MAIN:
BSR
INITIALISATION
:
:
LHDX
#FILE_PTR
JSR
EE_WRITE
NOTE:
The EE_WRITE routine is unable to check for incorrect data blocks,
such as the FLASH page boundary address and data size. It is the
responsibility of the user to ensure the starting address indicated in the
data block is at the FLASH page boundary and the data size is 2 to 15.
If the FLASH page is already programmed with a data array with a
different size, the EE_WRITE call will be ignored.
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ROM-Resident Routines
9.6.8 EE_READ
EE_READ is used to load the data array in RAM with a set of data from
FLASH.
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Table 9-18. EE_READ Routine
Routine Name
EE_READ
Routine Description
Emulated EEPROM read. Data size ranges from 2 to 15
bytes at a time.
Calling Address
$FDD0
Stack Used
16 bytes
Data Block Format
Bus speed (BUS_SPD)
Data size (DATASIZE)
Starting address (ADDRH)(1)
Starting address (ADDRL)(1)
Data 1
:
Data N
NOTES:
1. The start address must be a page boundary start address: $xx00, $xx40, $xx80, or $00C0.
The EE_READ routine reads data stored by the EE_WRITE routine. An
EE_READ call will retrieve the last data written to a FLASH page and
loaded into the data array in RAM. Same as EE_WRITE, the data size
indicated by DATASIZE is 2 to 15, and the start address
ADDRH:ADDRL must the FLASH page boundary address.
The coding example below uses the data stored by the EE_WRITE
coding example (see 9.6.7 EE_WRITE). It loads the 15-byte data set
stored in the $EF00–$EE7F page to the data array in RAM. The
initialization subroutine is the same as the coding example for
EE_WRITE (see 9.6.7 EE_WRITE).
EE_READ
EQU
$FDD0
MAIN:
BSR
:
:
LDHX
JSR
:
INITIALIZATION
FILE_PTR
EE_READ
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The EE_READ routine is unable to check for incorrect data blocks, such
as the FLASH page boundary address and data size. It is the
responsibility of the user to ensure the starting address indicated in the
data block is at the FLASH page boundary and the data size is 2 to 15.
If the FLASH page is programmed with a data array with a different size,
the EE_READ call will be ignored.
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NOTE:
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Technical Data – MC68HC908JL8
Section 10. Timer Interface Module (TIM)
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10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
10.5.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 152
10.5.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 153
10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 153
10.5.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 154
10.5.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 155
10.5.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
10.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
10.8
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 158
10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
10.9.1 TIM Clock Pin (T2CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
10.9.2 TIM Channel I/O Pins (T1CH0, T1CH1, T2CH0, T2CH1) . 159
10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
10.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 160
10.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
10.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 163
10.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .164
10.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
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10.2 Introduction
This section describes the timer interface (TIM) module. The TIM is a
two-channel timer that provides a timing reference with Input capture,
output compare, and pulse-width-modulation functions. Figure 10-1 is a
block diagram of the TIM.
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This particular MCU has two timer interface modules which are denoted
as TIM1 and TIM2.
10.3 Features
Features of the TIM include:
•
Two input capture/output compare channels:
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
•
Buffered and unbuffered pulse-width-modulation (PWM) signal
generation
•
Programmable TIM clock input
– 7-frequency internal bus clock prescaler selection
– External clock input on timer 2 (bus frequency ÷2 maximum)
•
Free-running or modulo up-count operation
•
Toggle any channel pin on overflow
•
TIM counter stop and reset bits
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Timer Interface Module (TIM)
Pin Name Conventions
10.4 Pin Name Conventions
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The text that follows describes both timers, TIM1 and TIM2. The TIM
input/output (I/O) pin names are T[1,2]CH0 (timer channel 0) and
T[1,2]CH1 (timer channel 1), where “1” is used to indicate TIM1 and “2”
is used to indicate TIM2. The two TIMs share four I/O pins with four I/O
port pins. The external clock input for TIM2 is shared with the an ADC
channel pin. The full names of the TIM I/O pins are listed in Table 10-1.
The generic pin names appear in the text that follows.
Table 10-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM
Pin Names:
NOTE:
T[1,2]CH0
T[1,2]CH1
T2CLK
TIM1
PTD4/T1CH0
PTD5/T1CH1
—
TIM2
PTE0/T2CH0
PTE1/T2CH1
ADC12/T2CLK
References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TCH0 may refer generically
to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
10.5 Functional Description
Figure 10-1 shows the structure of the TIM. The central component of
the TIM is the 16-bit TIM counter that can operate as a free-running
counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM
counter modulo registers, TMODH:TMODL, control the modulo value of
the TIM counter. Software can read the TIM counter value at any time
without affecting the counting sequence.
The two TIM channels (per timer) are programmable independently as
input capture or output compare channels.
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T2CLK
(FOR TIM2 ONLY)
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
Freescale Semiconductor, Inc...
TMODH:TMODL
TOV0
ELS0B
CHANNEL 0
ELS0A
CH0MAX
16-BIT COMPARATOR
PORT
LOGIC
T[1,2]CH0
CH0F
TCH0H:TCH0L
16-BIT LATCH
MS0A
CH0IE
INTERRUPT
LOGIC
MS0B
INTERNAL BUS
TOV1
ELS0B
CHANNEL 1
ELS0A
CH1MAX
PORT
LOGIC
CH01IE
INTERRUPT
LOGIC
T[1,2]CH1
16-BIT COMPARATOR
CH1F
TCH1H:TCH1L
16-BIT LATCH
MS0A
CH1IE
Figure 10-1. TIM Block Diagram
Figure 10-2 summarizes the timer registers.
NOTE:
References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TSC may generically refer to
both T1SC and T2SC.
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Functional Description
Addr.
$0020
Freescale Semiconductor, Inc...
$0021
$0022
$0023
$0024
$0025
Register Name
6
5
TOIE
TSTOP
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
Read:
TIM1 Status and Control
Register Write:
(T1SC)
Reset:
TOF
0
0
1
0
0
0
0
0
Read:
TIM1 Counter Register
High Write:
(T1CNTH)
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
TIM1 Counter Register
Low Write:
(T1CNTL)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Read:
TIM Counter Modulo
Register High Write:
(TMODH)
Reset:
Read:
TIM1 Counter Modulo
Register Low Write:
(T1MODL)
Reset:
Read:
TIM1 Channel 0 Status
and Control Register Write:
(T1SC0)
Reset:
Read:
TIM1 Channel 0
Register High Write:
(T1CH0H)
Reset:
$0026
Read:
TIM1 Channel 0
Register Low Write:
(T1CH0L)
Reset:
$0027
$0028
Bit 7
Read:
TIM1 Channel 1 Status
and Control Register Write:
(T1SC1)
Reset:
0
TRST
CH0F
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH1F
0
CH1IE
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-2. TIM I/O Register Summary (Sheet 1 of 3)
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Addr.
Register Name
Read:
TIM1 Channel 1
Register High Write:
(T1CH1H)
Reset:
$0029
Read:
TIM1 Channel 1
Register Low Write:
(T1CH1L)
Reset:
Freescale Semiconductor, Inc...
$002A
$0030
$0031
$0032
$0033
$0034
$0035
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
PS2
PS1
PS0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
Read:
TIM2 Status and Control
Register Write:
(T2SC)
Reset:
TOF
0
0
1
0
0
0
0
0
Read:
TIM2 Counter Register
High Write:
(T2CNTH)
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
TIM2 Counter Register
Low Write:
(T2CNTL)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Read:
TIM2 Counter Modulo
Register High Write:
(T2MODH)
Reset:
Read:
TIM2 Counter Modulo
Register Low Write:
(T2MODL)
Reset:
Read:
TIM2 Channel 0 Status
and Control Register Write:
(T2SC0)
Reset:
$0036
Read:
TIM2 Channel 0
Register High Write:
(T2CH0H)
Reset:
0
TOIE
0
TSTOP
0
TRST
CH0F
0
Indeterminate after reset
= Unimplemented
Figure 10-2. TIM I/O Register Summary (Sheet 2 of 3)
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Functional Description
Addr.
Register Name
Read:
TIM2 Channel 0
Register Low Write:
(T2CH0L)
Reset:
$0037
Freescale Semiconductor, Inc...
$0038
Read:
TIM2 Channel 1 Status
and Control Register Write:
(T2SC1)
Reset:
$0039
$003A
Read:
TIM2 Channel 1
Register High Write:
(T2CH1H)
Reset:
Read:
TIM2 Channel 1
Register Low Write:
(T2CH1L)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset
CH1F
0
CH1IE
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
= Unimplemented
Figure 10-2. TIM I/O Register Summary (Sheet 3 of 3)
10.5.1 TIM Counter Prescaler
The TIM1 clock source can be one of the seven prescaler outputs; TIM2
clock source can be one of the seven prescaler outputs or the TIM2 clock
pin, T2CLK. The prescaler generates seven clock rates from the internal
bus clock. The prescaler select bits, PS[2:0], in the TIM status and
control register select the TIM clock source.
10.5.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
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10.5.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
Freescale Semiconductor, Inc...
10.5.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in 10.5.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
•
When changing to a larger output compare value, enable TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an
output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same counter
overflow period.
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Functional Description
10.5.3.2 Buffered Output Compare
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Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the TCH0 pin. Writing
to the TIM channel 1 registers enables the TIM channel 1 registers to
synchronously control the output after the TIM overflows. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should
track the currently active channel to prevent writing a new value to the
active channel. Writing to the active channel registers is the same as
generating unbuffered output compares.
10.5.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel,
the TIM can generate a PWM signal. The value in the TIM counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIM counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 10-3 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.
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The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000. See 10.10.1 TIM Status and Control Register.
OVERFLOW
OVERFLOW
OVERFLOW
Freescale Semiconductor, Inc...
PERIOD
PULSE
WIDTH
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 10-3. PWM Period and Pulse Width
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
10.5.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in 10.5.4 Pulse Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel
registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
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Functional Description
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Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
NOTE:
•
When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
•
When changing to a longer pulse width, enable TIM overflow
interrupts and write the new value in the TIM overflow interrupt
routine. The TIM overflow interrupt occurs at the end of the current
PWM period. Writing a larger value in an output compare interrupt
routine (at the end of the current pulse) could cause two output
compares to occur in the same PWM period.
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
10.5.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the
buffered PWM function, and TIM channel 1 status and control register
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,
is available as a general-purpose I/O pin.
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NOTE:
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.
10.5.4.3 PWM Initialization
Freescale Semiconductor, Inc...
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset
bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB:MSxA. (See Table 10-3.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 10-3.)
NOTE:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
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Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels.
Freescale Semiconductor, Inc...
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100% duty cycle output. (See 10.10.4 TIM
Channel Status and Control Registers.)
10.6 Interrupts
The following TIM sources can generate interrupt requests:
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter reaches the modulo value programmed in the TIM counter
modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are
in the TIM status and control register.
•
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM
channel x status and control register.
10.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
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10.7.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait
mode, the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
Freescale Semiconductor, Inc...
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
10.7.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exits stop mode after an
external interrupt.
10.8 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 7.8.3 Break Flag Control Register
(BFCR).)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
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I/O Signals
10.9 I/O Signals
Port D shares two of its pins with TIM1 and port E shares two of its pins
with TIM2. The ADC12/T2CLK pin is an external clock input to TIM2. The
four TIM channel I/O pins are T1CH0, T1CH1, T2CH0, and T2CH1.
Freescale Semiconductor, Inc...
10.9.1 TIM Clock Pin (ADC12/T2CLK)
ADC12/T2CLK is an external clock input that can be the clock source for
the TIM2 counter instead of the prescaled internal bus clock. Select the
ADC12/T2CLK input by writing logic 1’s to the three prescaler select bits,
PS[2:0]. (See 10.10.1 TIM Status and Control Register.) The minimum
T2CLK pulse width, T2CLKLMIN or T2CLKHMIN, is:
1
------------------------------------- + t SU
bus frequency
The maximum T2CLK frequency is:
bus frequency ÷ 2
ADC12/T2CLK is available as a ADC input channel pin when not used
as the TIM2 clock input.
10.9.2 TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1, PTE0/T2CH0, PTE1/T2CH1)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. T1CH0 and T2CH0 can be
configured as buffered output compare or buffered PWM pins.
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10.10 I/O Registers
NOTE:
References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TSC may generically refer to
both T1SC AND T2SC.
Freescale Semiconductor, Inc...
These I/O registers control and monitor operation of the TIM:
•
TIM status and control register (TSC)
•
TIM counter registers (TCNTH:TCNTL)
•
TIM counter modulo registers (TMODH:TMODL)
•
TIM channel status and control registers (TSC0, TSC1)
•
TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
10.10.1 TIM Status and Control Register
The TIM status and control register (TSC):
•
Enables TIM overflow interrupts
•
Flags TIM overflows
•
Stops the TIM counter
•
Resets the TIM counter
•
Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $0030
Bit 7
Read:
6
5
TOIE
TSTOP
TOF
Write:
0
Reset:
0
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
TRST
0
1
0
0
= Unimplemented
Figure 10-4. TIM Status and Control Register (TSC)
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I/O Registers
TOF — TIM Overflow Flag Bit
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This read/write flag is set when the TIM counter reaches the modulo
value programmed in the TIM counter modulo registers. Clear TOF by
reading the TIM status and control register when TOF is set and then
writing a logic 0 to TOF. If another TIM overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a
logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic 0. Reset clears the
TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
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Timer Interface Module (TIM)
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the
input to the TIM counter as Table 10-2 shows. Reset clears the
PS[2:0] bits.
Freescale Semiconductor, Inc...
Table 10-2. Prescaler Selection
PS2
PS1
PS0
TIM Clock Source
0
0
0
Internal bus clock ÷ 1
0
0
1
Internal bus clock ÷ 2
0
1
0
Internal bus clock ÷ 4
0
1
1
Internal bus clock ÷ 8
1
0
0
Internal bus clock ÷ 16
1
0
1
Internal bus clock ÷ 32
1
1
0
Internal bus clock ÷ 64
1
1
1
T2CLK (for TIM2 only)
10.10.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $0031
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 10-5. TIM Counter Registers High (TCNTH)
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I/O Registers
Address: T1CNTL, $0022 and T2CNTL, $0032
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Freescale Semiconductor, Inc...
Figure 10-6. TIM Counter Registers Low (TCNTL)
10.10.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH)
inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is
written. Reset sets the TIM counter modulo registers.
Address: T1MODH, $0023 and T2MODH, $0033
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 10-7. TIM Counter Modulo Register High (TMODH)
Address: T1MODL, $0024 and T2MODL, $0034
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 10-8. TIM Counter Modulo Register Low (TMODL)
NOTE:
Reset the TIM counter before writing to the TIM counter modulo registers.
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10.10.4 TIM Channel Status and Control Registers
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Each of the TIM channel status and control registers:
•
Flags input captures and output compares
•
Enables input capture and output compare interrupts
•
Selects input capture, output compare, or PWM operation
•
Selects high, low, or toggling output on output compare
•
Selects rising edge, falling edge, or any edge as the active input
capture trigger
•
Selects output toggling on TIM overflow
•
Selects 0% and 100% PWM duty cycle
•
Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0035
Bit 7
Read:
CH0F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
Figure 10-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0038
Bit 7
Read:
6
CH1F
5
0
Reset:
0
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
CH1IE
Write:
4
0
0
Figure 10-10. TIM Channel 1 Status and Control Register (TSC1)
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I/O Registers
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
Freescale Semiconductor, Inc...
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading TIM channel x status and control register with CHxF
set and then writing a logic 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing logic 0
to CHxF has no effect. Therefore, an interrupt request cannot be lost
due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on
channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status
and control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input
capture operation or unbuffered output compare/PWM operation.
See Table 10-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
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When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output
level of the TCHx pin. See Table 10-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
Freescale Semiconductor, Inc...
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to an I/O port, and pin TCHx is available as a general-purpose I/O pin.
Table 10-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 10-3. Mode, Edge, and Level Selection
MSxB:MSxA
ELSxB:ELSxA
X0
00
Mode
Configuration
Pin under port control;
initial output level high
Output preset
X1
00
Pin under port control;
initial output level low
00
01
Capture on rising edge only
00
10
00
11
01
01
01
10
01
11
1X
01
1X
10
1X
11
Input capture
Capture on rising or
falling edge
Output
compare or
PWM
Buffered
output
compare or
buffered PWM
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Capture on falling edge only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
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Timer Interface Module (TIM)
I/O Registers
NOTE:
Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
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When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect.
Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow
0 = Channel x pin does not toggle on TIM counter overflow
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 10-11 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 10-11. CHxMAX Latency
10.10.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
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In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
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Address: T1CH0H, $0026 and T2CH0H, $0036
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Write:
Reset:
Indeterminate after reset
Figure 10-12. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0037
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Indeterminate after reset
Figure 10-13. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0029 and T2CH1H, $0039
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Write:
Reset:
Indeterminate after reset
Figure 10-14. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A and T2CH1L, $003A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Indeterminate after reset
Figure 10-15. TIM Channel 1 Register Low (TCH1L)
Technical Data
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Technical Data – MC68HC908JL8
Section 11. Serial Communications Interface (SCI)
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11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
11.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
11.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
11.5.2.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.5.2.2
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.5.2.3
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.5.2.4
Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.5.2.5
Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . . 179
11.5.2.6
Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 179
11.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.5.3.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.5.3.2
Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.5.3.3
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
11.5.3.4
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
11.5.3.5
Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
11.5.3.6
Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
11.5.3.7
Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.5.3.8
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.7
SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 189
11.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
11.8.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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11.8.2
RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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11.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
11.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
11.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
11.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
11.9.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
11.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
11.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
11.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
11.2 Introduction
This section describes the serial communications interface (SCI)
module, which allows high-speed asynchronous communications with
peripheral devices and other MCUs.
NOTE:
References to DMA (direct-memory access) and associated functions
are only valid if the MCU has a DMA module. This MCU does not have
the DMA function. Any DMA-related register bits should be left in their
reset state for normal MCU operation.
11.3 Features
Features of the SCI module include the following:
•
Full-duplex operation
•
Standard mark/space non-return-to-zero (NRZ) format
•
32 programmable baud rates
•
Programmable 8-bit or 9-bit character length
•
Separately enabled transmitter and receiver
•
Separate receiver and transmitter CPU interrupt requests
•
Programmable transmitter output polarity
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Serial Communications Interface (SCI)
Features
•
Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
•
Interrupt-driven operation with eight interrupt flags:
– Transmitter empty
– Transmission complete
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– Receiver full
– Idle receiver input
– Receiver overrun
– Noise error
– Framing error
– Parity error
•
Receiver framing error detection
•
Hardware parity checking
•
1/16 bit-time noise detection
•
OSCOUT as baud rate clock source
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11.4 Pin Name Conventions
The generic names of the SCI I/O pins are:
•
RxD (receive data)
•
TxD (transmit data)
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The SCI I/O (input/output) lines are dedicated pins for the SCI module.
Table 11-1 shows the full names and the generic names of the SCI I/O
pins.
The generic pin names appear in the text of this section.
Table 11-1. Pin Name Conventions
Generic Pin Names:
RxD
TxD
Full Pin Names:
PTD7/RxD
PTD6/TxD
11.5 Functional Description
Figure 11-1 shows the structure of the SCI module. The SCI allows fullduplex, asynchronous, NRZ serial communication among the MCU and
remote devices, including other MCUs. The transmitter and receiver of
the SCI operate independently, although they use the same baud rate
generator. During normal operation, the CPU monitors the status of the
SCI, writes the data to be transmitted, and processes received data.
The baud rate clock source for the SCI is OSCOUT clock.
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Serial Communications Interface (SCI)
Functional Description
INTERNAL BUS
SCI DATA
REGISTER
ERROR
INTERRUPT
CONTROL
RECEIVER
INTERRUPT
CONTROL
DMA
INTERRUPT
CONTROL
RECEIVE
SHIFT REGISTER
RxD
TRANSMITTER
INTERRUPT
CONTROL
SCI DATA
REGISTER
TRANSMIT
SHIFT REGISTER
TxD
TXINV
SCTIE
R8
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TCIE
T8
SCRIE
ILIE
DMARE
TE
SCTE
RE
DMATE
TC
RWU
SBK
SCRF
OR
ORIE
IDLE
NF
NEIE
FE
FEIE
PE
PEIE
LOOPS
LOOPS
WAKEUP
CONTROL
RECEIVE
CONTROL
ENSCI
ENSCI
FLAG
CONTROL
TRANSMIT
CONTROL
BKF
M
RPF
WAKE
ILTY
OSCOUT
÷4
PRESCALER
BAUD
DIVIDER
÷ 16
PEN
PTY
DATA SELECTION
CONTROL
Figure 11-1. SCI Module Block Diagram
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Serial Communications Interface (SCI)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
U
U
0
0
0
0
0
0
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
BKF
RPF
Read:
$0013
LOOPS
SCI Control Register 1
Write:
(SCC1)
Reset:
0
Read:
Freescale Semiconductor, Inc...
$0014
SCI Control Register 2
Write:
(SCC2)
Reset:
Read:
$0015
SCI Control Register 3
Write:
(SCC3)
Reset:
Read:
$0016
SCI Status Register 1
Write:
(SCS1)
Reset:
R8
Read:
$0017
$0018
SCI Status Register 2
Write:
(SCS2)
Reset:
0
0
0
0
0
0
0
0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
SCI Data Register
Write:
(SCDR)
Reset:
Read:
$0019
SCI Baud Rate Register
Write:
(SCBR)
Reset:
Unaffected by reset
0
0
0
0
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 11-2. SCI I/O Register Summary
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Functional Description
11.5.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 11-3.
8-BIT DATA FORMAT
BIT M IN SCC1 CLEAR
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START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
PARITY
BIT
BIT 6
BIT 7
9-BIT DATA FORMAT
BIT M IN SCC1 SET
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
STOP
BIT
NEXT
START
BIT
PARITY
BIT
BIT 6
BIT 7
BIT 8
STOP
BIT
NEXT
START
BIT
Figure 11-3. SCI Data Formats
11.5.2 Transmitter
Figure 11-4 shows the structure of the SCI transmitter.
The baud rate clock source for the SCI is the OSCOUT clock.
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Serial Communications Interface (SCI)
INTERNAL BUS
PRESCALER
÷4
BAUD
DIVIDER
÷ 16
SCI DATA REGISTER
11-BIT
TRANSMIT
SHIFT REGISTER
STOP
Freescale Semiconductor, Inc...
SCP1
SCP0
SCR1
H
SCR2
8
7
6
5
4
3
2
START
OSCOUT
1
0
L
TxD
MSB
TXINV
T8
DMATE
DMATE
SCTIE
SCTE
DMATE
SCTE
SCTIE
TC
TCIE
BREAK
ALL 0s
PTY
PARITY
GENERATION
PREAMBLE
ALL 1s
PEN
SHIFT ENABLE
M
LOAD FROM SCDR
TRANSMITTER DMA SERVICE REQUEST
TRANSMITTER CPU INTERRUPT REQUEST
SCR0
TRANSMITTER
CONTROL LOGIC
SCTE
SBK
LOOPS
SCTIE
ENSCI
TC
TE
TCIE
Figure 11-4. SCI Transmitter
Technical Data
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Serial Communications Interface (SCI)
Functional Description
11.5.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
11.5.2.2 Character Transmission
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During an SCI transmission, the transmit shift register shifts a character
out to the TxD pin. The SCI data register (SCDR) is the write-only buffer
between the internal data bus and the transmit shift register. To initiate
an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)
in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable
bit (TE) in SCI control register 2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status
register 1 (SCS1) and then writing to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic 1s. After the
preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes
into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the
SCDR transfers a byte to the transmit shift register. The SCTE bit
indicates that the SCDR can accept new data from the internal data bus.
If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the
SCTE bit generates a transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD
pin goes to the idle condition, logic 1. If at any time software clears the
ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver
relinquish control of the port pin.
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11.5.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit
shift register with a break character. A break character contains all logic
0s and has no start, stop, or parity bit. Break character length depends
on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic
continuously loads break characters into the transmit shift register. After
software clears the SBK bit, the shift register finishes transmitting the
last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be.
Receiving a break character has these effects on SCI registers:
•
Sets the framing error bit (FE) in SCS1
•
Sets the SCI receiver full bit (SCRF) in SCS1
•
Clears the SCI data register (SCDR)
•
Clears the R8 bit in SCC3
•
Sets the break flag bit (BKF) in SCS2
•
May set the overrun (OR), noise flag (NF), parity error (PE), or
reception in progress flag (RPF) bits
11.5.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit in SCC1. The preamble is a
synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle
after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle character to be
sent after the character currently being transmitted.
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Serial Communications Interface (SCI)
Functional Description
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the TxD pin. Setting TE after
the stop bit appears on TxD causes data previously written to the SCDR
to be lost.
Toggle the TE bit for a queued idle character when the SCTE bit
becomes set and just before writing the next byte to the SCDR.
Freescale Semiconductor, Inc...
11.5.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
(See 11.9.1 SCI Control Register 1.)
11.5.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI
transmitter:
•
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2
enables the SCTE bit to generate transmitter CPU interrupt
requests.
•
Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.
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11.5.3 Receiver
Figure 11-5 shows the structure of the SCI receiver.
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11.5.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
11.5.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in
from the RxD pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt
request.
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Serial Communications Interface (SCI)
Functional Description
INTERNAL BUS
SCR1
SCR2
SCP0
SCR0
BAUD
DIVIDER
÷ 16
DATA
RECOVERY
RxD
CPU INTERRUPT REQUEST
H
11-BIT
RECEIVE SHIFT REGISTER
8
7
6
5
4
ALL 1s
M
WAKE
ILTY
PEN
PTY
3
2
1
0
L
ALL 0s
RPF
ERROR CPU INTERRUPT REQUEST
DMA SERVICE REQUEST
Freescale Semiconductor, Inc...
BKF
STOP
PRESCALER
MSB
÷4
OSCOUT
SCI DATA REGISTER
START
SCP1
SCRF
WAKEUP
LOGIC
IDLE
R8
PARITY
CHECKING
IDLE
ILIE
DMARE
ILIE
SCRF
SCRIE
DMARE
SCRF
SCRIE
DMARE
RWU
SCRIE
DMARE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
Figure 11-5. SCI Receiver Block Diagram
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11.5.3.3 Data Sampling
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The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock is resynchronized at the following
times (see Figure 11-6):
•
After every start bit
•
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
START BIT
LSB
START BIT
VERIFICATION
DATA
SAMPLING
RT8
START BIT
QUALIFICATION
SAMPLES
RT3
RxD
RT4
RT3
RT2
RT1
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT7
RT6
RT5
RT4
RT2
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT CLOCK
STATE
RT1
RT
CLOCK
RT CLOCK
RESET
Figure 11-6. Receiver Data Sampling
Technical Data
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Serial Communications Interface (SCI)
Functional Description
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 11-2 summarizes the results of
the start bit verification samples.
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Table 11-2. Start Bit Verification
RT3, RT5, and RT7
Samples
Start Bit
Verification
Noise Flag
000
Yes
0
001
Yes
1
010
Yes
1
011
No
0
100
Yes
1
101
No
0
110
No
0
111
No
0
Start bit verification is not successful if any two of the three verification
samples are logic 1s. If start bit verification is not successful, the RT
clock is reset and a new search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic
takes samples at RT8, RT9, and RT10. Table 11-3 summarizes the
results of the data bit samples.
Table 11-3. Data Bit Recovery
RT8, RT9, and RT10
Samples
Data Bit
Determination
Noise Flag
000
0
0
001
0
1
010
0
1
011
1
1
100
0
1
101
1
1
110
1
1
111
1
0
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NOTE:
The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. Table 11-4 summarizes the results of the stop bit
samples.
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Table 11-4. Stop Bit Recovery
RT8, RT9, and RT10
Samples
Framing
Error Flag
Noise Flag
000
1
0
001
1
1
010
1
1
011
0
1
100
1
1
101
0
1
110
0
1
111
0
0
11.5.3.4 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error bit, FE, in
SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is
set.
11.5.3.5 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above
the receiver baud rate. Accumulated bit time misalignment can cause
one of the three stop bit data samples to fall outside the actual stop bit.
Then a noise error occurs. If more than one of the samples is outside the
stop bit, a framing error occurs. In most applications, the baud rate
tolerance is much more than the degree of misalignment that is likely to
occur.
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Serial Communications Interface (SCI)
Functional Description
As the receiver samples an incoming character, it resynchronizes the RT
clock on any valid falling edge within the character. Resynchronization
within characters corrects misalignments between transmitter bit times
and receiver bit times.
Slow Data Tolerance
RT16
RT15
RT14
RT13
RT11
RT10
RT9
RT8
RT7
RT6
STOP
RT5
RT4
RT3
RT2
RECEIVER
RT CLOCK
RT1
MSB
RT12
Freescale Semiconductor, Inc...
Figure 11-7 shows how much a slow received character can be
misaligned without causing a noise error or a framing error. The slow
stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit
data samples at RT8, RT9, and RT10.
DATA
SAMPLES
Figure 11-7. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 11-7, the receiver counts
154 RT cycles at the point when the count of the transmitting device is
9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit character with no errors is
154 – 147 × 100 = 4.54%
-------------------------154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 11-7, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
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The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is
170 – 163 × 100 = 4.12%
-------------------------170
Fast Data Tolerance
RT16
RT15
RT14
RT13
RT12
RT10
RT9
RT8
RT7
IDLE OR NEXT CHARACTER
RT6
RT5
RT4
RT3
RT2
RECEIVER
RT CLOCK
RT1
STOP
RT11
Freescale Semiconductor, Inc...
Figure 11-8 shows how much a fast received character can be
misaligned without causing a noise error or a framing error. The fast stop
bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
DATA
SAMPLES
Figure 11-8. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 11-8, the receiver counts
154 RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 8-bit character with no errors is
·
154 – 160 × 100 = 3.90%
-------------------------154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 11-8, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
11 bit times × 16 RT cycles = 176 RT cycles.
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Functional Description
The maximum percent difference between the receiver count and the
transmitter count of a fast 9-bit character with no errors is
170 – 176 × 100 = 3.53%
-------------------------170
11.5.3.6 Receiver Wakeup
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So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are
disabled.
Depending on the state of the WAKE bit in SCC1, either of two
conditions on the RxD pin can bring the receiver out of the standby state:
NOTE:
•
Address mark — An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
•
Idle input line condition — When the WAKE bit is clear, an idle
character on the RxD pin wakes the receiver from the standby
state by clearing the RWU bit. The idle character that wakes the
receiver does not set the receiver idle bit, IDLE, or the SCI receiver
full bit, SCRF. The idle line type bit, ILTY, determines whether the
receiver begins counting logic 1s as idle character bits after the
start bit or after the stop bit.
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
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11.5.3.7 Receiver Interrupts
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The following sources can generate CPU interrupt requests from the SCI
receiver:
•
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE, in SCC2 enables the
SCRF bit to generate receiver CPU interrupts.
•
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the RxD pin. The idle line
interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.
11.5.3.8 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt
requests:
•
Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI
error CPU interrupt requests.
•
Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, in SCC3 enables
NF to generate SCI error CPU interrupt requests.
•
Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI
error CPU interrupt requests.
•
Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU
interrupt requests.
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Low-Power Modes
11.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
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11.6.1 Wait Mode
The SCI module remains active after the execution of a WAIT
instruction. In wait mode, the SCI module registers are not accessible by
the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
Refer to 7.7 Low-Power Modes for information on exiting wait mode.
11.6.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect SCI register states. SCI module
operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
Refer to 7.7 Low-Power Modes for information on exiting stop mode.
11.7 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
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To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
11.8 I/O Signals
The two SCI I/O pins are:
•
PTD6/TxD — Transmit data
•
PTD7/RxD — Receive data
11.8.1 TxD (Transmit Data)
The PTD6/TxD pin is the serial data output from the SCI transmitter.
11.8.2 RxD (Receive Data)
The PTD7/RxD pin is the serial data input to the SCI receiver.
11.9 I/O Registers
These I/O registers control and monitor SCI operation:
•
SCI control register 1 (SCC1)
•
SCI control register 2 (SCC2)
•
SCI control register 3 (SCC3)
•
SCI status register 1 (SCS1)
•
SCI status register 2 (SCS2)
•
SCI data register (SCDR)
•
SCI baud rate register (SCBR)
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I/O Registers
11.9.1 SCI Control Register 1
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SCI control register 1:
•
Enables loop mode operation
•
Enables the SCI
•
Controls output polarity
•
Controls character length
•
Controls SCI wakeup method
•
Controls idle character detection
•
Enables parity function
•
Controls parity type
Address:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 11-9. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the
RxD pin is disconnected from the SCI, and the transmitter output goes
into the receiver input. Both the transmitter and the receiver must be
enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
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TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE:
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
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M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or
nine bits long. (See Table 11-5.) The ninth bit can serve as an extra
stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition on the RxD pin. Reset clears the WAKE
bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s
as idle character bits. The counting begins either after the start bit or
after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
Technical Data
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Serial Communications Interface (SCI)
I/O Registers
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 11-5.)
When enabled, the parity function inserts a parity bit in the most
significant bit position. (See Figure 11-3.) Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
Freescale Semiconductor, Inc...
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. (See Table 11-5.) Reset clears the PTY
bit.
1 = Odd parity
0 = Even parity
NOTE:
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 11-5. Character Format Selection
Control Bits
Character Format
M
PEN and
PTY
Start
Bits
Data
Bits
Parity
Stop
Bits
Character
Length
0
0X
1
8
None
1
10 bits
1
0X
1
9
None
1
11 bits
0
10
1
7
Even
1
10 bits
0
11
1
7
Odd
1
10 bits
1
10
1
8
Even
1
11 bits
1
11
1
8
Odd
1
11 bits
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11.9.2 SCI Control Register 2
SCI control register 2:
•
Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
Freescale Semiconductor, Inc...
– Enables the SCRF bit to generate receiver CPU interrupt
requests
– Enables the IDLE bit to generate receiver CPU interrupt
requests
•
Enables the transmitter
•
Enables the receiver
•
Enables SCI wakeup
•
Transmits SCI break characters
Address:
$0014
Bit 7
6
5
4
3
2
1
Bit 0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 11-10. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
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Serial Communications Interface (SCI)
I/O Registers
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
Freescale Semiconductor, Inc...
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests. Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition
(logic 1). Clearing and then setting TE during a transmission queues
an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE:
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
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NOTE:
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
Freescale Semiconductor, Inc...
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break
character followed by a logic 1. The logic 1 after the break character
guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s
between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE:
Do not toggle the SBK bit immediately after setting the SCTE bit.
Toggling SBK before the preamble begins causes the SCI to send a
break character instead of a preamble.
11.9.3 SCI Control Register 3
SCI control register 3:
•
Stores the ninth SCI data bit received and the ninth SCI data bit to
be transmitted
•
Enables these interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
•
Parity error interrupts
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Serial Communications Interface (SCI)
I/O Registers
Address:
$0015
Bit 7
Read:
6
5
4
3
2
1
Bit 0
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
U
0
0
0
0
0
0
R8
Write:
Reset:
U
= Unimplemented
U = Unaffected
Freescale Semiconductor, Inc...
Figure 11-11. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
DMARE — DMA Receive Enable Bit
CAUTION:
The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.
1 = DMA not enabled to service SCI receiver DMA service requests
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
0 = DMA not enabled to service SCI receiver DMA service requests
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
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DMATE — DMA Transfer Enable Bit
CAUTION:
The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.
1 = SCTE DMA service requests enabled; SCTE CPU interrupt
requests disabled
0 = SCTE DMA service requests disabled; SCTE CPU interrupt
requests enabled
Freescale Semiconductor, Inc...
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt
requests generated by the parity error bit, PE.
(See 11.9.4 SCI Status Register 1.) Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
Technical Data
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Serial Communications Interface (SCI)
I/O Registers
11.9.4 SCI Status Register 1
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SCI status register 1 (SCS1) contains flags to signal these conditions:
•
Transfer of SCDR data to transmit shift register complete
•
Transmission complete
•
Transfer of receive shift register data to SCDR complete
•
Receiver input idle
•
Receiver overrun
•
Noisy data
•
Framing error
•
Parity error
Address:
Read:
$0016
Bit 7
6
5
4
3
2
1
Bit 0
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 11-12. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
operation, clear the SCTE bit by reading SCS1 with SCTE set and
then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
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Serial Communications Interface (SCI)
TC — Transmission Complete Bit
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This read-only bit is set when the SCTE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is automatically cleared when data, preamble or break is
queued and ready to be sent. There may be up to 1.5 transmitter
clocks of latency between queueing data, preamble, and break and
the transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. When the SCRIE bit in SCC2 is set,
SCRF generates a CPU interrupt request. In normal operation, clear
the SCRF bit by reading SCS1 with SCRF set and then reading the
SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI receiver CPU
interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit
by reading SCS1 with IDLE set and then reading the SCDR. After the
receiver is enabled, it must receive a valid character that sets the
SCRF bit before an idle condition can set the IDLE bit. Also, after the
IDLE bit has been cleared, a valid character must again set the SCRF
bit before an idle condition can set the IDLE bit. Reset clears the IDLE
bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
Technical Data
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Serial Communications Interface (SCI)
I/O Registers
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Freescale Semiconductor, Inc...
Software latency may allow an overrun to occur between reads of
SCS1 and SCDR in the flag-clearing sequence. Figure 11-13 shows
the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of
SCDR does not clear the OR bit because OR was not set when SCS1
was read. Byte 2 caused the overrun and is lost. The next flagclearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the flagclearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the
RxD pin. NF generates an SCI error CPU interrupt request if the NEIE
bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then
reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
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BYTE 1
BYTE 2
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
NORMAL FLAG CLEARING SEQUENCE
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
BYTE 1
BYTE 2
BYTE 3
SCRF = 0
OR = 0
SCRF = 1
OR = 1
SCRF = 0
OR = 1
SCRF = 1
SCRF = 1
OR = 1
DELAYED FLAG CLEARING SEQUENCE
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 11-13. Flag Clearing Sequence
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates an SCI error CPU interrupt request if
the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1
with PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
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Serial Communications Interface (SCI)
I/O Registers
11.9.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
•
Break character detected
•
Incoming data
Address:
$0017
Freescale Semiconductor, Inc...
Bit 7
6
5
4
3
2
Read:
1
Bit 0
BKF
RPF
0
0
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 11-14. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break
character on the RxD pin. In SCS1, the FE and SCRF bits are also
set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.
BKF does not generate a CPU interrupt request. Clear BKF by
reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the RxD pin followed by another break character. Reset clears the
BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch) or when the receiver
detects an idle character. Polling RPF before disabling the SCI
module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
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11.9.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus
and the receive and transmit shift registers. Reset has no effect on data
in the SCI data register.
Freescale Semiconductor, Inc...
Address:
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by reset
Figure 11-15. SCI Data Register (SCDR)
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading the SCDR accesses the read-only received data bits, R[7:0].
Writing to the SCDR writes the data to be transmitted, T[7:0]. Reset
has no effect on the SCDR.
NOTE:
Do not use read/modify/write instructions on the SCI data register.
11.9.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver
and the transmitter.
Address:
Read:
$0019
Bit 7
6
0
0
5
4
3
2
1
Bit 0
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
R
= Reserved
Write:
Reset:
0
0
= Unimplemented
Figure 11-16. SCI Baud Rate Register (SCBR)
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown
in Table 11-6. Reset clears SCP1 and SCP0.
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Serial Communications Interface (SCI)
I/O Registers
Table 11-6. SCI Baud Rate Prescaling
SCP1 and SCP0
Prescaler Divisor (PD)
00
1
01
3
10
4
11
13
Freescale Semiconductor, Inc...
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in
Table 11-7. Reset clears SCR2–SCR0.
Table 11-7. SCI Baud Rate Selection
SCR2, SCR1, and SCR0
Baud Rate Divisor (BD)
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
Use this formula to calculate the SCI baud rate:
SCI clock source
baud rate = --------------------------------------------64 × PD × BD
where:
SCI clock source = OSCOUT
PD = prescaler divisor
BD = baud rate divisor
Table 11-8 shows the SCI baud rates that can be generated with a
4.9152MHz OSCOUT clock.
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Table 11-8. SCI Baud Rate Selection Examples
Prescaler
Divisor (PD)
SCR2, SCR1,
and SCR0
Baud Rate
Divisor (BD)
Baud Rate
(OSCOUT = 4.9152 MHz)
00
1
000
1
76,800
00
1
001
2
38,400
00
1
010
4
19,200
00
1
011
8
9,600
00
1
100
16
4,800
00
1
101
32
2,400
00
1
110
64
1,200
00
1
111
128
600
01
3
000
1
25,600
01
3
001
2
12,800
01
3
010
4
6,400
01
3
011
8
3,200
01
3
100
16
1,600
01
3
101
32
800
01
3
110
64
400
01
3
111
128
200
10
4
000
1
19,200
10
4
001
2
9,600
10
4
010
4
4,800
10
4
011
8
2,400
10
4
100
16
1,200
10
4
101
32
600
10
4
110
64
300
10
4
111
128
150
11
13
000
1
5,908
11
13
001
2
2,954
11
13
010
4
1,477
11
13
011
8
739
11
13
100
16
369
11
13
101
32
185
11
13
110
64
92
11
13
111
128
46
Freescale Semiconductor, Inc...
SCP1 and SCP0
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Section 12. Analog-to-Digital Converter (ADC)
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12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
12.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
12.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 212
12.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
12.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 212
12.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
12.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 215
12.2 Introduction
This section describes the 13-channel, 8-bit linear successive
approximation analog-to-digital converter (ADC).
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12.3 Features
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Features of the ADC module include:
Addr.
$003C
$003D
•
13 channels with multiplexed input
•
Linear successive approximation with monotonicity
•
8-bit resolution
•
Single or continuous conversion
•
Conversion complete flag or conversion complete interrupt
Register Name
Bit 7
Read:
ADC Status and Control
Register Write:
(ADSCR)
Reset:
Read:
ADC Data Register
Write:
(ADR)
Reset:
Read:
ADC Input Clock Register
$003E
Write:
(ADICLK)
Reset:
6
5
4
3
2
1
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
COCO
Indeterminate after reset
ADIV2
ADIV1
ADIV0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-1. ADC I/O Register Summary
12.4 Functional Description
Thirteen ADC channels are available for sampling external sources at
pins PTB0–PTB7, PTD0–PTD3, and ADC12/T2CLK. An analog
multiplexer allows the single ADC converter to select one of the 13 ADC
channels as ADC voltage input (ADCVIN). ADCVIN is converted by the
successive approximation register-based counters. The ADC resolution
is 8 bits. When the conversion is completed, ADC puts the result in the
ADC data register and sets a flag or generates an interrupt.
Figure 12-2 shows a block diagram of the ADC.
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Functional Description
INTERNAL
DATA BUS
READ DDRB/DDRD
DISABLE
WRITE DDRB/DDRD
DDRBx/DDRDx
RESET
WRITE PTB/PTD
ADCx
Freescale Semiconductor, Inc...
PTBx/PTDx
READ PTB/PTD
DISABLE
ADC CHANNEL x
ADC DATA REGISTER
ADC0–ADC11
INTERRUPT
LOGIC
AIEN
CONVERSION
COMPLETE
ADC
ADC VOLTAGE IN
ADCVIN
CHANNEL
SELECT
(1 OF 13 CHANNELS)
ADC12
ADCH[4:0]
ADC CLOCK
COCO
CLOCK
GENERATOR
BUS CLOCK
ADIV[2:0]
Figure 12-2. ADC Block Diagram
12.4.1 ADC Port I/O Pins
PTB0–PTB7 and PTD0–PTD3 are general-purpose I/O pins that are
shared with the ADC channels. The channel select bits (ADC status and
control register, $003C), define which ADC channel/port pin will be used
as the input signal. The ADC overrides the port I/O logic by forcing that
pin as input to the ADC. The remaining ADC channels/port pins are
controlled by the port I/O logic and can be used as general-purpose I/O.
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Writes to the port register or DDR will not have any affect on the port pin
that is selected by the ADC. Read of a port pin which is in use by the
ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the
DDR bit is at logic 1, the value in the port data latch is read.
Freescale Semiconductor, Inc...
12.4.2 Voltage Conversion
When the input voltage to the ADC equals VDD, the ADC converts the
signal to $FF (full scale). If the input voltage equals VSS, the ADC
converts it to $00. Input voltages between VDD and VSS are a straightline linear conversion. All other input voltages will result in $FF if greater
than VDD and $00 if less than VSS.
NOTE:
Input voltage should not exceed the analog supply voltages.
12.4.3 Conversion Time
Fourteen ADC internal clocks are required to perform one conversion.
The ADC starts a conversion on the first rising edge of the ADC internal
clock immediately following a write to the ADSCR. If the ADC internal
clock is selected to run at 1MHz, then one conversion will take 14µs to
complete. With a 1MHz ADC internal clock the maximum sample rate is
71.43kHz.
Conversion Time =
14 ADC Clock Cycles
ADC Clock Frequency
Number of Bus Cycles = Conversion Time × Bus Frequency
12.4.4 Continuous Conversion
In the continuous conversion mode, the ADC continuously converts the
selected channel filling the ADC data register with new data after each
conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until
the ADCO bit is cleared. The COCO bit (ADC status and control register,
$003C) is set after each conversion and can be cleared by writing the
ADC status and control register or reading of the ADC data register.
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Interrupts
12.4.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
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12.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit is at logic 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
12.6 Low-Power Modes
The following subsections describe the ADC in low-power modes.
12.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the ADCH[4:0] bits in the ADC status
and control register to logic 1’s before executing the WAIT instruction.
12.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
12.7 I/O Signals
The ADC module has 12 channels that are shared with I/O port B and
port D, and one channel on ADC12/T2CLK pin.
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12.7.1 ADC Voltage In (ADCVIN)
ADCVIN is the input voltage signal from one of the 13 ADC channels to
the ADC module.
12.8 I/O Registers
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These I/O registers control and monitor ADC operation:
•
ADC status and control register (ADSCR)
•
ADC data register (ADR)
•
ADC clock register (ADICLK)
12.8.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and
control register.
Address:
$003C
Bit 7
Read:
6
5
4
3
2
1
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
0
1
1
1
1
1
COCO
Write:
Reset:
0
= Unimplemented
Figure 12-3. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written or whenever the ADC
data register is read. Reset clears this bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)
When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is
a read-only bit, and will always be logic 0 when read.
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I/O Registers
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
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When set, the ADC will convert samples continuously and update the
ADR register at the end of each conversion. Only one conversion is
allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH[4:0] form a 5-bit field which is used to select one of the ADC
channels. The five channel select bits are detailed in the following
table. Care should be taken when using a port pin as both an analog
and a digital input simultaneously to prevent switching noise from
corrupting the analog signal. (See Table 12-1.)
The ADC subsystem is turned off when the channel select bits are all
set to one. This feature allows for reduced power consumption for the
MCU when the ADC is not used. Reset sets all of these bits to a
logic 1.
NOTE:
Recovery from the disabled state requires one conversion cycle to
stabilize.
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Table 12-1. MUX Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
ADC Channel
Input Select
0
0
0
0
0
ADC0
PTB0
0
0
0
0
1
ADC1
PTB1
0
0
0
1
0
ADC2
PTB2
0
0
0
1
1
ADC3
PTB3
0
0
1
0
0
ADC4
PTB4
0
0
1
0
1
ADC5
PTB5
0
0
1
1
0
ADC6
PTB6
0
0
1
1
1
ADC7
PTB7
0
1
0
0
0
ADC8
PTD3
0
1
0
0
1
ADC9
PTD2
0
1
0
1
0
ADC10
PTD1
0
1
0
1
1
ADC11
PTD0
0
1
1
0
0
ADC12
ADC12/T2CLK
0
1
1
0
1
:
:
:
:
:
—
Unused(1)
1
1
0
1
0
1
1
0
1
1
—
Reserved
1
1
1
0
0
—
Reserved
1
1
1
0
1
VDD(2)
1
1
1
1
0
VSS(2)
1
1
1
1
1
ADC power off
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the
operation of the ADC converter both in production test and for user applications.
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I/O Registers
12.8.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Address:
Read:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
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Write:
Reset:
Indeterminate after reset
= Unimplemented
Figure 12-4. ADC Data Register (ADR)
12.8.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address:
$003E
Bit 7
6
5
ADIV2
ADIV1
ADIV0
0
0
0
Read:
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 12-5. ADC Input Clock Register (ADICLK)
ADIV[2:0] — ADC Clock Prescaler Bits
ADIV[2:0] form a 3-bit field which selects the divide ratio used by the
ADC to generate the internal ADC clock. Table 12-2 shows the
available clock configurations. The ADC clock should be set to
approximately 1MHz.
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Table 12-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
0
0
0
Bus Clock ÷ 1
0
0
1
Bus Clock ÷ 2
0
1
0
Bus Clock ÷ 4
0
1
1
Bus Clock ÷ 8
1
X
X
Bus Clock ÷ 16
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X = don’t care
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Technical Data – MC68HC908JL8
Section 13. Input/Output (I/O) Ports
13.1 Contents
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13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
13.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
13.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . 220
13.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 221
13.3.3 Port A Input Pull-Up Enable Registers . . . . . . . . . . . . . . . . 223
13.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
13.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 224
13.4.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 225
13.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
13.5.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 227
13.5.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 228
13.5.3 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . . 230
13.6 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
13.6.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . 231
13.6.2 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . 232
13.2 Introduction
Twenty six (26) bidirectional input-output (I/O) pins form four parallel
ports. All I/O pins are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
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Addr.
Register Name
$0000
Read:
Port A Data Register
Write:
(PTA)
Reset:
$0001
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$0003
Read:
Port B Data Register
Write:
(PTB)
Reset:
Read:
Port D Data Register
Write:
(PTD)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTD2
PTD1
PTD0
Unaffected by reset
PTB7
PTD7
Read:
DDRD7
Data Direction Register D
$0007
Write:
(DDRD)
Reset:
0
Read:
Data Direction Register E
$000C
Write:
(DDRE)
Reset:
$000D
$000E
PTD6
PTD5
PTB3
PTD4
PTD3
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
PTE1
PTE0
Read:
Port E Data Register
Write:
(PTE)
Reset:
Read:
Port D Control Register
Write:
(PDCR)
Reset:
PTB4
Unaffected by reset
Read:
DDRB7
Data Direction Register B
$0005
Write:
(DDRB)
Reset:
0
$000A
PTB5
Unaffected by reset
Read:
DDRA7
Data Direction Register A
$0004
Write:
(DDRA)
Reset:
0
$0008
PTB6
Unaffected by reset
0
0
0
0
0
0
0
0
0
0
0
0
SLOWD7 SLOWD6 PTDPU7
0
0
0
0
PTDPU6
0
0
DDRE1
DDRE0
0
0
Port A Input Pull-up Read: PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Enable Register Write:
(PTAPUE)
Reset:
0
0
0
0
0
0
0
0
PTA7 Input Pull-up Read: PTAPUE7
Enable Register Write:
(PTA7PUE)
Reset:
0
0
0
0
0
0
0
0
Figure 13-1. I/O Port Register Summary
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Input/Output (I/O) Ports
Introduction
Table 13-1. Port Control Register Bits Summary
Module Control
Port
Bit
DDR
Pin
Module
Freescale Semiconductor, Inc...
Control Bit
0
DDRA0
KBIE0
PTA0/KBI0
1
DDRA1
KBIE1
PTA1/KBI1
2
DDRA2
KBIE2
PTA2/KBI2
KBI
A
Register
KBIER ($001B)
3
DDRA3
KBIE3
PTA3/KBI3
4
DDRA4
KBIE4
PTA4/KBI4
5
DDRA5
KBIE5
PTA5/KBI5
6
DDRA6
OSC
KBI
PTAPUE ($000D)
KBIER ($001B)
PTA6EN
KBIE6
RCCLK/PTA6/KBI6(1)
7
DDRA7
KBI
KBIER ($001B)
KBIE7
PTA7/KBI7
0
DDRB0
PTB0/ADC0
1
DDRB1
PTB1/ADC1
2
DDRB2
PTB2/ADC2
3
DDRB3
B
PTB3/ADC3
ADC
ADSCR ($003C)
ADCH[4:0]
4
DDRB4
PTB4/ADC4
5
DDRB5
PTB5/ADC5
6
DDRB6
PTB6/ADC6
7
DDRB7
PTB7/ADC7
0
DDRD0
PTD0/ADC11
1
DDRD1
PTD1/ADC10
ADC
ADSCR ($003C)
ADCH[4:0]
2
DDRD2
PTD2/ADC9
3
DDRD3
PTD3/ADC8
4
DDRD4
D
T1SC0 ($0025)
ELS0B:ELS0A
PTD4/T1CH0
T1SC1 ($0028)
ELS1B:ELS1A
PTD5/T1CH1
SCC1 ($0013)
ENSCI
TIM1
5
DDRD5
6
DDRD6
PTD6/TxD
SCI
7
DDRD7
0
DDRE0
PTD7/RxD
T2SC0 ($0035)
ELS0B:ELS0A
PTE0/T2CH0
T2SC1 ($0038)
ELS1B:ELS1A
PTE1/T2CH1
TIM2
E
1
DDRE1
NOTES:
1. RCCLK/PTA6/KBI6 pin is only available when OSCSEL=0 (RC option);
PTAPUE register has priority control over the port pin.
RCCLK/PTA6/KBI6 is the OSC2 pin when OSCSEL=1 (XTAL option).
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13.3 Port A
Port A is an 8-bit special function port that shares all of its pins with the
keyboard interrupt (KBI) module (see Section 15. Keyboard Interrupt
Module (KBI)). Each port A pin also has software configurable pull-up
device if the corresponding port pin is configured as input port.
PTA0–PTA5 and PTA7 has direct LED drive capability.
Freescale Semiconductor, Inc...
NOTE:
PTA0–PTA5 pins are available on 28-pin and 32-pin packages only.
PTA7 pin is available on 32-pin packages only.
13.3.1 Port A Data Register (PTA)
The port A data register (PTA) contains a data latch for each of the eight
port A pins.
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Read:
Write:
Reset:
Additional Functions:
Unaffected by Reset
LED
(Sink)
pull-up
Alternative Functions:
pull-up
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
Figure 13-2. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
KBI7–KBI0 — Port A Keyboard Interrupts
The keyboard interrupt enable bits, KBIE[7:0], in the keyboard
interrupt control register (KBIER) enable the port A pins as external
interrupt pins, (see Section 15. Keyboard Interrupt Module (KBI)).
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Port A
13.3.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
NOTE:
For those devices packaged in a 28-pin package, PTA7 is not
connected. DDRA7 should be set to a 1 to configure PTA7 as an output.
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For those devices packaged in a 20-pin package, PTA0–PTA5 and
PTA7 are not connected. DDRA0–DDRA5 and DDRA7 should be set to
a 1 to configure PTA0–PTA5 and PTA7 as outputs.
Address:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 13-3. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 13-4 shows the port A I/O logic.
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READ DDRA ($0004)
PTAPUEx
INTERNAL DATA BUS
WRITE DDRA ($0004)
RESET
DDRAx
WRITE PTA ($0000)
PTAx
PTAx
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READ PTA ($0000)
To KBI
Figure 13-4. Port A I/O Circuit
When DDRAx is a logic 1, reading address $0000 reads the PTAx data
latch. When DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
Table 13-2 summarizes the operation of the port A pins.
Table 13-2. Port A Pin Functions
PTAPUE
Bit
DDRA
Bit
PTA Bit
1
0
X(1)
0
0
X
1
I/O Pin
Mode
Accesses to DDRA
Accesses to PTA
Read/Write
Read
Write
Input, VDD(2)
DDRA[7:0]
Pin
PTA[7:0](3)
X
Input, Hi-Z(4)
DDRA[7:0]
Pin
PTA[7:0](3)
X
Output
DDRA[7:0]
PTA[7:0]
PTA[7:0]
NOTES:
1. X = Don’t care.
2. Pin pulled to VDD by internal pull-up.
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance.
Technical Data
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Input/Output (I/O) Ports
Port A
13.3.3 Port A Input Pull-Up Enable Registers
The port A input pull-up enable registers contain a software configurable
pull-up device for each of the eight port A pins. Each bit is individually
configurable and requires the corresponding data direction register,
DDRAx be configured as input. Each pull-up device is automatically
disabled when its corresponding DDRAx bit is configured as output.
Address:
$000D
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Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 13-5. Port A Input Pull-up Enable Register (PTAPUE)
Address:
$000E
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
Read:
PTAPUE7
Write:
Reset:
0
Figure 13-6. PTA7 Input Pull-up Enable Register (PTA7PUE)
PTA6EN — Enable PTA6 on OSC2
This read/write bit configures the OSC2 pin function when RC
oscillator option is selected. This bit has no effect for XTAL oscillator
option.
1 = OSC2 pin configured for PTA6 I/O, and has all the interrupt and
pull-up functions
0 = OSC2 pin outputs the RC oscillator clock (RCCLK)
PTAPUE[7:0] — Port A Input Pull-up Enable Bits
These read/write bits are software programmable to enable pull-up
devices on port A pins.
1 = Corresponding port A pin configured to have internal pull-up if
its DDRA bit is set to 0
0 = Pull-up device is disconnected on the corresponding port A pin
regardless of the state of its DDRA bit
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13.4 Port B
Port B is an 8-bit special function port that shares all of its port pins with
the analog-to-digital converter (ADC) module, see Section 12.
13.4.1 Port B Data Register (PTB)
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The port B data register contains a data latch for each of the eight port B
pins.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
ADC2
ADC2
ADC0
Read:
Write:
Reset:
Alternative Functions:
Unaffected by reset
ADC7
ADC6
ADC5
ADC4
ADC3
Figure 13-7. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
ADC7–ADC0 — ADC channels 7 to 0
ADC7–ADC0 are pins used for the input channels to the analog-todigital converter module. The channel select bits, ADCH[4:0], in the
ADC status and control register define which port pin will be used as
an ADC input and overrides any control from the port I/O logic. See
Section 12. Analog-to-Digital Converter (ADC).
Technical Data
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Port B
13.4.2 Data Direction Register B (DDRB)
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
Address:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
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Read:
Write:
Reset:
Figure 13-8. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 13-9 shows
the port B I/O logic.
READ DDRB ($0005)
INTERNAL DATA BUS
WRITE DDRB ($0005)
RESET
DDRBx
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
To Analog-To-Digital Converter
Figure 13-9. Port B I/O Circuit
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When DDRBx is a logic 1, reading address $0001 reads the PTBx data
latch. When DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 13-3 summarizes the operation
of the port B pins.
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Table 13-3. Port B Pin Functions
I/O Pin
Mode
Accesses to DDRB
Read/Write
Read
Write
X(1)
Input, Hi-Z(2)
DDRB[7:0]
Pin
PTB[7:0](3)
X
Output
DDRB[7:0]
PTB[7:0]
PTB[7:0]
DDRB
Bit
PTB Bit
0
1
Accesses to PTB
NOTES:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
Technical Data
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Input/Output (I/O) Ports
Port D
13.5 Port D
Port D is an 8-bit special function port that shares two of its pins with the
serial communications interface module (see Section 11.), two of its
pins with the timer 1 interface module, (see Section 10.), and four of its
pins with the analog-to-digital converter module (see Section 12.).
PTD6 and PTD7 each has high current sink (25mA) and programmable
pull-up. PTD2, PTD3, PTD6 and PTD7 each has LED sink capability.
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NOTE:
PTD0–PTD1 are available on 28-pin and 32-pin packages only.
13.5.1 Port D Data Register (PTD)
The port D data register contains a data latch for each of the eight port D
pins.
Address:
$0003
Bit 7
6
5
4
3
2
1
Bit 0
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
ADC10
ADC11
Read:
Write:
Reset:
Additional Functions
Unaffected by reset
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
ADC8
ADC9
25mA sink 25mA sink
(Slow Edge) (Slow Edge)
Alternative Functions:
pull-up
pull-up
RxD
TxD
T1CH1
T1CH0
Figure 13-10. Port D Data Register (PTD)
PTD[7:0] — Port D Data Bits
These read/write bits are software programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
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ADC11–ADC8 — ADC channels 11 to 8
ADC[11:8] are pins used for the input channels to the analog-to-digital
converter module. The channel select bits, ADCH[4:0], in the ADC
status and control register define which port pin will be used as an
ADC input and overrides any control from the port I/O logic. See
Section 12. Analog-to-Digital Converter (ADC).
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T1CH1, T1CH0 — Timer 1 Channel I/Os
The T1CH1 and T1CH0 pins are the TIM1 input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTD4/T1CH0 and PTD5/T1CH1 pins are timer channel
I/O pins or general-purpose I/O pins. See Section 10. Timer
Interface Module (TIM).
TxD, RxD — SCI Data I/O Pins
The TxD and RxD pins are the transmit data output and receive data
input for the SCI module. The enable SCI bit, ENSCI, in the SCI
control register 1 enables the PTD6/TxD and PTD7/RxD pins as SCI
TxD and RxD pins and overrides any control from the port I/O logic.
See Section 11. Serial Communications Interface (SCI).
13.5.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
NOTE:
For those devices packaged in a 20-pin package, PTD0–PTD1 and are
not connected. DDRD0–DDRD1 should be set to a 1 to configure
PTD0–PTD1 as outputs.
Address:
$0007
Bit 7
6
5
4
3
2
1
Bit 0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 13-11. Data Direction Register D (DDRD)
Technical Data
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Port D
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
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NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1. Figure 13-12 shows
the port D I/O logic.
READ DDRD ($0007)
PTDPU[6:7]
INTERNAL DATA BUS
WRITE DDRD ($0007)
RESET
DDRDx
WRITE PTD ($0003)
PTDx
PTDx
READ PTD ($0003)
To ADC, TIM1, SCI
Figure 13-12. Port D I/O Circuit
When DDRDx is a logic 1, reading address $0003 reads the PTDx data
latch. When DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 13-4 summarizes the operation
of the port D pins.
Table 13-4. Port D Pin Functions
DDRD
Bit
PTD Bit
0
X(1)
1
X
I/O Pin
Mode
Accesses to DDRD
Accesses to PTD
Read/Write
Read
Write
Input, Hi-Z(2)
DDRD[7:0]
Pin
PTD[7:0](3)
Output
DDRD[7:0]
PTD[7:0]
PTD[7:0]
NOTES:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
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13.5.3 Port D Control Register (PDCR)
The port D control register enables/disables the pull-up resistor and
slow-edge high current capability of pins PTD6 and PTD7.
Address:
Read:
$000A
Bit 7
6
5
4
0
0
0
0
3
2
1
Bit 0
SLOWD7 SLOWD6 PTDPU7
PTDPU6
Write:
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Reset:
0
0
0
0
0
0
0
0
Figure 13-13. Port D Control Register (PDCR)
SLOWDx — Slow Edge Enable
The SLOWD6 and SLOWD7 bits enable the slow-edge, open-drain,
high current output (25mA sink) of port pins PTD6 and PTD7
respectively. DDRDx bit is not affected by SLOWDx.
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull (standard I/O)
PTDPUx — Port D Pull-up Enable Bits
The PTDPU6 and PTDPU7 bits enable the pull-up device on PTD6
and PTD7 respectively, regardless the status of DDRDx bit.
1 = Enable pull-up device
0 = Disable pull-up device
Technical Data
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Port E
13.6 Port E
Port E is a 2-bit special function port that shares its pins with the timer 2
interface module (see Section 10.).
NOTE:
PTE0–PTE1 are available on 32-pin packages only.
13.6.1 Port E Data Register (PTE)
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The port E data register contains a data latch for each of the two port E
pins.
Address:
$0008
Bit 7
6
5
4
3
2
1
Bit 0
PTE1
PTE0
T2CH1
T2CH0
Read:
Write:
Reset:
Unaffected by reset
Alternative Functions:
Figure 13-14. Port E Data Register (PTE)
PTE[1:0] — Port E Data Bits
These read/write bits are software programmable. Data direction of
each port E pin is under the control of the corresponding bit in data
direction register E. Reset has no effect on port D data.
T2CH1, T2CH0 — Timer 2 Channel I/Os
The T2CH1 and T2CH0 pins are the TIM2 input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTE0/T2CH0 and PTE1/T2CH1 pins are timer channel
I/O pins or general-purpose I/O pins. See Section 10. Timer
Interface Module (TIM).
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13.6.2 Data Direction Register E (DDRE)
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
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NOTE:
For those devices packaged in a 20-pin package and 28-pin package,
PTE0–PTE1 are not connected. DDRE0–DDRE1 should be set to a 1 to
configure PTE0–PTE1 as outputs.
Address:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
DDRE1
DDRE0
0
0
Read:
Write:
Reset:
0
0
0
0
0
0
Figure 13-15. Data Direction Register E (DDRE)
DDRE[1:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[1:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE:
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1. Figure 13-16 shows
the port E I/O logic.
Technical Data
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Input/Output (I/O) Ports
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Port E
READ DDRE ($000C)
INTERNAL DATA BUS
WRITE DDRE ($000C)
RESET
DDREx
WRITE PTE ($0008)
PTEx
PTEx
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READ PTE ($0008)
To TIM2
Figure 13-16. Port E I/O Circuit
When DDREx is a logic 1, reading address $0008 reads the PTEx data
latch. When DDREx is a logic 0, reading address $0008 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 13-5 summarizes the operation
of the port E pins.
Table 13-5. Port E Pin Functions
DDRE
Bit
PTE Bit
0
X(1)
1
X
I/O Pin
Mode
Accesses to DDRE
Accesses to PTE
Read/Write
Read
Write
Input, Hi-Z(2)
DDRE[1:0]
Pin
PTE[1:0](3)
Output
DDRE[1:0]
PTE[1:0]
PTE[1:0]
NOTES:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
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Technical Data – MC68HC908JL8
Section 14. External Interrupt (IRQ)
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14.1 Contents
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
14.4.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
14.5
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .239
14.6
IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 239
14.2 Introduction
The external interrupt (IRQ) module provides a maskable interrupt input.
14.3 Features
Features of the IRQ module include the following:
•
A dedicated external interrupt pin (IRQ)
•
IRQ interrupt control bits
•
Hysteresis buffer
•
Programmable edge-only or edge and level interrupt sensitivity
•
Automatic interrupt acknowledge
•
Selectable internal pullup resistor
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External Interrupt (IRQ)
14.4 Functional Description
A logic zero applied to the external interrupt pin can latch a CPU interrupt
request. Figure 14-1 shows the structure of the IRQ module.
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Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the IRQ latch.
•
Software clear — Software can clear the interrupt latch by writing
to the acknowledge bit in the interrupt status and control register
(INTSCR). Writing a logic one to the ACK bit clears the IRQ latch.
•
Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be either falling-edge or falling-edge and low-leveltriggered. The MODE bit in the INTSCR controls the triggering sensitivity
of the IRQ pin.
When the interrupt pin is edge-triggered only, the CPU interrupt request
remains set until a vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the
CPU interrupt request remains set until both of the following occur:
•
Vector fetch or software clear
•
Return of the interrupt pin to logic one
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic one. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK bit is clear.
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External Interrupt (IRQ)
Functional Description
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See 7.6
Exception Control.)
RESET
INTERNAL ADDRESS BUS
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ACK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
IRQPUD
INTERNAL
PULLUP
DEVICE
VDD
IRQF
D
CLR
Q
IRQ
INTERRUPT
REQUEST
SYNCHRONIZER
CK
IRQ
IMASK
MODE
TO MODE
SELECT
LOGIC
HIGH
VOLTAGE
DETECT
Figure 14-1. IRQ Module Block Diagram
Addr.
$001D
Register Name
Read:
IRQ Status and Control
Register Write:
(INTSCR)
Reset:
Bit 7
6
5
4
3
2
0
0
0
0
IRQF
0
1
Bit 0
IMASK
MODE
0
0
ACK
0
0
0
0
0
0
= Unimplemented
Figure 14-2. IRQ I/O Register Summary
14.4.1 IRQ Pin
A logic zero on the IRQ pin can latch an interrupt request into the IRQ
latch. A vector fetch, software clear, or reset clears the IRQ latch.
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External Interrupt (IRQ)
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If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive. With MODE set, both of the following actions must occur
to clear IRQ:
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic one to
the ACK bit in the interrupt status and control register (INTSCR).
The ACK bit is useful in applications that poll the IRQ pin and
require software to clear the IRQ latch. Writing to the ACK bit prior
to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent
transitions on the IRQ pin. A falling edge that occurs after writing
to the ACK bit latches another interrupt request. If the IRQ mask
bit, IMASK, is clear, the CPU loads the program counter with the
vector address at locations $FFFA and $FFFB.
•
Return of the IRQ pin to logic one — As long as the IRQ pin is at
logic zero, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic
one may occur in any order. The interrupt request remains pending as
long as the IRQ pin is at logic zero. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
The IRQF bit in the INTSCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
NOTE:
An internal pull-up resistor to VDD is connected to the IRQ pin; this can
be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
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External Interrupt (IRQ)
IRQ Module During Break Interrupts
14.5 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can
be cleared during the break state. The BCFE bit in the break flag control
register (BFCR) enables software to clear the latches during the break
state. (See Section 7. System Integration Module (SIM).)
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To allow software to clear the IRQ latch during a break interrupt, write a
logic one to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic zero to the
BCFE bit. With BCFE at logic zero (its default state), writing to the ACK
bit in the IRQ status and control register during the break state has no
effect on the IRQ latch.
14.6 IRQ Status and Control Register (INTSCR)
The IRQ status and control register (INTSCR) controls and monitors
operation of the IRQ module. The INTSCR has the following functions:
•
Shows the state of the IRQ flag
•
Clears the IRQ latch
•
Masks IRQ and interrupt request
•
Controls triggering sensitivity of the IRQ interrupt pin
Address:
Read:
$001D
Bit 7
6
5
4
3
0
0
0
0
IRQF
Write:
Reset:
2
1
Bit 0
IMASK
MODE
0
0
ACK
0
0
0
0
0
0
= Unimplemented
Figure 14-3. IRQ Status and Control Register (INTSCR)
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External Interrupt (IRQ)
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic one to this write-only bit clears the IRQ latch. ACK
always reads as logic zero. Reset clears ACK.
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IMASK — IRQ Interrupt Mask Bit
Writing a logic one to this read/write bit disables IRQ interrupt
requests. Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
IRQPUD
R
R
LVIT1
LVIT0
R
R
R
Reset:
0
0
0
Not affected
Not affected
0
0
0
POR:
0
0
0
0
0
0
0
0
Read:
Write:
R
= Reserved
Figure 14-4. Configuration Register 2 (CONFIG2)
IRQPUD — IRQ Pin Pull-Up Disable Bit
IRQPUD disconnects the internal pull-up on the IRQ pin.
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ pin and VDD
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Technical Data – MC68HC908JL8
Section 15. Keyboard Interrupt Module (KBI)
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15.1 Contents
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
15.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
15.4
I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
15.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
15.5.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
15.6 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . 245
15.6.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 246
15.6.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 247
15.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
15.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
15.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
15.8
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .248
15.2 Introduction
The keyboard interrupt module (KBI) provides eight independently
maskable external interrupts which are accessible via PTA0–PTA7.
When a port pin is enabled for keyboard interrupt function, an internal
pull-up device is also enabled on the pin.
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Keyboard Interrupt Module (KBI)
15.3 Features
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Features of the keyboard interrupt module include the following:
•
Eight keyboard interrupt pins with pull-up devices
•
Separate keyboard interrupt enable bits and one keyboard
interrupt mask
•
Programmable edge-only or edge- and level- interrupt sensitivity
•
Exit from low-power modes
Addr.
Register Name
$001A
Read:
Keyboard Status and
Control Register Write:
(KBSCR)
Reset:
$001B
Read:
Keyboard Interrupt
Enable Register Write:
(KBIER)
Reset:
Bit 7
6
5
4
3
2
0
0
0
0
KEYF
0
1
Bit 0
IMASKK
MODEK
ACKK
0
0
0
0
0
0
0
0
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-1. KBI I/O Register Summary
15.4 I/O Pins
The eight keyboard interrupt pins are shared with standard port I/O pins.
The full name of the KBI pins are listed in Table 15-1. The generic pin
name appear in the text that follows.
Table 15-1. Pin Name Conventions
KBI
Generic Pin Name
Full MCU Pin Name
Pin Selected for KBI Function by
KBIEx Bit in KBIER
KBI0–KBI5
PTA0/KBI0–PTA5/KBI5
KBIE0–KBIE5
KBI6
OSC2/RCCLK/PTA6/KBI6(1)
KBIE6
KBI7
PTA7/KBI7
KBIE7
NOTES:
1. PTA6/KBI6 is only available when OSCSEL=0 at $FFD0 (RC option), and PTA6EN=1 at $000D.
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Keyboard Interrupt Module (KBI)
Functional Description
15.5 Functional Description
INTERNAL BUS
KBI0
ACKK
VDD
VECTOR FETCH
DECODER
KEYF
RESET
.
KBIE0
D
Q
SYNCHRONIZER
.
CK
TO PULLUP ENABLE
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CLR
.
KEYBOARD
INTERRUPT FF
KBI7
Keyboard
Interrupt
Request
IMASKK
MODEK
KBIE7
TO PULLUP ENABLE
Figure 15-2. Keyboard Interrupt Block Diagram
Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register
independently enables or disables each port A pin as a keyboard
interrupt pin. Enabling a keyboard interrupt pin in port A also enables its
internal pull-up device regardless of PTAPUEx bits in the port A input
pull-up enable register (see 13.3.3 Port A Input Pull-Up Enable
Registers). A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes
low after all were high. The MODEK bit in the keyboard status and
control register controls the triggering mode of the keyboard interrupt.
•
If the keyboard interrupt is edge-sensitive only, a falling edge on a
keyboard pin does not latch an interrupt request if another
keyboard pin is already low. To prevent losing an interrupt request
on one pin because another pin is still low, software can disable
the latter pin while it is low.
•
If the keyboard interrupt is falling edge- and low level-sensitive, an
interrupt request is present as long as any keyboard pin is low.
If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to
clear a keyboard interrupt request:
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Keyboard Interrupt Module (KBI)
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register KBSCR. The ACKK bit is useful in applications that poll
the keyboard interrupt pins and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFE0 and
$FFE1.
•
Return of all enabled keyboard interrupt pins to logic 1 — As long
as any enabled keyboard interrupt pin is at logic 0, the keyboard
interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, disable the pullup device, use the data direction register to configure the pin as an input
and then read the data register.
NOTE:
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.
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Keyboard Interrupt Module (KBI)
Keyboard Interrupt Registers
15.5.1 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal
pull-up to reach a logic 1. Therefore a false interrupt can occur as soon
as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the
keyboard status and control register.
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2. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register
to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRA bits in the data direction register A.
2. Write logic 1’s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
15.6 Keyboard Interrupt Registers
Two registers control the operation of the keyboard interrupt module:
•
Keyboard status and control register
•
Keyboard interrupt enable register
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15.6.1 Keyboard Status and Control Register
•
Flags keyboard interrupt requests
•
Acknowledges keyboard interrupt requests
•
Masks keyboard interrupt requests
•
Controls keyboard interrupt triggering sensitivity
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Address:
Read:
$001A
Bit 7
6
5
4
3
2
0
0
0
0
KEYF
0
Write:
Reset:
1
Bit 0
IMASKK
MODEK
0
0
ACKK
0
0
0
0
0
0
= Unimplemented
Figure 15-3. Keyboard Status and Control Register (KBSCR)
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on
port A. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt
request on port A. ACKK always reads as logic 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests on port A.
Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins on port A. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
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Keyboard Interrupt Module (KBI)
Low-Power Modes
15.6.2 Keyboard Interrupt Enable Register
The port-A keyboard interrupt enable register enables or disables each
port-A pin to operate as a keyboard interrupt pin.
Address:
$001B
Bit 7
6
5
4
3
2
1
Bit 0
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
Read:
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Write:
Reset:
Figure 15-4. Keyboard Interrupt Enable Register (KBIER)
KBIE7–KBIE0 — Port-A Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard
interrupt pin on port-A to latch interrupt requests. Reset clears the
keyboard interrupt enable register.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
15.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
15.7.1 Wait Mode
The keyboard modules remain active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
15.7.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
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15.8 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard
interrupt latch can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state.
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To allow software to clear the keyboard interrupt latch during a break
interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the
break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the keyboard
acknowledge bit (ACKK) in the keyboard status and control register
during the break state has no effect.
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Technical Data – MC68HC908JL8
Section 16. Computer Operating Properly (COP)
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16.1 Contents
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
16.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
16.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.4.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.4.4 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
16.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
16.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
16.4.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 252
16.5
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
16.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
16.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
16.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .254
16.2 Introduction
The computer operating properly (COP) module contains a free-running
counter that generates a reset if allowed to overflow. The COP module
helps software recover from runaway code. Prevent a COP reset by
clearing the COP counter periodically. The COP module can be disabled
through the COPD bit in the CONFIG1 register.
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16.3 Functional Description
Figure 16-1 shows the structure of the COP module.
SIM
RESET VECTOR FETCH
RESET STATUS REGISTER
COP TIMEOUT
CLEAR STAGES 5–12
CLEAR ALL STAGES
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INTERNAL RESET SOURCES(1)
SIM RESET CIRCUIT
12-BIT SIM COUNTER
ICLK
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COPD (FROM CONFIG1)
RESET
COPCTL WRITE
CLEAR
COP COUNTER
COP RATE SEL
(COPRS FROM CONFIG1)
NOTE:
1. See SIM section for more details.
Figure 16-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by the 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
218 – 24 or 213 – 24 ICLK cycles; depending on the state of the COP rate
select bit, COPRS, in configuration register 1. Writing any value to
location $FFFF before an overflow occurs prevents a COP reset by
clearing the COP counter and stages 12 through 5 of the SIM counter.
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
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Computer Operating Properly (COP)
I/O Signals
A COP reset pulls the RST pin low for 32 × ICLK cycles and sets the
COP bit in the reset status register (RSR). (See 7.8.2 Reset Status
Register (RSR).).
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NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
16.4 I/O Signals
The following paragraphs describe the signals shown in Figure 16-1.
16.4.1 ICLK
ICLK is the internal oscillator output signal, typically 50-kHz. The ICLK
frequency varies depending on the supply voltage. See Section 19.
Electrical Specifications for ICLK parameters.
16.4.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 16.5 COP
Control Register) clears the COP counter and clears bits 12 through 5
of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
16.4.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter
4096 × ICLK cycles after power-up.
16.4.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
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16.4.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the SIM counter.
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16.4.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register 1 (CONFIG1). (See Section 5. Configuration
and Mask Option Registers (CONFIG & MOR).)
16.4.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the configuration register 1.
Address:
$001F
Bit 7
6
5
4
3
2
1
Bit 0
COPRS
R
R
LVID
R
SSREC
STOP
COPD
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
R
= Reserved
Figure 16-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
1 = COP timeout period is (213 – 24) ICLK cycles
0 = COP timeout period is (218 – 24) ICLK cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
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Computer Operating Properly (COP)
COP Control Register
16.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address:
$FFFF
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Bit 7
6
5
4
3
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
2
1
Bit 0
Figure 16-3. COP Control Register (COPCTL)
16.6 Interrupts
The COP does not generate CPU interrupt requests.
16.7 Monitor Mode
The COP is disabled in monitor mode when VTST is present on the IRQ
pin or on the RST pin.
16.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
16.8.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP
reset during wait mode, periodically clear the COP counter in a CPU
interrupt routine.
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16.8.2 Stop Mode
Stop mode turns off the ICLK input to the COP if the STOP_ICLKDIS bit
is set in configuration register 2 (CONFIG2). Service the COP
immediately before entering or after exiting stop mode to ensure a full
COP timeout period after entering or exiting stop mode.
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After reset, the STOP_ICLKDIS bit is clear by default and ICLK is
enabled during stop mode.
16.9 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on
the RST pin.
Technical Data
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Section 17. Low Voltage Inhibit (LVI)
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17.1 Contents
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
17.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
17.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
17.5
LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . 257
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
17.2 Introduction
This section describes the low-voltage inhibit module (LVI), which
monitors the voltage on the VDD pin and generates a reset when the VDD
voltage falls to the LVI trip (LVITRIP) voltage.
17.3 Features
Features of the LVI module include the following:
•
Selectable LVI trip voltage
•
Selectable LVI circuit disable
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Low Voltage Inhibit (LVI)
17.4 Functional Description
Figure 17-1 shows the structure of the LVI module. The LVI is enabled
after a reset. The LVI module contains a bandgap reference circuit and
comparator. Setting LVI disable bit (LVID) disables the LVI to monitor
VDD voltage. The LVI trip voltage selection bits (LVIT1, LVIT0) determine
at which VDD level the LVI module should take actions.
The LVI module generates one output signal:
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LVI Reset — an reset signal will be generated to reset the CPU when
VDD drops to below the set trip point.
VDD
LVID
VDD > LVITRIP = 0
LOW VDD
LVI RESET
VDD < LVITRIP = 1
DETECTOR
LVIT1
LVIT0
Figure 17-1. LVI Module Block Diagram
Technical Data
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Low Voltage Inhibit (LVI)
LVI Control Register (CONFIG2/CONFIG1)
17.5 LVI Control Register (CONFIG2/CONFIG1)
The LVI module is controlled by three bits in the configuration registers,
CONFIG1 and CONFIG2.
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
IRQPUD
R
R
LVIT1
LVIT0
R
R
STOP_
ICLKDIS
Reset:
0
0
0
Not affected
Not affected
0
0
0
POR:
0
0
0
0
0
0
0
0
Read:
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Write:
Figure 17-2. Configuration Register 2 (CONFIG2)
Address:
$001F
Bit 7
6
5
4
3
2
1
Bit 0
COPRS
R
R
LVID
R
SSREC
STOP
COPD
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
R
= Reserved
Figure 17-3. Configuration Register 1 (CONFIG1)
LVID — Low Voltage Inhibit Disable Bit
LVID disables the LVI module. Reset clears LVID.
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
LVIT1, LVIT0 — LVI Trip Voltage Selection Bits
These two bits determine at which level of VDD the LVI module will
come into action. LVIT1 and LVIT0 are cleared by a power-on reset
only.
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Low Voltage Inhibit (LVI)
Table 17-1. Trip Voltage Selection
LVIT1
LVIT0
Trip Voltage(1)
Comments
0
0
VLVR3 (2.49V)
For VDD =3V operation
0
1
VLVR3 (2.49V)
For VDD =3V operation
1
0
VLVR5 (4.25V)
For VDD =5V operation
1
1
Reserved
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NOTES:
1. See Section 19. Electrical Specifications for full parameters.
17.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-powerconsumption standby modes.
17.6.1 Wait Mode
The LVI module, when enabled, will continue to operate in wait mode.
17.6.2 Stop Mode
The LVI module, when enabled, will continue to operate in stop mode.
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Section 18. Break Module (BREAK)
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18.1 Contents
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
18.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .262
18.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 262
18.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 262
18.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 262
18.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
18.5.1 Break Status and Control Register (BRKSCR) . . . . . . . . . 263
18.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .264
18.5.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
18.5.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 266
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
18.2 Introduction
This section describes the break module. The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.
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18.3 Features
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Features of the break module include the following:
•
Accessible I/O registers during the break Interrupt
•
CPU-generated break interrupts
•
Software-generated break interrupts
•
COP disabling during break interrupts
18.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the SIM. The SIM then causes the CPU to load the instruction register
with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD
($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
•
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
•
Software writes a logic one to the BRKA bit in the break status and
control register.
When a CPU generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return from interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 18-1 shows the structure of the break module.
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Break Module (BREAK)
Functional Description
IAB[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
BKPT
(TO SIM)
CONTROL
8-BIT COMPARATOR
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BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 18-1. Break Module Block Diagram
Addr.
$FE00
Register Name
Read:
Break Status Register
Write:
(BSR)
Reset:
Read:
Break Flag Control
Register Write:
(BFCR)
Reset:
$FE03
$FE0C
Read:
Break Address High
Register Write:
(BRKH)
Reset:
$FE0D
Read:
Break Address low
Register Write:
(BRKL)
Reset:
Read:
Break Status and Control
$FE0E
Register Write:
(BRKSCR)
Reset:
Note: Writing a logic 0 clears SBSW.
Bit 7
6
5
4
3
2
R
R
R
R
R
R
1
SBSW
See note
Bit 0
R
0
BCFE
R
R
R
R
R
R
R
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
R
0
= Reserved
Figure 18-2. Break I/O Register Summary
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Break Module (BREAK)
18.4.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module
status bits can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state. (See 7.8.3 Break Flag Control Register (BFCR)
and see the Break Interrupts subsection for each module.)
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18.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
Loading the instruction register with the SWI instruction
•
Loading the program counter with $FFFC:$FFFD
($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
18.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
18.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VTST is present on
the RST pin.
18.5 Break Module Registers
These registers control and monitor operation of the break module:
•
Break status and control register (BRKSCR)
•
Break address register high (BRKH)
•
Break address register low (BRKL)
•
Break status register (BSR)
•
Break flag control register (BFCR)
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Break Module (BREAK)
Break Module Registers
18.5.1 Break Status and Control Register (BRKSCR)
The break status and control register contains break module enable and
status bits.
Address:
$FE0E
Bit 7
6
BRKE
BRKA
0
0
Read:
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
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Write:
Reset:
= Unimplemented
Figure 18-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic zero to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic one to BRKA generates a break
interrupt. Clear BRKA by writing a logic zero to it before exiting the
break routine. Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
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18.5.2 Break Address Registers
The break address registers contain the high and low bytes of the
desired breakpoint address. Reset clears the break address registers.
Address:
$FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
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Write:
Reset:
Figure 18-4. Break Address Register High (BRKH)
Address:
$FE0D
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 18-5. Break Address Register Low (BRKL)
18.5.3 Break Status Register
The break status register contains a flag to indicate that a break caused
an exit from stop or wait mode.
Address:
$FE00
Bit 7
6
5
4
3
2
R
R
R
R
R
R
Read:
1
Bit 0
SBSW
Write:
Note(1)
Reset:
0
R
= Reserved
R
1. Writing a logic zero clears SBSW.
Figure 18-6. Break Status Register (BSR)
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Break Module (BREAK)
Break Module Registers
SBSW — SIM Break Stop/Wait
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This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE
EQU
5
LOBYTE
EQU
6
;
If not SBSW, do RTI
BRCLR
SBSW,BSR, RETURN
; See if wait mode or stop mode was exited
; by break.
TST
LOBYTE,SP
; If RETURNLO is not zero,
BNE
DOLO
; then just decrement low byte.
DEC
HIBYTE,SP
; Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN
PULH
RTI
; Restore H register.
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Break Module (BREAK)
18.5.4 Break Flag Control Register (BFCR)
The break control register contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
Read:
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Write:
Reset:
0
R
= Reserved
Figure 18-7. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
18.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
18.6.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set (see 7.7 Low-Power Modes). Clear the SBSW bit by writing logic
zero to it.
18.6.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in
the break status register. See 7.8 SIM Registers.
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Section 19. Electrical Specifications
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19.1 Contents
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
19.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .268
19.4
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 269
19.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
19.6
5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 270
19.7
5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
19.8
5V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 272
19.9
3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 273
19.10 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
19.11 3V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 275
19.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
19.13 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 277
19.14 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
19.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
19.2 Introduction
This section contains electrical and timing specifications.
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19.3 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to Sections 19.6 and 19.9 for guaranteed operating
conditions.
Table 19-1. Absolute Maximum Ratings
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Characteristic(1)
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +6.0
V
Input voltage
VIN
VSS –0.3 to VDD +0.3
V
VTST
VSS –0.3 to +8.5
V
I
± 25
mA
Storage temperature
TSTG
–55 to +150
°C
Maximum current out of VSS
IMVSS
100
mA
Maximum current into VDD
IMVDD
100
mA
Mode entry voltage, IRQ pin
Maximum current per pin
excluding VDD and VSS
NOTES:
1. Voltages referenced to VSS.
NOTE:
This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD.)
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Functional Operating Range
19.4 Functional Operating Range
Table 19-2. Operating Range
Characteristic
Operating temperature range
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Operating voltage range
Symbol
Value
Unit
TA
– 40 to +125
– 40 to +85
°C
VDD
—
5 ± 10%
3 ± 10%
5 ± 10%
V
19.5 Thermal Characteristics
Table 19-3. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
20-pin PDIP
20-pin SOIC
28-pin PDIP
28-pin SOIC
32-pin SDIP
32-pin LQFP
θJA
I/O pin power dissipation
PI/O
User determined
W
Power dissipation(1)
PD
PD = (IDD × VDD) + PI/O =
K/(TJ + 273 °C)
W
Constant(2)
K
Average junction temperature
TJ
70
70
70
70
70
95
°C/W
PD x (TA + 273 °C)
+ PD2 × θJA
TA + (PD × θJA)
W/°C
°C
NOTES:
1. Power dissipation is a function of temperature.
2. K constant unique to the device. K can be determined for a known TA and measured PD.
With this value of K, PD and TJ can be determined for any value of TA.
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19.6 5V DC Electrical Characteristics
Table 19-4. DC Electrical Characteristics (5V)
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Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage (ILOAD = –2.0mA)
PTA0–PTA7, PTB0–PTB7, PTD0–PTD7,
PTE0–PTE1
VOH
VDD –0.8
—
—
V
Output low voltage (ILOAD = 1.6mA)
PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5,
PTE0–PTE1
VOL
—
—
0.4
V
Output low voltage (ILOAD = 25mA)
PTD6, PTD7
VOL
—
—
0.5
V
LED drives (VOL = 3V)
PTA0–PTA5, PTA7, PTD2, PTD3, PTD6, PTD7
IOL
10
16
25
mA
Input high voltage
PTA0–PTA7, PTB0–PTB7, PTD0–PTD7,
PTE0–PTE1, RST, IRQ, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
PTA0–PTA7, PTB0–PTB7, PTD0–PTD7,
PTE0–PTE1, RST, IRQ, OSC1
VIL
VSS
—
0.3 × VDD
V
—
—
7.5
11
10
13
mA
mA
—
—
3
3.5
5.5
6
mA
mA
—
—
1.5
0.5
8
3
µA
µA
VDD supply current, fOP = 8MHz
Run(3)
XTAL oscillator option
RC oscillator option
Wait(4)
XTAL oscillator option
RC oscillator option
Stop(5)
(–40°C to 125°C)
XTAL oscillator option
RC oscillator option
IDD
Digital I/O ports Hi-Z leakage current
IIL
—
—
± 10
µA
Input current
IIN
—
—
±1
µA
Capacitance
Ports (as input or output)
COUT
CIN
—
—
—
—
12
8
pF
POR rearm voltage(6)
VPOR
0
—
100
mV
POR rise time ramp rate(7)
RPOR
0.035
—
—
V/ms
Monitor mode entry voltage
VTST
1.5 × VDD
—
8.5
V
Technical Data
270
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5V Control Timing
Table 19-4. DC Electrical Characteristics (5V)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
RPU1
RPU2
1.8
16
3.3
26
4.8
36
kΩ
kΩ
Low-voltage inhibit, trip falling voltage
VTRIPF
3.60
4.25
4.48
V
Low-voltage inhibit, trip rising voltage
VTRIPR
3.75
4.40
4.63
V
Freescale Semiconductor, Inc...
Pullup resistors(8)
PTD6, PTD7
RST, IRQ, PTA0–PTA7
NOTES:
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fOP = 8MHz). All inputs 0.2V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 8MHz). All inputs 0.2V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0V.
19.7 5V Control Timing
Table 19-5. Control Timing (5V)
Characteristic(1)
Symbol
Min
Max
Unit
Internal operating frequency(2)
fOP
—
8
MHz
RST input pulse width low(3)
tIRL
750
—
ns
fT2CLK
—
4
MHz
TIM2 external clock input
NOTES:
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
MC68HC908JL8 — Rev. 2.0
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Electrical Specifications
19.8 5V Oscillator Characteristics
Table 19-6. Oscillator Specifications (5V)
Characteristic
Internal oscillator clock frequency
fICLK
External reference clock to OSC1 (2)
fOSC
Crystal reference frequency (3)
Min
Typ
Max
dc
fXTALCLK
Hz
—
32M
Hz
—
32M
Hz
CL
—
—
—
Crystal fixed capacitance (3)
C1
—
2 × CL
—
Crystal tuning capacitance (3)
C2
—
2 × CL
—
Feedback bias resistor
RB
—
10 MΩ
—
Series resistor (3), (5)
RS
—
—
—
fRCCLK
2M
—
12M
External RC clock frequency
RC oscillator external R
REXT
RC oscillator external C
CEXT
Unit
50k(1)
Crystal load capacitance (4)
Hz
Ω
See Figure 19-1
—
10
—
pF
NOTES:
1. Typical value reflect average measurements at midpoint of voltage range, 25 °C only. See Figure 19-3 for plot.
2. No more than 10% duty cycle deviation from 50%.
3. Fundamental mode crystals only.
4. Consult crystal vendor data sheet.
5. Not required for high frequency crystals.
14
RC frequency, fRCCLK (MHz)
Freescale Semiconductor, Inc...
Symbol
12
CEXT = 10 pF
10
MCU
5V @ 25 °C
OSC1
8
6
VDD
4
REXT
CEXT
2
0
0
10
20
30
Resistor, REXT (kΩ)
40
50
Figure 19-1. RC vs. Frequency (5V @25°C)
Technical Data
272
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Electrical Specifications
3V DC Electrical Characteristics
19.9 3V DC Electrical Characteristics
Table 19-7. DC Electrical Characteristics (3V)
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage (ILOAD = –1.0mA)
PTA0–PTA7, PTB0–PTB7, PTD0–PTD7,
PTE0–PTE1
VOH
VDD – 0.4
—
—
V
Output low voltage (ILOAD = 0.8mA)
PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5,
PTE0–PTE1
VOL
—
—
0.4
V
Output low voltage (ILOAD = 20mA)
PTD6, PTD7
VOL
—
—
0.5
V
LED drives (VOL = 1.8V)
PTA0–PTA5, PTA7, PTD2, PTD3, PTD6, PTD7
IOL
3
8
12
mA
Input high voltage
PTA0–PTA7, PTB0–PTB7, PTD0–PTD7,
PTE0–PTE1, RST, IRQ, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
PTA0–PTA7, PTB0–PTB7, PTD0–PTD7,
PTE0–PTE1,RST, IRQ, OSC1
VIL
VSS
—
0.3 × VDD
V
—
—
3
4
8
10
mA
mA
—
—
1
2
4.5
6
mA
mA
—
—
0.5
0.3
5
2
µA
µA
VDD supply current, fOP = 4MHz
Run(3)
XTAL oscillator option
RC oscillator option
Wait(4)
XTAL oscillator option
RC oscillator option
Stop(5)
(–40°C to 85°C)
XTAL oscillator option
RC oscillator option
IDD
Digital I/O ports Hi-Z leakage current
IIL
—
—
± 10
µA
Input current
IIN
—
—
±1
µA
Capacitance
Ports (as input or output)
COUT
CIN
—
—
—
—
12
8
pF
POR rearm voltage(6)
VPOR
0
—
100
mV
POR rise time ramp rate(7)
RPOR
0.035
—
—
V/ms
Monitor mode entry voltage
VTST
1.5 × VDD
—
8.5
V
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Table 19-7. DC Electrical Characteristics (3V)
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Pullup resistors(8)
PTD6, PTD7
RST, IRQ, PTA0–PTA7
RPU1
RPU2
1.8
16
3.3
26
4.8
36
kΩ
kΩ
Low-voltage inhibit, trip voltage
(No hysteresis implemented for 3V LVI)
VLVI3
2.18
2.49
2.68
V
NOTES:
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0V.
19.10 3V Control Timing
Table 19-8. Control Timing (3V)
Characteristic(1)
Symbol
Min
Max
Unit
Internal operating frequency(2)
fOP
—
4
MHz
RST input pulse width low(3)
tIRL
1.5
—
µs
fT2CLK
—
2
MHz
TIM2 external clock input
NOTES:
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
Technical Data
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Electrical Specifications
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3V Oscillator Characteristics
19.11 3V Oscillator Characteristics
Table 19-9. Oscillator Specifications (3V)
Characteristic
Internal oscillator clock frequency
fICLK
External reference clock to OSC1 (2)
fOSC
Crystal reference frequency (3)
Min
Typ
Max
dc
fXTALCLK
Hz
—
16M
Hz
—
16M
Hz
CL
—
—
—
Crystal fixed capacitance (3)
C1
—
2 × CL
—
Crystal tuning capacitance (3)
C2
—
2 × CL
—
Feedback bias resistor
RB
—
10 MΩ
—
Series resistor (3), (5)
RS
—
—
—
fRCCLK
2M
—
10M
External RC clock frequency
RC oscillator external R
REXT
RC oscillator external C
CEXT
Unit
45k(1)
Crystal load capacitance (4)
Hz
Ω
See Figure 19-2
—
10
—
pF
NOTES:
1. Typical value reflect average measurements at midpoint of voltage range, 25 °C only. See Figure 19-3 for plot.
2. No more than 10% duty cycle deviation from 50%.
3. Fundamental mode crystals only.
4. Consult crystal vendor data sheet.
5. Not required for high frequency crystals.
14
RC frequency, fRCCLK (MHz)
Freescale Semiconductor, Inc...
Symbol
12
CEXT = 10 pF
10
MCU
3V @ 25 °C
OSC1
8
6
VDD
REXT
4
CEXT
2
0
0
10
20
30
Resistor, REXT (kΩ)
40
50
Figure 19-2. RC vs. Frequency (3V @25°C)
MC68HC908JL8 — Rev. 2.0
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Internal OSC frequency, fICLK (kHz)
70
60
–40 °C
50
+25 °C
40
+85 °C
+125 °C
30
20
2
3
4
5
Supply Voltage, VDD (V)
6
Figure 19-3. Internal Oscillator Frequency
19.12 Typical Supply Currents
IDD (mA)
10
XTAL oscillator option
8
5.5 V
3.3 V
6
4
2
0
0
1
2
3
4
5
6
fOP or fBUS (MHz)
7
8
9
Figure 19-4. Typical Operating IDD (XTAL osc),
with All Modules Turned On (25 °C)
5
XTAL oscillator option
4
IDD (mA)
Freescale Semiconductor, Inc...
Electrical Specifications
5.5 V
3.3 V
3
2
1
0
0
1
2
3
4
5
6
fOP or fBUS (MHz)
7
8
9
Figure 19-5. Typical Wait Mode IDD (XTAL osc),
with All Modules Turned Off (25 °C)
Technical Data
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Electrical Specifications
Timer Interface Module Characteristics
19.13 Timer Interface Module Characteristics
Table 19-10. Timer Interface Module Characteristics (5V and 3V)
Characteristic
Input capture pulse width
Input clock pulse width (T2CLK pulse width)
Symbol
Min
Max
tTIH, tTIL
1/fOP
—
tLMIN, tHMIN
(1/fOP) + 5ns
—
Unit
Freescale Semiconductor, Inc...
19.14 ADC Characteristics
Table 19-11. ADC Characteristics (5V and 3V)
Characteristic
Symbol
Min
Max
Unit
Supply voltage
VDDAD
2.7
(VDD min)
5.5
(VDD max)
V
Input voltages
VADIN
VSS
VDD
V
Resolution
BAD
8
8
Bits
Absolute accuracy
AAD
± 0.5
± 1.5
LSB
Includes quantization
ADC internal clock
fADIC
0.5
1.048
MHz
tAIC = 1/fADIC, tested
only at 1 MHz
Conversion range
RAD
VSS
VDD
V
Power-up time
tADPU
16
Conversion time
tADC
14
15
tAIC cycles
Sample time(1)
tADS
5
—
tAIC cycles
Zero input reading(2)
ZADI
00
01
Hex
VIN = VSS
Full-scale reading(3)
FADI
FE
FF
Hex
VIN = VDD
Input capacitance
CADI
—
(20) 8
pF
Not tested
—
—
±1
µA
Input leakage(3)
Port B/port D
Comments
tAIC cycles
NOTES:
1. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
3. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
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19.15 Memory Characteristics
Table 19-12. Memory Characteristics
Characteristic
Symbol
Min
Max
Unit
VRDR
1.3
—
V
—
1
—
MHz
FLASH read bus clock frequency
fread(1)
32k
8M
Hz
FLASH page erase time
terase(2)
4
—
ms
FLASH mass erase time
tmerase(3)
4
—
ms
FLASH PGM/ERASE to HVEN set up time
tnvs
10
—
µs
FLASH high-voltage hold time
tnvh
5
—
µs
FLASH high-voltage hold time (mass erase)
tnvhl
100
—
µs
FLASH program hold time
tpgs
5
—
µs
FLASH program time
tprog
30
40
µs
FLASH return to read time
trcv(4)
1
—
µs
FLASH cumulative program hv period
tHV(5)
—
4
ms
—
10k
—
cycles
—
10k
—
cycles
—
10
—
years
RAM data retention voltage
Freescale Semiconductor, Inc...
FLASH program bus clock frequency
FLASH row erase endurance(6)
FLASH row program endurance
FLASH data retention time(8)
(7)
NOTES:
1. fread is defined as the frequency range for which the FLASH memory can be read.
2. If the page erase time is longer than terase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
3. If the mass erase time is longer than tmerase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing
HVEN to logic 0.
5. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tnvs + tnvh + tpgs + (tprog × 32) ≤ tHV max.
6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase / program cycles.
7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase / program cycles.
8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.
Technical Data
278
MC68HC908JL8 — Rev. 2.0
Electrical Specifications
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Technical Data – MC68HC908JL8
Section 20. Mechanical Specifications
Freescale Semiconductor, Inc...
20.1 Contents
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
20.3
20-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . . 280
20.4
20-Pin Small Outline Integrated Circuit Package (SOIC) . . . . 280
20.5
28-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . . 281
20.6
28-Pin Small Outline Integrated Circuit Package (SOIC) . . . . 281
20.7
32-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . . 282
20.8
32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . 283
20.2 Introduction
This section gives the dimensions for:
•
20-pin plastic dual in-line package (case #738)
•
20-pin small outline integrated circuit package (case #751D)
•
28-pin plastic dual in-line package (case #710)
•
28-pin small outline integrated circuit package (case #751F)
•
32-pin shrink dual in-line package (case #1376)
•
32-pin low-profile quad flat pack (case #873A)
MC68HC908JL8 — Rev. 2.0
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Mechanical Specifications
20.3 20-Pin Plastic Dual In-Line Package (PDIP)
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
Freescale Semiconductor, Inc...
C
–T–
DIM
A
B
C
D
E
F
G
J
K
L
M
N
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
M
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
Figure 20-1. 20-Pin PDIP (Case #738)
20.4 20-Pin Small Outline Integrated Circuit Package (SOIC)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
20
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R X 45 _
C
–T–
18X
G
K
SEATING
PLANE
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
Figure 20-2. 20-Pin SOIC (Case #751D)
Technical Data
280
MC68HC908JL8 — Rev. 2.0
Mechanical Specifications
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Mechanical Specifications
28-Pin Plastic Dual In-Line Package (PDIP)
20.5 28-Pin Plastic Dual In-Line Package (PDIP)
28
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
15
B
DIM
A
B
C
D
F
G
H
J
K
L
M
N
14
1
L
C
A
Freescale Semiconductor, Inc...
N
H
G
F
M
K
D
J
SEATING
PLANE
MILLIMETERS
MIN
MAX
36.45
37.21
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0°
15°
0.51
1.02
INCHES
MIN
MAX
1.435
1.465
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.115
0.135
0.600 BSC
0°
15°
0.020
0.040
Figure 20-3. 28-Pin PDIP (Case #710)
20.6 28-Pin Small Outline Integrated Circuit Package (SOIC)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
-A15
28
14X
-B1
P
0.010 (0.25)
M
B
M
14
28X
D
0.010 (0.25)
M
T A
S
B
M
S
R
X 45
C
26X
-T-
G
SEATING
PLANE
K
F
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
17.80
18.05
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0°
8°
10.01
10.55
0.25
0.75
INCHES
MIN
MAX
0.701
0.711
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0°
8°
0.395
0.415
0.010
0.029
Figure 20-4. 28-Pin SOIC (Case #751F)
MC68HC908JL8 — Rev. 2.0
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Mechanical Specifications
20.7 32-Pin Shrink Dual In-Line Package (SDIP)
3
27.9
27.8
A
B
32
17
10.46
9.86
8.9
8.8
Freescale Semiconductor, Inc...
1
4.35
4.05
0.75
0.45
3
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5, 1994.
3. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR
PROTRUSIONS.
4. DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION.
16
30X
1.778
2X
0.889
C
2.49
2.39
C
32X
0.13
M
0.5
0.4 4
T A B
T
SEATING
PLANE
10 °
0°
0.34
0.22
SECTION C–C
Figure 20-5. 32-Pin SDIP (Case #1376)
Technical Data
282
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Mechanical Specifications
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Freescale Semiconductor, Inc.
Mechanical Specifications
32-Pin Low-Profile Quad Flat Pack (LQFP)
A
–T–, –U–, –Z–
20.8 32-Pin Low-Profile Quad Flat Pack (LQFP)
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
J
M
N
D
0.20 (0.008)
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
SECTION AE–AE
H
W
K
X
DETAIL AD
Q_
0.250 (0.010)
C E
GAUGE PLANE
Freescale Semiconductor, Inc...
P
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Figure 20-6. 32-Pin LQFP (Case #873A)
MC68HC908JL8 — Rev. 2.0
MOTOROLA
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Mechanical Specifications
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Mechanical Specifications
Technical Data
284
MC68HC908JL8 — Rev. 2.0
Mechanical Specifications
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Technical Data – MC68HC908JL8
Section 21. Ordering Information
Freescale Semiconductor, Inc...
21.1 Contents
21.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
21.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
21.2 Introduction
This section contains ordering numbers for the MC68HC908JL8.
21.3 MC Order Numbers
Table 21-1. MC Order Numbers
MC Order Number
Operating
Temperature Range
MC68HC908JK8CP
–40 °C to +85 °C
MC68HC908JK8MP
–40 °C to +125 °C
MC68HC908JK8CDW
–40 °C to +85 °C
MC68HC908JK8MDW
–40 °C to +125 °C
MC68HC908JL8CP
–40 °C to +85 °C
MC68HC908JL8MP
–40 °C to +125 °C
MC68HC908JL8CDW
–40 °C to +85 °C
MC68HC908JL8MDW
–40 °C to +125 °C
MC68HC908JL8CSP
–40 °C to +85 °C
MC68HC908JL8MSP
–40 °C to +125 °C
MC68HC908JL8CFA
–40 °C to +85 °C
MC68HC908JL8MFA
–40 °C to +125 °C
Package
20-pin PDIP
20-pin SOIC
28-pin PDIP
28-pin SOIC
32-pin SDIP
32-pin LQFP
NOTE: Temperature grade "M" is available for VDD = 5V only.
MC68HC908JL8 — Rev. 2.0
MOTOROLA
Technical Data
Ordering Information
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Ordering Information
Technical Data
286
MC68HC908JL8 — Rev. 2.0
Ordering Information
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HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217
1-303-675-2140 or 1-800-441-2447
JAPAN:
Motorola Japan Ltd.; SPS, Technical Information Center,
3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan
81-3-3440-3569
Freescale Semiconductor, Inc...
ASIA/PACIFIC:
Information in this document is provided solely to enable system and software
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852-26668334
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© Motorola, Inc. 2002
MC68HC908JL8/D
Rev. 2.0
12/2002
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