HEF4094B 8-stage shift-and-store register Rev. 11 — 29 August 2013 Product data sheet 1. General description The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (OE) signal is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4094B devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. This is used for cascading HEF4094B devices when the clock has a slow rise time. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C and 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4094BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4094BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4094BTS SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 HEF4094BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 HEF4094B NXP Semiconductors 8-stage shift-and-store register 4. Functional diagram 2 3 8-STAGE SHIFT REGISTER CP QS2 CP STR STR 10 9 8-BIT STORAGE REGISTER 2 15 1 D QS1 1 3 OE QS1 9 QS2 10 QP0 4 QP1 5 QP2 6 QP3 7 QP4 14 QP5 13 QP6 12 QP7 11 D 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 4 5 6 7 14 13 12 11 001aaf119 OE 15 Fig 1. Functional diagram Fig 2. STAGE 0 D Logic symbol STAGES 1 TO 6 Q D D 001aaf111 STAGE 7 Q CP D QS1 Q CP FF 0 D FF 7 CP CP Q QS2 LE LATCH D Q D Q LE LE LATCH 0 LATCH 7 STR OE QP2 QP0 QP1 Fig 3. QP4 QP3 001aag799 QP6 QP5 QP7 Logic diagram HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 2 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 5. Pinning information 5.1 Pinning HEF4094B STR 1 16 VDD D 2 15 OE CP 3 14 QP4 QP0 4 13 QP5 QP1 QP2 QP3 VSS +()% 12 QP6 5 11 QP7 6 10 QS2 7 9 8 QS1 675 9'' ' 2( &3 43 43 43 43 43 43 43 43 46 966 Fig 4. 46 DDD 001aae662 Pin configuration SOT38-4 and SOT109-1 Fig 5. Pin configuration SOT338-1 and SOT403-1 5.2 Pin description Table 2. Pin description Symbol Pin Description STR 1 strobe input D 2 data input CP 3 clock input QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output VSS 8 ground supply voltage QS1 9 serial output QS2 10 serial output OE 15 output enable input VDD 16 supply voltage HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 3 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 6. Functional description Table 3. Function table[1] Inputs Parallel outputs Serial outputs CP OE STR D QP0 QPn QS1 QS2 L X X Z Z Q6S NC L X X Z Z NC Q7S H L X NC NC Q6S NC H H L L QPn 1 Q6S NC H H H H QPn 1 Q6S NC H H H NC NC NC Q7S [1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs. H = HIGH voltage level; L = LOW voltage level; X = don’t care; = positive-going transition; = negative-going transition; Z = HIGH-impedance OFF-state; NC = no change; Q6S = the data in register stage 6 before the LOW to HIGH clock transition; Q7S = the data in register stage 7 before the HIGH to LOW clock transition. CLOCK INPUT DATA INPUT STROBE INPUT OUTPUT ENABLE INPUT INTERNAL Q0S (FF 0) Z-state OUTPUT QP0 INTERNAL Q6S (FF 6) Z-state OUTPUT QP6 SERIAL OUTPUT QS1 SERIAL OUTPUT QS2 001aaf117 Fig 6. Timing diagram HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 4 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature P [2] VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V total power dissipation Ptot [1] Conditions power dissipation Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V - 10 mA - 10 mA 40 +125 C DIP16 [1] - 750 mW SO16, SSOP16 and TSSOP16 [2] - 500 mW - 100 mW per output For DIP16 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD supply voltage 3 VI input voltage 0 Tamb ambient temperature in free air 40 t/V input transition rise and fall rate VDD = 5 V HEF4094B Product data sheet Conditions Max Unit - 15 V - VDD V - +125 C - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 Min Typ © NXP B.V. 2013. All rights reserved. 5 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter Conditions VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit Min VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage II input leakage current IDD supply current input capacitance HEF4094B Product data sheet Max Min Max 3.5 - 3.5 - 3.5 - 3.5 - V - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 - 1.1 mA VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA QPn output is HIGH; VO = 15 V 15 V - 0.4 - 0.4 - 12 - 12 A 15 V - 0.1 - 0.1 - 1.0 - 1.0 A all valid input 5V combinations; 10 V IO = 0 A 15 V - 5 - 5 - 150 - 150 A - 10 - 10 - 300 - 300 A - 20 - 20 - 600 - 600 A - - - 7.5 - - - - pF IO < 1 A IO < 1 A OFF-state output current Min 7.0 LOW-level output voltage LOW-level output current Max 5V IO < 1 A HIGH-level output current Min 10 V HIGH-level output voltage IOZ CI IO < 1 A Max All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 6 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 10. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 C; for test circuit see Figure 11; unless otherwise specified. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions CP to QS1; see Figure 7 CP to QS2; see Figure 7 CP to QPn; see Figure 7 STR to QPn; see Figure 8 VDD Extrapolation formula Min Typ Max Unit 108 ns + (0.55 ns/pF)CL - 135 270 ns 10 V 54 ns + (0.23 ns/pF)CL - 65 130 ns 15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V 78 ns + (0.55 ns/pF)CL - 105 210 ns 10 V 39 ns + (0.23 ns/pF)CL - 50 100 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 138 ns + (0.55 ns/pF)CL - 165 330 ns 10 V 64 ns + (0.23 ns/pF)CL - 75 150 ns 15 V 47 ns + (0.16 ns/pF)CL - 55 110 ns 5V 83 ns + (0.55 ns/pF)CL - 110 220 ns 10 V 39 ns + (0.23 ns/pF)CL - 50 100 ns 27 ns + (0.16 ns/pF)CL - 35 70 ns 78 ns + (0.55 ns/pF)CL - 105 210 ns 10 V 39 ns + (0.23 ns/pF)CL - 50 100 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 78 ns + (0.55 ns/pF)CL - 105 210 ns 10 V 39 ns + (0.23 ns/pF)CL - 50 100 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 123 ns + (0.55 ns/pF)CL - 150 300 ns 10 V 59 ns + (0.23 ns/pF)CL - 70 140 ns 15 V 47 ns + (0.16 ns/pF)CL - 55 110 ns 5V 73 ns + (0.55 ns/pF)CL - 100 200 ns 10 V 34 ns + (0.23 ns/pF)CL - 45 90 ns 27 ns + (0.16 ns/pF)CL - 35 70 ns 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V - 40 80 ns 10 V - 25 50 ns 15 V - 20 40 ns 5V - 40 80 ns 10 V - 25 50 ns 15 V - 20 40 ns 5V [1] 15 V tPLH LOW to HIGH propagation delay, CP to QS1; see Figure 7 CP to QS2; see Figure 7 CP to QPn; see Figure 7 STR to QPn; see Figure 8 5V [1] 15 V tt tPZH tPZL tPHZ transition time 5V OFF-state to HIGH propagation delay OE to QPn; see Figure 9 OFF-state to LOW propagation delay OE to QPn; see Figure 9 HIGH to OFF-state propagation delay HEF4094B Product data sheet OE to QPn; see Figure 9 [1] 5V - 75 150 ns 10 V - 40 80 ns 15 V - 30 60 ns All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 7 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 C; for test circuit see Figure 11; unless otherwise specified. Symbol Parameter Conditions tPLZ LOW to OFF-state propagation delay OE to QPn; see Figure 9 set-up time D to CP; see Figure 10 tsu hold time th maximum frequency fmax [1] Extrapolation formula Min Typ Max Unit 5V - 80 160 ns 10 V - 40 80 ns 15 V - 30 60 ns 5V 60 30 - ns 10 V 20 10 - ns 15 V 15 5 - ns 5V +5 15 - ns 10 V 20 5 - ns 15 V 20 5 - ns minimum LOW 5 V clock pulse; 10 V see Figure 7 15 V 60 30 - ns 30 15 - ns 24 12 - ns minimum HIGH 5 V strobe pulse; 10 V see Figure 8 15 V 40 20 - ns 30 15 - ns 24 12 - ns see Figure 7 5V 5 10 - MHz 10 V 11 22 - MHz 15 V 14 28 - MHz D to CP; see Figure 10 pulse width tW VDD The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). Table 8. Dynamic power dissipation VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation VDD Typical formula for PD (W) where: 5V PD = 2100 fi + (fo CL) VDD2 fi = input frequency in MHz, 10 V PD = 9700 fi + (fo CL) VDD fo = output frequency in MHz, 15 V PD = 26000 fi + (fo CL) 2 VDD2 CL = output load capacitance in pF, VDD = supply voltage in V, (fo CL) = sum of the outputs. HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 8 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 11. Waveforms 1/fmax VI CP input VM GND tW tPHL tPLH VOH QPn, QS1 output VM VOL tPHL tPLH VOH QS2 output VM VOL 001aaf113 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Clock to outputs propagation delays, and clock pulse width and maximum frequency Table 9. Measurement points Supply voltage Input Output VDD VM VM VX VY 5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD VI STR input VM GND tW tPHL tPLH VOH QPn output VM VOL 001aaj058 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Strobe to output propagation delays, and strobe pulse width, set up and hold times HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 9 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register VI VM OE input GND tPZL tPLZ VDD output LOW-to-OFF OFF-to-LOW VOL VM VX tPHZ tPZH VOH output HIGH-to-OFF OFF-to-HIGH GND VY VM outputs enabled outputs enabled outputs disabled 001aai545 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. 3-state output enable and disable times for OE input VI VM CP input GND t su t su th th VI VM D input GND VOH VM QPn, QS1, QS2 output VOL 001aaf115 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Data input data set up and hold times HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 10 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register tW VI 90 % 90 % negative pulse VM VM 10 % 0V 10 % tf tr tr tf VI 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveform VEXT VDD VI VO G RL DUT RT CL 001aaj915 b. Test circuit Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 11. Test circuit Table 10. Test data Supply voltage Input VDD VI tr, tf tPHL, tPLH tPHZ, tPZH tPLZ, tPZL CL RL 5 V to 15 V VSS or VDD 20 ns open VSS VDD 50 pF 1 k HEF4094B Product data sheet VEXT Load All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 11 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 12. Application information Some examples of applications for the HEF4094B are: • Serial-to-parallel data conversion • Remote control holding register DIGITALLY CONTROLLED EQUIPMENT (REQUIRES CONTINUOUS DIGITAL CONTROL) QP0 D QP7 HEF4094B STR CP QS2 DIGITALLY CONTROLLED EQUIPMENT QP0 D QP7 HEF4094B STR QS2 DIGITALLY CONTROLLED EQUIPMENT QP0 D CP QP7 HEF4094B STR CP CONTROL AND SYNC CIRCUITRY data clock from remote control panel 001aae666 Fig 12. Remote control holding register HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 12 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 13. Package outline SOT38-4 (DIP16) HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 13 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 14 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 15. Package outline SOT338-1 (SSOP16) HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 15 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 16. Package outline SOT403-1 (TSSOP16) HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 16 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4094B v.11 20130829 Product data sheet - HEF4094B v.10 - HEF4094B v.9 - HEF4094B v.8 Modifications: HEF4094B v.10 Modifications: HEF4094B v.9 Modifications: • Table 4: Table note corrected (errata). 20130625 • 20111116 • Product data sheet added type number HEF4094BTT. Product data sheet Table 6: IOH minimum values changed to maximum HEF4094B v.8 20100402 Product data sheet - HEF4094B v.7 HEF4094B v.7 20091216 Product data sheet - HEF4094B v.6 HEF4094B v.6 20091103 Product data sheet - HEF4094B v.5 HEF4094B v.5 20090728 Product data sheet - HEF4094B v.4 HEF4094B v.4 20081030 Product data sheet - HEF4094B_CNV v.3 HEF4094B_CNV v.3 19950101 Product specification - HEF4094B_CNV v.2 HEF4094B_CNV v.2 19950101 Product specification - - HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 17 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. HEF4094B Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 18 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4094B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 29 August 2013 © NXP B.V. 2013. All rights reserved. 19 of 20 HEF4094B NXP Semiconductors 8-stage shift-and-store register 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 29 August 2013 Document identifier: HEF4094B