NSC LM10 Lm10 operational amplifier and voltage reference Datasheet

LM10
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SNOSBH4D – MAY 1998 – REVISED MARCH 2013
LM10 Operational Amplifier and Voltage Reference
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FEATURES
DESCRIPTION
•
•
•
•
•
•
The LM10 series are monolithic linear ICs consisting
of a precision reference, an adjustable reference
buffer and an independent, high quality op amp.
1
2
Input Offset Voltage: 2 mV (max)
Input Offset Current: 0.7 nA (max)
Input Bias Current: 20 nA (max)
Reference Regulation: 0.1% (max)
Offset Voltage Drift: 2 μV/°C
Reference Drift: 0.002%/°C
The unit can operate from a total supply voltage as
low as 1.1V or as high as 40V, drawing only 270μA.
A complementary output stage swings within 15 mV
of the supply terminals or will deliver ±20 mA output
current with ±0.4V saturation. Reference output can
be as low as 200 mV.
The circuit is recommended for portable equipment
and is completely specified for operation from a
single power cell. In contrast, high output-drive
capability, both voltage and current, along with
thermal overload protection, suggest it in demanding
general-purpose applications.
The device is capable of operating in a floating mode,
independent of fixed supplies. It can function as a
remote comparator, signal conditioner, SCR controller
or transmitter for analog signals, delivering the
processed signal on the same line used to supply
power. It is also suited for operation in a wide range
of voltage- and current-regulator applications, from
low voltages to several hundred volts, providing
greater precision than existing ICs.
This series is available in the three standard
temperature ranges, with the commercial part having
relaxed limits. In addition, a low-voltage specification
(suffix “L”) is available in the limited temperature
ranges at a cost savings.
Connection and Functional Diagrams
Figure 1. TO Package (NEV)
See Package Number NEV0008A
Figure 2. SOIC Package (NPA)
See Package Number NPA0014B
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
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Figure 3. PDIP Package (P)
See Package Number P (R-PDIP-T8)
Figure 4.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
Total Supply Voltage
Differential Input Voltage
(4)
LM10/LM10B/
LM10BL/
LM10C
LM10CL
45V
7V
±40V
Power Dissipation (5)
±7V
internally limited
Output Short-circuit Duration (6)
continuous
−55°C to +150°C
Storage-Temp. Range
Lead Temp. (Soldering, 10 seconds)
TO
300°C
Lead Temp. (Soldering, 10 seconds) DIP
260°C
Vapor Phase (60 seconds)
215°C
Infrared (15 seconds)
220°C
ESD rating is to be determined.
Maximum Junction Temperature
LM10
150°C
LM10B
100°C
LM10C
85°C
(1)
(2)
(3)
(4)
(5)
(6)
2
Refer to RETS10X for LM10H military specifications.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
The Input voltage can exceed the supply voltages provided that the voltage from the input to any other terminal does not exceed the
maximum differential input voltage and excess dissipation is accounted for when VIN<V−.
The maximum, operating-junction temperature is 150°C for the LM10, 100°C for the LM10B(L) and 85°C for the LM10C(L). At elevated
temperatures, devices must be derated based on package thermal resistance.
Internal thermal limiting prevents excessive heating that could result in sudden failure, but the IC can be subjected to accelerated stress
with a shorted output and worst-case conditions.
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Operating Ratings
Package Thermal Resistance
θJA
NEV Package
150°C/W
P Package
87°C/W
NPA Package
90°C/W
θJC
NEV Package
45°C/W
Electrical Characteristics
TJ=25°C, TMIN≤TJ≤TMAX (Boldface type refers to limits over temperature range) (1)
Parameter
Conditions
LM10/LM10B
Min
Input offset voltage
LM10C
Typ
Max
0.3
2.0
Min
Max
0.5
4.0
mV
5.0
mV
2.0
nA
3.0
nA
30
nA
3.0
Input offset current (2)
0.25
0.7
0.4
1.5
Input bias current
10
20
12
30
Input resistance
250
500
VS=±20V, IOUT=0
120
gain
VOUT=±19.95V
80
VS=±20V, VOUT=±19.4V
50
IOUT=±20 mA (±15 mA)
20
VS=±0.6V (0.65V), IOUT=±2 mA
1.5
VOUT=±0.4V (±0.3V), VCM=−0.4V
0.5
1.2V (1.3V) ≤VOUT≤40V,
14
Shunt gain
(3)
40
150
150
Large signal voltage
Units
Typ
kΩ
400
V/mV
115
400
80
kΩ
50
130
25
V/mV
130
V/mV
15
3.0
1.0
V/mV
3.0
V/mV
0.75
33
10
nA
400
V/mV
33
V/mV
RL=1.1 kΩ
0.1 mA≤IOUT≤5 mA
6
+
1.5V≤V ≤40V, RL=250Ω
8
0.1 mA≤IOUT≤20 mA
4
Common-mode
−20V≤VCM≤19.15V (19V)
93
rejection
VS=±20V
87
Supply-voltage
−0.2V≥V−≥−39V
90
rejection
V+=1.0V (1.1V)
84
1.0V (1.1V) ≤V+≤39.8V
96
−
V =−0.2V
6
25
6
V/mV
25
V/mV
4
102
90
V/mV
102
dB
87
96
87
dB
96
dB
84
106
93
90
dB
106
dB
90
dB
Offset voltage drift
2.0
5.0
μV/°C
Offset current drift
2.0
5.0
pA/°C
Bias current drift
TC<100°C
Line regulation
1.2V (1.3V) ≤VS≤40V
60
0.001
0≤IREF≤1.0 mA, VREF=200 mV
(1)
(2)
(3)
90
0.003
0.006
0.001
pA/°C
0.008
%/V
0.01
%/V
These specifications apply for V−≤VCM≤V+−0.85V (1.0V), 1.2V (1.3V) <VS≤VMAX, VREF=0.2V and 0≤IREF≤1.0 mA, unless otherwise
specified: VMAX=40V for the standard part and 6.5V for the low voltage part. Normal typeface indicates 25°C limits. Boldface type
indicates limits and altered test conditions for full-temperature-range operation; this is −55°C to 125°C for the LM10, −25°C to
85°C for the LM10B(L) and 0°C to 70°C for the LM10C(L). The specifications do not include the effects of thermal gradients (τ1≃20 ms),
die heating (τ2≃0.2s) or package heating. Gradient effects are small and tend to offset the electrical error (see curves).
For TJ>90°C, IOS may exceed 1.5 nA for VCM=V−. With TJ=125°C and V−≤VCM≤V−+0.1V, IOS≤5 nA.
This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the V+
terminal of the IC and input common mode is referred to V− (see Typical Applications). Effect of larger output-voltage swings with higher
load resistance can be accounted for by adding the positive-supply rejection error.
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Electrical Characteristics (continued)
TJ=25°C, TMIN≤TJ≤TMAX (Boldface type refers to limits over temperature range)(1)
Parameter
Conditions
LM10/LM10B
Min
Load regulation
0≤IREF≤1.0 mA
Typ
Max
0.01
0.1
V+−VREF≥1.0V (1.1V)
Amplifier gain
LM10C
Min
Typ
Max
0.01
0.15
0.15
0.2V≤VREF≤35V
50
0.2
75
25
23
Feedback sense
195
voltage
194
Feedback current
70
20
205
190
206
189
50
Reference drift
0.002
Supply current
270
15
210
mV
211
mV
75
nA
90
0.003
300
500
1.2V (1.3V) ≤VS≤40V
75
%
V/mV
200
22
400
%
V/mV
15
200
65
Supply current change
Units
15
nA
%/°C
500
μA
570
μA
75
μA
Electrical Characteristics
TJ=25°C, TMIN≤TJ≤TMAX (Boldface type refers to limits over temperature range) (1)
Parameter
Conditions
LM10BL
Min
LM10CL
Typ
Max
Input offset voltage
0.3
2.0
Input offset current (2)
0.1
Min
Max
0.5
4.0
mV
5.0
mV
2.0
nA
3.0
nA
30
nA
3.0
0.7
0.2
1.5
Input bias current
10
20
12
30
Input resistance
250
500
150
Large signal voltage
VS=±3.25V, IOUT=0
60
gain
VOUT=±3.2V
40
VS=±3.25V, IOUT=10 mA
10
VOUT=±2.75 V
(3)
1.5
VOUT=±0.4V (±0.3V), VCM=−0.4V
0.5
+
1.5V≤V ≤6.5V, RL=500Ω
8
0.1 mA≤IOUT≤10 mA
4
Common-mode
−3.25V≤VCM≤2.4V (2.25V)
89
rejection
VS=±3.25V
83
Shunt gain
−
Supply-voltage
−0.2V≥V ≥−5.4V
86
rejection
V+=1.0V (1.2V)
80
1.0V (1.1V) ≤V+≤6.3V
94
−
V =0.2V
(1)
(2)
(3)
4
150
400
40
25
5
3.0
1.0
300
80
30
80
88
80
74
dB
dB
96
74
106
V/mV
V/mV
102
74
96
V/mV
V/mV
4
102
V/mV
V/mV
3.0
0.75
6
V/mV
V/mV
25
3
30
nA
kΩ
kΩ
25
4
VS=±0.6V (0.65V), IOUT=±2 mA
40
115
300
Units
Typ
dB
dB
106
dB
dB
These specifications apply for V−≤VCM≤V+−0.85V (1.0V), 1.2V (1.3V) <VS≤VMAX, VREF=0.2V and 0≤IREF≤1.0 mA, unless otherwise
specified: VMAX=40V for the standard part and 6.5V for the low voltage part. Normal typeface indicates 25°C limits. Boldface type
indicates limits and altered test conditions for full-temperature-range operation; this is −55°C to 125°C for the LM10, −25°C to
85°C for the LM10B(L) and 0°C to 70°C for the LM10C(L). The specifications do not include the effects of thermal gradients (τ1≃20 ms),
die heating (τ2≃0.2s) or package heating. Gradient effects are small and tend to offset the electrical error (see curves).
For TJ>90°C, IOS may exceed 1.5 nA for VCM=V−. With TJ=125°C and V−≤VCM≤V−+0.1V, IOS≤5 nA.
This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the V+
terminal of the IC and input common mode is referred to V− (see Typical Applications). Effect of larger output-voltage swings with higher
load resistance can be accounted for by adding the positive-supply rejection error.
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Electrical Characteristics (continued)
TJ=25°C, TMIN≤TJ≤TMAX (Boldface type refers to limits over temperature range)(1)
Parameter
Conditions
LM10BL
Min
Typ
LM10CL
Max
Min
Typ
Units
Max
Offset voltage drift
2.0
5.0
μV/°C
Offset current drift
2.0
5.0
pA/°C
Bias current drift
60
90
pA/°C
Line regulation
1.2V (1.3V) ≤VS≤6.5V
0.001
0≤IREF≤0.5 mA, VREF=200 mV
Load regulation
0≤IREF≤0.5 mA
0.01
V −VREF≥1.0V (1.1V)
0.2V≤VREF≤5.5V
0.1
70
195
0.02
%/V
0.03
%/V
0.15
%
0.2
20
70
200
20
205
190
206
189
50
V/mV
200
22
65
Reference drift
0.002
Supply current
260
%
V/mV
15
194
Feedback current
0.01
0.15
30
20
Feedback sense voltage
0.001
0.02
+
Amplifier gain
0.01
210
mV
211
mV
75
nA
90
nA
0.003
400
280
500
%/°C
500
μA
570
μA
Definition of Terms
Input offset voltage: That voltage which must be applied between the input terminals to bias the unloaded
output in the linear region.
Input offset current: The difference in the currents at the input terminals when the unloaded output is in the
linear region.
Input bias current: The absolute value of the average of the two input currents.
Input resistance: The ratio of the change in input voltage to the change in input current on either input with the
other grounded.
Large signal voltage gain: The ratio of the specified output voltage swing to the change in differential input
voltage required to produce it.
Shunt gain: The ratio of the specified output voltage swing to the change in differential input voltage required to
produce it with the output tied to the V+ terminal of the IC. The load and power source are connected
between the V+ and V− terminals, and input common-mode is referred to the V− terminal.
Common-mode rejection: The ratio of the input voltage range to the change in offset voltage between the
extremes.
Supply-voltage rejection: The ratio of the specified supply-voltage change to the change in offset voltage
between the extremes.
Line regulation: The average change in reference output voltage over the specified supply voltage range.
Load regulation: The change in reference output voltage from no load to that load specified.
Feedback sense voltage: The voltage, referred to V−, on the reference feedback terminal while operating in
regulation.
Reference amplifier gain: The ratio of the specified reference output change to the change in feedback sense
voltage required to produce it.
Feedback current: The absolute value of the current at the feedback terminal when operating in regulation.
Supply current: The current required from the power source to operate the amplifier and reference with their
outputs unloaded and operating in the linear range.
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Typical Performance Characteristics (Op Amp)
6
Input Current
Common Mode Limits
Figure 5.
Figure 6.
Output Voltage Drift
Input Noise Voltage
Figure 7.
Figure 8.
DC Voltage Gain
Transconductance
Figure 9.
Figure 10.
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Typical Performance Characteristics (Op Amp) (continued)
Output Saturation
Characteristics
Output Saturation
Characteristics
Figure 11.
Figure 12.
Output Saturation
Characteristics
Minimum Supply Voltage
Figure 13.
Figure 14.
Minimum Supply Voltage
Minimum Supply Voltage
Figure 15.
Figure 16.
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Typical Performance Characteristics (Op Amp) (continued)
8
Frequency Response
Output Impedance
Figure 17.
Figure 18.
Typical Stability Range
Large Signal Response
Figure 19.
Figure 20.
Comparator Response
Time For Various
Input Overdrives
Comparator Response
Time For Various
Input Overdrives
Figure 21.
Figure 22.
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Typical Performance Characteristics (Op Amp) (continued)
Follower Pulse
Response
Noise Rejection
Figure 23.
Figure 24.
Rejection Slew Limiting
Supply Current
Figure 25.
Figure 26.
Thermal Gradient
Feedback
Thermal Gradient
Cross-coupling
Figure 27.
Figure 28.
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Typical Performance Characteristics (Op Amp) (continued)
10
Shunt Gain
Shunt Gain
Figure 29.
Figure 30.
Shunt Gain
Shunt Gain
Figure 31.
Figure 32.
Shunt Gain
Shunt Gain
Figure 33.
Figure 34.
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Typical Performance Characteristics (Reference)
Line Regulation
Load Regulation
Figure 35.
Figure 36.
Reference Noise Voltage
Minimum Supply Voltage
Figure 37.
Figure 38.
Output Saturation
Typical Stability Range
Figure 39.
Figure 40.
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TYPICAL APPLICATIONS
(Pin numbers are for devices in 8-pin packages)
Circuit descriptions available in application note AN-211 (Literature Number SNOA638).
Op Amp Offset Adjustment
Figure 41. Standard
Figure 42. Limited Range
Figure 43. Limited Range With Boosted Reference
Positive Regulators
Figure 44. Low Voltage
12
Figure 45. Best Regulation
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(Pin numbers are for devices in 8-pin packages)
Use only electrolytic output capacitors.
Figure 46. Zero Output
Figure 47. Current Regulator
Required For Capacitive Loading
Figure 48. Shunt Regulator
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(Pin numbers are for devices in 8-pin packages)
*Electrolytic
Figure 49. Negative Regulator
Figure 50. Precision Regulator
*VOUT=10−4 R3
Figure 51. Laboratory Power Supply
14
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(Pin numbers are for devices in 8-pin packages)
Figure 52. HV Regulator
Figure 53. Protected HV Regulator
*800°C Threshold Is Established By Connecting Balance To VREF.
Figure 54. Flame Detector
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(Pin numbers are for devices in 8-pin packages)
*Provides Hysteresis
Figure 55. Light Level Sensor
Figure 56. Remote Amplifier
Figure 57. Remote Thermocouple Amplifier
16
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(Pin numbers are for devices in 8-pin packages)
Figure 58. Transmitter for Bridge Sensor
10 mA≤IOUT≤50 mA
500°C≤TP≤1500°C
*Gain Trim
Figure 59. Precision Thermocouple Transmitter
Figure 60. Resistance Thermometer Transmitter
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(Pin numbers are for devices in 8-pin packages)
††Level-shift Trim
*Scale Factor Trim
†Copper Wire Wound
Figure 61. Optical Pyrometer
200°C≤Tp≤700°C
1 mA≤IOUT≤5 mA
†Gain Trim
Figure 62. Thermocouple
Transmitter
18
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(Pin numbers are for devices in 8-pin packages)
1 mA≤IOUT≤5 mA
‡50 μA≤ID≤500 μA
††Center Scale Trim
†Scale Factor Trim
*Copper Wire Wound
Figure 63. Logarithmic Light Sensor
Figure 64. Battery-level Indicator
Figure 65. Battery-threshold Indicator
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(Pin numbers are for devices in 8-pin packages)
Flashes Above 1.2V
Rate Increases With
Voltage
Figure 66. Single-cell Voltage Monitor
Flash Rate Increases
Above 6V and Below 15V
Figure 67. Double-ended Voltage Monitor
INPUT
10 mV, 100nA
FULL-SCALE
Figure 68. Meter Amplifier
20
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(Pin numbers are for devices in 8-pin packages)
*Trim For Span
†Trim For Zero
Figure 69. Thermometer
1≤λ/λ0≤105
Figure 70. Light Meter
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(Pin numbers are for devices in 8-pin packages)
ZOUT∼680Ω @ 5 kHz
AV≤1k
f1∼100 Hz
f2∼5 kHz
RL∼500
*Max Gain Trim
Figure 71. Microphone Amplifier
†Controls “Loop Gain”
*Optional Frequency Shaping
Figure 72. Isolated Voltage Sensor
22
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Figure 73. Light-level Controller
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APPLICATION HINTS
With heavy amplifier loading to V−, resistance drops in the V− lead can adversely affect reference regulation.
Lead resistance can approach 1Ω. Therefore, the common to the reference circuitry should be connected as
close as possible to the package.
Operational Amplifier Schematic
(Pin numbers are for 8-pin packages)
Reference and Internal Regulator
(Pin numbers are for 8-pin packages)
24
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
26
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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PACKAGE OPTION ADDENDUM
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27-Mar-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM10BH
ACTIVE
TO
NEV
8
500
TBD
Call TI
Call TI
-40 to 85
LM10BH
LM10BH/NOPB
ACTIVE
TO
NEV
8
500
Green (RoHS
& no Sb/Br)
POST-PLATE
Level-1-NA-UNLIM
-40 to 85
LM10BH
LM10CH
ACTIVE
TO
NEV
8
500
TBD
Call TI
Call TI
0 to 70
LM10CH
LM10CH/NOPB
ACTIVE
TO
NEV
8
500
Green (RoHS
& no Sb/Br)
POST-PLATE
Level-1-NA-UNLIM
0 to 70
LM10CH
LM10CLN
LIFEBUY
PDIP
P
8
40
TBD
Call TI
Call TI
0 to 70
LM10CLN
LM10CLN/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
0 to 70
LM10CLN
LM10CN
LIFEBUY
PDIP
P
8
40
TBD
Call TI
Call TI
0 to 70
LM
10CN
LM10CN/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-1-NA-UNLIM
0 to 70
LM
10CN
LM10CWM
NRND
SOIC
NPA
14
50
TBD
Call TI
Call TI
0 to 70
LM10CWM
LM10CWM/NOPB
ACTIVE
SOIC
NPA
14
50
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 70
LM10CWM
LM10CWMX/NOPB
ACTIVE
SOIC
NPA
14
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 70
LM10CWM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Mar-2014
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM10CWMX/NOPB
Package Package Pins
Type Drawing
SOIC
NPA
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
10.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.5
3.2
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM10CWMX/NOPB
SOIC
NPA
14
1000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
NPA0014B
www.ti.com
MECHANICAL DATA
NEV0008A
LMC0008A
H08A (REV C)
www.ti.com
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