Hynix HY5S5B6ELF-HE 256mbit mobile sdr sdrams based on 4m x 4bank x16 i/o Datasheet

256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
Document Title
4Bank x 4M x 16bits Synchronous DRAM
Revision History
Revision No.
History
Draft Date
Remark
0.1
Initial Draft
Aug. 2004
Preliminary
0.2
Modification of IDD Current
Oct. 2004
Preliminary
0.3
Modification of IDD3P & IDD3PS
IDD3P / IDD3PS : 3mA / 2mA --> 5mA / 5mA
Jan. 2005
Preliminary
1.0
Final revision
Jul. 2005
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Jul. 2005
1
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
DESCRIPTION
The Hynix Low Power SDRAM(Mobile SDR) is suited for non-PC application which use the batteries such as PDAs, 2.5G
and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix HY5S5B6ELF(P) is a 268,435,456bit CMOS Synchronous Dynamic Random Access Memory. It is organized
as 4banks of 4,194,304x16.
The Low Power SDRAM(Mobile SDR) provides for programmable options including CAS latency of 1, 2, or 3, READ or
WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low
Power SDRAM(Mobile SDR) also provides for special programmable options including Partial Array Self Refresh of a
quarter bank, a half bank, 1bank, 2banks, or all banks.
The Hynix HY5S5B6ELF(P) has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh)
to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically adjust refresh rate according to temperature without external EMRS command. A burst of Read or Write cycles in
progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or
Write command on any cycle(This pipelined design is not restricted by a 2N rule).
Deep Power Down Mode is a additional operating mode for Low Power SDRAM(Mobile SDR). This mode can achieve
maximum power reduction by removing power to the memory array within each SDRAM. By using this feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board powerline layout flexibility.
FEATURES
Standard SDRAM Protocol
●
Programmable CAS latency of 1, 2 or 3
-25oC ~ 85oC Operation
●
Internal 4bank operation
●
●
Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V
●
●
LVCMOS compatible I/O Interface
●
Low Voltage interface to reduce I/O power
●
-
Package Type
: 54ball, 0.8mm pitch FBGA (Lead Free, Lead)
- HY5S5B6ELFP : Lead Free
- HY5S5B6ELF : Lead
Low Power Features
PASR(Partial Array Self Refresh)
Auto TCSR (Temperature Compensated Self Refresh)
DS (Drive Strength)
Deep Power Down Mode
256M SDRAM ORDERING INFORMATION
Part Number
Clock Frequency
CAS Latency
HY5S5B6ELF-HE
133MHz
3
HY5S5B6ELF-SE
105MHz
3
HY5S5B6ELFP-HE
133MHz
3
HY5S5B6ELFP-SE
105MHz
3
Rev 1.0 / Jul. 2005
Organization
Interface
54Ball FBGA
Lead
4banks x 4Mb x 16
LVCMOS
Lead Free
2
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
BALL DESCRIPTION
8
9
3
7
2
1
A
B
C
54 Ball
D
FBGA
E
0.8mm
Ball Pitch
F
G
H
J
<Bottom View>
1
2
3
7
8
9
VSS
DQ15
VSSQ
A
VDDQ
DQ0
VDD
DQ14
DQ13
VDDQ
B
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
C
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
D
VSSQ
DQ6
DQ5
DQ8
NC
VSS
E
VDD
LDQM
DQ7
UDQM
CLK
CKE
F
/CAS
/RAS
/WE
A12
A11
A9
G
BA0
BA1
/CS
A8
A7
A6
H
A0
A1
A10
VSS
A5
A4
J
A3
A2
VDD
< Top View >
Rev 1.0 / Jul. 2005
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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
BALL DESCRIPTION
Ball Out
SYMBOL
TYPE
F2
CLK
INPUT
Clock : The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
F3
CKE
INPUT
Clock Enable : Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among (deep) power down, suspend or
self refresh
G9
CS
INPUT
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and
LDQM
G7,G8
BA0, BA1
INPUT
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G1, G3,
H9, G2
A0 ~ A12
INPUT
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
F8, F7, F9
RAS, CAS, WE
INPUT
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
F1, E8
UDQM, LDQM
INPUT
Data Mask : Controls output buffers in read mode and masks input data
in write mode
A8, B9, B8,
C9, C8, D9,
D8, E9, E1,
D2, D1, C2,
C1, B2, B1, A2
DQ0 ~ DQ15
I/O
A9, E7, J9, A1,
E3, J1
VDD/VSS
SUPPLY
Power supply for internal circuits
A7, B3, C7, D3,
A3, B7, C3, D7
VDDQ/VSSQ
SUPPLY
Power supply for output buffers
NC
-
E2, G1
Rev 1.0 / Jul. 2005
DESCRIPTION
Data Input/Output : Multiplexed data input/output pin
No connection
4
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 16 I/O Mobile Synchronous DRAM
PASR
Extended
Mode
Register
Self refresh
logic & timer
Internal Row
Counter
4Mx16 Bank 3
CLK
Column
Pre
Decoder
U/LDQM
DQ0
I/O Buffer & Logic
Column Active
WE
Memory
Cell
Array
Sense AMP & I/O Gate
Refresh
4Mx16 Bank 0
Row decoders
CAS
4Mx16 Bank 1
Row decoders
Row decoders
RAS
State Machine
CS
Row decoders
CKE
4Mx16 Bank 2
Row
Pre
Decoder
Row Active
DQ15
Column decoders
Column Add
Counter
Bank Select
A0
Burst
Counter
Burst
Length
A12
BA1
Address Buffers
A1
Address
Register
Mode Register
CAS Latency
Data Out Control
BA0
Rev 1.0 / Jul. 2005
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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1
BA0
A12
A11
A10
A9
A8
A7
0
0
0
0
0
OP Code
0
0
A6
A5
A4
A3
CAS Latency
OP Code
BT
A2
A1
A0
Burst Length
Burst Type
A9
Write Mode
0
Burst Read and Burst Write
1
Burst Read and Single Write
CAS Latency
A3
Burst Type
0
Sequential
1
Interleave
Burst Length
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
0
1
0
1
1
0
1
0
A2
A1
A0
1
0
0
0
2
0
1
3
0
Reserved
1
Burst Length
A3 = 0
A3=1
0
1
1
0
1
2
2
0
1
0
4
4
0
1
1
8
8
Reserved
1
0
0
Reserved
Reserved
1
Reserved
Reserved
1
1
0
Reserved
1
0
1
1
1
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full page
Reserved
Rev 1.0 / Jul. 2005
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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
BASIC FUNCTIONAL DESCRIPTION (Continued)
Extended Mode Register
BA1
BA0
A12
A11
A10
A9
A8
A7
1
0
0
0
0
0
0
0
A6
A5
DS
A4
A3
0
0
A2
A1
A0
PASR
DS (Driver Strength)
A6
A5
Driver Strength
0
0
Full
0
1
1/2 Strength
1
0
1/4 Strength
1
1
Reserved
PASR (Partial Array Self Refresh)
Rev 1.0 / Jul. 2005
A2
A1
A0
Self Refresh Coverage
0
0
0
All Banks
0
0
1
Half of Total Bank (BA1=0 or Bank 0,1)
0
1
0
Quarter of Total Bank (BA1=BA0=0 or Bank 0)
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Half of Bank 0(Bank 0 and Row Address MSB=0)
1
1
0
Quarter of Bank 0(Bank 0 and Row Address 2 MSBs=0)
1
1
1
Reserved
7
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
Power Up and Initialization
Like a Synchronous DRAM, Mobile SDRAM must be powered up and initialized in a predefined manner. Apply power and
attempt to maintain CKE at a high state and all other inputs may be undefined. Power applied VDD before or at the
same time as VDDQ. After power up, an initial pause of 200 usec is required. And a precharge all command will be
issued to the Mobile SDRAM. Then, 8 or more Auto refresh cycles will be provided. After the Auto refresh cycles are
completed, a mode register set(MRS) command will be issued to program the specific mode of operation (Cas Latency,
Burst length, etc.) And a extended mode register set command will be issued to program specific mode of self refresh
operation(PASR). The following these cycles, the Mobile SDRAM is ready for normal opeartion.
VDD
VDDQ
T=200usec
tCK
tRP
8*tRFC
tMRD
CLK
LVCMOS
High Level
CKE
Programming the registers
Mode Register
The mode register contains the specific mode of operation of the Mobile SDRAM. This register includes the selection of
a burst length(1, 2, 4, 8, Full Page), a cas latency(1, 2 or 3), a burst type. The mode register set must be done before
any activate command after the power up sequence. Any contents of the mode register be altered by re-programming
the mode register through the execution of mode register set command.
Extended Mode Register
The extended mode register contains the specific features of self refresh opeartion of the Mobile SDRAM. This register
includes the selection of partial arrays to be refreshed(half array, quarter array, etc.). The extended mode register set
must be done before any activate command after the power up sequence. Any contents of the mode register be altered
by re-programming the mode register through the execution of extended mode register set command.
Bank(Row) Active
The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by
activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects
the bank, and the value on the A0-A12 selects the row. This row remains active for column access until a precharge
command is issued to that bank. Read and write operations can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command.
Read
The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and
deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select
the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not
selected, the row will remain active for subsequent accesses.
The length of burst and the CAS latency will be determined by the values programmed during the MRS command.
Rev 1.0 / Jul. 2005
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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
Write
The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE
and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select
the starting column location. The value on input A10 determines whether or not Auto Precharge is used.
If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.
Precharge
The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the
precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open
row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the
precharge command is issued.
Auto Precharge
The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If
A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated.
Burst Termination
The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst
Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts
a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the
bank open.
Data Mask
The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is
issued, data outputs are disabled and become high impedance after two clock delay. During a WRITE operation, When
this command is issued, data inputs can't be written with no clock delay.
CLK
Command
RD
CKE
Masked by CKE
Internal CLK
Frozen Int. CLK by CKE
(CKE = Fixed Low)
Q1
DQ
Q2
Q3
Q4
Clock Suspend
Mode
Command
WR
CKE
Masked by CKE
Internal CLK
Frozen Int. CLK by CKE
(CKE = Fixed Low)
DQ
D1
D2
D3
D4
Clock Suspend
Mode
Rev 1.0 / Jul. 2005
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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
Clock Suspend
The Clock Suspend command is used to suspend the internal clock of Mobile SDRAM. The clock suspend operation
stops transmission of the clock to the internal circuits of the device during burst transfer of data to stop the operation
of the device. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends data Read and Write operations. (See examples in next Figures)
Power Down
The Power Down command is used to reduce standby current. Before this command is issued, all banks must be precharged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping
CKE low, all of the input buffer except CKE are gated off.
Auto Refresh
The Auto Refresh command is used during normal operation and is similar to CBR refresh in Coventional DRAMs.
This command must be issued each time a refresh is required. When an Auto Refresh command is issued , the address
bits is ''Don't care'', because the specific address bits is generated by internal refresh address counter.
Self Refresh
The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM
operates refresh cycle asynchronously.
The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM
can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode registers.
The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature
Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of
PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(IDD6) by using these two
modes.
Deep Power Down
The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory
array of the devices.
For more information, see the special operation for Low Power consumption of this data sheet.
Rev 1.0 / Jul. 2005
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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
COMMAND TRUTH TABLE
Function
Mode Register Set
ADDR
A10
/AP
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
H
X
L
L
L
L
X
Op Code
2
2
Extended Mode Register Set
H
X
L
L
L
L
X
Op Code
No Operation
H
X
L
H
H
H
X
X
Device Deselect
H
X
H
X
X
X
X
Bank Active
H
X
L
L
H
H
X
BA
X
Row Address
V
Read
H
X
L
H
L
H
Column
L
V
Read with Autoprecharge
H
X
L
H
L
H
X
Column
H
V
Write
H
X
L
H
L
L
X
Column
L
V
Write with Autoprecharge
H
X
L
H
L
L
X
Column
H
V
Precharge All Banks
H
X
L
L
H
L
X
X
H
X
Precharge selected Bank
H
X
L
L
H
L
X
X
L
V
Burst stop
H
X
L
H
H
L
X
X
Data Write/Output Enable
H
X
X
X
Data Mask/Output Disable
H
X
Auto Refresh
H
H
Self Refresh Entry
H
L
Self Refresh Exit
L
H
Precharge Power Down Entry
H
L
Precharge Power Down Exit
L
H
Clock Suspend Entry
H
L
Clock Suspend Exit
L
H
Deep Power Down Entry
H
L
Deep Power Down Exit
L
H
X
X
L
L
V
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
L
H
H
X
X
L
H
L
Note
X
X
X
X
1
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.
Rev 1.0 / Jul. 2005
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256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
CURRENT STATE TRUTH TABLE (Sheet 1 of 4)
Current
State
idle
Row
Active
Read
Command
CS RAS CAS WE
BA0/
BA1
A11-A0
L
L
L
L
L
L
H
X
X
Auto or Self Refresh Start Auto or Self Refresh
L
L
H
L
BA
X
Precharge
No Operation
L
L
H
H
BA
Row Add.
Bank Activate
Activate the specified
bank and row
L
H
L
L
BA
Col Add.
A10
Write/WriteAP
ILLEGAL
4
L
H
L
H
BA
Col Add.
A10
Read/ReadAP
ILLEGAL
4
L
H
H
H
X
X
No Operation
No Operation
3
H
X
X
X
X
X
Device Deselect
No Operation or Power
Down
3
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
13
L
L
H
L
BA
X
Precharge
Precharge
7
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4
L
H
L
L
BA
Col Add.
A10
Write/WriteAP
Start Write : optional
AP(A10=H)
6
L
H
L
H
BA
Col Add.
A10
Read/ReadAP
Start Read : optional
AP(A10=H)
6
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
Termination Burst: Start
the Precharge
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
L
H
L
L
BA
Col Add.
A10
Write/WriteAP
Termination Burst: Start
Write(optional AP)
8,9
L
H
L
H
BA
Col Add.
A10
Read/ReadAP
Termination Burst: Start
Read(optional AP)
8
L
H
H
H
X
X
No Operation
Continue the Burst
OP CODE
OP CODE
Mode Register Set
Set the Mode Register
Notes
L
Rev 1.0 / Jul. 2005
OP CODE
Action
Description
14
5
13,14
13,14
13
4
12
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
CURRENT STATE TRUTH TABLE (Sheet 2 of 4)
Current
State
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
Command
CS RAS CAS WE
BA0/
BA1
A11-A0
X
X
Action
Description
H
X
X
X
L
L
L
L
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
Termination Burst: Start
the Precharge
10
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4
L
H
L
L
BA
Col Add.
A10
Write/WriteAP
Termination Burst: Start
Write(optional AP)
8
L
H
L
H
BA
Col Add.
A10
Read/ReadAP
Termination Burst: Start
Read(optional AP)
8,9
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
ILLEGAL
4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
12
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
ILLEGAL
4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
12
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
Rev 1.0 / Jul. 2005
OP CODE
OP CODE
OP CODE
Device Deselect
Continue the Burst
Mode Register Set
ILLEGAL
Notes
13,14
13
13,14
13
13,14
13
13
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
CURRENT STATE TRUTH TABLE (Sheet 3 of 4)
Current
State
Precharging
Row
Activating
Write
Recovering
Command
CS RAS CAS WE
BA0/
BA1
A11-A0
L
L
L
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
No Operation:
Bank(s) idle after tRP
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
4,12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
4,12
L
H
H
H
X
X
No Operation
No Operation:
Bank(s) idle after tRP
H
X
X
X
X
X
Device Deselect
No Operation:
Bank(s) idle after tRP
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
ILLEGAL
4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,11,1
2
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
4,12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
4,12
L
H
H
H
X
X
No Operation
No Operation: Row
Active after tRCD
H
X
X
X
X
X
Device Deselect
No Operation: Row
Active after tRCD
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
ILLEGAL
4,13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
Start Write:
Optional AP(A10=H)
L
H
L
H
BA
Col Add. A10
Read/ReadAP
Start Read: Optional
AP(A10=H)
L
H
H
H
X
X
No Operation
No Operation:
Row Active after tDPL
OP CODE
OP CODE
Mode Register Set
ILLEGAL
Notes
L
Rev 1.0 / Jul. 2005
OP CODE
Action
Description
13,14
13
13,14
13
13,14
13
9
14
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
CURRENT STATE TRUTH TABLE (Sheet 4 of 4)
Current
State
Write
Recovering
Write
Recovering
with Auto
Precharge
Refreshing
Mode
Register
Accessing
Command
CS RAS CAS WE
BA0/
BA1
A11-A0
X
X
Action
Description
Device Deselect
No Operation:
Row Active after tDPL
Mode Register Set
ILLEGAL
Notes
H
X
X
X
L
L
L
L
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
ILLEGAL
4,13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
4,12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
4,9,12
L
H
H
H
X
X
No Operation
No Operation:
Precharge after tDPL
H
X
X
X
X
X
Device Deselect
No Operation:
Precharge after tDPL
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
13
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
13
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
13
L
H
H
H
X
X
No Operation
No Operation:
idle after tRC
H
X
X
X
X
X
Device Deselect
No Operation:
idle after tRC
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
13
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
13
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
13
L
H
H
H
X
X
No Operation
No Operation:
idle after 2 clock cycles
H
X
X
X
X
X
Device Deselect
No Operation:
idle after 2 clock cycles
Rev 1.0 / Jul. 2005
OP CODE
OP CODE
OP CODE
13,14
13
13,14
13,14
15
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
Note :
1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge.
2. All entries assume that CKE was active during the preceding clock cycle.
3. If both banks are idle and CKE is inactive, then in power down cycle
4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,
depending on the state of that bank.
5. If both banks are idle and CKE is inactive, then Self Refresh mode.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. Must satisfy burst interrupt condition.
9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
10. Must mask preceding data which don't satisfy tDPL.
11. Illegal if tRRD is not satisfied
12. Illegal for single bank, but legal for other banks in multi-bank devices.
13. Illegal for all banks.
14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1.
Rev 1.0 / Jul. 2005
16
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 1)
Current
State
Self
Refresh
CKE
Command
Previous Current
Cycle
Cycle
CS
RAS
CAS
WE
BA0,
BA1
A11A0
Notes
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Exit Self Refresh with
Device Deselect
2
L
H
L
H
H
H
X
X
Exit Self Refresh with
No Operation
2
L
H
L
H
H
L
X
X
ILLEGAL
2
L
H
L
H
L
X
X
X
ILLEGAL
2
L
H
L
L
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Self Refresh
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
L
H
H
H
X
X
Power Down mode exit,
all banks idle
2
L
X
X
X
X
X
L
X
X
X
ILLEGAL
2
X
X
L
X
X
Power
Down
L
Deep
Power
Down
Action
H
L
L
L
X
X
X
X
X
X
Maintain Power Down Mode
H
X
X
X
X
X
X
X
INVALID
1
L
H
X
X
X
X
X
X
Deep Power
Down mode exit
5
L
L
X
X
X
X
X
X
Maintain Deep
Power Down Mode
Rev 1.0 / Jul. 2005
17
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 2)
Current
State
All
Banks
Idle
Any State
other than
listed above
CKE
Command
Previous Current
Cycle
Cycle
CS
RAS
CAS
WE
BA0,
BA1
A11A0
Action
H
H
H
X
X
X
H
H
L
H
X
X
H
H
L
L
H
X
H
H
L
L
L
H
X
H
H
L
L
L
L
OP CODE
H
L
H
X
X
X
H
L
L
H
X
X
H
L
L
L
H
X
H
L
L
L
L
H
X
X
Entry Self Refresh
H
L
L
L
L
L
OP CODE
Mode Register Set
L
X
X
X
X
X
X
X
Power Down
H
H
X
X
X
X
X
X
Refer to operations of
the Current State
Truth Table
H
L
X
X
X
X
X
X
Begin Clock Suspend
next cycle
L
H
X
X
X
X
X
X
Exit Clock Suspend
next cycle
L
L
X
X
X
X
X
X
Maintain Clock Suspend
Refer to the idle State section
of the Current State
Truth Table
X
Notes
3
3
3
Auto Refresh
Mode Register Set
Refer to the idle State section
of the Current State
Truth Table
4
3
3
3
4
4
Note :
1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
3. The address inputs depend on the command that is issued.
4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered
from the all banks idle state.
5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of
clock after CKE goes high and is maintained for a minimum 200usec.
Rev 1.0 / Jul. 2005
18
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
ABSOLUTE MAXIMUM RATING
Symbol
Rating
Unit
Ambient Temperature
Parameter
TA
-25 ~ 85
oC
Storage Temperature
TSTG
-55 ~ 125
oC
VIN, VOUT
VDD
VDDQ
IOS
PD
-1.0 ~ 2.6
-1.0 ~ 2.6
-1.0 ~ 2.6
50
1
V
V
V
mA
W
TSOLDER
260 . 10
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Short Circuit Output Current
Power Dissipation
Soldering Temperature . Time
oC . Sec
DC OPERATING CONDITION (TA= -25 to 85oC )
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VDD
VDDQ
VIH
VIL
Min
1.70
1.70
0.8*VDDQ
-0.3
Typ
1.8
1.8
-
Max
1.95
1.95
VDDQ+0.3
0.3
Unit
V
V
V
V
Note
1
1, 2
1, 2
1, 2
Note :
1. All Voltages are referenced to VSS = 0V
2. VDDQ must not exceed the level of VDD
AC OPERATING TEST CONDITION (TA= -25 to 85 oC, VDD = 1.8V, VSS = 0V)
Parameter
AC Input High/Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise/Fall Time
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Symbol
VIH / VIL
Vtrip
tR / tF
Voutref
CL
Value
0.9*VDDQ/0.2
0.5*VDDQ
1
0.5*VDDQ
30
Unit
V
V
ns
V
pF
Note
1
Note 1.
Vtt=0.5xVDDQ
50Ω
Output
ZO=50Ω
30pF
Rev 1.0 / Jul. 2005
19
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
CAPACITANCE (TA= 25 oC, f=1MHz)
Parameter
Input capacitance
Pin
Symbol
CLK
H/S
Unit
Min
Max
CI1
2
4.0
pF
A0~A12, BA0, BA1, CKE, CS, RAS,
CAS, WE, UDQM, LDQM
CI2
2
4.0
pF
DQ0 ~ DQ15
CI/O
3.5
6.0
pF
Data input/output capacitance
DC CHARACTERRISTICS I (TA= -25 to 85oC)
Parameter
Symbol
Min
Max
Unit
Note
Input Leakage Current
ILI
-1
1
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
VDDQ-0.2
-
V
3
Output Low Voltage
VOL
-
0.2
V
4
Note :
1. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V.
2. DOUT is disabled. VOUT= 0 to 1.95V.
3. IOUT = - 0.1mA
4. IOUT = + 0.1mA
Rev 1.0 / Jul. 2005
20
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
DC CHARACTERISTICS II (TA= -25 to 85oC)
Parameter
Symbol
Test Condition
Speed
H
S
60
50
Unit Note
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
Precharge Standby Current
in Power Down Mode
IDD2P
CKE ≤ VIL(max), tCK = 15ns
0.5
mA
IDD2PS
CKE ≤ VIL(max), tCK = ∞
0.35
mA
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
15
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
7
IDD3P
CKE ≤ VIL(max), tCK = 15ns
5
IDD3PS
CKE ≤ VIL(max), tCK = ∞
5
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
20
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
20
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5
Self Refresh Current
IDD6
CKE ≤ 0.2V
Standby Current in
Deep Power Down Mode
IDD7
See p.26~27
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
tRFC ≥ tRFC(min),
mA
1
mA
mA
mA
100
75
mA
95
mA
See Next
Page
mA
1
2
uA
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. See the tables of next page for more specific IDD6 current values.
Rev 1.0 / Jul. 2005
21
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
DC CHARACTERISTICS III - Low Power (IDD6)
Memory Array
Temp.
( oC)
4 Banks
2 Banks
1 Bank
45
300
240
200
uA
85
450
320
270
uA
Rev 1.0 / Jul. 2005
Unit
22
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
Symbol
H
S
Unit
Note
Min
Max
Min
Max
tCK3
7.5
1000
9.5
1000
ns
tCK2
12
1000
15
1000
ns
Clock High Pulse Width
tCHW
3.0
-
3.5
-
ns
1
Clock Low Pulse Width
tCLW
3.0
-
3.5
-
ns
1
CAS Latency=3
tAC3
-
6.5
-
7.0
ns
2
CAS Latency=2
tAC2
-
9.0
-
10
ns
2
Data-out Hold Time
tOH
2.0
-
2.0
-
ns
Data-Input Setup Time
tDS
2.0
-
3.0
-
ns
1
Data-Input Hold Time
tDH
1.0
-
1.5
-
ns
1
Address Setup Time
tAS
2.0
-
3.0
-
ns
1
Address Hold Time
tAH
1.0
-
1.5
-
ns
1
CKE Setup Time
tCKS
2.0
-
3.0
-
ns
1
CKE Hold Time
tCKH
1.0
-
1.5
-
ns
1
Command Setup Time
tCS
2.0
-
3.0
-
ns
1
Command Hold Time
tCH
1.0
-
1.5
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1.0
-
1.0
-
ns
CLK to Data Output in
High-Z Time
CAS Latency=3
tOHZ3
6.5
7.0
ns
CAS Latency=2
tOHZ2
9.0
10
ns
System Clock
Cycle Time
Access Time From Clock
CAS Latency=3
CAS Latency=2
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev 1.0 / Jul. 2005
23
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
Symbol
H
S
Min
Max
Min
Max
Unit Note
RAS Cycle Time
tRC
72.5
-
90
-
ns
RAS to CAS Delay
tRCD
22.5
-
28.5
-
ns
RAS Active Time
tRAS
50
100K
60
100K
ns
RAS Precharge Time
tRP
22.5
-
28.5
-
ns
RAS to RAS Bank Active Delay
tRRD
15
-
19
-
ns
AUTO REFRESH Period
tRFC
80
-
80
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
CLK
Data-in to Precharge Command
tDPL
2
-
2
-
CLK
Data-In to Active Command
tDAL
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
CLK
CAS Latency=3
tPROZ3
3
-
3
-
CLK
CAS Latency=2
tPROZ2
2
-
2
-
CLK
Power Down Exit Time
tDPE
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
ms
Precharge to Data Output
High-Z
tDPL+tRP
1
Note : 1. A new command can be given tRC after self refresh exit.
Rev 1.0 / Jul. 2005
24
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
Special Operation for Low Power Consumption
Deep Power Down Mode
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole
memory array of the devices.
Data will not be retained once the device enters Deep Power Down Mode.
Full initialization is required when the device exits from Deep Power Down Mode.
Truth Table
Current State
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
Idle
Deep Power Down Entry
H
L
L
H
H
L
Deep Power Down
Deep Power Down Exit
L
H
X
X
X
X
Deep Power Down Mode Entry
The Deep Power Down Mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of
the clock, while CKE is low. The following diagram illustrates deep power down mode entry.
CLK
CKE
CS
RAS
CAS
WE
tRP
Precharge
if needed
Rev 1.0 / Jul. 2005
Deep Power Down Entry
25
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
Deep Power Down Mode (Continued)
Deep Power Down Mode Exit Sequence
The Deep Power Down mode is exited by asserting CKE high.
After the exit, the following sequence is needed to enter a new command.
1. Maintain NOP input conditions for a minimum of 200usec
2. Issue precharge commands for all banks of the device
3. Issue 8 or more auto refresh commands
4. Issue a mode register set command to initialize the mode register
5. Issue an extended mode register set command to initialize the extended mode register
The following timing diagram illustrates deep power down mode exit sequence.
CLK
CKE
CS
RAS
CAS
WE
200µs
Deep Power Down
exit
Rev 1.0 / Jul. 2005
tRC
tRP
All Banks
Precharge
Auto
refresh
Auto
refresh
Mode
Register
Set
Extended
Mode
Register
Set
New
Command
Accepted
Here
26
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
PACKAGE INFORMATION
54 Ball FBGA 0.8mm pitch (Size 8.0mm x 12.0mm)
A1 INDEX MARK
8.00 Typ.
3.20
Unit
[mm]
0.80
1.60
0.80 Typ.
12.00
Typ.
Bottom
View
0.40
0.45
+/- 0.05
0.34
+/- 0.05
2.80
1.375
Rev 1.0 / Jul. 2005
0.80
Typ.
1.00 max
27