IN74LV573 OCTAL D-TYPE TRANSPARENT LATCH (3-STATE) • • • • • • By pinning IN74LV573 are compatible with IN74HC573A and IN74HCT573A series. Input voltage levels are compatible with stadard CMOS levels. Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS Voltage supply range from 1.2 to 5.5 V LOW input current: 1.0 µА; 0.1 µА at Т = 25 °С Output current 8 mА Latch current: not less than150 mА at Т = 125 °С ESD acceptable value: not less than 2000 V as per HBM and not less than 200 V as per MM ORDERING INFORMATION IN74LV573N Plastic DIP IN74LV573D SOIC TA = -40° to 125° C for all packages FUNCTION TABLE Inputs OE LE L H L H L L D H L X H X X H -HIGH voltage level L - LOW voltage level X - don’t care Z - High impedance state PIN ASSIGNMENT Outputs Q H L no change Z OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 10 11 LE GND 1 IN74LV573 ABSOLUTE MAXIMUM RATINGS Symb Parameter ol Vcc Supply voltage Iik, Input diode current Rating -0.5 to +7.0 ±20 Uni t V mA Iok Output diode current ±50 mA Io Icc Output current bus drivers DC Vcc or GND current for types bus driver outputs GND current Storage temperature range Power dissipation per package: DIP SO ±35 mA ±70 mA ±50 -65 to +150 mА о С 750 500 mW IGND Tstg PD Conditions VI<-0.5 V VI>Vcc>+0.5 V V0<-0.5 V VI>Vcc>+0.5 V -0.5 V<Vo<Vcc+0.5 V or or Notes: Power dissipation value decreases for: DIP - 12 mW°C the range from 70 to 125°С SO - 8 mW°C the range from 70 to 125°С RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Vcc Supply voltage 1.0 VI Input voltage 0 Vо Output voltage 0 T Operating temperature range -40 tr,tf Input rise and fall times Max 5.5 Vcc Vcc +125 500 200 100 50 Unit V V V o C ns/V Conditions Vcc= 1.0 ÷ 2.0 V Vcc= 2.0 ÷ 2.7 V Vcc= 2.7 ÷ 3.6 V Vcc= 3.6 ÷ 5.5 V - The IC function down to Vсс = 1.0 V (input levels - VIL=0 V, VIH=Vcc); DC characterisics are guaranteed at Vcc=1.2 ÷ 5.5 V. 2 IN74LV573 DC CHARACTERISTICS Sym bol Parameter VIH HIGH level input voltage VIL LOW level output voltage VOH HIGH level output voltage VOH HIGH level output voltage; BUS driver outputs VOL LOW level output voltage VOL LOW level voltage; BUS driver outputs II Input leakage current IOZ OFF-state current Icc Supply current Icc Additional supply current per input Conditions Limits Vcс VI +85 оС +125 оС Unit -40 to +25°C (V) Min Max Min Max Min Max 1.2 0.9 0.9 0.9 V 2.0 1.4 1.4 1.4 2.7 to 3.6 2.0 2.0 2.0 4.5 to 5.5 0.7 Vcc 0.7 Vcc 0.7 Vcc -1.2 0.3 0.3 0.3 V 2.0 0.6 0.6 0.6 2.7 to 3.6 0.8 0.8 0.8 4.5 to 5.5 0.3 Vcc 0.3 Vcc 0.3 Vcc 1.2 VIH IO =-100 µА 1.05 1.0 1.0 V 2.0 or 1.85 1.8 1.8 2.7 VIL 2.55 2.5 2.5 3.6 3.45 3.4 3.4 5.5 5.35 5.3 5.3 3.0 VIH IO =-8 mA 2.48 2.40 2.20 V 4.5 or IO =-16 mA 3.70 3.60 3.50 VIL 1.2 2.0 2.7 3.6 5.5 3.0 4.5 VIH IO =100µА or VIL 5.5 Vсс or GND VIH or VIL Vсс Io = 0 or GND VI = Vcc-0.6V 5.5 5.5 2.7 до 3.6 VIH IO =8 mA or IO =16 mA VIL - 0.15 0.15 0.15 0.15 0.15 0.33 0.40 - - 3 - 0.2 0.2 0.2 0.2 0.2 0.40 0.55 - 0.2 0.2 0.2 0.2 0.2 0.50 0.65 ±1.0 ±1.0 - ±1.0 µА ±0.5 ±5.0 - ±10.0 µА 8.0 80 160 µА 0.2 0.5 0.85 mA - V V IN74LV573 AC CHARACTERISICS (CL=50 pF, RL=1 KΩ, tLH = tHL = 2.5 ns) Sym bol Parameter tPHL/PLH Propagation delay Dn to Qn tPHL/PLH Propagation delay LE to Qn tPZH/PZL 3-state output enable time OE to Qn tPHZ/PLZ 3-state outpiut disable time OE to Qn tW LE pulse width HIGH tsu Setup time Dn to LE th Hold time Dn to LE CI Input capacitance Power dissipation capacitance per package CPD Conditions Vcc 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 VI = Vcc or GND 5.5 Т=+25 оС VI = Vcc or GND VI = Vcc or GND VI = Vcc or GND VI = Vcc or GND Т=+25 оС -40 to +25°C Min Max 150 30 23 18 15 160 34 28 20 17 140 28 22 17 14 160 31 23 20 17 100 29 21 17 15 50 15 11 8 6 40 8 8 8 8 7.0 52 4 Limits +85°C +125°C Min Max Min Max 160 170 39 49 29 36 23 29 19 24 180 190 43 53 31 34 25 31 21 26 160 170 37 48 28 35 22 28 18 23 160 170 39 48 29 36 24 29 20 24 125 150 34 41 25 30 20 24 18 21 75 100 17 20 13 15 10 12 8 10 40 40 8 8 8 8 8 8 8 8 - Unit ns ns ns ns ns ns ns ns ns IN74LV573 Drawing of the chip 1.9 mm 18 17 16 15 1.51 mm 19 14 13 12 On-chip marking 20 11 74LV573/574 1 10 9 2 3 Pad number 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 4 5 6 7 Pads allocation Table coordinates (counted from lower left corner), mm X Y 0.128 0.545 0.128 0.229 0.330 0.120 0.576 0.120 0.738 0.120 1.054 0.120 1.216 0.120 1.466 0.120 1.682 0.314 1.682 0.533 1.682 0.839 1.682 1.108 1.422 1.274 1.149 1.274 0.971 1.274 0.811 1.274 0.633 1.274 0.360 1.274 0.128 1.108 0.128 0.854 5 8 Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108