AD AD816 500 ma differential driver and dual low noise (vf) amplifier Datasheet

a
500 mA Differential Driver and
Dual Low Noise (VF) Amplifiers
AD816*
FEATURES
Flexible Configuration
Two Low Noise Voltage Feedback Amplifiers with
High Current Drive, Ideal for ADSL Receivers or
Drivers for Low Impedance Loads such as CRT Coils
Two High Current Drive Amplifiers, Ideal for an ADSL
Differential Driver or Single Ended Drivers for Low
Impedance Loads such as CRT Coils
Thermal Overload Protection
15
9
+VS 8
–VS 7
6
5
4
3
NC
OUT2 RECEIVER
–IN2 RECEIVER
+IN2 RECEIVER
+IN2 DRIVER
–IN2 DRIVER
OUT2 DRIVER
+VS
–VS
OUT1 DRIVER
–IN1 DRIVER
+IN1 DRIVER
+IN1 RECEIVER
2
1
–IN1 RECEIVER
OUT1 RECEIVER
14
13
12
11
B
10
TE
AD816
TAB IS
+VS
DRIVER A & B
RECEIVER B
FUNCTIONAL BLOCK DIAGRAM
CURRENT FEEDBACK AMPLIFIERS/DRIVERS
High Output Drive
26 dBm Differential Line Drive for ADSL Transmitters
40 V p-p Differential Output Voltage, RL = 50 ⍀ @ 1 MHz
500 mA Continuous Current, R L = 5 ⍀
1 A Peak Current, 1% Duty Cycle, RL = 15 ⍀ for DMT
Low Distortion
–68 dB @ 1 MHz THD, RL = 100 ⍀, V O = 40 V p-p
High Speed
120 MHz Bandwidth (–3 dB)
1500 V/␮s Differential Slew Rate, VO = 10 V p-p, G = +5
70 ns Settling Time to 0.1%
RECEIVER A
A
LE
NC = NO CONNECT
B
SO
VOLTAGE FEEDBACK AMPLIFIERS/RECEIVERS
High Input Performance
4 nV/√Hz Voltage Noise
15 mV Max Input Offset Voltage
Low Distortion
–68 dB @ 1 MHz THD, VO = 10 V p-p, RL = 200 ⍀
High Speed
100 MHz Bandwidth (–3 dB)
180 V/␮s Slew Rate
High Output Drive
70 mA Output Current Drive
O
APPLICATIONS
ADSL, VDSL and HDSL Line Interface Driver and Receiver
CRT Convergence and Astigmatism Adjustment
Coil and Transformer Drivers
Composite Audio Amplifiers
PRODUCT DESCRIPTION
The two high output drive amplifiers are capable of supplying
a minimum of 500 mA continuous output current and up to
1A peak output current, and when configured differentially,
40 V p-p differential output swing can be achieved on ± 15 V
supplies into a load of 50 Ω. The drivers have 120 MHz of
bandwidth and 1,500 V/µs of differential slew rate while
featuring total harmonic distortion of –68 dB at 1 MHz into a
100 Ω load, specifications required for high frequency telecommunication subscriber line drivers.
The low noise voltage feedback amplifiers are fully independent
and can be configured differentially for use as receiver amplifiers within a subscriber line hybrid interface or individually for
signal conditioning or filtering. The low noise of 4 nV/√Hz and
distortion of –68 dB at 1 MHz enable low level signals to be
resolved and amplified in the presence of large common-mode
voltages. 100 MHz of bandwidth and 180 V/µs of slew rate
combined with a load drive capability of 70 mA enable these
amplifiers to drive passive filters and low inductance coils. The
AD816 has thermal overload protection for system reliability
and is available in low thermal resistance power packages. The
AD816 operates over the industrial temperature range (–40°C
to +85°C).
The AD816 consists of two high current drive and two low
noise amplifiers. These can be configured differentially for driving low impedance loads and receiving signals over twisted pair
cable or could be used independently for single ended driving
application such as correction circuits within high resolution
CRT Monitors.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD816–SPECIFICATIONS
DRIVER AMPLIFIERS (@ T = +25ⴗC, V = ⴞ15 V dc, R = 1 k⍀ and R
Model
DYNAMIC PERFORMANCE
Small Signal Bandwidth (–3 dB)
Bandwidth (0.1 dB)
Differential Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion (Differential)
Input Voltage Noise
Input Current Noise (+I IN)
Input Current Noise (–I IN)
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
S
F
= 50 ⍀ unless otherwise noted)
Conditions
AD816A
Typ
Max
VS
Min
± 15
100
120
MHz
±5
90
110
MHz
± 15
± 15
± 15
1400
10
1500
70
MHz
V/µs
ns
f = 1 MHz, RLOAD = 100 Ω, VOUT = 40 V p-p
f = 10 kHz, G = +2 (Single Ended)
f = 10 kHz, G = +2
f = 10 kHz, G = +2
NTSC, G = +2, RLOAD = 25 Ω
NTSC, G = +2, RLOAD = 25 Ω
± 15
± 5, ± 15
± 5, ± 15
± 5, ± 15
± 15
± 15
–68
1.85
1.8
19
0.05
0.45
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
Degrees
±5
± 15
5
10
LE
± 5, ± 15
40
0.5
± 5, ± 15
5
20
± 5, ± 15
2
± 5, ± 15
10
TMIN to TMAX
Differential Offset Voltage Drift
–Input Bias Current
TMIN to TMAX
+Input Bias Current
TMIN to TMAX
B
SO
Differential Input Bias Current
Open-Loop Transresistance
INPUT CHARACTERISTICS
Differential Input Resistance
TMIN to TMAX
VOUT = ± 10 V, RL = 1 kΩ
TMIN to TMAX
+Input
–Input
Differential Input Capacitance
Input Common-Mode Voltage Range
O
Common-Mode Rejection Ratio
Differential Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Voltage Swing
Units
G = +2, R F = 499 Ω, VIN = 0.125 V rms,
RL = 100 Ω
G = +2, RF = 499 Ω, VIN = 0.125 V rms,
RL = 100 Ω
G = +2, R F = 499 Ω, VIN = 0.125 V rms,
RL = 100 Ω
VOUT = 10 V p-p, G = +5, RL = 100 Ω
10 V Step, G = +2
TMIN to TMAX
Input Offset Voltage Drift
Differential Offset Voltage
LOAD
TE
A
TMIN to TMAX
TMIN to TMAX
Single Ended, R LOAD = 25 Ω
Continuous Output Current
Differential, R LOAD = 50 Ω
TMIN to TMAX
RLOAD = 5 Ω
Peak Output Current
Short Circuit Current
10 µs Pulse, 1% Duty Cycle, RL = 15 Ω
Note 1
± 5, ± 15
0.7
0.6
± 15
± 15
± 15
±5
± 5, ± 15
± 5, ± 15
± 15
±5
± 15
± 15
± 15
±5
± 15
± 15
56
80
23
2.2
46
45
500
200
2
12
15
25
2
5
60
100
5
5
50
50
mV
mV
mV
µV/°C
mV
mV
µV/°C
µA
µA
µA
µA
µA
µA
MΩ
MΩ
7
15
1.4
13.5
3.5
60
100
MΩ
Ω
pF
±V
±V
dB
dB
24.5
3.6
49
V p-p
V p-p
V p-p
V p-p
mA
mA
A
A
750
100
1.0
1.0
NOTES
1
See Power Considerations section.
Specifications subject to change without notice.
–2–
REV. B
AD816
RECEIVER AMPLIFIERS (@ T = +25ⴗC, V
Model
DYNAMIC PERFORMANCE
Small Signal Bandwidth (–3 dB)
Bandwidth (0.1 dB)
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Current Noise
Differential Gain Error
Differential Phase Error
S
= ⴞ15 V dc, RF = 1 k⍀ and RLOAD = 500 ⍀ unless otherwise noted)
VS
G = +2, RL = 100 Ω
G = +2, RL = 100 Ω
G = +2
G = +2
VOUT = 4 V p-p
VOUT = 10 V p-p Step, G = +2
± 15
±5
± 15
±5
± 15
± 15
100
80
30
40
180
45
MHz
MHz
MHz
MHz
V/µs
ns
f = 1 MHz, RLOAD = 200 Ω
f = 10 kHz
f = 10 kHz
NTSC, G = +2, RLOAD = 150 Ω
± 15
± 5, ± 15
± 5, ± 15
± 15
±5
± 15
±5
–68
4
2
0.04
0.05
0.03
0.06
dBc
nV/√Hz
pA/√Hz
%
%
Degrees
Degrees
± 5, ± 15
7.5
NTSC, G = +2, RLOAD = 150 Ω
DC PERFORMANCE
Input Offset Voltage
LE
TMIN to TMAX
Offset Voltage Drift
Input Bias Current
± 5, ± 15
VOUT = ± 7.5 V, RLOAD = 150 Ω
TMIN to TMAX
B
SO
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
O
Output Current
Short Circuit Current
20
5
± 5, ± 15
TMIN to TMAX
Input Offset Current
Offset Current Drift
Open-Loop Gain
Min
AD816A
Typ Max
Conditions
TE
A
VCM = ± 5 V
Single Ended, RLOAD = 150 Ω
TMIN to TMAX
Single Ended, RLOAD = 150 Ω
TMIN to TMAX
RL = 150 Ω
± 15
± 15
3
1
± 15
± 15
±5
±5
± 15
+13
–12
+3.8
–2.7
82
± 15
± 15
±5
±5
± 15
± 15
25.2
25.2
6.2
6.0
65
0.5
1
6
0.08
0.1
0.1
0.1
15
15
7
15
2
Units
mV
mV
µV/°C
µA
µA
µA
nA/°C
V/mV
V/mV
300
1.5
+14.3
–13.4
+4.3
–3.4
110
kΩ
pF
V
V
V
V
dB
25.5
V p-p
V p-p
V p-p
V p-p
mA
mA
6.4
70
105
Specifications subject to change without notice.
(@ TA = +25ⴗC, VS = ⴞ15 V dc, RF = 1 k⍀ and RLOAD = 50 ⍀ (Driver), RLOAD = 500 ⍀ (Receiver)
COMMON CHARACTERISTICS unless otherwise noted)
Model
Conditions
VS
MATCHING CHARACTERISTICS
Crosstalk:
Driver to Driver
Drivers to Receivers
Receiver to Receiver
f = 1 MHz, VIN = 200 mV rms, RLOAD = 100 Ω ± 15
f = 1 MHz, VIN = 200 mV rms, RLOAD = 100 Ω ± 15
f = 1 MHz, VIN = 200 mV rms, RLOAD = 500 Ω ± 15
POWER SUPPLY
Operating Range
Quiescent Current
Driver Supply Rejection Ratio
Receiver Supply Rejection Ratio
± 15
± 15
± 15, ± 5
± 15, ± 5
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
Specifications subject to change without notice.
REV. B
–3–
Min
AD816A
Typ Max
–67
–64
–81
±5
46
–49
–69
–66
–75
Units
dB
dB
dB
± 18
56
59
V
mA
mA
dB
dB
AD816
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Total
Internal Power Dissipation2
Plastic (Y, YS and VR) . . 3.05 W (Observe Derating Curves)
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range
Y, YS, VR Package . . . . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD816A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300°C
The maximum power that can be safely dissipated by the
AD816 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for the plastic encapsulated parts is determined by the glass transition temperature
of the plastic, about 150°C. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure.
The AD816 has thermal shutdown protection, which guarantees
that the maximum junction temperature of the die remains below a
safe level. However, shorting the output to ground or either power
supply for an indeterminate period will result in device failure.
To ensure proper operation, it is important to observe the derating curves and refer to the section on power considerations.
TE
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air: 15-Lead Through Hole and Surface Mount:
θJA = 41°C/W.
It must also be noted that in high (noninverting) gain configurations (with low values of gain resistor), a high level of input
overdrive can result in a large input error current, which may
result in a significant power dissipation in the input stage. This
power must be included when computing the junction temperature rise due to total internal power.
PIN CONFIGURATION
VR-15, YS-15
LE
Y-15
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUT1 RECEIVER
–IN1 RECEIVER
+IN1 RECEIVER
+IN1 DRIVER
–IN1 DRIVER
OUT1 DRIVER
–VS
+VS
OUT2 DRIVER
–IN2 DRIVER
+IN2 DRIVER
+IN2 RECEIVER
–IN2 RECEIVER
OUT2 RECEIVER
NC
O
OUT1 RECEIVER
–IN1 RECEIVER
+IN1 RECEIVER
+IN1 DRIVER
–IN1 DRIVER
OUT1 DRIVER
–VS
+VS
OUT2 DRIVER
–IN2 DRIVER
+IN2 DRIVER
+IN2 RECEIVER
–IN2 RECEIVER
OUT2 RECEIVER
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B
SO
TOP VIEW
MAXIMUM POWER DISSIPATION – Watts
14
TJ = 1508C
13
12
11
10
θJA = 168C/W
SOLDERED DOWN TO
COPPER HEAT SINK AREA
(STILL AIR = 0FT/MIN)
9
AD816 AVR, AY
8
7
6
5
4
θJA = 418C/W
(STILL AIR = 0FT/MIN)
NO HEAT SINK
AD816 AVR, AY
3
2
1
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60
AMBIENT TEMPERATURE – 8C
70 80
90
Figure 1. Plot of Maximum Power Dissipation vs. Temperature (Copper Heat Sink Area = 2 in.2)
ORDERING GUIDE
Model
Temperature Range
Package Description
Package
Option
AD816AY
AD816AYS
AD816AVR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
15-Lead Through-Hole SIP with Staggered Leads and 90° Lead Form
15-Lead Through-Hole SIP with Staggered Leads and Straight Lead Form
15-Lead Surface Mount DDPAK
Y-15
YS-15
VR-15
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD816 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. B
Typical Driver Performance Characteristics–AD816
60
60
DIFFERENTIAL OUTPUT VOLTAGE – Volts p-p
VS = 615V
25
50
20
40
15
30
10
20
VS = 65V
10
5
–IB, VS = 615V
50
INPUT BIAS CURRENT – mA
SINGLE-ENDED OUTPUT VOLTAGE – Volts p-p
30
–20
100
TE
50V
100V
RL = 50V
(DIFFERENTIAL)
400V
–80
RL = 200V
(DIFFERENTIAL)
–90
–100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 6. Driver Total Harmonic Distortion vs. Frequency
80
VS = 615V
G = +2
RL = 100V
–40
–50
–70
–110
100
O
PSRR – dB
–30
TOTAL HARMONIC DISTORTION – dBc
1
100k
10k
80
VS = 615V
G = +10
VOUT = 40V p-p
–60
COMMON-MODE REJECTION – dB
–10
–50
LE
INPUT VOLTAGE
NOISE
Figure 3. Driver Input Current and Voltage Noise vs.
Frequency
0
0
20
40
60
JUNCTION TEMPERATURE – 8C
–40
CURRENT NOISE – pA/ Hz
NONINVERTING INPUT
CURRENT NOISE
1k
FREQUENCY – Hz
–20
Figure 5. Driver Input Bias Current vs. Temperature
B
SO
VOLTAGE NOISE – nV/ Hz
10
100
20
+IB, VS = 65V, 615V
100
10
1
10
–IB, VS = 65V
0
–40
Figure 2. Driver Output Voltage Swing vs. Load Resistance
INVERTING INPUT
CURRENT NOISE
30
10
0
0
10
100
1k
10k
LOAD RESISTANCE – (Differential – V) (Single-Ended – V/2)
100
40
–PSRR
+PSRR
–60
–70
–80
70
VS = 615V
60
50
1kV
40
1kV
30
20
VOUT
VIN
1kV
1kV
–90
–100
0.01
0.1
1
10
FREQUENCY – MHz
100
Figure 4. Driver Power Supply Rejection vs. Frequency
REV. B
10
10k
300
100k
1M
FREQUENCY – Hz
10M
100M
Figure 7. Driver Common-Mode Rejection vs. Frequency
–5–
AD816–Typical Driver Performance Characteristics
1400
G = +5
RL = 100V
2400
60
TA = +258C
DIFFERENTIAL SR
1000
80
2000
1600
800
+SR
600
1200
400
800
200
400
VS = 65V
40
RTI OFFSET – mV
1200
2800
DIFFERENTIAL SLEW RATE – V/ms
5
10
15
OUTPUT STEP SIZE – V p-p
10
RTI OFFSET – mV
SINGLE
DRIVER
49.9V
1kV
1kV
–15
–20
–16
VOUT
RL=
25V
B
SO
–10
–12
–8
–4
0
4
VOUT – Volts
8
12
16
10
0%
5V
RL = 100V
30
RL = 50V
20
RL = 25V
10
RL = 1V
0
2
4
10
6
8
FREQUENCY – MHz
12
14
Figure 12. Driver Large Signal Frequency Response
O
90
2.0
0
20
Figure 9. Driver Gain Nonlinearity vs. Output Voltage
100
1.6
TA = +258C
VS = 615V
40
LE
VS = 615V
VIN
f = 0.1Hz 100V
–5
1.2
TE
VS = 610V
0
RL=
5V
1kV
0
–0.8 –0.4
0.4
0.8
LOAD CURRENT – Amps
VOUT
Figure 11. Driver Thermal Nonlinearity vs. Output Current
Drive
15
5
SINGLE
DRIVER
1kV
–60
–2.0 –1.6 –1.2
20
VS = 65V
VIN
f = 0.1Hz 100V
–40
Figure 8. Driver Slew Rate vs. Output Step Size
TA = +258C
0
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
0
VS = 610V
49.9V
0
0
VS = 615V
20
–20
1ms
CLOSED-LOOP OUTPUT RESISTANCE – V
SINGLE-ENDED SLEW RATE – V/ms
(PER AMPLIFIER)
–SR
100
10
VS = 615V
1
0.1
0.01
30k
Figure 10. Driver 40 V p-p Differential Sine Wave; RL = 50 Ω,
f = 100 kHz
VS = 65V
100k
300k
1M
3M
10M
FREQUENCY – Hz
30M
100M
300M
Figure 13. Driver Closed-Loop Output Resistance vs.
Frequency
–6–
REV. B
Typical Driver Characteristics–AD816
5
6
7
8
9
2 BACK TERMINATED LOADS (75V)
3
4
5
6
7
8
9
0.12
0.10
0.08
0.06
G = +2
0.04
RF = 1kV 0.02
NTSC
0.00
–0.02
–0.04
10 11
CROSSTALK – dB
–30
499V
499V
499V
499V
–40
–50
DRIVER A = INPUT
DRIVER B = OUTPUT
–60
–70
–90
–100
10k
100k
1M
10M
FREQUENCY – Hz
100M 300M
Figure 15. Driver Output-to-Output Crosstalk vs.
Frequency
3
G = +1
RF = 499V
RL = 100V
RS = 100V
VIN = 1.0Vrms
–3
VIN = 0.5Vrms
–6
O
OUTPUT/INPUT LEVEL – dBV
0
–9
VIN = 0.25Vrms
–12
–15
–18
VIN = 125mVrms
–21
–24
–27
100k
VIN = 62.5mVrms
1M
10M
FREQUENCY – Hz
100M
VIN = 50mVrms
G +5
RL = 100V
RS = 100V
10M
FREQUENCY – Hz
100M
–21
300M
2
1
0
–1
RF = 604V
–2
RF = 750V
0.1
0
–3
–4
RF = 604V
–5
–0.1
RF = 750V
–0.2
–6
–0.3
–7
–0.4
100k
1M
10M
FREQUENCY – Hz
100M
–8
300M
Figure 18. Driver Frequency Response and Flatness,
G = +5
3
2
1
VIN = 200mVrms
G +2
RL = 100V
RS = 100V
RF = 499V
0
–1
RF = 604V
–2
–3
RF = 750V
–4
–5
–6
–7
100k
300M
Figure 16. Driver Small and Large Signal Frequency
Response, G = +1
REV. B
1M
–18
RF = 499V
B
SO
DRIVER B = INPUT
DRIVER A = OUTPUT
–80
–15
VIN = 62.5mVrms
TE
50V
100V 100V
–12
Figure 17. Driver Small and Large Signal Frequency
Response, G = +2
DRIVER
100V INPUT
B
50V
–18
LE
–20
OUTPUT OUTPUT
–9
VIN = 125mVrms
–27
100k
VIN = 200mVrms
DRIVER
A
–6
–15
–24
0
INPUT 100V
–12
–21
Figure 14. Driver Differential Gain and Differential
Phase (Per Amplifier)
–10
–3
VIN = 0.25Vrms
OUTPUT LEVEL – dBV
4
–9
NORMALIZED FREQUENCY RESPONSE – dB
0.010
0.005
0.000
–0.005 PHASE
–0.010
–0.015 GAIN
–0.020
–0.025
–0.030
1
2
3
VIN = 0.5Vrms
–6
INPUT LEVEL – dBV
2
–3
NORMALIZED FLATNESS – dB
1
6
G = +2
RF = 499V 3
RL = 100V
RS = 100V 0
0
NORMALIZED FREQUENCY RESPONSE – dB
GAIN
DIFF PHASE – Degrees
PHASE
0.5
0.4
0.3
G = +2
RF = 1kV 0.2
0.1
NTSC
0.0
–0.1
–0.2
–0.3
10 11
DIFF PHASE – Degrees
DIFF GAIN – %
DIFF GAIN – %
6 BACK TERMINATED LOADS (25V)
0.04
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
–0.04
1M
10M
FREQUENCY – Hz
100M
300M
Figure 19. Driver Frequency Response vs. RF, G = +2
–7–
AD816–Typical Driver Performance Characteristics
499V
1kV
0.1mF
0.1mF
499V
1kV
8
VIN
PULSE
GENERATOR
100V
100V
DRIVER A/B
0.1mF
7
TR/TF = 250ps
8
AD816
AD816
55V
10mF
+15V
10mF
+15V
VIN
RL = 100V
PULSE
GENERATOR
10mF
7
0.1mF
RL = 100V
10mF
50V
TR/TF = 500ps
–15V
DRIVER A/B
–15V
Figure 24. Driver Test Circuit, Gain = +2
LE
TE
Figure 20. Test Circuit Gain = –1
Figure 25. 10 V Step Response, G = +2
B
SO
Figure 21. Driver 500 mV Step Response, G = –1
O
Figure 22. Driver 4 V Step Response, G = –1
Figure 26. Driver 400 mV Step Response, G = +2
RF
+15V
10mF
0.1mF
RG
8
AD816
VIN
PULSE
GENERATOR
TR/TF = 250ps
100V
DRIVER A/B
0.1mF
7
50V
RL = 100V
10mF
–15V
Figure 27. Driver 20 V Step Response, G = +5
Figure 23. Test Circuit, Gain = 1 + RF/RG
–8–
REV. B
Typical Receiver Performance Characteristics–AD816
–40
HARMONIC DISTORTION – dB
40
30
20
10
3
10
100
1k
10k
100k
FREQUENCY – Hz
1M
–70
–80
–100
100
10M
1kV
10M
VOUT
VIN = 0.5Vrms
100V
VS = 615V
–1
–2
B
SO
–4
–5
100k
VS = 65V
INPUT LEVEL – dBV
50V
0
–3
1M
10M
FREQUENCY – Hz
100M
300M
Figure 29. Receiver Closed-Loop Gain vs. Frequency,
Gain = –1
O
–6
–9
–12
3
0
–6
–9
VIN = 0.125Vrms
–18
–12
–21
–15
VIN = 0.0625Vrms
–24
–18
–27
100k
1M
10M
FREQUENCY – Hz
100M
–21
300M
Figure 32. Receiver Small and Large Signal Frequency
Response, Gain = +2
100
90
80
PSR – dB
70
60
1kV
1kV
6
–3
VIN = 0.25Vrms
–15
80
VIN
9
G = +2
RF = 1kV
CF = 2.2pF
RL = 100V
RS = 0V
–3
1
40
1M
VIN = 1.0Vrms
0
LE
VIN
2
100
10k
100k
FREQUENCY – Hz
3
1kV
4
3
1k
Figure 31. Receiver Harmonic Distortion vs. Frequency
5
GAIN – dB
–60
–90
Figure 28. Receiver Input Voltage Noise Spectral Density
CMR – dB
G = +5
VOUT = 14V p-p
RF = 4kV
RL = 1kV
TE
0
–50
OUTPUT LEVEL (RTO) – dBV
INPUT VOLTAGE NOISE – nV/ Hz
50
POSITIVE
SUPPLY
60
NEGATIVE
SUPPLY
50
40
VOUT
1kV
30
1kV
20
0
1k
10k
100k
FREQUENCY – Hz
1M
10
100
10M
Figure 30. Receiver Common-Mode Rejection vs.
Frequency
REV. B
1k
10k
100k
1M
FREQUENCY – Hz
10M
100M
Figure 33. Receiver Power Supply Rejection vs. Frequency
–9–
AD816–Typical Receiver Performance Characteristics
2.2pF
1kV
1kV
0.1mF
1kV
0.1mF
VIN
1kV
AD816
VIN
VOUT
0.1mF
AD816
50V
VOUT
REC A/B
TR/ TF = 250ps
RL
7
PULSE
GENERATOR
8
PULSE
GENERATOR
8
REC A/B
10mF
+15V
10mF
+15V
0.1mF
RL = 500V
7
10mF
10mF
50V
–15V
–15V
TR/ TF = 500ps
Figure 38. Test Circuit, Gain = –1
Figure 34. Test Circuit, Gain = +2
TE
50ns
LE
5V
Figure 39. Receiver 10 V Step Response, G = –1
50ns
B
SO
Figure 35. Receiver 10 V Step Response, G = +2
Figure 40. Receiver 400 mV Step Response, G = –1
O
Figure 36. Receiver 400 mV Step Response, G = +2
0
0
REC A
INPUT
OUTPUT OUTPUT
REC B
CROSSTALK – dB
50V
–30
–40
1kV
100V
100V
–10
100V
INPUT
–20
1kV
2.2pF
–50
–60
–70
RECEIVER B : INPUT
RECEIVER A : OUTPUT
2.2pF
2.2pF
499V
OUTPUT OUTPUT
1kV
1kV
REC B
50V
100V
INPUT
50V DRV B
100V
100V
INPUT
DRIVER A: INPUT
RECEIVER A: OUTPUT
–60
–70
1kV
499V
–40
–50
50V
1kV
100V
499V
VIN = 200mVrms
INPUT
DRIVER B: INPUT
RECEIVER A: OUTPUT
DRIVER A: INPUT
RECEIVER B: OUTPUT
–80
–80
RECEIVER A = INPUT
RECEIVER B = OUTPUT
–90
–100
0.01
499V
–30
1kV
1kV
2.2pF
REC A
OUTPUT OUTPUT
50V
50V
CROSSTALK – dB
–20
INPUT 100V DRV A
VIN = 200mVrms
–10
0.1
1
10
FREQUENCY – MHz
–90
100
–100
0.01
300
DRIVER B: INPUT
RECEIVER A: OUTPUT
0.1
1
10
FREQUENCY – MHz
100
300
Figure 41. Driver-to-Receiver Crosstalk vs. Frequency
Figure 37. Receiver Output-to-Output Crosstalk
vs. Frequency
–10–
REV. B
AD816
THEORY OF OPERATION (DRIVER)
Table I. Driver Resistor Values
The AD816 driver is a dual current feedback amplifier with high
(500 mA) output current capability. Being a current feedback
amplifier, the AD816 driver’s open-loop behavior is expressed
as transimpedance, ∆VO/∆I–IN, or TZ. The open-loop transimpedance behaves just as the open-loop voltage gain of a voltage feedback amplifier, that is, it has a large dc value and decreases at roughly 6 dB/octave in frequency.
Since RIN is proportional to 1/gM, the equivalent voltage gain is
just TZ × gM, where the gM in question is the transconductance
of the input stage. Figure 42 shows the driver connected as a
follower with gain. Basic analysis yields the following results:
 R 
 R 
VOUT =VIO  1+ F  ± I BN RN  1+ F  ± I BI RF
 RG 
 RG 
B
SO
VIN
VOUT
LE
RIN
Figure 42. Current-Feedback Amplifier Operation
Recognizing that G × RIN << RF for low gains, it can be seen to
the first order that bandwidth for this amplifier is independent
of gain (G).
Considering that additional poles contribute excess phase at
high frequencies, there is a minimum feedback resistance below
which peaking or oscillation may result. This fact is used to
determine the optimum feedback resistance, RF. In practice
parasitic capacitance at the inverting input terminal will also add
phase in the feedback loop so that picking an optimum value for
RF can be difficult.
O
Achieving and maintaining gain flatness of better than 0.1 dB at
frequencies above 10 MHz requires careful consideration of
several issues.
Choice of Feedback and Gain Resistors
The fine scale gain flatness will, to some extent, vary with
feedback resistance. It is therefore recommended that once
optimum resistor values have been determined, 1% tolerance
values should be used if it is desired to maintain flatness over a
wide range of production lots. Table I shows optimum values
for several useful gain configurations. These should be used as a
starting point in any application.
REV. B
∞
499
499
125
110
TE
RF
RG
RIN = 1/gM ≈ 25 Ω
G = 1+
RN
604
499
499
499
1k
There are three major noise and offset terms to consider in a
current feedback amplifier. For offset errors refer to the equation below. For noise error the terms are root-sum-squared to
give a net output error. In the circuit below (Figure 43), they
are input offset (VIO) which appears at the output multiplied by
the noise gain of the circuit (1 + RF/RG), noninverting input
current (IBN × RN) also multiplied by the noise gain, and the
inverting input current, which when divided between RF and RG
and subsequently multiplied by the noise gain always appear at
the output as IBI × RF. The input voltage noise of the AD816 is
less than 4 nV/√Hz. At low gains, however, the inverting input
current noise times RF is the dominant noise source. Careful
layout and device matching contribute to better offset and drift.
The typical performance curves in conjunction with the equations
below can be used to predict the performance of the AD816 in
any application.
where:
RG
RG (⍀)
DRIVER DC ERRORS AND NOISE
T Z (S )
VO
=G×
VIN
T Z (S ) + G × RIN + RF
RF
G = +1
–1
+2
+5
+10
RF (⍀)
RF
I BI
RG
RN
VIO
I BN
AD816
DRIVERS
VOUT
Figure 43. Driver Output Offset Voltage
THEORY OF OPERATION (RECEIVER)
Each AD816 receiver is a wide band high performance operational amplifier. It also provides a constant slew rate, bandwidth
and settling time over its entire specified temperature range.
The AD816 receiver consists of a degenerated NPN differential
pair driving matched PNPs in a folded-cascode gain stage. The
output buffer stage employs emitter followers in a class AB
amplifier which deliver the necessary current to the load while
maintaining low levels of distortion.
A protection resistor in series with the noninverting input is
required in circuits where the input to the receiver could be
subject to transients on continuous overload voltages exceeding
the ± 6 V maximum differential limit. The resistor provides
protection for the input transistors, by limiting their maximum
base current.
–11–
AD816
relationship between junction temperature (TJ) and various
components of θJA.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
As to be expected for a wideband amplifier, PC board parasitics
can affect the overall closed-loop performance. Of concern are
stray capacitances at the output and the inverting input nodes. If
a ground plane is to be used on the same side of the board as
the signal traces, a space (5 mm min) should be left around the
signal lines to minimize coupling.
TJ = TA + PIN θJA
DIE MOUNT)
θ B (DIE MOUNT
TA
Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of
10.0 µF and 0.1 µF is recommended. Under some low frequency
applications, a bypass capacitance of greater than 10 µF may be
necessary. Due to the large load currents delivered by the AD816,
special consideration must be given to careful bypassing. The
ground returns on both supply bypass capacitors as well as signal
common must be “star” connected as shown in Figure 44.
RECEIVER A
+IN
IN
DRIVER A
RF
RF
θ CA
θ JC
θ JA
TA
TE
PIN
WHERE:
PIN = DEVICE POWER DISSIPATION
TA = AMBIENT TEMPERATURE
TJ = JUNCTION TEMPERATURE
θ JC = THERMAL RESISTANCE – JUNCTION TO CASE
θ CA = THERMAL RESISTANCE – CASE TO AMBIENT
Figure 45. A Breakdown of Various Package Thermal
Resistances
RG
Figure 46 gives the relationship between output voltage swing
into various loads and the power dissipated by the AD816 (PIN).
This data is given for both sine wave and square wave (worst
case) conditions. It should be noted that these graphs are for
mostly resistive (phase < ±10°) loads. When the power dissipation
requirements are known, Equation 1 and the graph on Figure 47
can be used to choose an appropriate heat sinking configuration.
RF
RG
OUT
IN
–IN
θ A + θ B = θ JC
CASE
TJ
B
SO
RF
–OUT
DRIVER B
OUT
TO CASE)
LE
+VS
RG
(OPTIONAL)
θ A (JUNCTION TO
TJ
POWER SUPPLY BYPASSING
+OUT
Equation 1
4
RECEIVER B
f = 1kHz
VS = 615V
SQUARE WAVE
–VS
SINE WAVE
PIN – Watts
Figure 44. Signal Ground Connected in “Star”
Configuration
RL = 50V
3
RL = 100V
2
POWER CONSIDERATIONS
O
The 500 mA drive capability of the AD816 driver enables it to
drive a 50 Ω load at 40 V p-p when it is configured as a differential driver. This implies a power dissipation, PIN, of nearly
5 watts. To ensure reliability, the junction temperature of the
AD816 should be maintained at less than 175°C. For this reason, the AD816 will require some form of heat sinking in most
applications. The thermal diagram of Figure 45 gives the basic
RL = 200V
1
10
20
30
VOUT – Volts p-p
40
Figure 46. Total Power Dissipation vs Differential Driver
Output Voltage
–12–
REV. B
AD816
Normally, the AD816 will be soldered directly to a copper pad.
Figure 47 plots θJA against size of copper pad. This data pertains
to copper pads on both sides of G10 epoxy glass board connected
together with a grid of feedthroughs on 5 mm centers.
This data shows that loads of 100 ohms or greater will usually
not require any more than this. This is a feature of the AD816’s
15-lead power SIP package.
TE
An important component of θJA is the thermal resistance of the
package to heatsink. The data given is for a direct soldered
connection of package to copper pad. The use of heatsink
grease either with or without an insulating washer will increase
this number. Several options now exist for dry thermal connections. These are available from Bergquist as part # SP600-90.
Consult with the manufacturer of these products for details of
their application.
The AD816 is equipped with a thermal shutdown circuit. This
circuit ensures that the temperature of the AD816 die remains
below a safe level. In normal operation, the circuit shuts down
the AD816 at approximately 180°C and allows the circuit to
turn back on at approximately 140°C. This built-in hysteresis
means that a sustained thermal overload will cycle between
power-on and power-off conditions. The thermal cycling typically occurs at a rate of 1 ms to several seconds, depending on
the power dissipation and the thermal time constants of the
package and heat sinking. Figures 48 and 49 illustrate the thermal shutdown operation after driving OUT1 to the + rail, and
OUT2 to the – rail, and then short-circuiting to ground each
output of the AD816. The AD816 will not be damaged by
momentary operation in this state, but the overload condition
should be removed.
COPPER HEAT SINK AREA (TOP AND BOTTOM) – in2
1
2
3
35
θJA – 8C/W
AD816AVR, AY (θJC = 28C/W)
25
20
LE
30
Figure 48. OUT2 Shorted to Ground Through a 2 Ω
Resistor, Square Wave Is OUT1, RF = 1 k Ω, RG = 222 Ω
10
0
B
SO
15
0.5k
1k
1.5k
2k
2.5k
COPPER HEAT SINK AREA (TOP AND BOTTOM) – mm2
Figure 47. Power Package Thermal Resistance vs. Heat
Sink Area
Other Power Considerations
O
There are additional power considerations applicable to the
AD816. First, as with many current feedback amplifiers, there is an
increase in supply current when delivering a large peak-to-peak
voltage to a resistive load at high frequencies. This behavior is
affected by the load present at the amplifier’s output. Figure 12
summarizes the full power response capabilities of the AD816
driver. These curves apply to the differential driver applications
(right-hand side of Figure 52). In Figure 12, maximum continuous peak-to-peak output voltage is plotted vs. frequency for
various resistive loads. Exceeding this value on a continuous
basis can damage the AD816.
REV. B
Figure 49. OUT1 Shorted to Ground Through a 2 Ω
Resistor, Square Wave Is OUT2, RF = 1 k Ω, RG = 222 Ω
–13–
AD816
ADSL Transceiver
The AD816 is designed for the primary purpose of providing an
integrated solution for the transmit and receive functions of an
ADSL modem. ADSL or Asymmetrical Digital Subscriber Line
is a means for delivering up to 6 Mbps from a telephone central
office (CO) into a home over the conventional telephone twisted
pair (local loop) and a few hundred kbps simultaneously in the
opposite direction.
The transmit/receive block is commonly referred to as a hybrid,
which is an old telephone term, and the function was originally
performed with passive circuitry in early phone systems. The
hybrid’s function is to deliver maximum transmit power down
the line, while providing the receive circuitry with a maximum
receive signal and a minimized (self) transmit signal. As the line
gets longer, this separation becomes much more difficult, because the transmit signal must be larger to reach the other end
with acceptable SNR, while the receive signal is more attenuated by the longer line.
+15V
0.1mF
The receive section (R1 and R2) is configured as a pair of difference amplifiers that together produce a differential output that
consists of the receive signal in addition to the transmit signal
attenuated by the trans-hybrid loss.
The circuit is highly symmetrical, so a single-ended explanation
can be easily generalized to understand the differential operation. D1 output terminals (Pin 6 of the AD816) drives the top
of the primary of T1 through R101. A voltage divider is formed
R101
15V
B
SO
V+
10mF
8
4
The power amplifiers of the AD816 (D1 and D2) are arranged
in a differential configuration that receives its inputs from the
differential outputs of a D/A converter. The outputs differentially drive the transformer primary with a turns ratio of 1:2.
The line on the secondary side of the transformer has an impedance of 120 Ω. Thus one quarter of this resistance (30 Ω) is
required for back termination on the primary side due to the
impedance scaling by the square of the turns ratio. This resistance is divided in half (15 Ω) and put on each side of the drive
buffers for symmetry (R101 and R201).
LE
The figure of merit for the performance of the hybrid is commonly called trans-hybrid loss and is a measure of how much
the transmit signal that appears in the receive circuit has been
attenuated relative to the amplitude of the transmit signal itself.
It is measured in dBs and is a function of frequency.
In addition to the passive circuits that have been used over time,
active circuit techniques can enhance the hybrid’s performance.
Figure 50 shows one of the various hybrid circuits that uses the
AD816 in an ADSL application. The high power op amps serve
as the transmitter, while the low noise amplifiers serve as the
receiver.
TE
APPLICATIONS
5
6
D1
T1
XFRMR
1
2
C601
0.1mF
TELEPHONE
4
715V
806V
V–
D2
7
9
AD816
0.1mF
5
R201
15V
10
11
7
715V
10mF
R103
196V
O
R203
196V
C201
8.2mF
R204
1.18kV
L201
12mH
C101
8.2mF
R104
1.18kV
9
6
8
R102
196V
R202
196V
–15V
10
C602
0.1mF
R106
348V
R105
162V
TWISTED PAIR
3
2
1
AD816
RCV OUT+
R1
R107
1kV
L101
12mH
R206
348V
R205
162V
R108
2.37kV
12
13 AD816
14
RCV OUT–
R2
R207
1kV
R208
2.37kV
Figure 50. AD816 as an ADSL Transceiver
–14–
REV. B
AD816
by R101 and all the downstream circuitry comprised of T1, the
transmission line and its termination. For an ideal transformer,
transmission line and termination, this will appear to be 15 Ω,
and thus the signal appearing at Pins 1 and 2 of T1 will be the
output of D1 divided by two in the ideal case. This signal is
applied to the input of R1 (Receive 1 of the AD816) (Pin 3) via
R105.
Dual Composite Amplifier
In some ADSL systems (DMT), there is a need to transmit
higher crest factor signals. Typically this is done by increasing
the turns ratio of T1 to as much as 4:1. In this case, R101 and
R201 would be 3.75 Ω, and the peak current of the AD816
(1 A) would be the drive limit of the transmitter.
The circuit in Figure 51 shows an example of such a circuit. It
uses receiver amp R1 for the low noise first stage and driver D1
for the high output current second stage. Both local and overall
feedback are used to get the desired response.
A composite amplifier uses two different op amps together in a
circuit to yield an overall performance that has some of the
advantages of each op amp. In the case of the AD816, two composite amplifiers can be constructed that offer the low noise of
the receiver amps in addition to the high current output of the
driver amps.
R1 is configured as a difference amplifier. The negative side
(Pin 2) is driven by another signal that is a divided down version
of the output of D1. This circuit is formed by R102 as one side
of the voltage divider along with R103, C101, R104 and L101
as the other half of the divider. If the frequency dependent
impedance part of this circuit matches the transformer, transmission line and termination impedance, then the signals
applied to both sides of the difference-amp-configured R1 will
be the same, and the transmit signal will be totally subtracted
out by the circuit.
2
4
TE
R1
3
VIN
D1
6
VOUT
5
Figure 51. AD816 Composite Amplifier
LE
Creating Differential Signals
B
SO
In a real-world situation, it is not practical (or even possible) to
subtract out all of the transmit signal (100% trans-hybrid loss),
but only provide a first order cancellation which goes a long way
toward reducing the dynamic range of the RCVOUT signal.
The overall performance of this circuit depends on the ability to
build a lumped element network that matches the impedance of
the transmission line over the frequency range required for
ADSL (≈ 20 kHz to 1.1 MHz).
The circuits formed by D2 and R2 of the AD816 are totally
symmetric with those formed by D1 and R1 and work in the
same fashion. All the components in the D1, R1 circuits that are
numbered with 100 range numbers are numbered with 200
range numbers in the D2, R2 circuits.
If only a single-ended signal is available to drive the AD816 and
a differential output signal is desired, a circuit can be used to
perform the single-ended to differential conversion.
The circuit shown in Figure 52 performs this function. It uses
the AD816 with the gain of one receiver set at +1 and the gain
of the other at –1. The 1 kΩ resistor across the input terminals
of the follower makes the noise gain (NG = 2) equal to the
inverter’s. The two receiver outputs then differentially drive the
inputs to the AD816 driver with no common-mode signal to first
order.
O
The receive signal from the telephone line creates a differential
signal across the primary of T1. There is, however, a two to one
reduction in amplitude due to turns ratio of T1. This differential signal is applied to the + inputs (Pins 3 and 12) of R1 and
R2. The receive amplifiers buffer this signal and present a differential output at Pins 1 and 14. There is no significant receive
signal applied to the negative inputs of R1 and R2 due to the
attenuating effects of R101 and R201 and the low output
impedances of D1 and D2.
+15V
+15V
0.1mF
100V
4
3
1kV
8
AD816
1
5
6
RF
499V
1kV
RG
100V
RL
1kV
1kV
6
RF
499V
10
RECEIVER #2 AD816
4
7
DRIVER #2
0.1mF
AD816
11
100V
9
7
0.1mF
–15V
–15V
Figure 52. Differential Driver with Single-Ended
Differential Converter
REV. B
–15–
10mF
8
DRIVER #1 AD816
2
5
Thus, the overall circuit provides first order cancellation of the
transmit signal and differential buffering of the receive signal.
0.1mF
RECEIVER #1
10mF
AD816
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.079 (2.006)
DIA
2 PLACES
0.600 (15.24)
BSC
8°
0°
0.671
±0.006
(17.043
±0.152)
SHORT
0.080 (2.03) LEAD
0.065 (1.65)
2 PLACES
0.079
(2.006) DIA
2 PLACES
0.042
(1.066)
TYP
1
15
0.798 (20.27)
0.778 (19.76)
0.182 (4.62)
0.172 (4.37)
0.182 (4.62)
0.172 (4.37)
0.031 (0.79)
SEATING
0.024 (0.60) PLANE
SEATING
PLANE
LE
0.100 (2.54)
BSC
0.137
(3.479)
TYP
PIN 1
0.024 (0.61)
0.014 (0.36)
0.798 (20.27)
0.778 (19.76)
0.063 (1.60)
0.057 (1.45)
0.394
(10.007)
0.666
±0.006
(16.916
±0.152)
LONG
LEAD
0.691 ±0.010
(17.551 ±0.254)
0.766 ±0.010
(19.456 ±0.254)
0.791 ±0.010
(20.091 ±0.254)
PIN 1
0.152 (3.86)
0.148 (3.76)
TE
0.080 (2.03)
0.065 (1.65)
2 PLACES
15
0.694 (17.63)
0.684 (17.37)
0.426 (10.82)
0.416 (10.57)
1
0.146 (3.70)
0.138 (3.50)
0.088 (2.24)
0.068 (1.72)
0.694 (17.63)
0.684 (17.37)
0.137
(3.479)
0.516
TYP
(13.106)
0.042
(1.066)
TYP
0.110
(2.79)
BSC
0.516 (13.106)
0.063 (1.60)
0.057 (1.45)
0.394
(10.007)
0.426 (10.82)
0.416 (10.57)
0.110
(2.79) 0.152 (3.86)
BSC 0.148 (3.76)
C2191b–0–12/99 (rev. B)
15-Lead Through-Hole SIP with Staggered Leads
and 90ⴗ Lead Form
(Y-15)
15-Lead Surface Mount DDPAK
(VR-15)
0.024 (0.61)
0.014 (0.36)
0.209 ±0.010
(5.308 ±0.254)
0.050 0.031 (0.79)
(1.27) 0.024 (0.60)
BSC
0.700 (17.78) BSC
O
0.394
(10.007)
0.137
(3.48)
TYP
0.042
(1.07)
TYP
1
15
0.516 (13.106)
0.694 (17.63)
0.684 (17.37)
0.426 (10.82)
0.416 (10.57)
0.110
0.152 (3.86)
(2.79)
BSC 0.148 (3.76)
0.080 (2.03)
0.065 (1.65)
2 PLACES
PIN 1
0.700 (17.78) BSC
0.079
(2.007) DIA
2 PLACES
0.063 (1.60)
0.057 (1.45)
0.601
±0.010
(15.265 0.710 (18.03)
±0.254) 0.690 (17.53)
LONG
LEAD
0.627
±0.010
(15.926
±0.254)
SHORT
LEAD
0.024 (0.61)
0.014 (0.36)
0.798 (20.27)
0.778 (19.76)
0.176 (4.47)
0.150 (3.81)
0.169 0.200
(4.29) (5.08)
BSC BSC
PRINTED IN U.S.A.
B
SO
15-Lead Through-Hole SIP with Staggered Leads
and Straight Lead Form
(YS-15)
0.182 (4.62)
0.172 (4.37)
SEATING
PLANE
0.050 (1.27)
BSC
0.031 (0.79)
0.024 (0.60)
–16–
REV. B