SEMICONDUCTOR TECHNICAL DATA ! The MC14597B and MC14598B are 8–bit latches, one addressed with an internal counter and the other addressed with an external binary address. The 8 latch–outputs are high drive, three–state and bus line compatible. The drive capability allows direct applications with MPU systems such as the Motorola 6800 family. With MC14597B, a 3–bit address counter (clocked on the falling edge of Increment) selects the appropriate latch. The latches of the MC14598B are accessed via the Address pins, A0, A1, and A2. A Full Flag is provided on the MC14597B to indicate the position of the Address counter. All 8 outputs from the latches are available in parallel when Enable is in the low state. Data is entered into a selected latch from the Data pin when the Strobe is high. Master reset is available on both parts. • Serial Data Input • Three–State Bus Compatible Parallel Outputs • Three–State Control Pin (Enable) TTL Compatible Input • Open Drain Full Flag (Multiple Latch Wire–O Ring) • Master Reset • Level Shifting Inputs on All Except Enable • Diode Protection — All Inputs • Supply Voltage Range — 3.0 Vdc to 18 Vdc • Capable of Driving TTL Over Rated Temperature Range With Fanout as Follows: 1 TTL Load 4 LSTTL Loads P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14597BCP MC14597BCL MC14597BDW 2 L SUFFIX CERAMIC CASE 726 4 ENABLE RESET LOGIC DATA STROBE 3–BIT ADDRESS COUNTER ADDRESS DECODER 3 6 THREE STATE OUTPUT BUFFERS 8 LATCHES 7 1 15 14 13 12 11 10 9 INCREMENT FULL LOGIC VDD = 16 VSS = 8 Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. BLOCK DIAGRAMS MC14597B RESET L SUFFIX CERAMIC CASE 620 D0 D1 D2 D3 D4 D5 D6 D7 D0 1 16 VDD RESET 2 15 D1 DATA 3 14 D2 ORDERING INFORMATION ENABLE 4 13 D3 FULL 5 12 D4 MC14598BCP MC14598BCL STROBE 6 11 D5 INCREMENT 7 10 D6 VSS 8 9 D7 5 FULL MC14598B OUTPUT TRUTH TABLE ENABLE 4 RESET DATA STROBE 2 3 6 A0 7 A1 8 ADDRESS A2 10 DECODER VDD = 18 VSS = 9 8 LATCHES 1 17 THREE 16 STATE 15 OUTPUT 14 BUFFERS 13 12 11 D0 D1 D2 D3 D4 D5 D6 D7 P SUFFIX PLASTIC CASE 707 Enable Outputs 1 High Impedance 0 Dn Dn = State of nth latch NC = NO CONNECTION Plastic Ceramic TA = – 55° to 125°C for all packages. D0 1 18 VDD RESET 2 17 D1 DATA 3 16 D2 ENABLE 4 15 D3 NC 5 14 D4 STROBE 6 13 D5 A0 7 12 D6 A1 8 11 D7 VSS 9 10 A2 REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14597B MC14598B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) Parameter Symbol VDD DC Supply Voltage Value Unit – 0.5 to + 18.0 V Vin Input Voltage, Enable (DC or Transient) – 0.5 to VDD + 0.5 V Vin Input Voltage, All other Inputs (DC or Transient) – 0.5 to VDD + 12 V Vout Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C 260 _C Iin, lout TL Lead Temperature (8–Second Soldering) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: “P and D/DW” Packages: – 7.0 mW/C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 0.8 1.6 2.4 — — — 1.1 2.2 3.4 0.8 1.6 2.4 — — — 0.8 1.6 2.4 5.0 10 15 2.0 6.0 10 — — — 2.0 6.0 10 1.9 3.1 4.3 — — — 2.0 6.0 10 — — — Vin = 0 or VDD Input Voltage** — Enable “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIL VIH Input Voltage “0” Level Other Inputs (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL (VO = 0.5 or 4.5 Vdc) “1” Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current Source (Full — Sink Only) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) VIH Vdc Vdc Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — IOH Vdc mAdc 5.0 10 15 – 1.0 — — – — — – 1.0 — — – 2.0 – 6.0 – 12 — — — – 1.0 — — — — — IOL 5.0 10 15 1.6 — — — — — 1.6 — — 3.2 6.0 12 — — — 1.6 — — — — — mAdc 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Three–State Leakage Current Iin ITL 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 3.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Sink IT = (2.0 µA/kHz) f + IDD IT = (4.0 µA/kHz) f + IDD IT = (6.0 µA/kHz) f + IDD †Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. **Total Supply Current at an **External Load Capacitance of **130 pF MC14597B MC14598B 2 IT 5.0 10 µAdc MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (TA = 25_C, CL = 130 pF + 1 TTL Load) All Types VDD Vdc Min Typ # Max 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 160 125 100 320 250 200 Strobe to Output 5.0 10 15 — — — 200 100 80 400 200 160 Strobe to Full (MC14597B only) 5.0 10 15 — — — 200 100 80 400 200 160 Reset to Output 5.0 10 15 — — — 175 90 70 350 180 140 5.0 10 15 320 240 160 160 120 80 — — — Strobe 5.0 10 15 200 100 80 100 50 40 — — — Increment (MC14597B only) 5.0 10 15 200 100 80 100 50 40 — — — Reset 5.0 10 15 300 160 100 150 80 50 — — — 5.0 10 15 100 50 35 50 25 20 — — — Address (MC14598B only) 5.0 10 15 200 100 70 100 50 35 — — — Increment (MC14597B only) 5.0 10 15 400 200 170 200 100 85 — — — 5.0 10 15 100 50 35 50 25 20 — — — 5.0 10 15 100 50 35 50 25 20 — — — 5.0 10 15 20 20 20 – 25 – 15 – 10 — — — Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (0.5 ns/pF) CL + 35 ns tTLH, tTHL = (0.2 ns/pF) CL + 25 ns tTLH, tTHL = (0.16 ns/pF) CL + 20 ns tTLH, tTHL Propagation Delay Time Enable to Output tPLH, tPHL Pulse Width Enable Setup Time Data Hold Time Data tWH, tWL Reset Removal Time ns ns ns tsu ns th Address (MC14598B only) trem Unit ns ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. MOTOROLA CMOS LOGIC DATA MC14597B MC14598B 3 MC14597B FUNCTION DIAGRAM VDD ENABLE 4 TO OTHER LATCHES RESET 2 VDD 5 FULL R D Q CLK STROBE 6 VDD DATA 3 1 D0 TO OTHER LATCHES SEVEN SELECT VSS ONE LATCH ZERO SELECT R 3 STAGE COUNTER AND DECODER 15 14 13 12 11 10 9 ADDITIONAL 7 LATCHES CLK D1 D2 D3 D4 D5 D6 D7 INCREMENT 7 MC14597B TIMING DIAGRAMS D6 (INTERNAL) D7 (INTERNAL) tWL tWH INCREMENT 20 ns 90% DATA tsu tsu 10% th STROBE 10% 20 ns tW FULL tPHL trem 50% RESET tW NOTE: Enable in High state. tTLH Dn 90% 1 10% 90% tTHL 90% 10% tPHL FULL ENABLE * * tWL * 1.4 V with VDD = 5.0 V NOTES: 1. High–impedance output state (another device controls bus). 2. Reset in High state. MC14597B MC14598B 4 MOTOROLA CMOS LOGIC DATA MC14598B FUNCTION DIAGRAM RESET 2 VDD DATA 3 1 D0 TO OTHER LATCHES STROBE 6 ENABLE 4 VSS EACH LATCH TO OTHER LATCHES ZERO SELECT 17 16 15 14 13 12 11 A0 7 ADDRESS DECODER A1 8 ADDITIONAL 7 LATCHES A2 10 (M.S.B) D1 D2 D3 D4 D5 D6 D7 MC14598B TIMING DIAGRAM 90% 10% 50% tPLH tTHL D7 90% 10% 50% 1 tPLH RESET tPHL tTLH 20 ns tW 90% 10% 50% A0, A1, A2 tsu th DATA 90% 10% STROBE tsu th 50% 90% 10% 20 ns 20 ns ENABLE tW * tW * 1.4 V with VDD = 5.0 V NOTES: 1. High–impedance output state (another device controls bus). 2. Output Load as for MC14597B. MOTOROLA CMOS LOGIC DATA MC14597B MC14598B 5 LATCH TRUTH TABLE TRUTH TABLE FOR MC14597B Address Latch Other Latches 1 * 1 Data 0 0 0 Strobe Reset 0 1 X Increment Address Counter Enable Reset * X 1 Count Up — * X 1 No Change — X 1 0 Reset to Zero Set to One X 0 1 No Change Set to One 1 If at ADDRESS 7 To Zero on Falling Edge of STROBE * = No change in state of latch X = Don’t care X 1 Full X = Don’t care TEST LOAD ALL OUTPUTS +5.0 V RL = 2.5 k Dn 130 pF 11.7 k Circuit diagrams external to or containing Motorola products are included as a means of illustration only. Complete information sufficient for construction purposes may not be fully illustrated. Although the information herein has been carefully checked and is believed to be reliable. Motorola assumes no responsibility for inaccuracies. Information herein does not convey to the purchaser any license under the MC14597B MC14598B 6 patent rights of Motorola or others. The information contained herein is for guidance only, with no warranty of any type, expressed or implied. Motorola reserves the right to make any changes to the information and the product(s) to which the information applies and to discontinue manufacture of the product(s) at any time. MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) MOTOROLA CMOS LOGIC DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14597B MC14598B 7 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) T B M A S S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 L SUFFIX CERAMIC DIP PACKAGE CASE 726–04 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F FOR FULL LEADS. HALF LEADS OPTIONAL AT LEAD POSITIONS 1, 9, 10, AND 18. –A– 18 10 1 9 –B– OPTIONAL LEAD CONFIGURATION (1, 9, 10, 18) DIM A B C D F G J K L M N L C N –T– SEATING PLANE K F M G D 18 PL 0.25 (0.010) MC14597B MC14598B 8 M T A S J 18 PL 0.25 (0.010) M T B INCHES MIN MAX 0.880 0.910 0.240 0.295 ––– 0.200 0.015 0.021 0.055 0.070 0.100 BSC 0.008 0.012 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 22.35 23.11 6.10 7.49 ––– 5.08 0.38 0.53 1.40 1.78 2.54 BSC 0.20 0.30 3.18 4.32 7.62 BSC 0_ 15_ 0.51 1.02 S MOTOROLA CMOS LOGIC DATA P SUFFIX PLASTIC DIP PACKAGE CASE 707–02 ISSUE C 18 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 10 B 1 9 A L C N F H D G K SEATING PLANE M J DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0_ 15 _ 0.020 0.040 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC DATA ◊ *MC14597B/D* MC14597B MC14598B MC14597B/D 9