Catalyst CAT25C09YITE13 1k/2k/4k/8k/16k spi serial cmos eeprom Datasheet

CAT25C11/03/05/09/17
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
FEATURES
■ 10 MHz SPI compatible
■ 1,000,000 program/erase cycles
■ 1.8 to 6.0 volt operation
■ 100 year data retention
■ Hardware and software protection
■ Self-timed write cycle
■ Low power CMOS technology
■ 8-pin DIP/SOIC, 8-pin TSSOP and 8-pin MSOP
■ SPI modes (0,0 & 1,1)*
■ 16/32-byte page write buffer
■ Commercial, industrial, automotive and extended
■ Write protection
temperature ranges
a
P
DESCRIPTION
input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C11/03/05/09/17 is designed
with software and hardware write protection features
including Block Write protection. The device is available
in 8-pin DIP, 8-pin SOIC, 8/14-pin TSSOP and 8-pin
MSOP packages.
The CAT25C11/03/05/09/17 is a 1K/2K/4K/8K/16K-Bit
SPI Serial CMOS EEPROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s
advanced CMOS Technology substantially reduces
device power requirements. The CAT25C11/03/05
features a 16-byte page write buffer. The 25C09/17
features a 32-byte page write buffer.The device operates
via the SPI bus serial interface and is enabled though a
Chip Select (CS). In addition to the Chip Select, the clock
it
n
o
PIN CONFIGURATION
d
e
u
n
DIP Package (P, L, GL)
MSOP Package (R, Z, GZ)* SOIC Package (S, V, GV)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
*CAT25C11/03 only
SO
SCK
WP
VCC
WP
VSS
1
2
3
4
8
7
6
5
VCC
CS
SO
WP
VSS
HOLD
SCK
SI
SO
SI
Write Protect
CS
+1.8V to +6.0V Power Supply
Chip Select
SI
Serial Data Input
HOLD
Suspends Serial Input
NC
No Connect
4
5
SI
CS
SO
WP
VSS
WORD ADDRESS
BUFFERS
Serial Clock
CS
VCC
HOLD
SCK
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
SENSE AMPS
SHIFT REGISTERS
Serial Data Output
Ground
8
7
6
TSSOP Package (U, Y, GY)
BLOCK DIAGRAM
Function
VSS
1
2
3
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
CONTROL LOGIC
i
D
Pin Name
CS
SO
c
s
PIN FUNCTIONS
s
t
r
– Protect first page, last page, any 1/4 array or
lower 1/2 array
XDEC
COLUMN
DECODERS
EEPROM
ARRAY
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Other SPI modes available on request.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
STATUS
REGISTER
1
Doc. No. 1017, Rev. L
CAT25C11/03/05/09/17
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS(1) .................. –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
a
P
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
NEND(3)
Endurance
TDR(3)
Data Retention
100
VZAP(3)
ESD Susceptibility
2000
ILTH(3)(4)
Latch-up
100
Max.
1,000,000
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol
Typ.
it
n
o
Parameter
Min.
Typ.
d
e
mA
5
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
3
mA
VCC = 5.5V
FCLK = 5MHz
1
µA
CS = VCC
VIN = VSS or VCC
ICC2
Power Supply Current
(Operating Read)
ISB(6)
Power Supply Current
(Standby)
ILI
Input Leakage Current
2
µA
ILO
Output Leakage Current
3
µA
VIL(5)
Input Low Voltage
-1
VCC x 0.3
V
VIH(5)
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage
0.4
V
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
VCC - 0.8
V
0.2
VCC-0.2
Volts
Units
Power Supply Current
(Operating Write)
i
D
Years
Max.
ICC1
c
s
Units
Cycles/Byte
u
n
Limits
s
t
r
Test Conditions
VOUT = 0V to VCC,
CS = 0V
2.7V≤VCC<5.5V
IOL = 3.0mA
IOH = -1.6mA
V
1.8V≤VCC<2.7V
V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) VILMIN and VIHMAX are reference values only and are not tested.
(6) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1017, Rev. L
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C11/03/05/09/17
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
Test Conditions
Max.
Units
Conditions
COUT
Output Capacitance (SO)
8
pF
VOUT=0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN=0V
ns
s
t
r
ns
VOH = 2.0v
A.C. CHARACTERISTICS
Limits
1.8V-6.0V
SYMBOL PARAMETER
Min.
2.5V-6.0V
Max. Min.
Max.
4.5V-5.5V
Min.
a
P
Max.
UNITS Conditions
tSU
Data Setup Time
50
20
20
tH
Data Hold Time
50
20
20
tWH
SCK High Time
250
75
40
tWL
SCK Low Time
250
75
fSCK
Clock Frequency
DC
tLZ
HOLD to Output Low Z
tRI(1)
Input Rise Time
tFI(1)
Input Fall Time
tHD
HOLD Setup Time
100
tCD
HOLD Hold Time
100
tWC(3)
Write Cycle Time
tV
Output Valid from Clock Low
tHO
Output Hold Time
tDIS
Output Disable Time
250
75
75
ns
tHZ
HOLD to Output High Z
150
50
50
ns
tCS
CS High Time
tCSS
CS Setup Time
tCSH
CS Hold Time
tWPS
tCSH
(3)
50
u
n
2
2
it
n
o
c
s
0
d
e
DC
40
40
5
DC
ns
ns
VIH = 2.4V
CL = 100pF
VOL = 0.8V
10
MHz
50
50
ns
2
2
µs
CL = 50pF
2
2
µs
(note 2)
40
ns
40
ns
10
5
5
ms
250
75
40
ns
0
0
CL = 100pF
ns
500
100
100
ns
500
100
100
ns
500
100
100
ns
WP Setup Time
150
50
50
ns
CS Hold Time
150
50
50
ns
i
D
(1)
(2)
1
40
Test
This parameter is tested initially and after a design or process change that affects the parameter.
AC Test Conditions:
Input Pulse Voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5VCC
Output load: current source IOL max/IOH max; CL = 50pF
tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1017, Rev. L
CAT25C11/03/05/09/17
FUNCTIONAL DESCRIPTION
the operation to be performed.
The CAT25C11/03/05/09/17 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C11/03/05/09/17 to
interface directly with many of today’s popular
microcontrollers. The CAT25C11/03/05/09/17 contains
an 8-bit instruction register. (The instruction set and the
operation codes are detailed in the instruction set table)
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C11/03/05/09/17.Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
Figure 1. Sychronous Data Timing
1
2
3
4
5
6
7
8
CS
SO
NC
NC
NC
NC
WP
VSS
it
n
o
Note: Dashed Line= mode (1, 1) – – – –
INSTRUCTION SET
c
s
Instruction
WREN
i
D
WRDI
RDSR
WRSR
READ
WRITE
s
t
r
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the 25C11/03/05/09/17. During a read cycle,
data is shifted out on the falling edge of the serial clock for
a
P
16
VCC
15
14
13
12
11
10
9
HOLD
u
n
d
e
NC
NC
NC
NC
SCK
SI
Opcode
Operation
0000 0110
Enable Write Operations
0000 0100
Disable Write Operations
0000 0101
Read Status Register
0000 0001
Write Status Register
0000 X011(1)
Read Data from Memory
0000 X010(1)
Write Data to Memory
Power-Up Timing(2)(3)
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Note:
(1) X=0 for 25C11, 25C03, 25C09, 25C17. X=A8 for 25C05
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Doc. No. 1017, Rev. L
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C11/03/05/09/17
and forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25C11/03/
05/09/17 draws ZERO current in the Standby mode. A
high to low transition on CS is required prior to any
sequence being initiated. A low to high transition on CS
after a valid write sequence is what initiates an internal
write cycle.
SPI modes (0,0 & 1,1).
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
25C11/03/05/09/17. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK for SPI modes (0,0 & 1,1).
WP
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will allow
normal read/write operations when held high. When WP is
tied low and the WPEN bit in the status register is set to "1",
all write operations to the status register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle as already been
initiated, WP going low will have no effect on any write
CS
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C11/
03/05/09/17 and CS high disables the CAT25C11/03/05/
09/17. CS high takes the SO output pin to high impedance
BYTE ADDRESS
Device
Address Significant Bits
Address Don't Care Bits
CAT25C11
A6 - A0
A7
CAT25C03
A7 - A0
CAT25C05
A7 - A0 (A8 = X bit from Opcode)
CAT25C09
A9 - A0
A15 - A10
CAT25C17
A10 - A0
A15 - A11
6
WPEN
1
d
e
4
1
BP2
8
3
BP1
8
16
16
2
1
0
BP0
WEL
RDY
25C11
25C03
25C05
25C09
25C17
Q1
00-1F
00-3F
000-07F
000-0FF
000-1FF
Q1 Protected
Q2
20-3F
40-7F
080-0FF
100-1FF
200-3FF
Q2 Protected
Q3
40-5F
80-BF
100-17F
200-2FF
400-5FF
Q3 Protected
Q4
60-7F
C0-FF
180-1FF
300-3FF
600-7FF
Q4 Protected
H1
00-3F
00-7F
000-0FF
000-1FF
000-3FF
H1 Protected
P0
00-0F
00-0F
000-00F
000-01F
000-01F
0
P0 Protected
Pn
70-7F
F0-FF
1F0-1FF 3E0-3FF
7E0-7FF
1
Pn Protected
BP2
BP1
BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
c
s
i
D
8
—
u
n
5
it
n
o
MEMORY PROTECTION
# Address Clock Pulse
—
STATUS REGISTER
7
a
P
s
t
r
Non-Protection
WRITE PROTECT ENABLE OPERATION
WPEN
0
WP
X
WEL
0
Protected
Blocks
Protected
Unprotected
Blocks
Protected
Status
Register
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1017, Rev. L
CAT25C11/03/05/09/17
operation to the status register. The WP pin function is
blocked when the WPEN bit is set to 0. Figure 10 illustrates
the WP timing sequence during a write operation.
03/05/09/17 is busy with a write operation. When set to
1 a write cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only the WEL (Write
Enable) bit indicates the status of the write enable latch.
When set to 1, the device is in a Write Enable state and
when set to 0 the device is in a Write Disable state. The
WEL bit can only be set by the WREN instruction and can
be reset by the WRDI instruction.
HOLD
HOLD: Hold
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C11/03/05/09/17 while in the
middle of a serial sequence without having to re-transmit
entire sequence at a later time. To pause, HOLD must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication, HOLD is brought high, while SCK is low.
HOLD should be held high any time this function is not
being used. HOLD may be tied high directly to VCC or tied
to VCC through a resistor. Figure 9 illustrates hold timing
sequence.
d
e
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C11/
CS
it
n
o
SK
0
SI
0
0
c
s
SO
u
n
0
a
P
The WPEN (Write Protect Enable) is an enable b it for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect feature. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
to the status register, (including the block protect bits
STATUS REGISTER
Figure 2. WREN Instruction Timing
s
t
r
The BP0, BP1 and BP2 bits indicate which part of the
memory array is currently protected. These bits are set
by the user issuing the WRSR instruction. The user is
allowed to protect from one page to as much as half the
entire array. Once the three protection bits are set the
associated memory can be read but not written until the
protection bits are reset. These bits are non volatile.
0
1
1
0
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – –
i
D
Figure 3. WRDI Instruction Timing
CS
SK
SI
SO
0
0
0
0
0
1
0
0
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – –
Doc. No. 1017, Rev. L
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C11/03/05/09/17
and the WPEN bit) and the block protected sections in
the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continuing
to provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000h allowing the read cycle to be continued indefinitely.
DEVICE OPERATION
Write Enable and Disable
The CAT25C11/03/05/09/17 contains a write enable
latch. This latch must be set before any write operation.
The device powers up in a write disable state when Vcc
is applied. WREN instruction will enable writes (set the
latch) to the device. WRDI instruction will disable writes
(reset the latch) to the device. Disabling writes will
protect the device against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C11/03/05/09/17,
followed by the 16-bit address for 25C09/17 (only 10-bit
addresses are used for 25C09, 11-bit addresses are
used for 25C17. The rest of the bits are don't care bits)
and 8-bit address for 25C11/03/05 (for the 25C05, bit 3
of the read data instruction contains address A8).
it
n
o
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
c
s
SK
5
6
7
8
OPCODE
SI
SO
i
D
0
0
0
0
X*
9
s
t
r
The read operation is terminated by pulling the CS high.
Read sequece is illustrated in Figure 4. Reading status
register is illustrated in Figure 5. To read the status
register, RDSR instruction should be sent. The contents
of the status register are shifted out on the SO line. If a
non-volatile write is in progress, the RDSR instruction
returns a high on SO. When the non-volatile write cycle
is completed, the status register data is read out.
a
P
WRITE Sequence
The CAT25C11/03/05/09/17 powers up in a Write Disable state. Prior to any write instructions, the WREN
instruction must be sent to CAT25C11/03/05/09/17.
The device goes into Write enable state by pulling the
CS low and then clocking the WREN instruction into
CAT25C11/03/05/09/17. The CS must be brought high
d
e
u
n
10
20
21
22
*
23
24
25
26
27
28
29
*
30
2
1
BYTE ADDRESS*
0
1
1
AN
A0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
0
MSB
*Please check the Byte Address Table.
*X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05.
Note: Dashed Line= mode (1, 1) – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 1017, Rev. L
CAT25C11/03/05/09/17
enable latch will not have been properly set. Also, for a
successful write operation the address of the memory
location(s) to be programmed must be outside the protected address field.
device. If the write operation is initiated immediately after
the WREN instruction without CS being brought high,
the data will not be written to the array because the write
up to 16 bytes of data to the CAT25C11/03/05 and 32
bytes of data for 25C09/17. After each byte of data
received, lower order address bits are internally
incremented by one; the high order bits of address
willremain constant.The only restriction is that the X
(X=16 for 25C11/03/05 and X=32 for 25C09/17) bytes
must reside on the same page. If the address counter
reaches the end of the page and clock continues, the
counter will “roll over” to the first address of the page and
overwrite any data that may have been written. The
CAT25C11/03/05/09/17 is automatically returned to the
write disable state at the completion of the write cycle.
Figure 8 illustrates the page write sequence.
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C09/17. (only 10-bit addresses are
used for 25C09, 11-bit addresses are used for 25C17.
The rest of the bits are don't care bits) and 8-bit address
for 25C11/03/05 (for the 25C05, bit 3 of the read data
instruction contains address A8). Programming will start
after the CS is brought high. Figure 6 illustrates byte write
sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3, Bit 4 and Bit 7 of the
status register can be written using the write status
register instruction. Figure 7 illustrates the sequence of
writing to status register.
Page Write
The CAT25C11/03/05/09/17 features page write capability. After the initial byte, the host may continue to write
after the WREN instruction to enable writes to thee
d
e
Figure 5. RDSR Instruction Timing
CS
0
1
it
n
o
2
3
SCK
OPCODE
0
SI
0
4
0
0
0
5
6
1
0
u
n
7
8
c
s
9
10
11
6
5
4
12
13
14
2
1
1
HIGH IMPEDANCE
SO
a
P
s
t
r
7
DATA OUT
3
0
MSB
Note: Dashed Line= mode (1, 1) – – – –
i
D
Figure 6. Write Instruction Timing
CS
0
SK
SI
0
1
0
2
3
4
5
6
7
8
0
X*
22
*
23
24
25
26
BYTE ADDRESS*
OPCODE
0
21
0
1
0
AN
A0 D7
27
28
29
30
*
31
DATA IN
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE
SO
*Please check the Byte Address Table
X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05
Note: Dashed Line= mode (1, 1) – – – –
Doc. No. 1017, Rev. L
8
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C11/03/05/09/17
DESIGN CONSIDERATIONS
The CAT25C11/03/05/09/17 powers up in a write disable state and in a low power standby mode. A WREN
instruction must be issued to perform any writes to the
device after power up. Also,on power up CS should be
brought low to enter a ready state and receive an
instruction. After a successful byte/page write or status
register write the CAT25C11/03/05/09/17 goes into a
write disable mode. CS must be set high after the proper
number of clock cycles to start an internal write cycle.
Access to the array during an internal write cycle is
ignored and programming is continued. On power up,
SO is in a high impedance. If an invalid op code is
received, no data will be shifted into the CAT25C11/03/
05/09/17, and the serial output pin (SO) will remain in a
high impedance state until the falling edge of CS is
detected again.
When powering down, the supply should be taken down
to 0V, so that the CAT25C11/03/05/09/17 will be reset
when power is ramped back up. If this is not possible,
then, following a brown-out episode, the CAT25C11/
03/05/09/17 can be reset by refreshing the contents of
the Status Register (See Application Note AN10).
Figure 7. WRSR Instruction Timing
d
e
CS
0
1
2
3
4
5
6
SCK
OPCODE
SI
0
0
it
n
o
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – –
c
s
7
8
9
10
11
5
4
u
n
1
7
6
MSB
12
a
P
13
14
15
2
1
0
s
t
r
DATA IN
3
Figure 8. Page Write Instruction Timing
i
D
CS
0
SK
SI
0
1
2
3
4
5
6
7
8
0
0
X*
SO
22
23 24-31
0
1
0
AN
A0
32-39
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
DATA IN
BYTE ADDRESS*
OPCODE
0
21
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
HIGH IMPEDANCE
*Please check the Byte Address Table.
*X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05
Note: Dashed Line= mode (1, 1) – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 1017, Rev. L
CAT25C11/03/05/09/17
Figure 9. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
Figure 10. WP Timing
tWPS
CS
SCK
it
n
o
WP
WP
d
e
tWPH
u
n
a
P
s
t
r
tCSH
Note: Dashed Line= mode (1, 1) – – – –
c
s
i
D
Doc. No. 1017, Rev. L
10
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C11/03/05/09/17
ORDERING INFORMATION
Prefix
Device #
Suffix
25C17
CAT
Optional
Company ID
Product
Number
25C17:16K
25C09: 8K
25C05: 4K
25C03: 2K
25C11: 1K
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
E = Extended (-40°C to +125°C)
Package
P: PDIP
R: MSOP2
S: SOIC
U: TSSOP
L: PDIP (Lead free, Halogen free)
V: SOIC, JEDEC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Z: MSOP2 (Lead free, Halogen free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GV: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GZ: MSOP2 (Lead-free, Halogen-free, NiPdAu lead plating)
it
n
o
-1.8
I
S
d
e
u
n
TE13
s
t
r
Tape & Reel
a
P
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
Notes:
(1) The device used in the above example is a 25C17SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
(2) CAT25C11 and CAT25C03 only.
c
s
i
D
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 1017, Rev. L
REVISION HISTORY
Date
Rev.
Reason
08/03/2004
J
Updated Features
Updated DC Operating Characteristics table & notes
07/08/2005
K
Update Features
Update Pin Configuration
Update Reliability Characteristics
Update Ordering Information
09/22/2005
L
Update Pin Configuration
DPP ™
AE2 ™
it
n
o
MiniPot™
d
e
u
n
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
a
P
s
t
r
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
c
s
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
i
D
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.caalyst-semiconductor.com
Publication #:
Revison:
Issue date:
1017
L
09/22/05