Microsemi A42MX09-1CQG208M 40mx and 42mx fpga family Datasheet

Revision 11
40MX and 42MX FPGA Families
Features
HiRel Features
High Capacity
•
Commercial, Industrial, Automotive,
Temperature Plastic Packages
•
Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
•
Single-Chip ASIC Alternative
•
3,000 to 54,000 System Gates
•
Up to 2.5 kbits Configurable Dual-Port SRAM
•
QML Certification
•
Fast Wide-Decode Circuitry
•
Ceramic Devices Available to DSCC SMD
•
Up to 202 User-Programmable I/O Pins
and
Military
Ease of Integration
High Performance
•
Mixed-Voltage Operation (5.0V or 3.3V for core and
I/Os), with PCI-Compliant I/Os
•
5.6 ns Clock-to-Out
•
250 MHz Performance
•
Up to 100% Resource Utilization and 100% Pin Locking
•
5 ns Dual-Port SRAM Access
•
Deterministic, User-Controllable Timing
•
100 MHz FIFOs
•
•
7.5 ns 35-Bit Address Decode
Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
•
Low Power Consumption
•
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Capacity
System Gates
SRAM Bits
3,000
–
6,000
–
14,000
–
24,000
–
36,000
–
54,000
2,560
Logic Modules
Sequential
Combinatorial
Decode
–
295
–
–
547
–
348
336
–
624
608
–
954
912
24
1,230
1,184
24
9.5 ns
9.5 ns
5.6 ns
6.1 ns
6.1 ns
6.3 ns
SRAM Modules
(64x4 or 32x8)
–
–
–
–
–
10
Dedicated Flip-Flops
–
–
348
624
954
1,230
Maximum Flip-Flops
147
273
516
928
1,410
1,822
Clocks
1
1
2
2
2
6
User I/O (maximum)
57
69
104
140
176
202
PCI
–
–
–
–
Yes
Yes
Boundary Scan Test (BST)
–
–
–
–
Yes
Yes
44, 68
100
80
–
–
–
44, 68, 84
100
80
–
–
–
84
100, 160
100
176
–
–
84
100, 160, 208
100
176
–
–
84
160, 208
–
176
–
–
–
208, 240
–
–
208, 256
272
Clock-to-Out
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
May 2012
© 2012 Microsemi Corporation
i
40MX and 42MX FPGA Families
Ordering Information
A42MX16 _
PQ
1
100
G
ES
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
A = Automotive (–40 to +125°C)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
PL = Plastic Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
BG = Plastic Ball Grid Array
CQ =Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
= 3,000 System Gates
= 6,000 System Gates
= 14,000 System Gates
= 24,000 System Gates
= 36,000 System Gates
= 54,000 System Gates
Plastic Device Resources
User I/Os
PLCC
44-Pin
PLCC
68-Pin
PLCC
84-Pin
PQFP
100-Pin
PQFP
160-Pin
PQFP
208-Pin
PQFP
240-Pin
VQFP
80-Pin
VQFP
100-Pin
TQFP
176-Pin
PBGA
272-Pin
A40MX02
34
57
–
57
–
–
–
57
–
–
–
A40MX04
34
57
69
69
–
–
–
69
–
–
–
A42MX09
–
–
72
83
101
–
–
–
83
104
–
A42MX16
–
–
72
83
125
140
–
–
83
140
–
A42MX24
–
–
72
–
125
176
–
–
–
150
–
A42MX36
–
–
–
–
–
176
202
–
–
–
202
Device
Note: Package Definitions
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad
Flat Pack, PBGA = Plastic Ball Grid Array
ii
R evis i o n 11
40MX and 42MX FPGA Families
Ceramic Device Resources
User I/Os
Device
A42MX36
Note: Package Definitions
CQFP 208-Pin
CQFP 256-Pin
176
202
CQFP = Ceramic Quad Flat Pack
Temperature Grade Offerings
Package
A40MX02
A40MX04
PLCC 44
C, I, M
C, I, M
PLCC 68
C, I, A, M
C, I, M
PLCC 84
PQFP 100
C, I, A, M
A42MX09
A42MX16
A42MX24
C, I, A, M
C, I, A, M
C, I, M
C, I, M
C, I, A, M
C, I, A, M
C, I, M
C, I, A, M
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
PQFP 160
PQFP 208
PQFP 240
VQFP 80
A42MX36
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
VQFP 100
C, I, A, M
C, I, A, M
TQFP 176
C, I, A, M
C, I, A, M
C, I, A, M
PBGA 272
C, I, M
CQFP 208
C, M, B
CQFP 256
C, M, B
Note:
C = Commercial
I = Industrial
A = Automotive
M = Military
B = MIL-STD-883 Class B
Speed Grade Offerings
–F
Std
–1
–2
–3
✓
✓
✓
✓
✓
I
✓
✓
✓
✓
A
✓
M
✓
✓
B
✓
✓
C
Note: Refer to the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX offerings.
Contact your local Microsemi SoC Products Group representative for device availability.
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iii
40MX and 42MX FPGA Families
Table of Contents
40MX and 42MX FPGA Families
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
5.0 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-83
Package Pin Assignments
PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
R ev i si o n 1 1
iv
1 – 40MX and 42MX FPGA Families
General Description
Microsemi's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are
single-chip solutions and provide high performance while shortening the system design and development
cycle. MX devices can integrate and consolidate logic implemented in multiple PALs, CPLDs, and
FPGAs. Example applications include high-speed controllers and address decoding, peripheral bus
interfaces, DSP, and co-processor functions.
The MX device architecture is based on Microsemi’s patented antifuse technology implemented in a
0.45µm triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX
devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby power
consumption of comparable FPGAs. MX FPGAs provide up to 202 user I/Os and are available in a wide
variety of packages and speed grades.
A42MX24 and A42MX36 devices also feature MultiPlex I/Os, which support mixed-voltage systems,
enable programmable PCI, deliver high-performance operation at both 5.0V and 3.3V, and provide a lowpower mode. The devices are fully compliant with the PCI Local Bus Specification (version 2.1). They
deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance.
The 42MX24 and 42MX36 devices include system-level features such as IEEE Standard 1149.1 (JTAG)
Boundary Scan Testing and fast wide-decode modules. In addition, the A42MX36 device offers dual-port
SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The storage elements can
efficiently address applications requiring wide datapath manipulation and can perform transformation
functions such as those required for telecommunications, networking, and DSP.
All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest
member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened
to MIL-STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and
PQ208 devices are pin-compatible.
MX Architectural Overview
The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All
devices within these families are composed of logic modules, I/O modules, routing resources and clock
networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains
embedded dual-port SRAM modules, which are optimized for high-speed datapath functions such as
FIFOs, LIFOs and scratchpad memory. A42MX24 and A42MX36 also contain wide-decode modules.
Logic Modules
The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of
logic functions with efficient use of interconnect routing resources (Figure 1-1 on page 1-2).
The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of
two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity
functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the
array; latches and flip-flops can be constructed from logic modules whenever required in the
application.
R ev i si o n 1 1
1 -1
40MX and 42MX FPGA Families
Figure 1-1 •
40MX Logic Module
The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (Smodules) and decode (D-modules). Figure 1-2 illustrates the combinatorial logic module. The S-module,
shown in Figure 1-3, implements the same combinatorial logic function as the C-module while adding a
sequential element. The sequential element can be configured as either a D-flip-flop or a transparent
latch. The S-module register can be bypassed so that it implements purely combinatorial logic.
A0
B0
S0
D00
D01
Y
D10
D11
S1
A1
B1
Figure 1-2 •
1- 2
42MX C-Module Implementation
R ev isio n 1 1
40MX and 42MX FPGA Families
D00
D01
D00
D01
Y
D10
D
S0
D11
S1
Q
OUT
CLR
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D10
D11
S1
Y
S0
D
Q
OUT
GATE
Up to 7-Input Function Plus Latch
D00
D0
Y
D1
S
D
Q
OUT
D11
S1
GATE
CLR
Up to 4-Input Function Plus Latch with Clear
Figure 1-3 •
D01
D10
Y
OUT
S0
Up to 8-Input Function (Same as C-Module)
42MX S-Module Implementation
A42MX24 and A42MX36 devices contain D-modules, which are arranged around the periphery of the
device. D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that
found in CPLD architectures (Figure 1-4). The D-module allows A42MX24 and A42MX36 devices to
perform wide-decode functions at speeds comparable to CPLDs and PALs. The output of the D-module
has a programmable inverter for active HIGH or LOW assertion. The D-module output is hardwired to an
output pin, and can also be fed back into the array to be incorporated into other logic.
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules that have been optimized for synchronous or
asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as
32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user-definable width
and depth. A block diagram of the A42MX36 dual-port SRAM block is shown in Figure 1-5.
The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports.
Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0],
respectively) for 64x4-bit blocks. When configured in byte mode, the highest order address bits (RDAD5
and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks
(RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The
SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]), which are connected to
segmented vertical routing tracks.
The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications
requiring FIFO and LIFO queues. The ACTgen Macro Builder within Microsemi's Designer software
R ev i si o n 1 1
1 -3
40MX and 42MX FPGA Families
provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can
be used to implement registers for other user logic within the design.
7 Inputs
Hard-Wire to I/O
Programmable
Inverter
Feedback to Array
Figure 1-4 •
A42MX24 and A42MX36 D-Module Implementation
WD[7:0]
Latches
[7:0]
WRAD[5:0]
MODE
BLKEN
WEN
[5:0]
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
[5:0]
Read
Port
Logic
Latches
Read
Logic
Latches
RD[7:0]
Write
Logic
WCLK
Figure 1-5 •
Write
Port
Logic
RDAD[5:0]
REN
RCLK
Routing Tracks
A42MX36 Dual-Port SRAM Block
Routing Structure
The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O
modules. These routing tracks are metal interconnects that may be continuous or split into segments.
Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two
antifuse connections. Segments can be joined together at the ends using antifuses to increase their
lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four
antifuses.
Horizontal Routing
Horizontal routing tracks span the whole row length or are divided into multiple segments and are located
in between the rows of modules. Any segment that spans more than one-third of the row length is
considered a long horizontal segment. A typical channel is shown in Figure 1-6. Within horizontal routing,
dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. Nondedicated tracks are used for signal nets.
Vertical Routing
Another set of routing tracks run vertically through the module. There are three types of vertical tracks:
input, output, and long. Long tracks span the column length of the module, and can be divided into
multiple segments. Each segment in an input track is dedicated to the input of a particular module; each
segment in an output track is dedicated to the output of a particular module. Long segments are
1- 4
R ev isio n 1 1
40MX and 42MX FPGA Families
uncommitted and can be assigned during routing. Each output segment spans four channels (two above
and two below), except near the top and bottom of the array, where edge effects occur. Long vertical
tracks contain either one or two segments. An example of vertical routing tracks and segments is shown
in Figure 1-6.
Antifuse Structures
An antifuse is a "normally open" structure. The use of antifuses to implement a programmable logic
device results in highly testable structures as well as efficient programming algorithms. There are no preexisting connections; temporary connections can be made using pass transistors. These temporary
connections can isolate individual antifuses to be programmed and individual circuit structures to be
tested, which can be done before and after programming. For instance, all metal tracks can be tested for
continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified.
Segmented
Horizontal
Routing
Logic
Modules
Antifuses
Vertical Routing Tracks
Figure 1-6 •
MX Routing Structure
Clock Networks
The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK
network by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout clock distribution networks, referred to as CLKA
and CLKB. Each network has a clock module (CLKMOD) that can select the source of the clock signal
from any of the following (Figure 1-7 on page 1-6):
•
Externally from the CLKA pad, using CLKBUF buffer
•
Externally from the CLKB pad, using CLKBUF buffer
•
Internally from the CLKINTA input, using CLKINT buffer
•
Internally from the CLKINTB input, using CLKINT buffer
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal
clock track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock
networks.
The A42MX36 device has four additional register control resources, called quadrant clock networks
(Figure 1-8 on page 1-6). Each quadrant clock provides a local, high-fanout resource to the contiguous
logic modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O
R ev i si o n 1 1
1 -5
40MX and 42MX FPGA Families
pins or from the internal array and can be used as a secondary register clock, register clear, or output
enable.
CLKB
CLKINB
CLKA
From
Pads
CLKINA
CLKMOD
S0
S1
Internal
Signal
CLKO(17)
Clock
Drivers
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
Clock Tracks
Figure 1-7 •
Clock Networks of 42MX Devices
QCLKA
QCLKB
QCLKC
Quad
Clock
Modul
QCLK1
QCLK3
Quad
Clock
Modul
*QCLK1IN
QCLKD
*QCLK3IN
S0 S1
Quad
Clock
Modul
S1 S0
QCLK2
QCLK4
Quad
Clock
Modul
*QCLK2IN
*QCLK4IN
S0 S1
S1 S0
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 • Quadrant Clock Network of A42MX36 Devices
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R ev isio n 1 1
40MX and 42MX FPGA Families
MultiPlex I/O Modules
42MX devices feature Multiplex I/Os and support 5.0V, 3.3V, and mixed 3.3V/5.0V operations.
The MultiPlex I/O modules provide the interface between the device pins and the logic array. Figure 1-9
is a block diagram of the 42MX I/O module. A variety of user functions, determined by a library macro
selection, can be implemented in the module. (Refer to the Antifuse Macro Library Guide for more
information.) All 42MX I/O modules contain tristate buffers, with input and output latches that can be
configured for input, output, or bidirectional operation.
All 42MX devices contain flexible I/O structures, where each output pin has a dedicated output-enable
control (Figure 1-9). The I/O module can be used to latch input or output data, or both, providing fast setup time. In addition, the Designer software tools can build a D-type flip-flop using a C-module combined
with an I/O module to register input and output signals. Refer to the Antifuse Macro Library Guide for
more details.
A42MX24 and A42MX36 devices also offer selectable PCI output drives, enabling 100% compliance with
version 2.1 of the PCI specification. For low-power systems, all inputs and outputs are turned off to
reduce current consumption to below 500μA.
To achieve 5.0V or 3.3V PCI-compliant output drives on A42MX24 and A42MX36 devices, a chip-wide
PCI fuse is programmed via the Device Selection Wizard in the Designer software (Figure 1-10). When
the PCI fuse is not programmed, the output drive is standard.
Designer software development tools provide a design library of I/O macro functions that can implement
all I/O configurations supported by the MX FPGAs.
EN
Q
D
PAD
From Array
G/CLK*
To Array
Q
D
G/CLK*
Note: *Can be configured as a Latch or D Flip-Flop (Using
C-Module)
Figure 1-9 •
42MX I/O Module
STD
Signal
Output
PCI
Drive
PCI Enable
Fuse
Figure 1-10 • PCI Output Structure of A42MX24 and A42MX36 Devices
R ev i si o n 1 1
1 -7
40MX and 42MX FPGA Families
Other Architectural Features
Performance
MX devices can operate with internal clock frequencies of 250 MHz, enabling fast execution of complex
logic functions. MX devices are live on power-up and do not require auxiliary configuration devices and
thus are an optimal platform to integrate the functionality contained in multiple programmable logic
devices. In addition, designs that previously would have required a gate array to meet performance can
be integrated into an MX device with improvements in cost and time-to-market. Using timing-driven
place-and-route (TDPR) tools, designers can achieve highly deterministic device performance.
User Security
Microsemi FuseLock provides robust security against design theft. Special security fuses are hidden in
the fabric of the device and protect against unauthorized users attempting to access the programming
and/or probe interfaces. It is virtually impossible to identify or bypass these fuses without damaging the
device, making Microsemi antifuse FPGAs protected with the highest level of security available from both
invasive and noninvasive attacks.
Special security fuses in 40MX devices include the Probe Fuse and Program Fuse. The former disables
the probing circuitry while the latter prohibits further programming of all fuses, including the Probe Fuse.
In 42MX devices, there is the Security Fuse which, when programmed, both disables the probing circuitry
and prohibits further programming of the device.
Programming
Device programming is supported through the Silicon Sculptor series of programmers. Silicon Sculptor II
is a compact, robust, single-site and multi-site device programmer for the PC. With standalone software,
Silicon Sculptor II is designed to allow concurrent programming of multiple units from the same PC.
Silicon Sculptor II programs devices independently to achieve the fastest programming times possible.
After being programmed, each fuse is verified to insure that it has been programmed correctly.
Furthermore, at the end of programming, there are integrity tests that are run to ensure no extra fuses
have been programmed. Not only does it test fuses (both programmed and nonprogrammed), Silicon
Sculptor II also allows self-test to verify its own hardware extensively.
The procedure for programming an MX device using Silicon Sculptor II is as follows:
1. Load the *.AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Microsemi offers device volume-programming services
either through distribution partners or via In-House Programming from the factory.
For more details on programming MX devices, please refer to the Programming Antifuse Devices and the
Silicon Sculptor II user's guides.
1- 8
R ev isio n 1 1
40MX and 42MX FPGA Families
Power Supply
MX devices are designed to operate in both 5.0V and 3.3V environments. In particular, 42MX devices
can operate in mixed 5.0V/3.3V systems. Table 1-1 describes the voltage support of MX devices.
Table 1-1 •
Voltage Support of MX Devices
Device
VCC
VCCA
VCCI
Maximum Input Tolerance
Nominal Output Voltage
40MX
5.0 V
–
–
5.5 V
5.0V
3.3 V
–
–
3.6 V
3.3V
–
5.0 V
5.0 V
5.5 V
5.0V
–
3.3 V
3.3 V
3.6 V
3.3V
–
5.0 V
3.3 V
5.5 V
3.3V
42MX
Power-Up/Down in Mixed-Voltage Mode
When powering up 42MX in mixed voltage mode (VCCA = 5.0 V and VCCI = 3.3 V), VCCA must be
greater than or equal to VCCI throughout the power-up sequence. If VCCI exceeds VCCA during powerup, one of two things will happen:
•
The input protection diode on the I/Os will be forward biased
•
The I/Os will be at logical High
In either case, ICC rises to high levels.
For power-down, any sequence with VCCA and VCCI can be implemented.
Transient Current
Due to the simultaneous random logic switching activity during power-up, a transient current may appear
on the core supply (VCC). Customers must use a regulator for the VCC supply that can source a
minimum of 100 mA for transient current during power-up. Failure to provide enough power can prevent
the system from powering up properly and result in functional failure. However, there are no reliability
concerns, since transient current is distributed across the die instead of confined to a localized spot.
Since the transient current is not due to I/O switching, its value and duration are independent of the
VCCI.
Low Power Mode
42MX devices have been designed with a Low Power Mode. This feature, activated with setting the
special LP pin to HIGH for a period longer than 800 ns, is particularly useful for battery-operated systems
where battery life is a primary concern. In this mode, the core of the device is turned off and the device
consumes minimal power with low standby current. In addition, all input buffers are turned off, and all
outputs and bidirectional buffers are tristated. Since the core of the device is turned off, the states of the
registers are lost. The device must be re-initialized when exiting Low Power Mode. I/Os can be driven
during LP mode, and clock pins should be driven HIGH or LOW and should not float to avoid drawing
current. To exit LP mode, the LP pin must be pulled LOW for over 200 µs to allow for charge pumps to
power up, and device initialization will begin.
R ev i si o n 1 1
1 -9
40MX and 42MX FPGA Families
Power Dissipation
The general power consumption of MX devices is made up of static and dynamic power and can be
expressed with the following equation:
General Power Equation
P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N + IOH * (VCCI – VOH) * M
where:
ICCstandby is the current flowing when no inputs or outputs are changing.
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to VOL.
M equals the number of outputs driving TTL loads to VOH.
Accurate values for N and M are difficult to determine because they depend on the family type, on design
details, and on the system I/O. The power can be divided into two components: static and active.
Static Power Component
The static power due to standby current is typically a small component of the overall power consumption.
Standby power is calculated for commercial, worst-case conditions. The static power dissipation by TTL
loads depends on the number of outputs driving, and on the DC load current. For instance, a 32-bit bus
sinking 4mA at 0.33V will generate 42mW with all outputs driving LOW, and 140mW with all outputs
driving HIGH. The actual dissipation will average somewhere in between, as I/Os switch states with time.
Active Power Component
Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation. Dynamic
power consumption is frequency-dependent and is a function of the logic and the external I/O. Active
power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external capacitances due to PC board traces and
load device inputs. An additional component of the active power dissipation is the totem pole current in
the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be
combined with frequency and voltage to represent active power dissipation.
The power dissipated by a CMOS circuit can be expressed by the equation:
Power (µW) = CEQ * VCCA2 * F(1)
where:
CEQ = Equivalent capacitance expressed in picofarads (pF)
VCCA = Power supply in volts (V)
F = Switching frequency in megahertz (MHz)
Equivalent Capacitance
Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for
each circuit component of interest. Measurements have been made over a range of frequencies at a
fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a
wide range of operating conditions. Equivalent capacitance values are shown below.
1- 10
R ev i sio n 1 1
40MX and 42MX FPGA Families
CEQ Values for Microsemi MX FPGAs
Modules (CEQM)3.5
Input Buffers (CEQI)6.9
Output Buffers (CEQO)18.2
Routed Array Clock Buffer Loads (CEQCR)1.4
To calculate the active power dissipated from the complete design, the switching frequency of each part
of the logic must be known. The equation below shows a piece-wise linear summation over all
components.
Power = VCCA2 * [(m x CEQM * fm)Modules +
(n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs +
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 +
0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2)
where:
m
= Number of logic modules switching at frequency fm
n
= Number of input buffers switching at frequency fn
p
= Number of output buffers switching at frequency fp
q1
= Number of clock loads on the first routed array clock
q2
= Number of clock loads on the second routed array clock
r1
= Fixed capacitance due to first routed array clock
r2
= Fixed capacitance due to second routed array clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQC = Equivalent capacitance of routed array clock in pF
R
CL
= Output load capacitance in pF
fm
= Average logic module switching rate in MHz
fn
= Average input buffer switching rate in MHz
fp
= Average output buffer switching rate in MHz
fq1
= Average first routed array clock rate in MHz
fq2
= Average second routed array clock rate in MHz
Fixed Capacitance Values for MX FPGAs (pF)
Device Type
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
r1
routed_Clk1
41.4
68.6
118
165
185
220
r2
routed_Clk2
N/A
N/A
118
165
185
220
R ev i si o n 1 1
1- 11
40MX and 42MX FPGA Families
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides built-in access to every node in a design, via the use of
Silicon Explorer II. Silicon Explorer II is an integrated hardware and software solution that, in conjunction
with the Designer software, allow users to examine any of the internal nets of the device while it is
operating in a prototyping or a production system. The user can probe into an MX device without
changing the placement and routing of the design and without using any additional resources. Silicon
Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle
and providing a true representation of the device under actual functional situations.
Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II
attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer.
Silicon Explorer II allows designers to complete the design verification process at their desks and
reduces verification time from several hours per cycle to a few seconds.
Silicon Explorer II is used to control the MODE, DCLK, SDI and SDO pins in MX devices to select the
desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II
software to the PRA/PRB output pins for observation. Probing functionality is activated when the MODE
pin is held HIGH.
Figure 1-11 illustrates the interconnection between Silicon Explorer II and 40MX devices, while Figure 112 on page 1-12 illustrates the interconnection between Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must not be programmed. (Refer to "User Security"
section on page 1-8 for the security fuses of 40MX and 42MX devices). Table 1-2 on page 1-13
summarizes the possible device configurations for probing.
PRA and PRB pins are dual-purpose pins. When the "Reserve Probe Pin" is checked in the
Designer software, PRA and PRB pins are reserved as dedicated outputs for probing. If PRA and PRB
pins are required as user I/Os to achieve successful layout and "Reserve Probe Pin" is checked, the
layout tool will override the option and place user I/Os on PRA and PRB pins.
16 Logic Analyzer Channels
Serial Connection
to Windows PC
40MX
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRB
PRA
Figure 1-11 • Silicon Explorer II Setup with 40MX
16 Logic Analyzer Channels
Serial Connection
to Windows PC
42MX
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRB
Figure 1-12 • Silicon Explorer II Setup with 42MX
1- 12
R ev i sio n 1 1
PRA
40MX and 42MX FPGA Families
Table 1-2 •
Device Configuration Options for Probe Capability
Security Fuse(s)
Programmed
Mode
PRA, PRB1
SDI, SDO, DCLK1
No
LOW
User I/Os2
User I/Os2
No
HIGH
Probe Circuit Outputs
Probe Circuit Inputs
Yes
–
Probe Circuit Secured
Probe Circuit Secured
Notes:
1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are
active during probing, input signals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the "Pin
Descriptions" section on page 1-83 for information on unused I/O pins.
Design Consideration
It is recommended to use a series 70Ω termination resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70Ω series termination is used to prevent data transmission corruption
during probing and reading back the checksum.
IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry
42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint
Testing Action Group Standard or JTAG), which defines a set of hardware architecture and mechanisms
for cost-effective board-level testing. The basic MX boundary-scan logic circuit is composed of the TAP
(test access port), TAP controller, test data registers and instruction register (Figure 1-13 on page 1-14).
This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and
BYPASS) and some optional instructions. Table 1-3 on page 1-14 describes the ports that control JTAG
testing, while Table 1-4 on page 1-14 describes the test instructions supported by these MX devices.
Each test section is accessed through the TAP, which has four associated pins: TCK (test clock input),
TDI and TDO (test data input and output), and TMS (test mode selector).
The TAP controller is a four-bit state machine. The '1's and '0's represent the values that must be
present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the
instruction register or the data register is operating in that state.
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals
for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset
state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for
five TCK cycles.
42MX24 and 42MX36 devices support three types of test data registers: bypass, device identification,
and boundary scan. The bypass register is selected when no other register needs to be accessed in a
device. This speeds up test data transfer to other devices in a test data path. The 32-bit device
identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part
number and version). The boundary-scan register observes and controls the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and
parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a
device into a boundary-scan register chain, which starts at the TDI pin and ends at the TDO pin. The
R ev i si o n 1 1
1- 13
40MX and 42MX FPGA Families
parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O
buffer to capture and load data into the register to control or observe the logic state of each I/O.
Boundary Scan Register
Output
MUX
TDO
Bypass
Register
Control Logic
JTAG
TMS
TAP Controller
TCK
Instruction
Decode
JTAG
Instruction
Register
TDI
Figure 1-13 • 42MX IEEE 1149.1 Boundary Scan Circuitry
Table 1-3 •
Test Access Port Descriptions
Port
Description
TMS
(Test Mode Select)
Serial input for the test logic control bits. Data is captured on the rising edge of the test logic
clock (TCK).
TCK
(Test Clock Input)
Dedicated test logic clock used serially to shift test instruction, test data, and control inputs
on the rising edge of the clock, and serially to shift the output data on the falling edge of the
clock. The maximum clock frequency for TCK is 20 MHz.
TDI
(Test Data Input)
Serial input for instruction and test data. Data is captured on the rising edge of the test logic
clock.
TDO
(Test Data Output)
Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive
state (high impedance) when data scanning is not in progress.
Table 1-4 •
Supported BST Public Instructions
Instruction
IR Code Instruction
(IR2.IR0)
Type
Description
EXTEST
000
Mandatory
Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
SAMPLE/PRELOAD
001
Mandatory
Allows a snapshot of the signals at the device pins to be captured
and examined during operation
HIGH Z
101
Optional
Tristates all I/Os to allow external signals to drive pins. Please refer to
the IEEE Standard 1149.1 specification.
CLAMP
110
Optional
Allows state of signals driven from component pins to be determined
from the Boundary-Scan Register. Please refer to the IEEE Standard
1149.1 specification for details.
BYPASS
111
Mandatory
Enables the bypass register between the TDI and TDO pins. The test
data passes through the selected device to adjacent devices in the
test chain.
1- 14
R ev i sio n 1 1
40MX and 42MX FPGA Families
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer software by selecting Tools -> Device Selection.
This brings up the Device Selection dialog box as shown in Figure 1-14. The JTAG test logic circuit can
be enabled by clicking the "Reserve JTAG Pins" check box. Table 1-5 explains the pins' behavior in
either mode.
Figure 1-14 • Device Selection Wizard
Table 1-5 •
Boundary Scan Pin Configuration and Functionality
Reserve JTAG
Checked
Unchecked
TCK
BST input; must be terminated to logical HIGH or LOW to avoid floating
User I/O
TDI, TMS
BST input; may float or be tied to HIGH
User I/O
TDO
BST output; may float or be connected to TDI of another device
User I/O
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX devices contain power-on circuitry that resets
the boundary scan circuitry upon power-up. Also, the TMS pin is equipped with an internal pull-up
resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is
no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five
TCK cycles.
Boundary Scan Description Language (BSDL) File
Conforming to the IEEE Standard 1149.1 requires that the operation of the various JTAG components be
documented. The BSDL file provides the standard format to describe the JTAG components that can be
used by automatic test equipment software. The file includes the instructions that are supported,
instruction bit pattern, and the boundary-scan chain order. For an in-depth discussion on BSDL files,
please refer to Actel BSDL Files Format Description application note.
BSDL files are grouped into two categories - generic and device-specific. The generic files assign all user
I/Os as inouts. Device-specific files assign user I/Os as inputs, outputs or inouts.
Generic files for MX devices are available on the Microsemi SoC Product Group's website:
http://www.microsemi.com/soc/techdocs/models/bsdl.html.
R ev i si o n 1 1
1- 15
40MX and 42MX FPGA Families
Development Tool Support
The MX family of FPGAs is fully supported by Libero® Integrated Design Environment (IDE). Libero IDE
is a design management environment, seamlessly integrating design tools while guiding the user through
the design flow, managing all design and log files, and passing necessary design data among tools.
Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the
entire design in a single environment. Libero IDE includes SynplifyPro from Synopsys, ModelSim® HDL
Simulator from Mentor Graphics,® and Viewdraw.
Libero IDE includes place-and-route and provides a comprehensive suite of backend support tools for
FPGA development, including timing-driven place-and-route, and a world-class integrated static timing
analyzer and constraints editor.
Additionally, the back-annotation flow is compatible with all the major simulators and the simulation
results can be cross-probed with Silicon Explorer II, Microsemi’s integrated verification and logic analysis
tool. Another tool included in the Libero software is the SmartGen macro builder, which easily creates
popular and commonly used logic functions for implementation into your schematic or HDL design.
Microsemi’s Libero software is compatible with the most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synopsys, and Cadence Design Systems.
Refer to the Libero IDE web content at www.microsemi.com/soc/products/software/libero/default.aspx for
further information on licensing and current operating system support.
Related Documents
Application Notes
Actel BSDL Files Format Description
www.microsemi.com/soc/documents/BSDLformat_AN.pdf
Programming Antifuse Devices
http://www.microsemi.com/soc/documents/AntifuseProgram_AN.pdf
Actel's Implementation of Security in Actel Antifuse FPGAs
www.microsemi.com/documents/Antifuse_Security_AN.pdf
User’s Guides and Manuals
Antifuse Macro Library Guide
www.microsemicom/soc/documents/libguide_UG.pdf
Silicon Sculptor II
www.microsemi.com/soc/techdocs/manuals/default.asp#programmers
Miscellaneous
Libero IDE Flow Diagram
www.microsemi.com/soc/products/tools/libero/flow.html
5.0 V Operating Conditions
Table 1-6 •
Absolute Maximum Ratings for 40MX Devices*
Symbol
Parameter
Limits
Units
–0.5 to +7.0
V
VCC
DC Supply Voltage
VI
Input Voltage
–0.5 to VCC+0.5
V
VO
Output Voltage
–0.5 to VCC+0.5
V
1- 16
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-6 •
Absolute Maximum Ratings for 40MX Devices*
Symbol
Parameter
tSTG
Storage Temperature
Limits
Units
–65 to +150
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-7 •
Absolute Maximum Ratings for 42MX Devices*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.5 to +7.0
V
VCCA
DC Supply Voltage for Array
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCCI+0.5
V
VO
Output Voltage
–0.5 to VCCI+0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-8 •
Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
0 to +70
–40 to +85
–55 to +125
°C
VCC (40MX)
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCA (42MX)
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCI (42MX)
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
Temperature Range*
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for
military grades.
R ev i si o n 1 1
1- 17
40MX and 42MX FPGA Families
5 V TTL Electrical Specifications
Table 1-9 •
5V TTL Electrical Specifications
Commercial
Symbol
1
VOH
Parameter
Min.
IOH = –10 mA
2.4
Max.
Commercial -F
Min.
Max.
Min.
Max.
Min.
Max.
0.5
Units
V
3.7
IOL = 10 mA
Military
2.4
IOH = –4 mA
VOL1
Industrial
3.7
V
0.5
V
IOL = 6 mA
0.4
0.8
–0.3
0.8
0.4
V
–0.3
0.8
V
VIL
–0.3
0.8
–0.3
VIH (40MX)
2.0
VCC + 0.3
2.0
VCC + 0.3 2.0 VCC + 0.3
2.0
VCC + 0.3
V
VIH (42MX)
2.0
VCCI + 0.3
2.0
VCCI + 0.3 2.0 VCCI + 0.3 2.0
VCCI + 0.3
V
IIL
VIN = 0.5 V
–10
–10
–10
–10
µA
IIH
VIN = 2.7 V
–10
–10
–10
–10
µA
Input Transition
Time, TR and TF
500
500
500
500
ns
CIO I/O
Capacitance
10
10
10
10
pF
Standby Current, A40MX02,
ICC2
A40MX04
3
25
10
25
mA
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24,
A42MX36
20
25
25
25
mA
0.5
ICC – 5.0
ICC – 5.0
ICC – 5.0
mA
Low power mode 42MX devices
Standby Current only
IIO, I/O source
sink current
Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
Notes:
1. Only one output tested at a time. VCC/VCCI = min.
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
1- 18
R ev i sio n 1 1
40MX and 42MX FPGA Families
3.3 V Operating Conditions
Table 1-10 • Absolute Maximum Ratings for 40MX Devices*
Symbol
Parameter
Limits
Units
–0.5 to +7.0
V
VCC
DC Supply Voltage
VI
Input Voltage
–0.5 to VCC + 0.5
V
VO
Output Voltage
–0.5 to VCC + 0.5
V
tSTG
Storage Temperature
–65 to + 150
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-11 • Absolute Maximum Ratings for 42MX Devices*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.5 to +7.0
V
VCCA
DC Supply Voltage for Array
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCCI+0.5
V
VO
Output Voltage
–0.5 to VCCI+0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-12 • Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
Temperature Range*
0 to +70
–40 to +85
–55 to +125
°C
VCC (40MX)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
VCCA (42MX)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
VCCI (42MX)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for
military grades.
R ev i si o n 1 1
1- 19
40MX and 42MX FPGA Families
3.3 V LVTTL Electrical Specifications
Table 1-13 • 3.3V LVTTL Electrical Specifications
Commercial
Symbol
Parameter
Min.
VOH
IOH = –4 mA
2.15
VOL1
IOL = 6 mA
1
Max.
Commercial -F
Min.
Max.
2.15
0.4
Industrial
Min.
Max.
2.4
0.4
Military
Min.
Max.
Units
2.4
0.48
V
0.48
V
VIL
–0.3
0.8
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
VIH (40MX)
2.0
VCC + 0.3
2.0
VCC + 0.3
2.0
VCC + 0.3
2.0
VCC + 0.3
V
VIH (42MX)
2.0
VCCI + 0.3
2.0
VCCI + 0.3
2.0
VCCI + 0.3
2.0
VCCI + 0.3
V
IIL
–10
–10
–10
–10
µA
IIH
–10
–10
–10
–10
µA
Input Transition
Time, TR and TF
500
500
500
500
ns
CIO I/O
Capacitance
10
10
10
10
pF
A40MX02,
A40MX04
3
25
10
25
mA
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24,
A42MX36
15
25
25
25
mA
42MX
devices only
0.5
ICC - 5.0
ICC - 5.0
ICC - 5.0
mA
Standby
Current, ICC2
Low-Power
Mode Standby
Current
IIO, I/O source Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
sink current
Notes:
1. Only one output tested at a time. VCC/VCCI = min.
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
1- 20
R ev i sio n 1 1
40MX and 42MX FPGA Families
Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX Devices
Only)
Table 1-14 • Absolute Maximum Ratings*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.5 to +7.0
V
VCCA
DC Supply Voltage for Array
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCCA +0.5
V
VO
Output Voltage
–0.5 to VCCI + 0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices
should not be operated outside the Recommended Operating Conditions.
Table 1-15 • Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
0 to +70
–40 to +85
–55 to +125
°C
VCCA
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCI
3.14 to 3.47
3.0 to 3.6
3.0 to 3.6
V
Temperature Range*
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for
military grades.
R ev i si o n 1 1
1- 21
40MX and 42MX FPGA Families
Mixed 5.0V/3.3V Electrical Specifications
Table 1-16 • Mixed 5.0V/3.3V Electrical Specifications
Commercial
Symbol
VOH1
Parameter
Min.
Max.
IOH = –10 mA 2.4
Commercial –F
Min.
Max.
Min.
Max.
Min.
Max.
0.5
2.4
V
0.5
V
IOL = 6 mA
0.4
0.8
–0.3
Units
V
2.4
IOL = 10 mA
Military
2.4
IOH = –4 mA
VOL1
Industrial
0.8
–0.3
0.8
–0.3
0.4
V
0.8
V
VIL
–0.3
VIH
2.0 VCCA + 0.3 2.0 VCCA + 0.3 2.0 VCCA + 0.3 2.0 VCCA + 0.3
V
IL
VIN = 0.5 V
–10
–10
–10
–10
µA
IH
VIN = 2.7 V
–10
–10
–10
–10
µA
500
500
500
500
ns
10
10
10
10
pF
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24,
A42MX36
20
25
25
25
mA
0.5
ICC – 5.0
ICC – 5.0
ICC – 5.0
mA
Input Transition
Time, TR and TF
C
IO I/O
Capacitance
Standby Current,
ICC2
Low Power Mode
Standby Current
IIO I/O source sink Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
current
Notes:
1. Only one output tested at a time. VCCI = min.
2. All outputs unloaded. All inputs = VCCI or GND.
1- 22
R ev i sio n 1 1
40MX and 42MX FPGA Families
Output Drive Characteristics for 5.0 V PCI Signaling
MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 1-15 on
page 1-25 shows the typical output drive characteristics of the MX devices. MX output drivers are
compliant with the PCI Local Bus Specification.
Table 1-17 • DC Specification (5.0 V PCI Signaling)1
PCI
Symbol
Parameter
Condition
Min.
MX
Max.
Min.
Max.
2
Units
VCCI
Supply Voltage for I/Os
4.75
5.25
4.75
5.25
VIH
Input High Voltage
2.0
VCC + 0.5
2.0
VCCI + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current
VIN = 2.7 V
70
—
10
µA
IIL
Input Low Leakage Current
VIN=0.5 V
–70
—
–10
µA
VOH
Output High Voltage
VOL
Output Low Voltage
CIN
Input Pin Capacitance
CCLK
CLK Pin Capacitance
LPIN
IOUT = –2 mA
IOUT = –6 mA
2.4
V
V
3.84
IOUT = 3 mA, 6 mA
5
Pin Inductance
0.55
—
0.33
V
10
—
10
pF
12
—
10
pF
20
—
nH3
<8
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.
2. Maximum rating for VCCI –0.5 V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and
capacitance.
Table 1-18 • AC Specifications (5.0V PCI Signaling)*
PCI
Symbol
Parameter
Condition
Min.
–5 < VIN ≤ –1
–25 + (VIN +1) /0.015
MX
Max.
Min.
Max.
Units
–60
–10
mA
ICL
Low Clamp Current
Slew (r)
Output Rise Slew Rate 0.4 V to 2.4 V load
1
5
1.8
2.8
V/ns
Slew (f)
Output Fall Slew Rate
1
5
2.8
4.3
V/ns
2.4 V to 0.4 V load
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.
R ev i si o n 1 1
1- 23
40MX and 42MX FPGA Families
Output Drive Characteristics for 3.3 V PCI Signaling
Table 1-19 • DC Specification (3.3 V PCI Signaling)1
PCI
Symbol
Parameter
Condition
MX
Min.
Max.
Min.
Max.
Units
VCCI
Supply Voltage for I/Os
3.0
3.6
3.0
3.6
V
VIH
Input High Voltage
0.5
VCC + 0.5
0.5
VCCI + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current
70
10
µA
IIL
Input Leakage Current
–70
–10
µA
VOH
Output High Voltage
IOUT = –2 mA
VOL
Output Low Voltage
IOUT = 3 mA, 6 mA
CIN
Input Pin Capacitance
CCLK
CLK Pin Capacitance
LPIN
VIN = 2.7V
0.9
3.3
5
Pin Inductance
V
0.1
0.1 VCCI
V
10
10
pF
12
10
pF
20
<8
nH3
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.
2. Maximum rating for VCCI –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and
capacitance.
Table 1-20 • AC Specifications for (3.3 V PCI Signaling)*
PCI
Symbol
Condition
Min.
–5 < VIN ≤ –1
–25 + (VIN +1) /0.015
Slew (r) Output Rise Slew Rate
0.2 V to 0.6 V load
1
Slew (f) Output Fall Slew Rate
0.6 V to 0.2 V load
1
ICL
Parameter
Low Clamp Current
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.
1- 24
R ev i sio n 1 1
MX
Max.
Min.
Max.
Units
–60
–10
mA
4
1.8
2.8
V/ns
4
2.8
4.0
V/ns
40MX and 42MX FPGA Families
0.50
0.45
0.40
PCI IOL Maximum
0.35
0.30
0.25
Current (A)
0.20
MX PCI IOL
0.15
0.10
PCI IOL Minimum
0.05
0.00
0
–0.05
1
2
3
4
PCI IOH Maximum
5
6
MX PCI IOH
–0.10
–0.15
PCI IOH Minimum
–0.20
Voltage Out (V)
Figure 1-15 • Typical Output Drive Characteristics (Based Upon Measured Data)
Junction Temperature (TJ)
The temperature variable in the Designer software refers to the junction temperature, not the ambient
temperature. This is an important distinction because the heat generated from dynamic power
consumption is usually hotter than the ambient temperature. EQ , shown below, can be used to calculate
junction temperature.
Junction Temperature = ΔT + Ta (1)
EQ 1
Where:
Ta = Ambient Temperature
ΔT = Temperature gradient between junction (silicon) and ambient
ΔT = θja * P (2)
P = Power
θja = Junction to ambient of package. θja numbers are located in Table 1-21 on page 1-26.
R ev i si o n 1 1
1- 25
40MX and 42MX FPGA Families
Package Thermal Characteristics
The device junction-to-case thermal characteristic is θjc, and the junction-to-ambient air characteristic is
θja. The thermal characteristics for θja are shown with two different air flow rates.
The maximum junction temperature is 150°C.
Maximum power dissipation for commercial- and industrial-grade devices is a function of θja.
A sample calculation of the absolute maximum power dissipation allowed for a TQ176 package at
commercial temperature and still air is given in EQ 2.
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 70°C
Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------ = ------------------------------------- = 2.86 W
28°C/W
θ ja (°C/W)
EQ 2
The maximum power dissipation for military-grade devices is a function of θjc. A sample calculation of the
absolute maximum power dissipation allowed for CQFP 208-pin package at military temperature and still
air is given in EQ 3.
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 125°C
Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------ = ---------------------------------------- = 3.97 W
6.3°C/W
θ jc (°C/W)
EQ 3
Table 1-21 • Package Thermal Characteristics
θja
Pin Count
θjc
Still Air
1.0 m/s
200 ft/min.
2.5 m/s
500 ft/min.
Units
Plastic Quad Flat Pack
100
12.0
27.8
23.4
21.2
°C/W
Plastic Quad Flat Pack
160
10.0
26.2
22.8
21.1
°C/W
Plastic Quad Flat Pack
208
8.0
26.1
22.5
20.8
°C/W
Plastic Quad Flat Pack
240
8.5
25.6
22.3
20.8
°C/W
Plastic Leaded Chip Carrier
44
16.0
20.0
24.5
22.0
°C/W
Plastic Leaded Chip Carrier
68
13.0
25.0
21.0
19.4
°C/W
Plastic Leaded Chip Carrier
84
12.0
22.5
18.9
17.6
°C/W
Thin Plastic Quad Flat Pack
176
11.0
24.7
19.9
18.0
°C/W
Very Thin Plastic Quad Flat Pack
80
12.0
38.2
31.9
29.4
°C/W
Very Thin Plastic Quad Flat Pack
100
10.0
35.3
29.4
27.1
°C/W
Plastic Ball Grid Array
272
3.0
18.3
14.9
13.9
°C/W
Ceramic Quad Flat Pack
208
2.0
22.0
19.8
18.0
°C/W
Ceramic Quad Flat Pack
256
2.0
20.0
16.5
15.0
°C/W
Plastic Packages
Ceramic Packages
1- 26
R ev i sio n 1 1
40MX and 42MX FPGA Families
Timing Models
Input Delay
Predicted
Routing
Delays
Internal Delays
I/O Module
tINYL = 0.62 ns
Output Delay
I/O Module
tIRD2 = 2.59 ns
Logic Module
tIRD1 = 2.09 ns
tIRD4 = 3.64 ns
tIRD8 = 5.73 ns
Array
Clock
tCKH
= 4.55 ns
tPD = 1.24 ns
tCO = 1.24 ns
tRD1 = 1.28 ns
tRD2 = 1.80 ns
tRD4 = 2.33 ns
tRD8 = 4.93 ns
tDLH = 3.32 ns
tENHZ = 7.92 ns
FO = 128
FMAX = 180 MHz
Note: Values are shown for 40MX –3 speed devices at 5.0 V worst-case commercial conditions.
Figure 1-16 • 40MX Timing Model*
Input Delays
Predicted
Routing
Delays
Internal Delays
I/O Module
tINYL = 0.8 ns
Output Delays
I/O Module
tIRD1 = 2.0 ns1
Combinatorial
Logic Module
D
Q
tDLH = 2.5 ns
tRD1 = 0.7 ns
tRD2 = 1.9 ns
tRD4 = 1.4 ns
tRD8 = 2.3 ns
tPD=1.2 ns
G
tDLH = 2.5 ns
Sequential
Logic Module
tINH = 0.0 ns
tINSU = 0.3 ns
tINGL = 1.3 ns
D
Q
Comb.
Logic
Include
Array
Clocks
tCKH = 2.70 ns
I/O Module
FO = 32
FMAX = 296 MHz
tSUD = 0.3 ns
tHD = 0.00 ns
D
Q
tRD1 = 0.70 ns
tENHZ = 4.9 ns
G
tCO = 1.3 ns
tOUTH = 0.00 ns
tOUTSU = 0.3 ns
tGLH = 2.6 ns
tLCO = 5.2 ns (light loads, pad-to-pad)
Notes:
1. Input module predicted routing delay
2. Values are shown for A42MX09 –3 at 5.0 V worst-case commercial conditions.
Figure 1-17 • 42MX Timing Model
R ev i si o n 1 1
1- 27
40MX and 42MX FPGA Families
Input Delays
I/O Module
tINPY = 1.0 ns
D
Q
Predicted
Routing
Delays
Internal Delays
Output Delays
I/O Module
tIRD1= 2.0 ns
Combinatorial
Module
tDLH = 2.6 ns
tRD1 = 0.9 ns
tRD2 = 1.3 ns
tRD4 = 2.0 ns
tPD=1.3 ns
G
tINH = 0.0 ns
tINSU = 0.5 ns
tINGO = 1.4 ns
Decode
Module
tRDD = 0.3 ns
tPDD = 1.6 ns
I/O Module
tDLH = 2.6 ns
Sequential
Logic Module
D
Comb.
Logic
Include
tRD1 = 0.9 ns
Q
G
tCO = 1.3 ns
tCKH=3.03 ns1
FMAX=180 MHz
Notes:
1. Load-dependent
2. Values are shown for A42MX36 –3 at 5.0 V worst-case commercial conditions.
Figure 1-18 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)
1- 28
D
tENHZ = 5.3 ns
tSUD = 3.0 ns
tHD = 0.0 ns
Quadrant
Clocks
Q
R ev i sio n 1 1
tLH = 0.00 ns
tLSU = 0.5 ns
tGHL = 2.9 ns
40MX and 42MX FPGA Families
Input Delays
I/O Module
tINPY = 1 .0 ns
D
tIRD1 = 2.0 ns
Q
G
tINSU = 0.5 ns
tINH = 0.0 ns
tINGO = 1.4 ns
Predicted
Routing
Delays
WD [7:0]
WRAD [5:0]
RD [7:0]
RDAD [5:0]
t
RD1
= 0.9 ns
BLKEN
REN
D
WEN
WCLK
RCLK
G
tADSU = 1.6 ns
tADH = 0.0 ns
tWENSU = 2.7 ns
tBENS = 2.8 ns
Array
Clocks
I/O Module
tDLH = 2.6 ns
tADSU = 1.6 ns
tADH = 0.0 ns
tRENSU = 0.6 ns
tRCO = 3.4 ns
Q
tGHL = 2.9 ns
tLSU = 0.5 ns
tLH = 0.0 ns
FMAX = 167 MHz
Note: Values are shown for A42MX36 –3 at 5.0 V worst-case commercial conditions.
Figure 1-19 • 42MX Timing Model (SRAM Functions)
R ev i si o n 1 1
1- 29
40MX and 42MX FPGA Families
Parameter Measurement
E
D
In
E
50% 50%
VOH
PAD
1.5 V
VOL
tDLH
PAD To AC test loads (shown below)
TRIBUFF
E
50% 50%
VCCI
1.5 V
PAD
VOL
1.5 V
tDHL
tENZL
10%
PAD
GND
tENLZ
50% 50%
VOH
1.5 V
tENZH
90%
tENHZ
Figure 1-20 • Output Buffer Delays
Load 2
(Used to measure rising/falling edges)
Load 1
(Used to measure propagation delay)
VCCI
GND
To the output under test
R to VCCI for tPLZ / tPZL
R to GND for tPHZ / tPZH
R =1 kΩ
35 pF
To the output under test
35 pF
Figure 1-21 • AC Test Loads
PAD
3V
PAD 1.5 V 1.5 V
VCCI
Y
50%
GND
tINYH
Figure 1-22 • Input Buffer Delays
1- 30
Y
INBUF
R ev i sio n 1 1
0V
50%
tINYL
40MX and 42MX FPGA Families
S
A
B
Y
S, A or B 50% 50%
Y
Y
50%
50%
tPLH
PHL
50%
tPHL
50%
tPLH
Figure 1-23 • Module Delays
Sequential Module Timing Characteristics
D
E
CLK
Y
PRE
CLR
(Positive Edge-Triggered)
tHD
D*
tSUD
tA
tWCLKA
G, CLK
tSUENA
tHENA
E
tWCLK1
tCO
Q
tRS
PRE, CLR
tWASYN
Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops.
Figure 1-24 • Flip-Flops and Latches
R ev i si o n 1 1
1- 31
40MX and 42MX FPGA Families
Sequential Timing Characteristics
PAD
DATA
IBDL
G
CLK PAD
DATA
tINH
INSU
G
tINSU
tHEXT
CLK
tSU EXT
Figure 1-25 • Input Buffer Latches
D
PAD
OBDLHS
G
D
tOUTSU
G
tOUTH
Figure 1-26 • Output Buffer Latches
1- 32
R ev i sio n 1 1
40MX and 42MX FPGA Families
Decode Module Timing
A
B
C
D
E
F
G
Y
H
A–G, H
50%
Y
tPHL
tPLH
Figure 1-27 • Decode Module Timing
SRAM Timing Characteristics
Read Port
Write Port
WRAD [5:0]
RDAD [5:0]
RAM Array
3 2x8 or 64x4
(2 56 Bits)
BLKEN
WEN
WCLK
LEW
REN
RCLK
WD [7:0]
RD [7:0]
Figure 1-28 • SRAM Timing Characteristics
Dual-Port SRAM Timing Waveforms
tRCKHL
tRCKHL
WCLK
tADSU
WD[7:0]
WRAD[5:0]
tADH
Valid
tWENSU
tWENH
tBENSU
tBENH
WEN
Valid
BLKEN
Note: Identical timing for falling edge clock.
Figure 1-29 • 42MX SRAM Write Operation
R ev i si o n 1 1
1- 33
40MX and 42MX FPGA Families
tRCKHL
tCKHL
RCLK
tRENSU
tRENH
tADSU
tADH
REN
Valid
RDAD[5:0]
tRCO
tDOH
Old Data
RD[7:0]
New Data
Note: Identical timing for falling edge clock.
Figure 1-30 • 42MX SRAM Synchronous Read Operation
tRDADV
RDAD[5:0]
ADDR1
ADDR2
tRPD
tDOH
Data 1
RD[7:0]
Data 2
Figure 1-31 • 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled)
WEN
WD[7:0]
WRAD[5:0]
tWENSU
tWENH
Valid
BLKEN
tADSU
WCLK
tADH
tRPD
tDOH
RD[7:0]
Old Data
New Data
Figure 1-32 • 42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled)
1- 34
R ev i sio n 1 1
40MX and 42MX FPGA Families
Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends on the resistive and capacitive loading of the routing
tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as
the length of routing tracks, the number of interconnect elements, or the number of inputs increases.
From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout
(number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing
tracks.
The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the
delay of the interconnect elements and by decreasing the number of interconnect elements per path.
Microsemi’s patented antifuse offers a very low resistive/capacitive interconnect. The antifuses,
fabricated in 0.45 µm lithography, offer nominal levels of 100Ω resistance and 7.0 fF capacitance per
antifuse.
MX fanout distribution is also tight due to the low number of antifuses required for each interconnect
path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with
90 percent of interconnects using only two antifuses.
Timing Characteristics
Device timing characteristics fall into three categories: family-dependent, device-dependent, and designdependent. The input and output buffer characteristics are common to all MX devices. Internal routing
delays are device-dependent; actual delays are not determined until after place-and-route of the user's
design is complete. Delay values may then be determined by using the Designer software utility or by
performing simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance
evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are
determined by net property assignment in Microsemi's Designer software prior to placement and routing.
Up to 6% of the nets in a design may be designated as critical.
Long Tracks
Some nets in the design use long tracks, which are special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and sometimes four antifuse connections, which
increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks.
Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks add
approximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout (FO=8) routing
delays in the data sheet specifications section, shown in Table 1-28 on page 1-40.
Timing Derating
MX devices are manufactured with a CMOS process. Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating
voltage, minimum operating temperature and best-case processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating temperature and worst-case processing.
R ev i si o n 1 1
1- 35
40MX and 42MX FPGA Families
Temperature and Voltage Derating Factors
Table 1-22 • 42MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCCA = 5.0 V)
42MX
Voltage
Temperature
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
4.50
0.93
0.95
1.05
1.09
1.25
1.29
1.41
4.75
0.88
0.90
1.00
1.03
1.18
1.22
1.34
5.00
0.85
0.87
0.96
1.00
1.15
1.18
1.29
5.25
0.84
0.86
0.95
0.97
1.12
1.14
1.28
5.50
0.83
0.85
0.94
0.96
1.10
1.13
1.26
1.50
1.40
Factor
1.30
–55°C
1.20
–40°C
1.10
Derating
0°C
1.00
25°C
0.90
70°C
0.80
85°C
0.70
125°C
0.60
4.50
4.75
5.00
Voltage
5.25
5.50
(V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-33 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 5.0 V)
Table 1-23 • 40MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCC = 5.0 V)
40MX
Voltage
1- 36
Temperature
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
4.50
0.89
0.93
1.02
1.09
1.25
1.31
1.45
4.75
0.84
0.88
0.97
1.03
1.18
1.24
1.37
5.00
0.82
0.85
0.94
1.00
1.15
1.20
1.33
5.25
0.80
0.82
0.91
0.97
1.12
1.16
1.29
5.50
0.79
0.82
0.90
0.96
1.10
1.15
1.28
R ev i sio n 1 1
40MX and 42MX FPGA Families
1.50
1.40
Factor
1.30
–55°C
1.20
–40°C
1.10
Derating
0°C
1.00
25°C
0.90
70°C
0.80
85°C
0.70
125°C
0.60
4.50
4.75
5.00
Voltage
5.25
5.50
(V)
Note: This derating factor applies to all routing and propagation delays
Figure 1-34 • 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 5.0 V)
Table 1-24 • 42MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCCA = 3.3 V)
Temperature
42MX Voltage
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
3.00
0.97
1.00
1.10
1.15
1.32
1.36
1.45
3.30
0.84
0.87
0.96
1.00
1.15
1.18
1.26
3.60
0.81
0.84
0.92
0.96
1.10
1.13
1.21
1.60
1.50
Derating Factor
1.40
1.30
55°C
1.20
40°C
1.10
0°C
1.00
25°C
0.90
70°C
0.80
85°C
0.70
125°C
0.60
0.50
0.40
3.00
3.30
3.60
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-35 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 3.3 V)
R ev i si o n 1 1
1- 37
40MX and 42MX FPGA Families
Table 1-25 • 40MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCC = 3.3 V)
Temperature
40MX Voltage
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
3.00
1.08
1.12
1.21
1.26
1.50
1.64
2.00
3.30
0.86
0.89
0.96
1.00
1.19
1.30
1.59
3.60
0.83
0.85
0.92
0.96
1.14
1.25
1.53
2.20
2.00
55˚C
1.80
40˚C
0˚C
g
1.60
25˚C
1.40
70˚C
1.20
85˚C
1.00
125˚C
0.80
0.60
3.00
3.30
3.60
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-36 • 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 3.3 V)
1- 38
R ev i sio n 1 1
40MX and 42MX FPGA Families
PCI System Timing Specification
Table 1-26 and Table 1-27 list the critical PCI timing parameters and the corresponding timing
parameters for the MX PCI-compliant devices.
PCI Models
Microsemi provides synthesizable VHDL and Verilog-HDL models for a PCI Target interface, a PCI
Target and Target+DMA Master interface. Contact your Microsemi sales representative for more
details.
Table 1-26 • Clock Specification for 33 MHz PCI
PCI
Symbol
Parameter
tCYC
A42MX24
A42MX36
Min.
Max.
Min.
Max.
Min.
Max.
Units
CLK Cycle Time
30
–
4.0
–
4.0
–
ns
tHIGH
CLK High Time
11
–
1.9
–
1.9
–
ns
tLOW
CLK Low Time
11
–
1.9
–
1.9
–
ns
Table 1-27 • Timing Parameters for 33 MHz PCI
PCI
Symbol Parameter
tVAL
Min.
CLK to Signal Valid—Bused Signals
tVAL(PTP) CLK to Signal Valid—Point-to-Point
tON
Float to Active
2
2
2
2
A42MX24
A42MX36
Max. Min. Max. Min. Max. Units
11
2.0
9.0
2.0
9.0
ns
12
2.0
9.0
2.0
9.0
ns
–
2.0
4.0
2.0
4.0
ns
–
8.31
ns
tOFF
Active to Float
–
28
–
8.31
tSU
Input Set-Up Time to CLK—Bused Signals
7
–
1.5
–
1.5
–
ns
–
1.5
–
1.5
–
ns
–
0
–
0
–
ns
tSU(PTP)
Input Set-Up Time to CLK—Point-to-Point
tH
Input Hold to CLK
10,
122
0
Notes:
1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional
10 ns.
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times
than do bussed signals. GNT# has a setup of 10; REW# has a setup of 12.
R ev i si o n 1 1
1- 39
40MX and 42MX FPGA Families
Timing Characteristics
Table 1-28 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
Parameter / Description
Min. Max.
–2 Speed
Min.
–1 Speed
Std Speed
Max.
Min. Max. Min.
Max.
–F Speed
Min.
Max. Units
Logic Module Propagation Delays
tPD1
Single Module
1.2
1.4
1.6
1.9
2.7
ns
tPD2
Dual-Module Macros
2.7
3.1
3.5
4.1
5.7
ns
tCO
Sequential Clock-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.4
1.6
1.9
2.7
ns
Logic Module Predicted Routing Delays1
tRD1
FO = 1 Routing Delay
1.3
1.5
1.7
2.0
2.8
ns
tRD2
FO = 2 Routing Delay
1.8
2.1
2.4
2.8
3.9
ns
tRD3
FO = 3 Routing Delay
2.3
2.7
3.0
3.6
5.0
ns
tRD4
FO = 4 Routing Delay
2.9
3.3
3.7
4.4
6.1
ns
tRD8
FO = 8 Routing Delay
4.9
5.7
6.5
7.6
10.6
ns
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch)
Data Input Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHD3
Flip-Flop (Latch)
Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch)
Enable Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA Flip-Flop (Latch)
Clock Active Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tA
Flip-Flop Clock Input Period
4.8
5.6
6.3
7.5
10.4
ns
fMAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
181
168
154
134
80
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
0.7
0.8
0.9
1.1
1.5
ns
tINYL
Pad-to-Y LOW
0.6
0.7
0.8
1.0
1.3
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35pF loading.
1- 40
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-28 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
Parameter / Description
Min. Max.
–2 Speed
Min.
–1 Speed
Std Speed
Max.
Min. Max. Min.
Max.
–F Speed
Min.
Max. Units
1
Input Module Predicted Routing Delays
tIRD1
FO = 1 Routing Delay
2.1
2.4
2.2
3.2
4.5
ns
tIRD2
FO = 2 Routing Delay
2.6
3.0
3.4
4.0
5.6
ns
tIRD3
FO = 3 Routing Delay
3.1
3.6
4.1
4.8
6.7
ns
tIRD4
FO = 4 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD8
FO = 8 Routing Delay
5.7
6.6
7.5
8.8
12.4
ns
Global Clock Network
tCKH
Input Low to HIGH FO = 16
FO = 128
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
tCKL
Input High to LOW FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
ns
tPWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
ns
tPWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
tP
Minimum Period
FO = 16
FO = 128
fMAX
Maximum
Frequency
FO = 16
FO = 128
0.4
0.5
4.7
4.8
0.5
0.6
5.4
5.6
188
181
0.5
0.7
6.1
6.3
175
168
0.6
0.8
7.2
7.5
160
154
0.8
1.2
10.0
10.4
139
134
ns
ns
83
80
MHz
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35pF loading.
R ev i si o n 1 1
1- 41
40MX and 42MX FPGA Families
Table 1-28 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
Parameter / Description
TTL Output Module Timing
Min. Max.
–2 Speed
Min.
–1 Speed
Std Speed
Max.
Min. Max. Min.
Max.
–F Speed
Min.
Max. Units
4
tDLH
Data-to-Pad HIGH
3.3
3.8
4.3
5.1
7.2
ns
tDHL
Data-to-Pad LOW
4.0
4.6
5.2
6.1
8.6
ns
tENZH
Enable Pad Z to HIGH
3.7
4.3
4.9
5.8
8.0
ns
tENZL
Enable Pad Z to LOW
4.7
5.4
6.1
7.2
10.1
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.1
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.02
0.02
0.03
0.03
0.04
ns/pF
dTHL
Delta HIGH to LOW
0.03
0.03
0.03
0.04
0.06
ns/pF
CMOS Output Module
Timing4
tDLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.05
8.5
ns
tDHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3
ns
tENZH
Enable Pad Z to HIGH
3.4
3.9
4.4
5.2
7.3
ns
tENZL
Enable Pad Z to LOW
4.9
5.6
6.4
7.5
10.5
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.0
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.03
0.04
0.04
0.05
0.07
ns/pF
dTHL
Delta HIGH to LOW
0.02
0.02
0.03
0.03
0.04
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35pF loading.
1- 42
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-29 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
Single Module
1.7
2.0
2.3
2.7
3.7
ns
tPD2
Dual-Module Macros
3.7
4.3
4.9
5.7
8.0
ns
tCO
Sequential Clock-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tGO
Latch G-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.7
2.0
2.3
2.7
3.7
ns
Logic Module Predicted Routing
Delays1
tRD1
FO = 1 Routing Delay
2.0
2.2
2.5
3.0
4.2
ns
tRD2
FO = 2 Routing Delay
2.7
3.1
3.5
4.1
5.7
ns
tRD3
FO = 3 Routing Delay
3.4
3.9
4.4
5.2
7.3
ns
tRD4
FO = 4 Routing Delay
4.2
4.8
5.4
6.3
8.9
ns
tRD8
FO = 8 Routing Delay
7.1
8.2
9.2
10.9
15.2
ns
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch)
Data Input Set-Up
4.3
4.9
5.6
6.6
9.2
ns
tHD3
Flip-Flop (Latch)
Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
4.3
4.9
5.6
6.6
9.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
4.6
5.3
6.0
7.0
9.8
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.6
5.3
6.0
7.0
9.8
ns
tA
Flip-Flop Clock Input Period
6.8
7.8
8.9
10.4
14.6
ns
fMAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
109
101
92
80
48
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.0
1.1
1.3
1.5
2.1
ns
tINYL
Pad-to-Y LOW
0.9
1.0
1.1
1.3
1.9
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 43
40MX and 42MX FPGA Families
Table 1-29 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays1
tIRD1
FO = 1 Routing Delay
2.9
3.4
3.8
4.5
6.3
ns
tIRD2
FO = 2 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD3
FO = 3 Routing Delay
4.4
5.0
5.7
6.7
9.4
ns
tIRD4
FO = 4 Routing Delay
5.1
5.9
6.7
7.8
11.0
ns
tIRD8
FO = 8 Routing Delay
8.0
9.26
10.5
12.6
17.3
ns
Global Clock Network
tCKH
Input LOW to HIGH FO = 16
FO = 128
6.4
6.4
7.4
7.4
8.3
8.3
9.8
9.8
13.7
13.7
ns
tCKL
Input HIGH to LOW FO = 16
FO = 128
6.7
6.7
7.8
7.8
8.8
8.8
10.4
10.4
14.5
14.5
ns
tPWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
tPWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
tP
Minimum Period
FO = 16
FO = 128
fMAX
Maximum
Frequency
FO = 16
FO = 128
0.6
0.8
6.5
6.8
0.6
0.9
7.5
7.8
0.7
1.0
8.5
8.9
0.8
1.2
10.1
10.4
1.2
1.6
14.1
14.6
ns
ns
113
109
105
101
96
92
83
80
50
48
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
4.7
5.4
6.1
7.2
10.0
ns
tDHL
Data-to-Pad LOW
5.6
6.4
7.3
8.6
12.0
ns
tENZH
Enable Pad Z to HIGH
5.2
6.0
6.8
8.1
11.3
ns
tENZL
Enable Pad Z to LOW
6.6
7.6
8.6
10.1
14.1
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
Delta LOW to HIGH
0.03
0.03
0.04
0.04
0.06 ns/pF
dTHL
Delta HIGH to LOW
0.04
0.04
0.05
0.06
0.08 ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
1- 44
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-29 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
4
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
5.5
6.4
7.2
8.5
11.9
ns
tDHL
Data-to-Pad LOW
4.8
5.5
6.2
7.3
10.2
ns
tENZH
Enable Pad Z to HIGH
4.7
5.5
6.2
7.3
10.2
ns
tENZL
Enable Pad Z to LOW
6.8
7.9
8.9
10.5
14.7
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
Delta LOW to HIGH
0.05
0.05
0.06
0.07
0.10 ns/pF
dTHL
Delta HIGH to LOW
0.03
0.03
0.04
0.04
0.06 ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 45
40MX and 42MX FPGA Families
Table 1-30 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
Single Module
1.2
1.4
1.6
1.9
2.7
ns
tPD2
Dual-Module Macros
2.3
3.1
3.5
4.1
5.7
ns
tCO
Sequential Clock-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.4
1.6
1.9
2.7
ns
Logic Module Predicted Routing Delays1
tRD1
FO = 1 Routing Delay
1.2
1.6
1.8
2.1
3.0
ns
tRD2
FO = 2 Routing Delay
1.9
2.2
2.5
2.9
4.1
ns
tRD3
FO = 3 Routing Delay
2.4
2.8
3.2
3.7
5.2
ns
tRD4
FO = 4 Routing Delay
2.9
3.4
3.9
4.5
6.3
ns
tRD8
FO = 8 Routing Delay
5.0
5.8
6.6
7.8
10.9
ns
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch)
Data Input Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHD3
Flip-Flop (Latch)
Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch)
Enable Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHENA
Flip-Flop (Latch)
Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tA
Flip-Flop Clock Input Period
4.8
5.6
6.3
7.5
10.4
ns
fMAX
Flip-Flop (Latch)
Clock Frequency
(FO = 128)
181
167
154
134
80
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
0.7
0.8
0.9
1.1
1.5
ns
tINYL
Pad-to-Y LOW
0.6
0.7
0.8
1.0
1.3
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.
1- 46
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-30 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays1
tIRD1
FO = 1 Routing Delay
2.1
2.4
2.2
3.2
4.5
ns
tIRD2
FO = 2 Routing Delay
2.6
3.0
3.4
4.0
5.6
ns
tIRD3
FO = 3 Routing Delay
3.1
3.6
4.1
4.8
6.7
ns
tIRD4
FO = 4 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD8
FO = 8 Routing Delay
5.7
6.6
7.5
8.8
12.4
ns
Global Clock Network
tCKH
Input Low to HIGH
FO = 16
FO = 128
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
tCKL
Input High to LOW
FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
ns
tPWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
ns
tPWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
tP
Minimum Period
FO = 16
FO = 128
fMAX
Maximum
Frequency
FO = 16
FO = 128
0.4
0.5
4.7
4.8
0.5
0.6
5.4
5.6
0.5
0.7
6.1
6.3
0.6
0.8
7.2
7.5
0.8
1.2
10.0
10.4
ns
ns
188
181
175
168
160
154
139
134
83
80
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
3.3
3.8
4.3
5.1
7.2
ns
tDHL
Data-to-Pad LOW
4.0
4.6
5.2
6.1
8.6
ns
tENZH
Enable Pad Z to HIGH
3.7
4.3
4.9
5.8
8.0
ns
tENZL
Enable Pad Z to LOW
4.7
5.4
6.1
7.2
10.1
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.1
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.02
0.02
0.03
0.03
0.04
ns/pF
dTHL
Delta HIGH to LOW
0.03
0.03
0.03
0.04
0.06
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 47
40MX and 42MX FPGA Families
Table 1-30 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
Parameter / Description
CMOS Output Module Timing
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
1
tDLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.05
8.5
ns
tDHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3
ns
tENZH
Enable Pad Z to HIGH
3.4
3.9
4.4
5.2
7.3
ns
tENZL
Enable Pad Z to LOW
4.9
5.6
6.4
7.5
10.5
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.0
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.03
0.04
0.04
0.05
0.07
ns/pF
dTHL
Delta HIGH to LOW
0.02
0.02
0.03
0.03
0.04
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.
1- 48
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-31 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
Single Module
1.7
2.0
2.3
2.7
3.7
ns
tPD2
Dual-Module Macros
3.7
4.3
4.9
5.7
8.0
ns
tCO
Sequential Clock-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tGO
Latch G-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.7
2.0
2.3
2.7
3.7
ns
Logic Module Predicted Routing
Delays1
tRD1
FO = 1 Routing Delay
1.9
2.2
2.5
3.0
4.2
ns
tRD2
FO = 2 Routing Delay
2.7
3.1
3.5
4.1
5.7
ns
tRD3
FO = 3 Routing Delay
3.4
3.9
4.4
5.2
7.3
ns
tRD4
FO = 4 Routing Delay
4.1
4.8
5.4
6.3
8.9
ns
tRD8
FO = 8 Routing Delay
7.1
8.1
9.2
10.9
15.2
ns
Logic Module Sequential
Timing2
tSUD
Flip-Flop (Latch)
Data Input Set-Up
4.3
5.0
5.6
6.6
9.2
ns
tHD3
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
4.3
5.0
5.6
6.6
9.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
4.6
5.3
5.6
7.0
9.8
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.6
5.3
5.6
7.0
9.8
ns
tA
Flip-Flop Clock Input Period
6.8
7.8
8.9
10.4
14.6
ns
fMAX
Flip-Flop (Latch) Clock Frequency
(FO = 128)
109
101
92
80
48
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.0
1.1
1.3
1.5
2.1
ns
tINYL
Pad-to-Y LOW
0.9
1.0
1.1
1.3
1.9
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 49
40MX and 42MX FPGA Families
Table 1-31 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays1
tIRD1
FO = 1 Routing Delay
2.9
3.3
3.8
4.5
6.3
ns
tIRD2
FO = 2 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD3
FO = 3 Routing Delay
4.4
5.0
5.7
6.7
9.4
ns
tIRD4
FO = 4 Routing Delay
5.1
5.9
6.7
7.8
11.0
ns
tIRD8
FO = 8 Routing Delay
8.0
9.3
10.5
12.4
17.2
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 16
FO = 128
6.4
6.4
7.4
7.4
8.4
8.4
9.9
9.9
13.8
13.8
ns
tCKL
Input HIGH to LOW
FO = 16
FO = 128
6.8
6.8
7.8
7.8
8.9
8.9
10.4
10.4
14.6
14.6
ns
tPWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
tPWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
tP
Minimum Period
FO = 16
FO = 128
fMAX
Maximum Frequency FO = 16
FO = 128
0.6
0.8
6.5
6.8
0.6
0.9
7.5
7.8
0.7
1.0
8.5
8.9
0.8
1.2
10.1
10.4
1.2
1.6
14.1
14.6
ns
ns
113
109
105
101
96
92
83
80
50
48
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
4.7
5.4
6.1
7.2
10.0
ns
tDHL
Data-to-Pad LOW
5.6
6.4
7.3
8.6
12.0
ns
tENZH
Enable Pad Z to HIGH
5.2
6.0
6.9
8.1
11.3
ns
tENZL
Enable Pad Z to LOW
6.6
7.6
8.6
10.1
14.1
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
Delta LOW to HIGH
0.03
0.03
0.04
0.04
0.06
ns/pF
dTHL
Delta HIGH to LOW
0.04
0.04
0.05
0.06
0.08
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
1- 50
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-31 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
4
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
5.5
6.4
7.2
8.5
11.9
ns
tDHL
Data-to-Pad LOW
4.8
5.5
6.2
7.3
10.2
ns
tENZH
Enable Pad Z to HIGH
4.7
5.5
6.2
7.3
10.2
ns
tENZL
Enable Pad Z to LOW
6.8
7.9
8.9
10.5
14.7
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
Delta LOW to HIGH
0.05
0.05
0.06
0.07
0.10
ns/pF
dTHL
Delta HIGH to LOW
0.03
0.03
0.04
0.04
0.06
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 51
40MX and 42MX FPGA Families
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed
Parameter / Description
Logic Module Propagation
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Delays1
tPD1
Single Module
1.2
1.3
1.5
1.8
2.5
ns
tCO
Sequential Clock-to-Q
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.8
2.6
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.6
1.8
2.1
2.9
ns
Logic Module Predicted Routing Delays2
tRD1
FO = 1 Routing Delay
0.7
0.8
0.9
1.0
1.4
ns
tRD2
FO = 2 Routing Delay
0.9
1.0
1.2
1.4
1.9
ns
tRD3
FO = 3 Routing Delay
1.2
1.3
1.5
1.7
2.4
ns
tRD4
FO = 4 Routing Delay
1.4
1.5
1.7
2.0
2.9
ns
tRD8
FO = 8 Routing Delay
2.3
2.6
2.9
3.4
4.8
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch)
Data Input Set-Up
0.3
0.4
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.4
0.5
0.5
0.6
0.8
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.4
3.8
4.3
5.0
7.0
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.5
4.9
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
3.5
3.8
4.3
5.1
7.1
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.3
0.3
0.4
0.4
0.6
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.3
0.3
0.4
0.4
0.6
ns
fMAX
Flip-Flop (Latch) Clock Frequency
268
244
224
195
117
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 52
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.0
1.2
1.3
1.6
2.2
ns
tINYL
Pad-to-Y LOW
0.8
0.9
1.0
1.2
1.7
ns
tINGH
G to Y HIGH
1.3
1.4
1.6
1.9
2.7
ns
tINGL
G to Y LOW
1.3
1.4
1.6
1.9
2.7
ns
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
2.0
2.2
2.5
3.0
4.2
ns
tIRD2
FO = 2 Routing Delay
2.3
2.5
2.9
3.4
4.7
ns
tIRD3
FO = 3 Routing Delay
2.5
2.8
3.2
3.7
5.2
ns
tIRD4
FO = 4 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
tIRD8
FO = 8 Routing Delay
3.7
4.1
4.7
5.5
7.7
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 256
2.4
2.7
2.7
3.0
3.0
3.4
3.6
4.0
5.0
5.5
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 256
3.5
3.9
3.9
4.3
4.4
4.9
5.2
5.7
7.3
8.0
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO = 32
FO = 256
1.2
1.3
1.4
1.5
1.5
1.7
1.8
2.0
2.5
2.7
ns
ns
tPWL
Minimum Pulse
Width LOW
FO = 32
FO = 256
1.2
1.3
1.4
1.5
1.5
1.7
1.8
2.0
2.5
2.7
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
tSUEXT
Input Latch
External Set-Up
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch
External Hold
FO = 32
FO = 256
2.3
2.2
2.6
2.4
3.0
3.3
3.5
3.9
4.9
5.5
ns
ns
tP
Minimum Period
FO = 32
FO = 256
3.4
3.7
3.7
4.1
4.0
4.5
4.7
5.2
7.8
8.6
ns
ns
fMAX
Maximum Frequency FO = 32
FO = 256
0.3
0.3
0.3
0.3
296
268
269
244
0.4
0.4
247
224
0.5
0.5
215
195
0.6
0.6
129
117
ns
ns
MHz
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 53
40MX and 42MX FPGA Families
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
TTL Output Module Timing
tDLH
Data-to-Pad HIGH
2.5
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tENZH
Enable Pad Z to HIGH
2.6
2.9
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.2
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
4.9
5.4
6.2
7.3
10.2
ns
tENLZ
Enable Pad LOW to Z
5.3
5.9
6.7
7.9
11.1
ns
tGLH
G-to-Pad HIGH
2.6
2.9
3.3
3.8
5.3
ns
tGHL
G-to-Pad LOW
2.6
2.9
3.3
3.8
5.3
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
5.2
5.8
6.6
7.7
10.8
ns
tACO
Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
7.4
8.2
9.3
10.9
15.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06 ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07 ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 54
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
2.4
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tENZH
Enable Pad Z to HIGH
2.7
2.9
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.2
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
4.9
5.4
6.2
7.3
10.2
ns
tENLZ
Enable Pad LOW to Z
5.3
5.9
6.7
7.9
11.1
ns
tGLH
G-to-Pad HIGH
4.2
4.6
5.2
6.1
8.6
ns
tGHL
G-to-Pad LOW
4.2
4.6
5.2
6.1
8.6
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
5.2
5.8
6.6
7.7
10.8
ns
tACO
Array Clock-to-Out (
Pad-to-Pad), 64 Clock Loading
7.4
8.2
9.3
10.9
15.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06 ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07 ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 55
40MX and 42MX FPGA Families
Table 1-33 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed
Parameter / Description
Logic Module Propagation
–2 Speed
–1 Speed Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Delays1
tPD1
Single Module
1.6
1.8
2.1
2.5
3.5
ns
tCO
Sequential Clock-to-Q
1.8
2.0
2.3
2.7
3.8
ns
tGO
Latch G-to-Q
1.7
1.9
2.1
2.5
3.5
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.0
2.2
2.5
2.9
4.1
ns
2
Logic Module Predicted Routing Delays
tRD1
FO = 1 Routing Delay
1.0
1.1
1.2
1.4
2.0
ns
tRD2
FO = 2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD3
FO = 3 Routing Delay
1.6
1.8
2.0
2.4
3.3
ns
tRD4
FO = 4 Routing Delay
1.9
2.1
2.4
2.9
4.0
ns
tRD8
FO = 8 Routing Delay
3.2
3.6
4.1
4.8
6.7
ns
Logic Module Sequential Timing
3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up 0.5
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.6
0.7
0.8
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
4.7
5.3
6.0
7.0
9.8
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
6.2
6.9
7.8
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
5.0
5.6
6.2
7.1
9.9
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.3
0.3
0.3
0.4
0.6
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.3
0.3
0.3
0.4
0.6
ns
fMAX
Flip-Flop (Latch) Clock Frequency
161
146
135
117
70
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 56
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-33 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.5
1.6
1.8
2.17
3.0
ns
tINYL
Pad-to-Y LOW
1.2
1.3
1.4
1.7
2.4
ns
tINGH
G to Y HIGH
1.8
2.0
2.3
2.7
3.7
ns
tINGL
G to Y LOW
1.8
2.0
2.3
2.7
3.7
ns
2
Input Module Predicted Routing Delays
tIRD1
FO = 1 Routing Delay
2.8
3.2
3.6
4.2
5.9
ns
tIRD2
FO = 2 Routing Delay
3.2
3.5
4.0
4.7
6.6
ns
tIRD3
FO = 3 Routing Delay
3.5
3.9
4.4
5.2
7.3
ns
tIRD4
FO = 4 Routing Delay
3.9
4.3
4.9
5.7
8.0
ns
tIRD8
FO = 8 Routing Delay
5.2
5.8
6.6
7.7
10.8
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 256
4.1
4.5
4.5
5.0
5.1
5.6
6.0
6.7
8.4
9.3
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 256
5.0
5.4
5.5
6.0
6.2
6.8
7.3
8.0
10.2
11.2
ns
ns
tPWH
Minimum Pulse Width FO = 32
HIGH
FO = 256
1.7
1.9
1.9
2.1
2.1
2.3
2.5
2.7
3.5
3.8
ns
ns
tPWL
Minimum Pulse Width FO = 32
LOW
FO = 256
1.7
1.9
1.9
2.1
2.1
2.3
2.5
2.7
3.5
3.8
ns
ns
tCKSW
Maximum Skew
tSUEXT
Input Latch External FO = 32
Set-Up
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO = 32
Hold
FO = 256
3.3
3.7
3.7
4.1
4.2
4.6
4.9
5.5
6.9
7.6
ns
ns
tP
Minimum Period
FO = 32
FO = 256
5.6
6.1
6.2
6.8
6.7
7.4
7.8
8.5
12.9
14.2
ns
ns
fMAX
Maximum Frequency
FO = 32
FO = 256
FO = 32
FO = 256
0.4
0.4
177
161
0.5
0.5
161
146
0.5
0.5
148
135
0.6
0.6
129
117
0.9
0.9
77
70
ns
ns
MHz
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 57
40MX and 42MX FPGA Families
Table 1-33 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
TTL Output Module Timing
tDLH
Data-to-Pad HIGH
3.4
3.8
4.3
5.1
7.1
ns
tDHL
Data-to-Pad LOW
4.0
4.5
5.1
6.1
8.3
ns
tENZH
Enable Pad Z to HIGH
3.7
4.1
4.6
5.5
7.6
ns
tENZL
Enable Pad Z to LOW
4.1
4.5
5.1
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
6.9
7.6
8.6
10.2
14.2
ns
tENLZ
Enable Pad LOW to Z
7.5
8.3
9.4
11.1
15.5
ns
tGLH
G-to-Pad HIGH
5.8
6.5
7.3
8.6
12.0
ns
tGHL
G-to-Pad LOW
5.8
6.5
7.3
8.6
12.0
ns
tLSU
I/O Latch Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.7
9.7
10.9
12.9
18.0
ns
tACO
Array Clock-to-Out
(Pad-to-Pad),64 Clock Loading
12.2
13.5
15.4
18.1
25.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.00
0.00
0.00
0.10
0.01 ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.09
0.10
0.10
0.10
0.10 ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 58
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-33 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
3.4
3.8
5.5
6.4
9.0
ns
tDHL
Data-to-Pad LOW
4.1
4.5
4.2
5.0
7.0
ns
tENZH
Enable Pad Z to HIGH
3.7
4.1
4.6
5.5
7.6
ns
tENZL
Enable Pad Z to LOW
4.1
4.5
5.1
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
6.9
7.6
8.6
10.2
14.2
ns
tENLZ
Enable Pad LOW to Z
7.5
8.3
9.4
11.1
15.5
ns
tGLH
G-to-Pad HIGH
5.8
6.5
7.3
8.6
12.0
ns
tGHL
G-to-Pad LOW
5.8
6.5
7.3
8.6
12.0
ns
tLSU
I/O Latch Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.7
9.7
10.9
12.9
18.0
ns
tACO
Array Clock-to-Out
(Pad-to-Pad),
64 Clock Loading
12.2
13.5
15.4
18.1
25.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08 ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10 ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 59
40MX and 42MX FPGA Families
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation
Delays1
tPD1
Single Module
1.4
1.5
1.7
2.0
2.8
ns
tCO
Sequential Clock-to-Q
1.4
1.6
1.8
2.1
3.0
ns
tGO
Latch G-to-Q
1.4
1.5
1.7
2.0
2.8
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.6
1.7
2.0
2.3
3.3
ns
2
Logic Module Predicted Routing Delays
tRD1
FO = 1 Routing Delay
0.8
0.9
1.0
1.2
1.6
ns
tRD2
FO = 2 Routing Delay
1.0
1.2
1.3
1.5
2.1
ns
tRD3
FO = 3 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD4
FO = 4 Routing Delay
1.6
1.7
2.0
2.3
3.2
ns
tRD8
FO = 8 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
Logic Module Sequential
Timing3,4
tSUD
Flip-Flop (Latch)
Data Input Set-Up
0.3
0.4
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
3.4
3.8
4.3
5.0
7.1
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.5
5.0
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
6.8
7.6
8.6
10.1
14.1
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
fMAX
Flip-Flop (Latch) Clock Frequency
215
195
179
156
94
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 60
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.1
1.2
1.3
1.6
2.2
ns
tINYL
Pad-to-Y LOW
0.8
0.9
1.0
1.2
1.7
ns
tINGH
G to Y HIGH
1.4
1.6
1.8
2.1
2.9
ns
tINGL
G to Y LOW
1.4
1.6
1.8
2.1
2.9
ns
2
Input Module Predicted Routing Delays
tIRD1
FO = 1 Routing Delay
1.8
2.0
2.3
2.7
4.0
ns
tIRD2
FO = 2 Routing Delay
2.1
2.3
2.6
3.1
4.3
ns
tIRD3
FO = 3 Routing Delay
2.3
2.6
3.0
3.5
4.9
ns
tIRD4
FO = 4 Routing Delay
2.6
3.0
3.3
3.9
5.4
ns
tIRD8
FO = 8 Routing Delay
3.6
4.0
4.6
5.4
7.5
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
6.0
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
3.8
4.5
4.2
5.0
4.8
5.6
5.6
6.6
7.8
9.2
ns
ns
tPWH
Minimum Pulse Width FO = 32
HIGH
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
tPWL
Minimum Pulse Width FO = 32
LOW
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
tCKSW
Maximum Skew
tSUEXT
Input Latch External FO = 32
Set-Up
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO = 32
Hold
FO = 384
2.8
3.2
3.1
3.5
5.5
4.0
4.1
4.7
5.7
6.6
ns
ns
tP
Minimum Period
4.2
4.6
4.67
5.1
5.1
5.6
5.8
6.4
9.7
10.7
ns
ns
fMAX
Maximum Frequency FO = 32
FO = 384
FO = 32
FO = 384
FO = 32
FO = 384
0.3
0.3
237
215
0.4
0.4
215
195
0.4
0.4
198
179
0.5
0.5
172
156
0.7
0.7
103
94
ns
ns
MHz
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 61
40MX and 42MX FPGA Families
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
TTL Output Module Timing
tDLH
Data-to-Pad HIGH
2.5
2.8
3.2
3.7
5.2
ns
tDHL
Data-to-Pad LOW
3.0
3.3
3.7
4.4
6.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.4
4.0
5.6
ns
tENZL
Enable Pad Z to LOW
3.0
3.3
3.8
4.4
6.2
ns
tENHZ
Enable Pad HIGH to Z
5.4
6.0
6.8
8.0
11.2
ns
tENLZ
Enable Pad LOW to Z
5.0
5.6
6.3
7.4
10.4
ns
tGLH
G-to-Pad HIGH
2.9
3.2
3.6
4.3
6.0
ns
tGHL
G-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
5.7
6.3
7.1
8.4
11.9
ns
tACO
Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
dTLH
Capacitive Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07 ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 62
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
3.2
3.6
4.0
4.7
6.6
ns
tDHL
Data-to-Pad LOW
2.5
2.7
3.1
3.6
5.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.4
4.0
5.6
ns
tENZL
Enable Pad Z to LOW
3.0
3.3
3.8
4.4
6.2
ns
tENHZ
Enable Pad HIGH to Z
5.4
6.0
6.8
8.0
11.2
ns
tENLZ
Enable Pad LOW to Z
5.0
5.6
6.3
7.4
10.4
ns
tGLH
G-to-Pad HIGH
5.1
5.6
6.4
7.5
10.5
ns
tGHL
G-to-Pad LOW
5.1
5.6
6.4
7.5
10.5
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
5.7
6.3
7.1
8.4
11.9
ns
tACO
Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
dTLH
Capacitive Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06 ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 63
40MX and 42MX FPGA Families
Table 1-35 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation
Delays1
tPD1
Single Module
1.9
2.1
2.4
2.8
4.0
ns
tCO
Sequential Clock-to-Q
2.0
2.2
2.5
3.0
4.2
ns
tGO
Latch G-to-Q
1.9
2.1
2.4
2.8
4.0
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.2
2.4
2.8
3.3
4.6
ns
2
Logic Module Predicted Routing Delays
tRD1
FO = 1 Routing Delay
1.1
1.2
1.4
1.6
2.3
ns
tRD2
FO = 2 Routing Delay
1.5
1.6
1.8
2.1
3.0
ns
tRD3
FO = 3 Routing Delay
1.8
2.0
2.3
2.7
3.8
ns
tRD4
FO = 4 Routing Delay
2.2
2.4
2.7
3.2
4.5
ns
tRD8
FO = 8 Routing Delay
3.6
4.0
4.5
5.3
7.5
ns
Logic Module Sequential
Timing3, 4
tSUD
Flip-Flop (Latch)
Data Input Set-Up
0.5
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
4.8
5.3
6.0
7.1
9.9
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
6.2
6.9
7.9
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
9.5
10.6
12.0
14.1
19.8
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.7
0.8
0.9
1.01
1.4
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.7
0.8
0.89
1.01
1.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
129
117
108
94
56
MHz
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 64
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-35 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.5
1.6
1.9
2.2
3.1
ns
tINYL
Pad-to-Y LOW
1.1
1.3
1.4
1.7
2.4
ns
tINGH
G to Y HIGH
2.0
2.2
2.5
2.9
4.1
ns
tINGL
G to Y LOW
2.0
2.2
2.5
2.9
4.1
ns
2
Input Module Predicted Routing Delays
tIRD1
FO = 1 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
tIRD2
FO = 2 Routing Delay
2.9
3.2
3.7
4.3
6.1
ns
tIRD3
FO = 3 Routing Delay
3.3
3.6
4.1
4.9
6.8
ns
tIRD4
FO = 4 Routing Delay
3.6
4.0
4.6
5.4
7.6
ns
tIRD8
FO = 8 Routing Delay
5.1
5.6
6.4
7.5
10.5
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.0
9.9
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO = 32
FO = 384
5.7
6.6
6.3
7.4
7.1
8.3
8.4
9.8
11.8
13.7
ns
ns
tPWL
Minimum Pulse
Width LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
tSUEXT
Input Latch External FO = 32
Set-Up
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO = 32
Hold
FO = 384
3.9
4.5
4.3
4.9
4.9
5.6
5.7
6.6
8.0
9.2
ns
ns
tP
Minimum Period
7.0
7.7
7.8
8.6
8.4
9.3
9.7
10.7
16.2
17.8
ns
ns
fMAX
Maximum Frequency FO = 32
FO = 384
FO = 32
FO = 384
0.5
2.2
142
129
0.5
2.4
129
117
0.6
2.7
119
108
0.7
3.2
103
94
1.0
4.5
62
56
ns
ns
MHz
MHz
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 65
40MX and 42MX FPGA Families
Table 1-35 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
3.5
3.9
4.4
5.2
7.3
ns
tDHL
Data-to-Pad LOW
4.1
4.6
5.2
6.1
8.6
ns
tENZH
Enable Pad Z to HIGH
3.8
4.2
4.8
5.6
7.8
ns
tENZL
Enable Pad Z to LOW
4.2
4.6
5.3
6.2
8.7
ns
tENHZ
Enable Pad HIGH to Z
7.6
8.4
9.5
11.2
15.7
ns
tENLZ
Enable Pad LOW to Z
7.0
7.8
8.8
10.4
14.5
ns
tGLH
G-to-Pad HIGH
4.8
5.3
6.0
7.2
10.0
ns
tGHL
G-to-Pad LOW
4.8
5.3
6.0
7.2
10.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
tACO
Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10 ns/pF
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
4.5
5.0
5.6
6.6
9.3
ns
tDHL
Data-to-Pad LOW
3.4
3.8
4.3
5.1
7.1
ns
tENZH
Enable Pad Z to HIGH
3.8
4.2
4.8
5.6
7.8
ns
tENZL
Enable Pad Z to LOW
4.2
4.6
5.3
6.2
8.7
ns
tENHZ
Enable Pad HIGH to Z
7.6
8.4
9.5
11.2
15.7
ns
tENLZ
Enable Pad LOW to Z
7.0
7.8
8.8
10.4
14.5
ns
tGLH
G-to-Pad HIGH
7.1
7.9
8.9
10.5
14.7
ns
tGHL
G-to-Pad LOW
7.1
7.9
8.9
10.5
14.7
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
tACO
Array Clock-to-Out
(Pad-to-Pad),64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10 ns/pF
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 66
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Combinatorial
Functions1
tPD
Internal Array Module Delay
1.2
1.3
1.5
1.8
2.5
ns
tPDD
Internal Decode Module Delay
1.4
1.6
1.8
2.1
3.0
ns
Logic Module Predicted Routing
Delays2
tRD1
FO = 1 Routing Delay
0.8
0.9
1.0
1.2
1.7
ns
tRD2
FO = 2 Routing Delay
1.0
1.2
1.3
1.5
2.1
ns
tRD3
FO = 3 Routing Delay
1.3
1.4
1.6
1.9
2.6
ns
tRD4
FO = 4 Routing Delay
1.5
1.7
1.9
2.2
3.1
ns
tRD5
FO = 8 Routing Delay
2.4
2.7
3.0
3.6
5.0
ns
Logic Module Sequential
Timing3, 4
tCO
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch Gate-to-Output
1.2
1.3
1.5
1.8
2.5
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.3
0.4
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.4
0.5
0.5
0.6
0.8
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
3.3
3.7
4.2
4.9
6.9
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.4
4.8
5.3
6.5
9.0
1.4
1.6
1.8
2.1
2.9
ns
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.0
1.1
1.3
1.5
2.1
ns
tINGO
Input Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.6
ns
tINH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tILA
Latch Active Pulse Width
4.7
5.2
5.9
6.9
9.7
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 67
40MX and 42MX FPGA Families
Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
2
Input Module Predicted Routing Delays
tIRD1
FO = 1 Routing Delay
1.8
2.0
2.3
2.7
3.8
ns
tIRD2
FO = 2 Routing Delay
2.1
2.3
2.6
3.1
4.3
ns
tIRD3
FO = 3 Routing Delay
2.3
2.5
2.9
3.4
4.8
ns
tIRD4
FO = 4 Routing Delay
2.5
2.8
3.2
3.7
5.2
ns
tIRD8
FO = 8 Routing Delay
3.4
3.8
4.3
5.1
7.1
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 486
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
5.9
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 486
3.7
4.3
4.1
4.7
4.6
5.4
5.4
6.3
7.6
8.8
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO = 32
FO = 486
2.2
2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
tPWL
Minimum Pulse
Width LOW
FO = 32
FO = 486
2.2
2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 486
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 486
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External
Hold
FO = 32
FO = 486
2.8
3.3
3.1
3.7
3.5
4.2
4.1
4.9
5.7
6.9
ns
ns
tP
Minimum Period
(1/fMAX)
FO = 32
FO = 486
4.7
5.1
5.2
5.7
5.7
6.2
6.5
7.1
10.9
11.9
ns
ns
0.5
0.5
0.6
0.6
0.7
0.7
0.8
0.8
1.1
1.1
ns
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 68
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
TTL Output Module Timing
tDLH
Data-to-Pad HIGH
2.4
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.8
3.2
3.6
4.2
5.9
ns
tENZH
Enable Pad Z to HIGH
2.5
2.8
3.2
3.8
5.3
ns
tENZL
Enable Pad Z to LOW
2.8
3.1
3.5
4.2
5.9
ns
tENHZ
Enable Pad HIGH to Z
5.2
5.7
6.5
7.6
10.7
ns
tENLZ
Enable Pad LOW to Z
4.8
5.3
6.0
7.1
9.9
ns
tGLH
G-to-Pad HIGH
2.9
3.2
3.6
4.3
6.0
ns
tGHL
G-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tLSU
I/O Latch Output Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.6
6.1
6.9
8.1
11.4
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.6
11.8
13.4
15.7
22.0
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.04
0.04
0.05
0.07 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.03
0.03
0.03
0.04
0.06 ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 69
40MX and 42MX FPGA Families
Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
3.1
3.5
3.9
4.6
6.4
ns
tDHL
Data-to-Pad LOW
2.4
2.6
3.0
3.5
4.9
ns
tENZH
Enable Pad Z to HIGH
2.5
2.8
3.2
3.8
5.3
ns
tENZL
Enable Pad Z to LOW
2.8
3.1
3.5
4.2
5.8
ns
tENHZ
Enable Pad HIGH to Z
5.2
5.7
6.5
7.6
10.7
ns
tENLZ
Enable Pad LOW to Z
4.8
5.3
6.0
7.1
9.9
ns
tGLH
G-to-Pad HIGH
4.9
5.4
6.2
7.2
10.1
ns
tGHL
G-to-Pad LOW
4.9
5.4
6.2
7.2
10.1
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.5
6.1
6.9
8.1
11.3
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.6
11.8
13.4
15.7
22.0
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.04
0.04
0.05
0.07 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.03
0.03
0.03
0.04
0.06 ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 70
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-37 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Combinatorial
Functions1
tPD
Internal Array Module Delay
2.0
1.8
2.1
2.5
3.4
ns
tPDD
Internal Decode Module Delay
1.1
2.2
2.5
3.0
4.2
ns
Logic Module Predicted Routing
Delays2
tRD1
FO = 1 Routing Delay
1.7
1.3
1.4
1.7
2.3
ns
tRD2
FO = 2 Routing Delay
2.0
1.6
1.8
2.1
3.0
ns
tRD3
FO = 3 Routing Delay
1.1
2.0
2.2
2.6
3.7
ns
tRD4
FO = 4 Routing Delay
1.5
2.3
2.6
3.1
4.3
ns
tRD5
FO = 8 Routing Delay
1.8
3.7
4.2
5.0
7.0
ns
Logic Module Sequential
Timing3, 4
tCO
Flip-Flop Clock-to-Output
2.1
2.0
2.3
2.7
3.7
ns
tGO
Latch Gate-to-Output
3.4
1.9
2.1
2.5
3.4
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.6
0.7
0.8
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
4.6
5.2
5.8
6.9
9.6
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
6.1
6.8
7.7
9.0
12.6
2.0
2.2
2.5
2.9
4.1
ns
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.4
1.6
1.8
2.2
3.0
ns
tINGO
Input Latch Gate-to-Output
1.8
1.9
2.2
2.6
3.6
ns
tINH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tILA
Latch Active Pulse Width
6.5
7.3
8.2
9.7
13.5
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 71
40MX and 42MX FPGA Families
Table 1-37 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
2
Input Module Predicted Routing Delays
tIRD1
FO = 1 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
tIRD2
FO = 2 Routing Delay
2.9
3.2
3.6
4.3
6.0
ns
tIRD3
FO = 3 Routing Delay
3.2
3.6
4.0
4.8
6.6
ns
tIRD4
FO = 4 Routing Delay
3.5
3.9
4.4
5.2
7.3
ns
tIRD8
FO = 8 Routing Delay
4.8
5.3
6.1
7.1
10.0
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 486
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.1
10.0
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 486
5.1
6.0
5.7
6.6
6.4
7.5
7.6
8.8
10.6
12.4
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO = 32
FO = 486
3.0
3.3
3.3
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
ns
tPWL
Minimum Pulse
Width LOW
FO = 32
FO = 486
3.0
3.3
3.4
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 486
tSUEXT
Input Latch External FO = 32
Set-Up
FO = 486
0.8
0.8
0.0
0.0
0.8
0.8
0.0
0.0
1.0
1.0
0.0
0.0
1.1
1.1
0.0
0.0
1.6
1.6
0.0
0.0
ns
ns
ns
ns
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
3.4
3.8
4.3
5.0
7.1
ns
tDHL
Data-to-Pad LOW
4.0
4.4
5.0
5.9
8.3
ns
tENZH
Enable Pad Z to HIGH
3.6
4.0
4.5
5.3
7.4
ns
tENZL
Enable Pad Z to LOW
3.9
4.4
5.0
5.8
8.2
ns
tENHZ
Enable Pad HIGH to Z
7.2
8.0
9.1
10.7
14.9
ns
tENLZ
Enable Pad LOW to Z
6.7
7.5
8.5
9.9
13.9
ns
tGLH
G-to-Pad HIGH
4.8
5.3
6.0
7.2
10.0
ns
tGHL
G-to-Pad LOW
4.8
5.3
6.0
7.2
10.0
ns
tLSU
I/O Latch Output Set-Up
0.7
0.7
0.8
1.0
1.4
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 72
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-37 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
TTL Output Module Timing (continued)
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7
8.5
9.6
11.3
15.9
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8
16.5
18.7
22.0
30.8
ns
dTLH
Capacitive Loading, LOW to HIGH
0.05
0.05
0.06
0.07
0.10 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.04
0.04
0.05
0.06
0.08 ns/pF
5
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
4.8
5.3
5.5
6.4
9.0
ns
tDHL
Data-to-Pad LOW
3.5
3.9
4.1
4.9
6.8
ns
tENZH
Enable Pad Z to HIGH
3.6
4.0
4.5
5.3
7.4
ns
tENZL
Enable Pad Z to LOW
3.4
4.0
5.0
5.8
8.2
ns
tENHZ
Enable Pad HIGH to Z
7.2
8.0
9.0
10.7
14.9
ns
tENLZ
Enable Pad LOW to Z
6.7
7.5
8.5
9.9
13.9
ns
tGLH
G-to-Pad HIGH
6.8
7.6
8.6
10.1
14.2
ns
tGHL
G-to-Pad LOW
6.8
7.6
8.6
10.1
14.2
ns
tLSU
I/O Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7
8.5
9.6
11.3
15.9
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8
16.5
18.7
22.0
30.8
ns
dTLH
Capacitive Loading, LOW to HIGH
0.05
0.05
0.06
0.07
0.10 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.04
0.04
0.05
0.06
0.08 ns/pF
tHEXT
Input Latch External FO = 32
Hold
FO = 486
3.9
4.6
4.3
5.2
4.9
5.8
5.7
6.9
8.1
9.6
ns
ns
tP
Minimum Period
(1/fMAX)
7.8
8.6
8.7
9.5
9.5
10.4
10.8
11.9
18.2
19.9
ns
ns
FO = 32
FO = 486
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 73
40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Combinatorial
Functions1
tPD
Internal Array Module Delay
1.3
1.5
1.7
2.0
2.7
ns
tPDD
Internal Decode Module Delay
1.6
1.8
2.0
2.4
3.3
ns
Logic Module Predicted Routing
Delays2
tRD1
FO = 1 Routing Delay
0.9
1.0
1.2
1.4
2.0
ns
tRD2
FO = 2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD3
FO =3 Routing Delay
1.6
1.8
2.0
2.4
3.4
ns
tRD4
FO = 4 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
tRD5
FO = 8 Routing Delay
3.3
3.7
4.2
4.9
6.9
ns
tRDD
Decode-to-Output Routing Delay
0.3
0.4
0.4
0.5
0.7
ns
Logic Module Sequential
Timing3, 4
tCO
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.3
0.3
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active 3.3
Pulse Width
3.7
4.2
4.9
6.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous 4.4
Pulse Width
4.8
5.5
6.4
9.0
ns
1.6
1.7
2.0
2.3
3.2
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
tWC
Write Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
tRCKHL
Clock HIGH/LOW Time
3.4
3.8
4.3
5.0
7.0
ns
tRCO
Data Valid After Clock HIGH/LOW
tADSU
Address/Data Set-Up Time
3.4
1.6
3.8
4.3
5.0
7.0
ns
1.8
2.0
2.4
3.4
ns
0.0
0.0
0.0
0.0
ns
Synchronous SRAM Operations (continued)
tADH
Address/Data Hold Time
0.0
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 74
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tRENSU
Read Enable Set-Up
0.6
0.7
0.8
0.9
1.3
ns
tRENH
Read Enable Hold
3.4
3.8
4.3
5.0
7.0
ns
tWENSU
Write Enable Set-Up
2.7
3.0
3.4
4.0
5.6
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tBENS
Block Enable Set-Up
2.8
3.1
3.5
4.1
5.7
ns
tBENH
Block Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
tRDADV
Read Address Valid
8.8
9.8
11.1
13.0
18.2
ns
tADSU
Address/Data Set-Up Time
1.6
1.8
2.0
2.4
3.4
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSUA Read Enable Set-Up to Address 0.6
Valid
0.7
0.8
0.9
1.3
ns
8.1
9.0
10.2
12.0
16.8
ns
tRENHA
Read Enable Hold
3.4
3.8
4.3
5.0
7.0
ns
tWENSU
Write Enable Set-Up
2.7
3.0
3.4
4.0
5.6
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tDOH
Data Out Hold Time
1.2
1.3
1.5
1.8
2.5
ns
1.0
1.1
1.3
1.5
2.1
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
tINGO
Input Latch Gate-to-Output
tINH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tILA
Latch Active Pulse Width
4.7
5.2
5.9
6.9
9.7
ns
1.4
1.6
1.8
2.1
2.9
ns
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
tIRD2
FO = 2 Routing Delay
2.3
2.6
2.9
3.4
4.8
ns
tIRD3
FO = 3 Routing Delay
2.6
2.9
3.3
3.9
5.5
ns
tIRD4
FO = 4 Routing Delay
3.0
3.3
3.8
4.4
6.2
ns
tIRD8
FO = 8 Routing Delay
4.3
4.8
5.5
6.4
9.0
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 75
40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 635
2.7
3.0
3.0
3.3
3.4
3.8
4.0
4.4
5.6
6.2
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 635
3.8
4.9
4.2
5.4
4.8
6.1
5.6
7.2
7.8
10.1
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO = 32
FO = 635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
tPWL
Minimum Pulse
Width LOW
FO = 32
FO = 635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 635
tSUEXT
Input Latch External FO = 32
Set-Up
FO = 635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO = 32
Hold
FO = 635
2.8
3.3
3.2
3.7
3.6
4.2
4.2
4.9
5.9
6.9
ns
ns
tP
Minimum Period
(1/fMAX)
5.5
6.0
6.1
6.6
6.6
7.2
7.6
8.3
12.7
13.8
ns
ns
fMAX
Maximum Datapath FO = 32
Frequency
FO = 635
FO = 32
FO = 635
0.8
0.8
180
166
0.8
0.8
164
151
0.9
0.9
151
139
1.0
1.0
131
121
1.4
1.4
79
73
ns
ns
MHz
MHz
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
2.6
2.8
3.2
3.8
5.3
ns
tDHL
Data-to-Pad LOW
3.0
3.3
3.7
4.4
6.2
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
3.0
3.3
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 76
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
TTL Output Module Timing (Continued)
tENLZ
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
2.9
3.3
3.7
4.4
6.1
ns
tGHL
G-to-Pad LOW
2.9
3.3
3.7
4.4
6.1
ns
tLSU
I/O Latch Output Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.7
6.3
7.1
8.4
11.8
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.8
8.6
9.8
11.5
16.1
ns
dTLH
Capacitive Loading,
LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
dTHL
Capacitive Loading,
HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 77
40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed
–F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
3.5
3.9
4.5
5.2
7.3
ns
tDHL
Data-to-Pad LOW
2.5
2.7
3.1
3.6
5.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.3
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9
ns
tENLZ
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
5.0
5.6
6.3
7.5
10.4
ns
tGHL
G-to-Pad LOW
5.0
5.6
6.3
7.5
10.4
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.7
6.3
7.1
8.4
11.8
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.8
8.6
9.8
11.5
16.1
ns
dTLH
Capacitive Loading,
LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
dTHL
Capacitive Loading,
HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 78
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Combinatorial
Functions1
tPD
Internal Array Module Delay
1.9
2.1
2.3
2.7
3.8
ns
tPDD
Internal Decode Module Delay
2.2
2.5
2.8
3.3
4.7
ns
Logic Module Predicted Routing
Delays2
tRD1
FO = 1 Routing Delay
1.3
1.5
1.7
2.0
2.7
ns
tRD2
FO = 2 Routing Delay
1.8
2.0
2.3
2.7
3.7
ns
tRD3
FO = 3 Routing Delay
2.3
2.5
2.8
3.4
4.7
ns
tRD4
FO = 4 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
tRD5
FO = 8 Routing Delay
4.6
5.2
5.8
6.9
9.6
ns
tRDD
Decode-to-Output Routing Delay
0.5
0.5
0.6
0.7
1.0
ns
Logic Module Sequential
Timing3, 4
tCO
Flip-Flop Clock-to-Output
1.8
2.0
2.3
2.7
3.7
ns
tGO
Latch Gate-to-Output
1.8
2.0
2.3
2.7
3.7
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
4.6
5.2
5.8
6.9
9.6
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
6.1
6.8
7.7
9.0
12.6
ns
2.2
2.4
2.7
3.2
4.5
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
tWC
Write Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
tRCKHL
Clock HIGH/LOW Time
4.8
5.3
6.0
7.0
9.8
ns
tRCO
Data Valid After Clock HIGH/LOW
tADSU
Address/Data Set-Up Time
4.8
2.3
5.3
2.5
6.0
2.8
7.0
3.4
9.8
4.8
ns
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 79
40MX and 42MX FPGA Families
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Synchronous SRAM Operations (continued)
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSU
Read Enable Set-Up
0.9
1.0
1.1
1.3
1.8
ns
tRENH
Read Enable Hold
4.8
5.3
6.0
7.0
9.8
ns
tWENSU
Write Enable Set-Up
3.8
4.2
4.8
5.6
7.8
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tBENS
Block Enable Set-Up
3.9
4.3
4.9
5.7
8.0
ns
tBENH
Block Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
tRDADV
Read Address Valid
12.3
13.7
15.5
18.2
25.5
ns
tADSU
Address/Data Set-Up Time
2.3
2.5
2.8
3.4
4.8
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSUA
Read Enable Set-Up to Address 0.9
Valid
1.0
1.1
1.3
1.8
ns
tRENHA
Read Enable Hold
4.8
5.3
6.0
7.0
9.8
ns
tWENSU
Write Enable Set-Up
3.8
4.2
4.8
5.6
7.8
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tDOH
Data Out Hold Time
11.3
12.6
14.3
16.8
23.5
ns
1.8
2.0
2.1
2.5
3.5
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.4
1.6
1.8
2.1
3.0
ns
tINGO
Input Latch Gate-to-Output
2.0
2.2
2.5
2.9
4.1
ns
tINH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tILA
Latch Active Pulse Width
6.5
7.3
8.2
9.7
13.5
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 80
R ev i sio n 1 1
40MX and 42MX FPGA Families
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
tIRD2
FO = 2 Routing Delay
3.2
3.5
4.1
4.8
6.7
ns
tIRD3
FO = 3 Routing Delay
3.7
4.1
4.7
5.5
7.7
ns
tIRD4
FO = 4 Routing Delay
4.2
4.6
5.3
6.2
8.7
ns
tIRD8
FO = 8 Routing Delay
6.1
6.8
7.7
9.0
12.6
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 635
4.6
5.0
5.1
5.6
5.7
6.3
6.7
7.4
9.3
10.3
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 635
5.3
6.8
5.9
7.6
6.7
8.6
7.8
10.1
11.0
14.1
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO = 32
FO = 635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
tPWL
Minimum Pulse
Width LOW
FO = 32
FO = 635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 635
tSUEXT
Input Latch
External Set-Up
FO = 32
FO = 635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch
External Hold
FO = 32
FO = 635
4.0
4.6
4.4
5.2
5.0
5.9
5.9
6.9
8.2
9.6
ns
ns
tP
Minimum Period
(1/fMAX)
FO = 32
FO = 635
9.2
9.9
10.2
11.0
11.1
12.0
12.7
13.8
21.2
23.0
ns
ns
fMAX
Maximum
Frequency
Datapath FO = 32
FO = 635
1.0
1.0
108
100
1.2
1.2
98
91
1.3
1.3
90
83
1.5
1.5
79
73
2.2
2.2
47
44
ns
ns
MHz
MHz
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
3.6
4.0
4.5
5.3
7.4
ns
tDHL
Data-to-Pad LOW
4.2
4.6
5.2
6.2
8.6
ns
tENZH
Enable Pad Z to HIGH
3.7
4.2
4.7
5.5
7.7
ns
tENZL
Enable Pad Z to LOW
4.1
4.6
5.2
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
7.34
8.2
9.3
10.9
15.3
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
R ev i si o n 1 1
1- 81
40MX and 42MX FPGA Families
Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, T J = 70°C)
–3 Speed
Parameter / Description
–2 Speed
–1 Speed
Std Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
TTL Output Module Timing
tENLZ
Enable Pad LOW to Z
6.9
7.6
8.7
10.2
14.3
ns
tGLH
G-to-Pad HIGH
4.9
5.5
6.2
7.3
10.2
ns
tGHL
G-to-Pad LOW
4.9
5.5
6.2
7.3
10.2
ns
tLSU
I/O Latch Output Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.9
8.8
10.0
11.8
16.5
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.9
12.1
13.7
16.1
22.5
ns
dTLH
Capacitive Loading, LOW to HIGH
0.10
0.11
0.12
0.14
0.20 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.10
0.11
0.12
0.14
0.20 ns/pF
CMOS Output Module
Timing5
tDLH
Data-to-Pad HIGH
4.9
5.5
6.2
7.3
10.3
ns
tDHL
Data-to-Pad LOW
3.4
3.8
4.3
5.1
7.1
ns
tENZH
Enable Pad Z to HIGH
3.7
4.1
4.7
5.5
7.7
ns
tENZL
Enable Pad Z to LOW
4.1
4.6
5.2
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
7.4
8.2
9.3
10.9
15.3
ns
tENLZ
Enable Pad LOW to Z
6.9
7.6
8.7
10.2
14.3
ns
tGLH
G-to-Pad HIGH
7.0
7.8
8.9
10.4
14.6
ns
tGHL
G-to-Pad LOW
7.0
7.8
8.9
10.4
14.6
ns
tLSU
I/O Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.9
8.8
10.0
11.8
16.5
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1- 82
R ev i sio n 1 1
40MX and 42MX FPGA Families
Pin Descriptions
CLK/A/B, I/O
Global Clock
Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX
devices. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an
I/O.
DCLK, I/O
Diagnostic Clock
Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground
Input LOW supply voltage.
I/O
Input/Output
Input, output, tristate or bidirectional buffer. Input and output levels are compatible with standard TTL and
CMOS specifications. Unused I/Os pins are configured by the Designer software as shown in Table 1-40.
Table 1-40 • Configuration of Unused I/Os
Device
Configuration
A40MX02, A40MX04
Pulled LOW
A42MX09, A42MX16
Pulled LOW
A42MX24, A42MX36
Tristated
In all cases, it is recommended to tie all unused MX I/O pins to LOW on the board. This applies to all
dual-purpose pins when configured as I/Os as well.
LP
Low Power Mode
Controls the low power mode of all 42MX devices. The device is placed in the low power mode by
connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned
OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set LOW.
The device enters the low power mode 800 ns after the LP pin is driven to a logic HIGH. It will resume
normal operation in 200 µs after the LP pin is driven to a logic LOW.
MODE
Mode
Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). The MODE pin is held HIGH to
provide verification capability. The MODE pin should be terminated to GND through a 10kΩ resistor so
that the MODE pin can be pulled HIGH when required.
NC
No Connection
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
PRA, I/O
PRB, I/O
Probe A/B
The Probe pin is used to output data from any user-defined design node within the device. Each
diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of
any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has
been completed. The pin's probe capabilities can be permanently disabled to protect programmed design
confidentiality. The Probe pin is accessible when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.
QCLKA/B/C/D, I/O
Quadrant Clock
Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can
function as user I/Os.
R ev i si o n 1 1
1- 83
40MX and 42MX FPGA Families
SDI, I/O
Serial Data Input
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is LOW.
SDO, I/O
Serial Data Output
Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is LOW. SDO is available for 42MX devices only.
When Silicon Explorer II is being used, SDO will act as an output while the "checksum" command is run.
It will return to user I/O when "checksum" is complete.
TCK, I/O
Test Clock
Clock signal to shift the Boundary Scan Test (BST) data into the device. This pin functions as an I/O
when "Reserve JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24
and A42MX36 devices.
TDI, I/O
Test Data In
Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. This pin
functions as an I/O when "Reserve JTAG" is not checked in the Designer Software. BST pins are only
available in A42MX24 and A42MX36 devices.
TDO, I/O
Test Data Out
Serial data output for BST instructions and test data. This pin functions as an I/O when "Reserve JTAG"
is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36
devices.
TMS, I/O
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set LOW, the TCK, TDI and TDO pins are boundary scan pins. Once the boundary
scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine
reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as
regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In
dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. IEEE JTAG
specification recommends a 10kΩ pull-up resistor on the pin. BST pins are only available in A42MX24
and A42MX36 devices.
VCC
Supply Voltage
Input supply voltage for 40MX devices
VCCA
Supply Voltage
Supply voltage for array in 42MX devices
VCCI
Supply Voltage
Supply voltage for I/Os in 42MX devices
WD, I/O
Wide Decode Output
When a wide decode module is used in a 42MX device this pin can be used as a dedicated output from
the wide decode module. This direct connection eliminates additional interconnect delays associated
with regular logic modules. To implement the direct I/O connection, connect an output buffer of any type
to the output of the wide decode macro and place this output on one of the reserved WD pins.
1- 84
R ev i sio n 1 1
2 – Package Pin Assignments
PL44
1 44
44-Pin
PLCC
R ev i si o n 1 1
2 -1
Package Pin Assignments
PL44
PL44
Pin Number A40MX02 Function A40MX04 Function
Pin Number A40MX02 Function A40MX04 Function
2- 2
1
I/O
I/O
37
DCLK, I/O
DCLK, I/O
2
I/O
I/O
38
PRA, I/O
PRA, I/O
3
VCC
VCC
39
PRB, I/O
PRB, I/O
4
I/O
I/O
40
I/O
I/O
5
I/O
I/O
41
I/O
I/O
6
I/O
I/O
42
I/O
I/O
7
I/O
I/O
43
GND
GND
8
I/O
I/O
44
I/O
I/O
9
I/O
I/O
10
GND
GND
11
I/O
I/O
12
I/O
I/O
13
I/O
I/O
14
VCC
VCC
15
I/O
I/O
16
VCC
VCC
17
I/O
I/O
18
I/O
I/O
19
I/O
I/O
20
I/O
I/O
21
GND
GND
22
I/O
I/O
23
I/O
I/O
24
I/O
I/O
25
VCC
VCC
26
I/O
I/O
27
I/O
I/O
28
I/O
I/O
29
I/O
I/O
30
I/O
I/O
31
I/O
I/O
32
GND
GND
33
CLK, I/O
CLK, I/O
34
MODE
MODE
35
VCC
VCC
36
SDI, I/O
SDI, I/O
R ev isio n 1 1
40MX and 42MX FPGA Families
PL68
1 68
68-Pin
PLCC
R ev i si o n 1 1
2 -3
40MX and 42MX FPGA Families
PL44
PL44
Pin
Number
A40MX02
Function
A40MX04
Function
Pin
Number
A40MX02
Function
A40MX04
Function
1
I/O
I/O
36
I/O
I/O
2
I/O
I/O
37
I/O
I/O
3
I/O
I/O
38
VCC
VCC
4
VCC
VCC
39
I/O
I/O
5
I/O
I/O
40
I/O
I/O
6
I/O
I/O
41
I/O
I/O
7
I/O
I/O
42
I/O
I/O
8
I/O
I/O
43
I/O
I/O
9
I/O
I/O
44
I/O
I/O
10
I/O
I/O
45
I/O
I/O
11
I/O
I/O
46
I/O
I/O
12
I/O
I/O
47
I/O
I/O
13
I/O
I/O
48
I/O
I/O
14
GND
GND
49
GND
GND
15
GND
GND
50
I/O
I/O
16
I/O
I/O
51
I/O
I/O
17
I/O
I/O
52
CLK, I/O
CLK, I/O
18
I/O
I/O
53
I/O
I/O
19
I/O
I/O
54
MODE
MODE
20
I/O
I/O
55
VCC
VCC
21
VCC
VCC
56
SDI, I/O
SDI, I/O
22
I/O
I/O
57
DCLK, I/O
DCLK, I/O
23
I/O
I/O
58
PRA, I/O
PRA, I/O
24
I/O
I/O
59
PRB, I/O
PRB, I/O
25
VCC
VCC
60
I/O
I/O
26
I/O
I/O
61
I/O
I/O
27
I/O
I/O
62
I/O
I/O
28
I/O
I/O
63
I/O
I/O
29
I/O
I/O
64
I/O
I/O
30
I/O
I/O
65
I/O
I/O
31
I/O
I/O
66
GND
GND
32
GND
GND
67
I/O
I/O
33
I/O
I/O
68
I/O
I/O
34
I/O
I/O
35
I/O
I/O
R ev i si o n 1 1
2 -4
40MX and 42MX FPGA Families
PL84
1 84
84-Pin
PLCC
R ev i si o n 1 1
2 -5
Package Pin Assignments
PL84
2- 6
Pin Number
A40MX04 Function
A42MX09 Function
A42MX16 Function
A42MX24 Function
1
I/O
I/O
I/O
I/O
2
I/O
CLKB, I/O
CLKB, I/O
CLKB, I/O
3
I/O
I/O
I/O
I/O
4
VCC
PRB, I/O
PRB, I/O
PRB, I/O
5
I/O
I/O
I/O
WD, I/O
6
I/O
GND
GND
GND
7
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
WD, I/O
9
I/O
I/O
I/O
WD, I/O
10
I/O
DCLK, I/O
DCLK, I/O
DCLK, I/O
11
I/O
I/O
I/O
I/O
12
NC
MODE
MODE
MODE
13
I/O
I/O
I/O
I/O
14
I/O
I/O
I/O
I/O
15
I/O
I/O
I/O
I/O
16
I/O
I/O
I/O
I/O
17
I/O
I/O
I/O
I/O
18
GND
I/O
I/O
I/O
19
GND
I/O
I/O
I/O
20
I/O
I/O
I/O
I/O
21
I/O
I/O
I/O
I/O
22
I/O
VCCA
VCCI
VCCI
23
I/O
VCCI
VCCA
VCCA
24
I/O
I/O
I/O
I/O
25
VCC
I/O
I/O
I/O
26
VCC
I/O
I/O
I/O
27
I/O
I/O
I/O
I/O
28
I/O
GND
GND
GND
29
I/O
I/O
I/O
I/O
30
I/O
I/O
I/O
I/O
31
I/O
I/O
I/O
I/O
32
I/O
I/O
I/O
I/O
33
VCC
I/O
I/O
I/O
34
I/O
I/O
I/O
TMS, I/O
35
I/O
I/O
I/O
TDI, I/O
36
I/O
I/O
I/O
WD, I/O
R ev isio n 1 1
40MX and 42MX FPGA Families
PL84
Pin Number
A40MX04 Function
A42MX09 Function
A42MX16 Function
A42MX24 Function
37
I/O
I/O
I/O
I/O
38
I/O
I/O
I/O
WD, I/O
39
I/O
I/O
I/O
WD, I/O
40
GND
I/O
I/O
I/O
41
I/O
I/O
I/O
I/O
42
I/O
I/O
I/O
I/O
43
I/O
VCCA
VCCA
VCCA
44
I/O
I/O
I/O
WD, I/O
45
I/O
I/O
I/O
WD, I/O
46
VCC
I/O
I/O
WD, I/O
47
I/O
I/O
I/O
WD, I/O
48
I/O
I/O
I/O
I/O
49
I/O
GND
GND
GND
50
I/O
I/O
I/O
WD, I/O
51
I/O
I/O
I/O
WD, I/O
52
I/O
SDO, I/O
SDO, I/O
SDO, TDO, I/O
53
I/O
I/O
I/O
I/O
54
I/O
I/O
I/O
I/O
55
I/O
I/O
I/O
I/O
56
I/O
I/O
I/O
I/O
57
I/O
I/O
I/O
I/O
58
I/O
I/O
I/O
I/O
59
I/O
I/O
I/O
I/O
60
GND
I/O
I/O
I/O
61
GND
I/O
I/O
I/O
62
I/O
I/O
I/O
TCK, I/O
63
I/O
LP
LP
LP
64
CLK, I/O
VCCA
VCCA
VCCA
65
I/O
VCCI
VCCI
VCCI
66
MODE
I/O
I/O
I/O
67
VCC
I/O
I/O
I/O
68
VCC
I/O
I/O
I/O
69
I/O
I/O
I/O
I/O
70
I/O
GND
GND
GND
71
I/O
I/O
I/O
I/O
72
SDI, I/O
I/O
I/O
I/O
R ev i si o n 1 1
2 -7
Package Pin Assignments
PL84
2- 8
Pin Number
A40MX04 Function
A42MX09 Function
A42MX16 Function
A42MX24 Function
73
DCLK, I/O
I/O
I/O
I/O
74
PRA, I/O
I/O
I/O
I/O
75
PRB, I/O
I/O
I/O
I/O
76
I/O
SDI, I/O
SDI, I/O
SDI, I/O
77
I/O
I/O
I/O
I/O
78
I/O
I/O
I/O
WD, I/O
79
I/O
I/O
I/O
WD, I/O
80
I/O
I/O
I/O
WD, I/O
81
I/O
PRA, I/O
PRA, I/O
PRA, I/O
82
GND
I/O
I/O
I/O
83
I/O
CLKA, I/O
CLKA, I/O
CLKA, I/O
84
I/O
VCCA
VCCA
VCCA
R ev isio n 1 1
40MX and 42MX FPGA Families
PQ100
100-Pin
PQFP
100
1
R ev i si o n 1 1
2 -9
Package Pin Assignments
PQ100
2- 10
Pin Number
A40MX02 Function
A40MX04 Function
A42MX09 Function
A42MX16 Function
1
NC
NC
I/O
I/O
2
NC
NC
DCLK, I/O
DCLK, I/O
3
NC
NC
I/O
I/O
4
NC
NC
MODE
MODE
5
NC
NC
I/O
I/O
6
PRB, I/O
PRB, I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
9
I/O
I/O
GND
GND
10
I/O
I/O
I/O
I/O
11
I/O
I/O
I/O
I/O
12
I/O
I/O
I/O
I/O
13
GND
GND
I/O
I/O
14
I/O
I/O
I/O
I/O
15
I/O
I/O
I/O
I/O
16
I/O
I/O
VCCA
VCCA
17
I/O
I/O
VCCI
VCCA
18
I/O
I/O
I/O
I/O
19
VCC
VCC
I/O
I/O
20
I/O
I/O
I/O
I/O
21
I/O
I/O
I/O
I/O
22
I/O
I/O
GND
GND
23
I/O
I/O
I/O
I/O
24
I/O
I/O
I/O
I/O
25
I/O
I/O
I/O
I/O
26
I/O
I/O
I/O
I/O
27
NC
NC
I/O
I/O
28
NC
NC
I/O
I/O
29
NC
NC
I/O
I/O
30
NC
NC
I/O
I/O
31
NC
I/O
I/O
I/O
32
NC
I/O
I/O
I/O
33
NC
I/O
I/O
I/O
34
I/O
I/O
GND
GND
35
I/O
I/O
I/O
I/O
36
GND
GND
I/O
I/O
R ev i sio n 1 1
40MX and 42MX FPGA Families
PQ100
Pin Number
A40MX02 Function
A40MX04 Function
A42MX09 Function
A42MX16 Function
37
GND
GND
I/O
I/O
38
I/O
I/O
I/O
I/O
39
I/O
I/O
I/O
I/O
40
I/O
I/O
VCCA
VCCA
41
I/O
I/O
I/O
I/O
42
I/O
I/O
I/O
I/O
43
VCC
VCC
I/O
I/O
44
VCC
VCC
I/O
I/O
45
I/O
I/O
I/O
I/O
46
I/O
I/O
GND
GND
47
I/O
I/O
I/O
I/O
48
NC
I/O
I/O
I/O
49
NC
I/O
I/O
I/O
50
NC
I/O
I/O
I/O
51
NC
NC
I/O
I/O
52
NC
NC
SDO, I/O
SDO, I/O
53
NC
NC
I/O
I/O
54
NC
NC
I/O
I/O
55
NC
NC
I/O
I/O
56
VCC
VCC
I/O
I/O
57
I/O
I/O
GND
GND
58
I/O
I/O
I/O
I/O
59
I/O
I/O
I/O
I/O
60
I/O
I/O
I/O
I/O
61
I/O
I/O
I/O
I/O
62
I/O
I/O
I/O
I/O
63
GND
GND
I/O
I/O
64
I/O
I/O
LP
LP
65
I/O
I/O
VCCA
VCCA
66
I/O
I/O
VCCI
VCCI
67
I/O
I/O
VCCA
VCCA
68
I/O
I/O
I/O
I/O
69
VCC
VCC
I/O
I/O
70
I/O
I/O
I/O
I/O
71
I/O
I/O
I/O
I/O
72
I/O
I/O
GND
GND
R ev i si o n 1 1
2- 11
Package Pin Assignments
PQ100
2- 12
Pin Number
A40MX02 Function
A40MX04 Function
A42MX09 Function
A42MX16 Function
73
I/O
I/O
I/O
I/O
74
I/O
I/O
I/O
I/O
75
I/O
I/O
I/O
I/O
76
I/O
I/O
I/O
I/O
77
NC
NC
I/O
I/O
78
NC
NC
I/O
I/O
79
NC
NC
SDI, I/O
SDI, I/O
80
NC
I/O
I/O
I/O
81
NC
I/O
I/O
I/O
82
NC
I/O
I/O
I/O
83
I/O
I/O
I/O
I/O
84
I/O
I/O
GND
GND
85
I/O
I/O
I/O
I/O
86
GND
GND
I/O
I/O
87
GND
GND
PRA, I/O
PRA, I/O
88
I/O
I/O
I/O
I/O
89
I/O
I/O
CLKA, I/O
CLKA, I/O
90
CLK, I/O
CLK, I/O
VCCA
VCCA
91
I/O
I/O
I/O
I/O
92
MODE
MODE
CLKB, I/O
CLKB, I/O
93
VCC
VCC
I/O
I/O
94
VCC
VCC
PRB, I/O
PRB, I/O
95
NC
I/O
I/O
I/O
96
NC
I/O
GND
GND
97
NC
I/O
I/O
I/O
98
SDI, I/O
SDI, I/O
I/O
I/O
99
DCLK, I/O
DCLK, I/O
I/O
I/O
100
PRA, I/O
PRA, I/O
I/O
I/O
R ev i sio n 1 1
40MX and 42MX FPGA Families
PQ160
160
1
160-Pin
PQFP
R ev i si o n 1 1
2- 13
Package Pin Assignments
PQ160
2- 14
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
1
I/O
I/O
I/O
2
DCLK, I/O
DCLK, I/O
DCLK, I/O
3
NC
I/O
I/O
4
I/O
I/O
WD, I/O
5
I/O
I/O
WD, I/O
6
NC
VCCI
VCCI
7
I/O
I/O
I/O
8
I/O
I/O
I/O
9
I/O
I/O
I/O
10
NC
I/O
I/O
11
GND
GND
GND
12
NC
I/O
I/O
13
I/O
I/O
WD, I/O
14
I/O
I/O
WD, I/O
15
I/O
I/O
I/O
16
PRB, I/O
PRB, I/O
PRB, I/O
17
I/O
I/O
I/O
18
CLKB, I/O
CLKB, I/O
CLKB, I/O
19
I/O
I/O
I/O
20
VCCA
VCCA
VCCA
21
CLKA, I/O
CLKA, I/O
CLKA, I/O
22
I/O
I/O
I/O
23
PRA, I/O
PRA, I/O
PRA, I/O
24
NC
I/O
WD, I/O
25
I/O
I/O
WD, I/O
26
I/O
I/O
I/O
27
I/O
I/O
I/O
28
NC
I/O
I/O
29
I/O
I/O
WD, I/O
30
GND
GND
GND
31
NC
I/O
WD, I/O
32
I/O
I/O
I/O
33
I/O
I/O
I/O
34
I/O
I/O
I/O
35
NC
VCCI
VCCI
36
I/O
I/O
WD, I/O
R ev i sio n 1 1
40MX and 42MX FPGA Families
PQ160
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
37
I/O
I/O
WD, I/O
38
SDI, I/O
SDI, I/O
SDI, I/O
39
I/O
I/O
I/O
40
GND
GND
GND
41
I/O
I/O
I/O
42
I/O
I/O
I/O
43
I/O
I/O
I/O
44
GND
GND
GND
45
I/O
I/O
I/O
46
I/O
I/O
I/O
47
I/O
I/O
I/O
48
I/O
I/O
I/O
49
GND
GND
GND
50
I/O
I/O
I/O
51
I/O
I/O
I/O
52
NC
I/O
I/O
53
I/O
I/O
I/O
54
NC
VCCA
VCCA
55
I/O
I/O
I/O
56
I/O
I/O
I/O
57
VCCA
VCCA
VCCA
58
VCCI
VCCI
VCCI
59
GND
GND
GND
60
VCCA
VCCA
VCCA
61
LP
LP
LP
62
I/O
I/O
TCK, I/O
63
I/O
I/O
I/O
64
GND
GND
GND
65
I/O
I/O
I/O
66
I/O
I/O
I/O
67
I/O
I/O
I/O
68
I/O
I/O
I/O
69
GND
GND
GND
70
NC
I/O
I/O
71
I/O
I/O
I/O
72
I/O
I/O
I/O
R ev i si o n 1 1
2- 15
Package Pin Assignments
PQ160
2- 16
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
73
I/O
I/O
I/O
74
I/O
I/O
I/O
75
NC
I/O
I/O
76
I/O
I/O
I/O
77
NC
I/O
I/O
78
I/O
I/O
I/O
79
NC
I/O
I/O
80
GND
GND
GND
81
I/O
I/O
I/O
82
SDO, I/O
SDO, I/O
SDO, TDO, I/O
83
I/O
I/O
WD, I/O
84
I/O
I/O
WD, I/O
85
I/O
I/O
I/O
86
NC
VCCI
VCCI
87
I/O
I/O
I/O
88
I/O
I/O
WD, I/O
89
GND
GND
GND
90
NC
I/O
I/O
91
I/O
I/O
I/O
92
I/O
I/O
I/O
93
I/O
I/O
I/O
94
I/O
I/O
I/O
95
I/O
I/O
I/O
96
I/O
I/O
WD, I/O
97
I/O
I/O
I/O
98
VCCA
VCCA
VCCA
99
GND
GND
GND
100
NC
I/O
I/O
101
I/O
I/O
I/O
102
I/O
I/O
I/O
103
NC
I/O
I/O
104
I/O
I/O
I/O
105
I/O
I/O
I/O
106
I/O
I/O
WD, I/O
107
I/O
I/O
WD, I/O
108
I/O
I/O
I/O
R ev i sio n 1 1
40MX and 42MX FPGA Families
PQ160
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
109
GND
GND
GND
110
NC
I/O
I/O
111
I/O
I/O
WD, I/O
112
I/O
I/O
WD, I/O
113
I/O
I/O
I/O
114
NC
VCCI
VCCI
115
I/O
I/O
WD, I/O
116
NC
I/O
WD, I/O
117
I/O
I/O
I/O
118
I/O
I/O
TDI, I/O
119
I/O
I/O
TMS, I/O
120
GND
GND
GND
121
I/O
I/O
I/O
122
I/O
I/O
I/O
123
I/O
I/O
I/O
124
NC
I/O
I/O
125
GND
GND
GND
126
I/O
I/O
I/O
127
I/O
I/O
I/O
128
I/O
I/O
I/O
129
NC
I/O
I/O
130
GND
GND
GND
131
I/O
I/O
I/O
132
I/O
I/O
I/O
133
I/O
I/O
I/O
134
I/O
I/O
I/O
135
NC
VCCA
VCCA
136
I/O
I/O
I/O
137
I/O
I/O
I/O
138
NC
VCCA
VCCA
139
VCCI
VCCI
VCCI
140
GND
GND
GND
141
NC
I/O
I/O
142
I/O
I/O
I/O
143
I/O
I/O
I/O
144
I/O
I/O
I/O
R ev i si o n 1 1
2- 17
Package Pin Assignments
PQ160
2- 18
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
145
GND
GND
GND
146
NC
I/O
I/O
147
I/O
I/O
I/O
148
I/O
I/O
I/O
149
I/O
I/O
I/O
150
NC
VCCA
VCCA
151
NC
I/O
I/O
152
NC
I/O
I/O
153
NC
I/O
I/O
154
NC
I/O
I/O
155
GND
GND
GND
156
I/O
I/O
I/O
157
I/O
I/O
I/O
158
I/O
I/O
I/O
159
MODE
MODE
MODE
160
GND
GND
GND
R ev i sio n 1 1
40MX and 42MX FPGA Families
PQ208
208
1
208-Pin PQFP
R ev i si o n 1 1
2- 19
Package Pin Assignments
PQ208
2- 20
Pin Number
A42MX16 Function
A42MX24 Function
A42MX36 Function
1
GND
GND
GND
2
NC
VCCA
VCCA
3
MODE
MODE
MODE
4
I/O
I/O
I/O
5
I/O
I/O
I/O
6
I/O
I/O
I/O
7
I/O
I/O
I/O
8
I/O
I/O
I/O
9
NC
I/O
I/O
10
NC
I/O
I/O
11
NC
I/O
I/O
12
I/O
I/O
I/O
13
I/O
I/O
I/O
14
I/O
I/O
I/O
15
I/O
I/O
I/O
16
NC
I/O
I/O
17
VCCA
VCCA
VCCA
18
I/O
I/O
I/O
19
I/O
I/O
I/O
20
I/O
I/O
I/O
21
I/O
I/O
I/O
22
GND
GND
GND
23
I/O
I/O
I/O
24
I/O
I/O
I/O
25
I/O
I/O
I/O
26
I/O
I/O
I/O
27
GND
GND
GND
28
VCCI
VCCI
VCCI
29
VCCA
VCCA
VCCA
30
I/O
I/O
I/O
31
I/O
I/O
I/O
32
VCCA
VCCA
VCCA
33
I/O
I/O
I/O
34
I/O
I/O
I/O
35
I/O
I/O
I/O
36
I/O
I/O
I/O
R ev i sio n 1 1
40MX and 42MX FPGA Families
PQ208
Pin Number
A42MX16 Function
A42MX24 Function
A42MX36 Function
37
I/O
I/O
I/O
38
I/O
I/O
I/O
39
I/O
I/O
I/O
40
I/O
I/O
I/O
41
NC
I/O
I/O
42
NC
I/O
I/O
43
NC
I/O
I/O
44
I/O
I/O
I/O
45
I/O
I/O
I/O
46
I/O
I/O
I/O
47
I/O
I/O
I/O
48
I/O
I/O
I/O
49
I/O
I/O
I/O
50
NC
I/O
I/O
51
NC
I/O
I/O
52
GND
GND
GND
53
GND
GND
GND
54
I/O
TMS, I/O
TMS, I/O
55
I/O
TDI, I/O
TDI, I/O
56
I/O
I/O
I/O
57
I/O
WD, I/O
WD, I/O
58
I/O
WD, I/O
WD, I/O
59
I/O
I/O
I/O
60
VCCI
VCCI
VCCI
61
NC
I/O
I/O
62
NC
I/O
I/O
63
I/O
I/O
I/O
64
I/O
I/O
I/O
65
I/O
I/O
QCLKA, I/O
66
I/O
WD, I/O
WD, I/O
67
NC
WD, I/O
WD, I/O
68
NC
I/O
I/O
69
I/O
I/O
I/O
70
I/O
WD, I/O
WD, I/O
71
I/O
WD, I/O
WD, I/O
72
I/O
I/O
I/O
R ev i si o n 1 1
2- 21
Package Pin Assignments
PQ208
2- 22
Pin Number
A42MX16 Function
A42MX24 Function
A42MX36 Function
73
I/O
I/O
I/O
74
I/O
I/O
I/O
75
I/O
I/O
I/O
76
I/O
I/O
I/O
77
I/O
I/O
I/O
78
GND
GND
GND
79
VCCA
VCCA
VCCA
80
NC
VCCI
VCCI
81
I/O
I/O
I/O
82
I/O
I/O
I/O
83
I/O
I/O
I/O
84
I/O
I/O
I/O
85
I/O
WD, I/O
WD, I/O
86
I/O
WD, I/O
WD, I/O
87
I/O
I/O
I/O
88
I/O
I/O
I/O
89
NC
I/O
I/O
90
NC
I/O
I/O
91
I/O
I/O
QCLKB, I/O
92
I/O
I/O
I/O
93
I/O
WD, I/O
WD, I/O
94
I/O
WD, I/O
WD, I/O
95
NC
I/O
I/O
96
NC
I/O
I/O
97
NC
I/O
I/O
98
VCCI
VCCI
VCCI
99
I/O
I/O
I/O
100
I/O
WD, I/O
WD, I/O
101
I/O
WD, I/O
WD, I/O
102
I/O
I/O
I/O
103
SDO, I/O
SDO, TDO, I/O
SDO, TDO, I/O
104
I/O
I/O
I/O
105
GND
GND
GND
106
NC
VCCA
VCCA
107
I/O
I/O
I/O
108
I/O
I/O
I/O
R ev i sio n 1 1
40MX and 42MX FPGA Families
PQ208
Pin Number
A42MX16 Function
A42MX24 Function
A42MX36 Function
109
I/O
I/O
I/O
110
I/O
I/O
I/O
111
I/O
I/O
I/O
112
NC
I/O
I/O
113
NC
I/O
I/O
114
NC
I/O
I/O
115
NC
I/O
I/O
116
I/O
I/O
I/O
117
I/O
I/O
I/O
118
I/O
I/O
I/O
119
I/O
I/O
I/O
120
I/O
I/O
I/O
121
I/O
I/O
I/O
122
I/O
I/O
I/O
123
I/O
I/O
I/O
124
I/O
I/O
I/O
125
I/O
I/O
I/O
126
GND
GND
GND
127
I/O
I/O
I/O
128
I/O
TCK, I/O
TCK, I/O
129
LP
LP
LP
130
VCCA
VCCA
VCCA
131
GND
GND
GND
132
VCCI
VCCI
VCCI
133
VCCA
VCCA
VCCA
134
I/O
I/O
I/O
135
I/O
I/O
I/O
136
VCCA
VCCA
VCCA
137
I/O
I/O
I/O
138
I/O
I/O
I/O
139
I/O
I/O
I/O
140
I/O
I/O
I/O
141
NC
I/O
I/O
142
I/O
I/O
I/O
143
I/O
I/O
I/O
144
I/O
I/O
I/O
R ev i si o n 1 1
2- 23
Package Pin Assignments
PQ208
2- 24
Pin Number
A42MX16 Function
A42MX24 Function
A42MX36 Function
145
I/O
I/O
I/O
146
NC
I/O
I/O
147
NC
I/O
I/O
148
NC
I/O
I/O
149
NC
I/O
I/O
150
GND
GND
GND
151
I/O
I/O
I/O
152
I/O
I/O
I/O
153
I/O
I/O
I/O
154
I/O
I/O
I/O
155
I/O
I/O
I/O
156
I/O
I/O
I/O
157
GND
GND
GND
158
I/O
I/O
I/O
159
SDI, I/O
SDI, I/O
SDI, I/O
160
I/O
I/O
I/O
161
I/O
WD, I/O
WD, I/O
162
I/O
WD, I/O
WD, I/O
163
I/O
I/O
I/O
164
VCCI
VCCI
VCCI
165
NC
I/O
I/O
166
NC
I/O
I/O
167
I/O
I/O
I/O
168
I/O
WD, I/O
WD, I/O
169
I/O
WD, I/O
WD, I/O
170
I/O
I/O
I/O
171
NC
I/O
QCLKD, I/O
172
I/O
I/O
I/O
173
I/O
I/O
I/O
174
I/O
I/O
I/O
175
I/O
I/O
I/O
176
I/O
WD, I/O
WD, I/O
177
I/O
WD, I/O
WD, I/O
178
PRA, I/O
PRA, I/O
PRA, I/O
179
I/O
I/O
I/O
180
CLKA, I/O
CLKA, I/O
CLKA, I/O
R ev i sio n 1 1
40MX and 42MX FPGA Families
PQ208
Pin Number
A42MX16 Function
A42MX24 Function
A42MX36 Function
181
NC
I/O
I/O
182
NC
VCCI
VCCI
183
VCCA
VCCA
VCCA
184
GND
GND
GND
185
I/O
I/O
I/O
186
CLKB, I/O
CLKB, I/O
CLKB, I/O
187
I/O
I/O
I/O
188
PRB, I/O
PRB, I/O
PRB, I/O
189
I/O
I/O
I/O
190
I/O
WD, I/O
WD, I/O
191
I/O
WD, I/O
WD, I/O
192
I/O
I/O
I/O
193
NC
I/O
I/O
194
NC
WD, I/O
WD, I/O
195
NC
WD, I/O
WD, I/O
196
I/O
I/O
QCLKC, I/O
197
NC
I/O
I/O
198
I/O
I/O
I/O
199
I/O
I/O
I/O
200
I/O
I/O
I/O
201
NC
I/O
I/O
202
VCCI
VCCI
VCCI
203
I/O
WD, I/O
WD, I/O
204
I/O
WD, I/O
WD, I/O
205
I/O
I/O
I/O
206
I/O
I/O
I/O
207
DCLK, I/O
DCLK, I/O
DCLK, I/O
208
I/O
I/O
I/O
R ev i si o n 1 1
2- 25
Package Pin Assignments
•
•
•
PQ240
240
1
240-Pin
PQFP
•
•
•
•
•
•
Note: 240-Pin PQFP Package (Top View)
2- 26
R ev i sio n 1 1
•
•
•
40MX and 42MX FPGA Families
PQ240
PQ240
PQ240
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
1
I/O
37
WD, I/O
73
I/O
2
DCLK, I/O
38
WD, I/O
74
I/O
3
I/O
39
I/O
75
I/O
4
I/O
40
I/O
76
I/O
5
I/O
41
I/O
77
I/O
6
WD, I/O
42
I/O
78
I/O
7
WD, I/O
43
I/O
79
I/O
8
VCCI
44
I/O
80
I/O
9
I/O
45
QCLKD, I/O
81
I/O
10
I/O
46
I/O
82
I/O
11
I/O
47
WD, I/O
83
I/O
12
I/O
48
WD, I/O
84
I/O
13
I/O
49
I/O
85
VCCA
14
I/O
50
I/O
86
I/O
15
QCLKC, I/O
51
I/O
87
I/O
16
I/O
52
VCCI
88
VCCA
17
WD, I/O
53
I/O
89
VCCI
18
WD, I/O
54
WD, I/O
90
VCCA
19
I/O
55
WD, I/O
91
LP
20
I/O
56
I/O
92
TCK, I/O
21
WD, I/O
57
SDI, I/O
93
I/O
22
WD, I/O
58
I/O
94
GND
23
I/O
59
VCCA
95
I/O
24
PRB, I/O
60
GND
96
I/O
25
I/O
61
GND
97
I/O
26
CLKB, I/O
62
I/O
98
I/O
27
I/O
63
I/O
99
I/O
28
GND
64
I/O
100
I/O
29
VCCA
65
I/O
101
I/O
30
VCCI
66
I/O
102
I/O
31
I/O
67
I/O
103
I/O
32
CLKA, I/O
68
I/O
104
I/O
33
I/O
69
I/O
105
I/O
34
PRA, I/O
70
I/O
106
I/O
35
I/O
71
VCCI
107
I/O
36
I/O
72
I/O
108
VCCI
R ev i si o n 1 1
2- 27
Package Pin Assignments
PQ240
PQ240
PQ240
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
109
I/O
145
I/O
181
VCCA
110
I/O
146
I/O
182
GND
111
I/O
147
I/O
183
I/O
112
I/O
148
I/O
184
I/O
113
I/O
149
I/O
185
I/O
114
I/O
150
VCCI
186
I/O
115
I/O
151
VCCA
187
I/O
116
I/O
152
GND
188
I/O
117
I/O
153
I/O
189
I/O
118
VCCA
154
I/O
190
I/O
119
GND
155
I/O
191
I/O
120
GND
156
I/O
192
VCCI
121
GND
157
I/O
193
I/O
122
I/O
158
I/O
194
I/O
123
SDO, TDO, I/O
159
WD, I/O
195
I/O
124
I/O
160
WD, I/O
196
I/O
125
WD, I/O
161
I/O
197
I/O
126
WD, I/O
162
I/O
198
I/O
127
I/O
163
WD, I/O
199
I/O
128
VCCI
164
WD, I/O
200
I/O
129
I/O
165
I/O
201
I/O
130
I/O
166
QCLKA, I/O
202
I/O
131
I/O
167
I/O
203
I/O
132
WD, I/O
168
I/O
204
I/O
133
WD, I/O
169
I/O
205
I/O
134
I/O
170
I/O
206
VCCA
135
QCLKB, I/O
171
I/O
207
I/O
136
I/O
172
VCCI
208
I/O
137
I/O
173
I/O
209
VCCA
138
I/O
174
WD, I/O
210
VCCI
139
I/O
175
WD, I/O
211
I/O
140
I/O
176
I/O
212
I/O
141
I/O
177
I/O
213
I/O
142
WD, I/O
178
TDI, I/O
214
I/O
143
WD, I/O
179
TMS, I/O
215
I/O
144
I/O
180
GND
216
I/O
2- 28
R ev i sio n 1 1
40MX and 42MX FPGA Families
PQ240
Pin Number
A42MX36 Function
217
I/O
218
I/O
219
VCCA
220
I/O
221
I/O
222
I/O
223
I/O
224
I/O
225
I/O
226
I/O
227
VCCI
228
I/O
229
I/O
230
I/O
231
I/O
232
I/O
233
I/O
234
I/O
235
I/O
236
I/O
237
GND
238
MODE
239
VCCA
240
GND
R ev i si o n 1 1
2- 29
Package Pin Assignments
VQ80
80
1
80-Pin
VQFP
2- 30
R ev i sio n 1 1
40MX and 42MX FPGA Families
VQ80
VQ80
VQ80
Pin
Number
A40MX02
Function
A40MX04
Function
Pin
Number
A40MX02
Function
A40MX04
Function
Pin
Number
A40MX02
Function
A40MX04
Function
1
I/O
I/O
28
I/O
I/O
55
NC
I/O
2
NC
I/O
29
I/O
I/O
56
NC
I/O
3
NC
I/O
30
I/O
I/O
57
SDI, I/O
SDI, I/O
4
NC
I/O
31
I/O
I/O
58
DCLK, I/O
DCLK, I/O
5
I/O
I/O
32
I/O
I/O
59
PRA, I/O
PRA, I/O
6
I/O
I/O
33
VCC
VCC
60
NC
NC
7
GND
GND
34
I/O
I/O
61
PRB, I/O
PRB, I/O
8
I/O
I/O
35
I/O
I/O
62
I/O
I/O
9
I/O
I/O
36
I/O
I/O
63
I/O
I/O
10
I/O
I/O
37
I/O
I/O
64
I/O
I/O
11
I/O
I/O
38
I/O
I/O
65
I/O
I/O
12
I/O
I/O
39
I/O
I/O
66
I/O
I/O
13
VCC
VCC
40
I/O
I/O
67
I/O
I/O
14
I/O
I/O
41
NC
I/O
68
GND
GND
15
I/O
I/O
42
NC
I/O
69
I/O
I/O
16
I/O
I/O
43
NC
I/O
70
I/O
I/O
17
NC
I/O
44
I/O
I/O
71
I/O
I/O
18
NC
I/O
45
I/O
I/O
72
I/O
I/O
19
NC
I/O
46
I/O
I/O
73
I/O
I/O
20
VCC
VCC
47
GND
GND
74
VCC
VCC
21
I/O
I/O
48
I/O
I/O
75
I/O
I/O
22
I/O
I/O
49
I/O
I/O
76
I/O
I/O
23
I/O
I/O
50
CLK, I/O
CLK, I/O
77
I/O
I/O
24
I/O
I/O
51
I/O
I/O
78
I/O
I/O
25
I/O
I/O
52
MODE
MODE
79
I/O
I/O
26
I/O
I/O
53
VCC
VCC
80
I/O
I/O
27
GND
GND
54
NC
I/O
R ev i si o n 1 1
2- 31
Package Pin Assignments
VQ100
100
1
100-Pin
VQFP
2- 32
R ev i sio n 1 1
40MX and 42MX FPGA Families
VQ100
VQ100
VQ100
Pin
Number
A42MX09
Function
A42MX16
Function
Pin
Number
A42MX09
Function
A42MX16
Function
Pin
Number
A42MX09
Function
A42MX16
Function
1
I/O
I/O
36
I/O
I/O
71
I/O
I/O
2
MODE
MODE
37
I/O
I/O
72
I/O
I/O
3
I/O
I/O
38
VCCA
VCCA
73
I/O
I/O
4
I/O
I/O
39
I/O
I/O
74
I/O
I/O
5
I/O
I/O
40
I/O
I/O
75
I/O
I/O
6
I/O
I/O
41
I/O
I/O
76
I/O
I/O
7
GND
GND
42
I/O
I/O
77
SDI, I/O
SDI, I/O
8
I/O
I/O
43
I/O
I/O
78
I/O
I/O
9
I/O
I/O
44
GND
GND
79
I/O
I/O
10
I/O
I/O
45
I/O
I/O
80
I/O
I/O
11
I/O
I/O
46
I/O
I/O
81
I/O
I/O
12
I/O
I/O
47
I/O
I/O
82
GND
GND
13
I/O
I/O
48
I/O
I/O
83
I/O
I/O
14
VCCA
NC
49
I/O
I/O
84
I/O
I/O
15
VCCI
VCCI
50
SDO, I/O
SDO, I/O
85
PRA, I/O
PRA, I/O
16
I/O
I/O
51
I/O
I/O
86
I/O
I/O
17
I/O
I/O
52
I/O
I/O
87
CLKA, I/O
CLKA, I/O
18
I/O
I/O
53
I/O
I/O
88
VCCA
VCCA
19
I/O
I/O
54
I/O
I/O
89
I/O
I/O
20
GND
GND
55
GND
GND
90
CLKB, I/O
CLKB, I/O
21
I/O
I/O
56
I/O
I/O
91
I/O
I/O
22
I/O
I/O
57
I/O
I/O
92
PRB, I/O
PRB, I/O
23
I/O
I/O
58
I/O
I/O
93
I/O
I/O
24
I/O
I/O
59
I/O
I/O
94
GND
GND
25
I/O
I/O
60
I/O
I/O
95
I/O
I/O
26
I/O
I/O
61
I/O
I/O
96
I/O
I/O
27
I/O
I/O
62
LP
LP
97
I/O
I/O
28
I/O
I/O
63
VCCA
VCCA
98
I/O
I/O
29
I/O
I/O
64
VCCI
VCCI
99
I/O
I/O
30
I/O
I/O
65
VCCA
VCCA
100
DCLK, I/O
DCLK, I/O
31
I/O
I/O
66
I/O
I/O
32
GND
GND
67
I/O
I/O
33
I/O
I/O
68
I/O
I/O
34
I/O
I/O
69
I/O
I/O
35
I/O
I/O
70
GND
GND
R ev i si o n 1 1
2- 33
Package Pin Assignments
TQ176
176
1
176-Pin
TQFP
2- 34
R ev i sio n 1 1
40MX and 42MX FPGA Families
TQ176
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
1
GND
GND
GND
2
MODE
MODE
MODE
3
I/O
I/O
I/O
4
I/O
I/O
I/O
5
I/O
I/O
I/O
6
I/O
I/O
I/O
7
I/O
I/O
I/O
8
NC
NC
I/O
9
I/O
I/O
I/O
10
NC
I/O
I/O
11
NC
I/O
I/O
12
I/O
I/O
I/O
13
NC
VCCA
VCCA
14
I/O
I/O
I/O
15
I/O
I/O
I/O
16
I/O
I/O
I/O
17
I/O
I/O
I/O
18
GND
GND
GND
19
NC
I/O
I/O
20
NC
I/O
I/O
21
I/O
I/O
I/O
22
NC
I/O
I/O
23
GND
GND
GND
24
NC
VCCI
VCCI
25
VCCA
VCCA
VCCA
26
NC
I/O
I/O
27
NC
I/O
I/O
28
VCCI
VCCA
VCCA
29
NC
I/O
I/O
30
I/O
I/O
I/O
31
I/O
I/O
I/O
32
I/O
I/O
I/O
33
NC
NC
I/O
34
I/O
I/O
I/O
35
I/O
I/O
I/O
36
I/O
I/O
I/O
R ev i si o n 1 1
2- 35
Package Pin Assignments
TQ176
2- 36
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
37
NC
I/O
I/O
38
NC
NC
I/O
39
I/O
I/O
I/O
40
I/O
I/O
I/O
41
I/O
I/O
I/O
42
I/O
I/O
I/O
43
I/O
I/O
I/O
44
I/O
I/O
I/O
45
GND
GND
GND
46
I/O
I/O
TMS, I/O
47
I/O
I/O
TDI, I/O
48
I/O
I/O
I/O
49
I/O
I/O
WD, I/O
50
I/O
I/O
WD, I/O
51
I/O
I/O
I/O
52
NC
VCCI
VCCI
53
I/O
I/O
I/O
54
NC
I/O
I/O
55
NC
I/O
WD, I/O
56
I/O
I/O
WD, I/O
57
NC
NC
I/O
58
I/O
I/O
I/O
59
I/O
I/O
WD, I/O
60
I/O
I/O
WD, I/O
61
NC
I/O
I/O
62
I/O
I/O
I/O
63
I/O
I/O
I/O
64
NC
I/O
I/O
65
I/O
I/O
I/O
66
NC
I/O
I/O
67
GND
GND
GND
68
VCCA
VCCA
VCCA
69
I/O
I/O
WD, I/O
70
I/O
I/O
WD, I/O
71
I/O
I/O
I/O
72
I/O
I/O
I/O
R ev i sio n 1 1
40MX and 42MX FPGA Families
TQ176
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
73
I/O
I/O
I/O
74
NC
I/O
I/O
75
I/O
I/O
I/O
76
I/O
I/O
I/O
77
NC
NC
WD, I/O
78
NC
I/O
WD, I/O
79
I/O
I/O
I/O
80
NC
I/O
I/O
81
I/O
I/O
I/O
82
NC
VCCI
VCCI
83
I/O
I/O
I/O
84
I/O
I/O
WD, I/O
85
I/O
I/O
WD, I/O
86
NC
I/O
I/O
87
SDO, I/O
SDO, I/O
SDO, TDO, I/O
88
I/O
I/O
I/O
89
GND
GND
GND
90
I/O
I/O
I/O
91
I/O
I/O
I/O
92
I/O
I/O
I/O
93
I/O
I/O
I/O
94
I/O
I/O
I/O
95
I/O
I/O
I/O
96
NC
I/O
I/O
97
NC
I/O
I/O
98
I/O
I/O
I/O
99
I/O
I/O
I/O
100
I/O
I/O
I/O
101
NC
NC
I/O
102
I/O
I/O
I/O
103
NC
I/O
I/O
104
I/O
I/O
I/O
105
I/O
I/O
I/O
106
GND
GND
GND
107
NC
I/O
I/O
108
NC
I/O
TCK, I/O
R ev i si o n 1 1
2- 37
Package Pin Assignments
TQ176
2- 38
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
109
LP
LP
LP
110
VCCA
VCCA
VCCA
111
GND
GND
GND
112
VCCI
VCCI
VCCI
113
VCCA
VCCA
VCCA
114
NC
I/O
I/O
115
NC
I/O
I/O
116
NC
VCCA
VCCA
117
I/O
I/O
I/O
118
I/O
I/O
I/O
119
I/O
I/O
I/O
120
I/O
I/O
I/O
121
NC
NC
I/O
122
I/O
I/O
I/O
123
I/O
I/O
I/O
124
NC
I/O
I/O
125
NC
I/O
I/O
126
NC
NC
I/O
127
I/O
I/O
I/O
128
I/O
I/O
I/O
129
I/O
I/O
I/O
130
I/O
I/O
I/O
131
I/O
I/O
I/O
132
I/O
I/O
I/O
133
GND
GND
GND
134
I/O
I/O
I/O
135
SDI, I/O
SDI, I/O
SDI, I/O
136
NC
I/O
I/O
137
I/O
I/O
WD, I/O
138
I/O
I/O
WD, I/O
139
I/O
I/O
I/O
140
NC
VCCI
VCCI
141
I/O
I/O
I/O
142
I/O
I/O
I/O
143
NC
I/O
I/O
144
NC
I/O
WD, I/O
R ev i sio n 1 1
40MX and 42MX FPGA Families
TQ176
Pin Number
A42MX09 Function
A42MX16 Function
A42MX24 Function
145
NC
NC
WD, I/O
146
I/O
I/O
I/O
147
NC
I/O
I/O
148
I/O
I/O
I/O
149
I/O
I/O
I/O
150
I/O
I/O
WD, I/O
151
NC
I/O
WD, I/O
152
PRA, I/O
PRA, I/O
PRA, I/O
153
I/O
I/O
I/O
154
CLKA, I/O
CLKA, I/O
CLKA, I/O
155
VCCA
VCCA
VCCA
156
GND
GND
GND
157
I/O
I/O
I/O
158
CLKB, I/O
CLKB, I/O
CLKB, I/O
159
I/O
I/O
I/O
160
PRB, I/O
PRB, I/O
PRB, I/O
161
NC
I/O
WD, I/O
162
I/O
I/O
WD, I/O
163
I/O
I/O
I/O
164
I/O
I/O
I/O
165
NC
NC
WD, I/O
166
NC
I/O
WD, I/O
167
I/O
I/O
I/O
168
NC
I/O
I/O
169
I/O
I/O
I/O
170
NC
VCCI
VCCI
171
I/O
I/O
WD, I/O
172
I/O
I/O
WD, I/O
173
NC
I/O
I/O
174
I/O
I/O
I/O
175
DCLK, I/O
DCLK, I/O
DCLK, I/O
176
I/O
I/O
I/O
R ev i si o n 1 1
2- 39
Package Pin Assignments
CQ208
208207206205204203202201200
164163162161160159158157
Pin #1
Index
1
2
3
4
5
6
7
8
156
155
154
153
152
151
150
149
A42MX36
208-Pin
CQFP
44
45
46
47
48
49
50
51
52
113
112
111
110
109
108
107
106
105
53 54 55 56 57 58 59 60 61
2- 40
97 98 99 100101102103104
R ev i sio n 1 1
40MX and 42MX FPGA Families
CQ208
CQ208
CQ208
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
1
GND
37
I/O
73
I/O
2
VCCA
38
I/O
74
I/O
3
MODE
39
I/O
75
I/O
4
I/O
40
I/O
76
I/O
5
I/O
41
I/O
77
I/O
6
I/O
42
I/O
78
GND
7
I/O
43
I/O
79
VCCA
8
I/O
44
I/O
80
VCCI
9
I/O
45
I/O
81
I/O
10
I/O
46
I/O
82
I/O
11
I/O
47
I/O
83
I/O
12
I/O
48
I/O
84
I/O
13
I/O
49
I/O
85
WD, I/O
14
I/O
50
I/O
86
WD, I/O
15
I/O
51
I/O
87
I/O
16
I/O
52
GND
88
I/O
17
VCCA
53
GND
89
I/O
18
I/O
54
TMS, I/O
90
I/O
19
I/O
55
TDI, I/O
91
QCLKB, I/O
20
I/O
56
I/O
92
I/O
21
I/O
57
WD, I/O
93
WD, I/O
22
GND
58
WD, I/O
94
WD, I/O
23
I/O
59
I/O
95
I/O
24
I/O
60
VCCI
96
I/O
25
I/O
61
I/O
97
I/O
26
I/O
62
I/O
98
VCCI
27
GND
63
I/O
99
I/O
28
VCCI
64
I/O
100
WD, I/O
29
VCCA
65
QCLKA, I/O
101
WD, I/O
30
I/O
66
WD, I/O
102
I/O
31
I/O
67
WD, I/O
103
TDO, I/O
32
VCCA
68
I/O
104
I/O
33
I/O
69
I/O
105
GND
34
I/O
70
WD, I/O
106
VCCA
35
I/O
71
WD, I/O
107
I/O
36
I/O
72
I/O
108
I/O
R ev i si o n 1 1
2- 41
Package Pin Assignments
CQ208
CQ208
CQ208
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
109
I/O
145
I/O
181
I/O
110
I/O
146
I/O
182
VCCI
111
I/O
147
I/O
183
VCCA
112
I/O
148
I/O
184
GND
113
I/O
149
I/O
185
I/O
114
I/O
150
GND
186
CLKB, I/O
115
I/O
151
I/O
187
I/O
116
I/O
152
I/O
188
PRB, I/O
117
I/O
153
I/O
189
I/O
118
I/O
154
I/O
190
WD, I/O
119
I/O
155
I/O
191
WD, I/O
120
I/O
156
I/O
192
I/O
121
I/O
157
GND
193
I/O
122
I/O
158
I/O
194
WD, I/O
123
I/O
159
SDI, I/O
195
WD, I/O
124
I/O
160
I/O
196
QCLKC, I/O
125
I/O
161
WD, I/O
197
I/O
126
GND
162
WD, I/O
198
I/O
127
I/O
163
I/O
199
I/O
128
TCK, I/O
164
VCCI
200
I/O
129
LP
165
I/O
201
I/O
130
VCCA
166
I/O
202
VCCI
131
GND
167
I/O
203
WD, I/O
132
VCCI
168
WD, I/O
204
WD, I/O
133
VCCA
169
WD, I/O
205
I/O
134
I/O
170
I/O
206
I/O
135
I/O
171
QCLKD, I/O
207
DCLK, I/O
136
VCCA
172
I/O
208
I/O
137
I/O
173
I/O
138
I/O
174
I/O
139
I/O
175
I/O
140
I/O
176
WD, I/O
141
I/O
177
WD, I/O
142
I/O
178
PRA, I/O
143
I/O
179
I/O
144
I/O
180
CLKA, I/O
2- 42
R ev i sio n 1 1
40MX and 42MX FPGA Families
CQ256
256255254253252251250249248
200199198197196195194193
Pin #1
Index
1
2
3
4
5
6
7
8
192
191
190
189
188
187
186
185
A42MX36
256-Pin
CQFP
56
57
58
59
60
61
62
63
64
137
136
135
134
133
132
131
130
129
65 66 67 68 69 70 71 72 73
121122123124125126127128
R ev i si o n 1 1
2- 43
Package Pin Assignments
CQ256
CQ256
CQ256
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
1
NC
37
I/O
73
I/O
2
GND
38
I/O
74
I/O
3
I/O
39
I/O
75
I/O
4
I/O
40
I/O
76
WD, I/O
5
I/O
41
I/O
77
GND
6
I/O
42
I/O
78
WD, I/O
7
I/O
43
I/O
79
I/O
8
I/O
44
I/O
80
QCLKB, I/O
9
I/O
45
I/O
81
I/O
10
GND
46
I/O
82
I/O
11
I/O
47
I/O
83
I/O
12
I/O
48
GND
84
I/O
13
I/O
49
I/O
85
I/O
14
I/O
50
I/O
86
I/O
15
I/O
51
I/O
87
WD, I/O
16
I/O
52
I/O
88
WD, I/O
17
I/O
53
I/O
89
I/O
18
I/O
54
I/O
90
I/O
19
I/O
55
I/O
91
I/O
20
I/O
56
I/O
92
I/O
21
I/O
57
I/O
93
I/O
22
I/O
58
I/O
94
I/O
23
I/O
59
I/O
95
VCCI
24
I/O
60
VCCA
96
VCCA
25
I/O
61
GND
97
GND
26
VCCA
62
GND
98
GND
27
I/O
63
NC
99
I/O
28
I/O
64
NC
100
I/O
29
VCCA
65
NC
101
I/O
30
VCCI
66
I/O
102
I/O
31
GND
67
SDO, TDO, I/O
103
I/O
32
VCCA
68
I/O
104
I/O
33
LP
69
WD, I/O
105
WD, I/O
34
TCK, I/O
70
WD, I/O
106
WD, I/O
35
I/O
71
I/O
107
I/O
36
GND
72
VCCI
108
I/O
2- 44
R ev i sio n 1 1
40MX and 42MX FPGA Families
CQ256
CQ256
CQ256
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
109
WD, I/O
145
I/O
181
I/O
110
WD, I/O
146
I/O
182
I/O
111
I/O
147
I/O
183
I/O
112
QCLKA, I/O
148
I/O
184
I/O
113
I/O
149
I/O
185
I/O
114
GND
150
I/O
186
I/O
115
I/O
151
I/O
187
I/O
116
I/O
152
I/O
188
MODE
117
I/O
153
I/O
189
VCCA
118
I/O
154
I/O
190
GND
119
VCCI
155
VCCA
191
NC
120
I/O
156
I/O
192
NC
121
WD, I/O
157
I/O
193
NC
122
WD, I/O
158
VCCA
194
I/O
123
I/O
159
VCCI
195
DCLK, I/O
124
I/O
160
GND
196
I/O
125
I/O
161
I/O
197
I/O
126
I/O
162
I/O
198
I/O
127
GND
163
I/O
199
WD, I/O
128
NC
164
I/O
200
WD, I/O
129
NC
165
GND
201
VCCI
130
NC
166
I/O
202
I/O
131
GND
167
I/O
203
I/O
132
I/O
168
I/O
204
I/O
133
I/O
169
I/O
205
I/O
134
I/O
170
VCCA
206
GND
135
I/O
171
I/O
207
I/O
136
I/O
172
I/O
208
I/O
137
I/O
173
I/O
209
QCLKC, I/O
138
I/O
174
I/O
210
I/O
139
GND
175
I/O
211
WD, I/O
140
I/O
176
I/O
212
WD, I/O
141
I/O
177
I/O
213
I/O
142
I/O
178
I/O
214
I/O
143
I/O
179
I/O
215
WD, I/O
144
I/O
180
GND
216
WD, I/O
R ev i si o n 1 1
2- 45
Package Pin Assignments
CQ256
CQ256
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
217
I/O
253
SDI, I/O
218
PRB, I/O
254
I/O
219
I/O
255
GND
220
CLKB, I/O
256
NC
221
I/O
222
GND
223
GND
224
VCCA
225
VCCI
226
I/O
227
CLKA, I/O
228
I/O
229
PRA, I/O
230
I/O
231
I/O
232
WD, I/O
233
WD, I/O
234
I/O
235
I/O
236
I/O
237
I/O
238
I/O
239
I/O
240
QCLKD, I/O
241
I/O
242
WD, I/O
243
GND
244
WD, I/O
245
I/O
246
I/O
247
I/O
248
VCCI
249
I/O
250
WD, I/O
251
WD, I/O
252
I/O
2- 46
R ev i sio n 1 1
40MX and 42MX FPGA Families
BG272
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
A
B
C
D
E
F
G
272-Pin PBGA
H
J
K
L
M
N
P
R
T
U
V
W
Y
R ev i si o n 1 1
2- 47
Package Pin Assignments
BG272
BG272
BG272
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
A1
GND
B17
WD, I/O
D13
I/O
A2
GND
B18
I/O
D14
VCCI
A3
I/O
B19
GND
D15
I/O
A4
WD, I/O
B20
GND
D16
VCCA
A5
I/O
C1
I/O
D17
GND
A6
I/O
C2
MODE
D18
I/O
A7
WD, I/O
C3
GND
D19
I/O
A8
WD, I/O
C4
I/O
D20
I/O
A9
I/O
C5
WD, I/O
E1
I/O
A10
I/O
C6
I/O
E2
I/O
A11
CLKA
C7
QCLKC, I/O
E3
I/O
A12
I/O
C8
I/O
E4
VCCA
A13
I/O
C9
I/O
E17
VCCI
A14
I/O
C10
CLKB
E18
I/O
A15
I/O
C11
PRA, I/O
E19
I/O
A16
WD, I/O
C12
WD, I/O
E20
I/O
A17
I/O
C13
I/O
F1
I/O
A18
I/O
C14
QCLKD, I/O
F2
I/O
A19
GND
C15
I/O
F3
I/O
A20
GND
C16
WD, I/O
F4
VCCI
B1
GND
C17
SDI, I/O
F17
I/O
B2
GND
C18
I/O
F18
I/O
B3
DCLK, I/O
C19
I/O
F19
I/O
B4
I/O
C20
I/O
F20
I/O
B5
I/O
D1
I/O
G1
I/O
B6
I/O
D2
I/O
G2
I/O
B7
WD, I/O
D3
I/O
G3
I/O
B8
I/O
D4
I/O
G4
VCCI
B9
PRB, I/O
D5
VCCI
G17
VCCI
B10
I/O
D6
I/O
G18
I/O
B11
I/O
D7
I/O
G19
I/O
B12
WD, I/O
D8
VCCA
G20
I/O
B13
I/O
D9
WD, I/O
H1
I/O
B14
I/O
D10
VCCI
H2
I/O
B15
WD, I/O
D11
I/O
H3
I/O
B16
I/O
D12
VCCI
H4
VCCA
2- 48
R ev i sio n 1 1
40MX and 42MX FPGA Families
BG272
BG272
BG272
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
H17
I/O
L17
VCCI
R17
VCCI
H18
I/O
L18
I/O
R18
I/O
H19
I/O
L19
I/O
R19
I/O
H20
I/O
L20
TCK, I/O
R20
I/O
J1
I/O
M1
I/O
T1
I/O
J2
I/O
M2
I/O
T2
I/O
J3
I/O
M3
I/O
T3
I/O
J4
VCCI
M4
VCCI
T4
I/O
J9
GND
M9
GND
T17
VCCA
J10
GND
M10
GND
T18
I/O
J11
GND
M11
GND
T19
I/O
J12
GND
M12
GND
T20
I/O
J17
VCCA
M17
I/O
U1
I/O
J18
I/O
M18
I/O
U2
I/O
J19
I/O
M19
I/O
U3
I/O
J20
I/O
M20
I/O
U4
I/O
K1
I/O
N1
I/O
U5
VCCI
K2
I/O
N2
I/O
U6
WD, I/O
K3
I/O
N3
I/O
U7
I/O
K4
VCCI
N4
VCCI
U8
I/O
K9
GND
N17
VCCI
U9
WD, I/O
K10
GND
N18
I/O
U10
VCCA
K11
GND
N19
I/O
U11
VCCI
K12
GND
N20
I/O
U12
I/O
K17
I/O
P1
I/O
U13
I/O
K18
VCCA
P2
I/O
U14
QCLKB, I/O
K19
VCCA
P3
I/O
U15
I/O
K20
LP
P4
VCCA
U16
VCCI
L1
I/O
P17
I/O
U17
I/O
L2
I/O
P18
I/O
U18
GND
L3
VCCA
P19
I/O
U19
I/O
L4
VCCA
P20
I/O
U20
I/O
L9
GND
R1
I/O
V1
I/O
L10
GND
R2
I/O
V2
I/O
L11
GND
R3
I/O
V3
GND
L12
GND
R4
VCCI
V4
GND
R ev i si o n 1 1
2- 49
Package Pin Assignments
BG272
BG272
Pin Number
A42MX36 Function
Pin Number
A42MX36 Function
V5
I/O
Y1
GND
V6
I/O
Y2
GND
V7
I/O
Y3
I/O
V8
WD, I/O
Y4
TDI, I/O
V9
I/O
Y5
WD, I/O
V10
I/O
Y6
I/O
V11
I/O
Y7
QCLKA, I/O
V12
I/O
Y8
I/O
V13
WD, I/O
Y9
I/O
V14
I/O
Y10
I/O
V15
WD, I/O
Y11
I/O
V16
I/O
Y12
I/O
V17
I/O
Y13
I/O
V18
SDO, TDO, I/O
Y14
I/O
V19
I/O
Y15
I/O
V20
I/O
Y16
I/O
W1
GND
Y17
I/O
W2
GND
Y18
WD, I/O
W3
I/O
Y19
GND
W4
TMS, I/O
Y20
GND
W5
I/O
W6
I/O
W7
I/O
W8
WD, I/O
W9
WD, I/O
W10
I/O
W11
I/O
W12
I/O
W13
WD, I/O
W14
I/O
W15
I/O
W16
WD, I/O
W17
I/O
W18
WD, I/O
W19
GND
W20
GND
2- 50
R ev i sio n 1 1
3 – Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Revision
Revision 11
(May 2012)
Revision 10
(April 2012)
Revision 9
(v6.1, April 2009)
v6.0
(January 2004)
Changes
Page
The FuseLock logo and accompanying text was removed from the "User Security"
section. This marking is no longer used on Microsemi devices (PCN 0915).
1-8
The "Development Tool Support" section was updated (SAR 38512).
1-16
"Ordering Information" was updated to include lead-free package ordering codes
(SAR 21968).
ii
The "User Security" section was revised to clarify that although no existing security
measures can give an absolute guarantee, Microsemi FPGAs implement the best
security available in the industry (SAR 34673).
1-8
The "Transient Current" section is new (SAR 36930).
1-9
Package names were revised according to standards established in Package
Mechanical Drawings (SAR 34774).
2-1
In Table 1-14 • Absolute Maximum Ratings*, the limits in VI were changed from -0.5 to
VCCI + 0.5 to -0.5 to VCCA + 0.5.
1-21
In Table 1-16 • Mixed 5.0V/3.3V Electrical Specifications, VOH was changed from 3.7
to 2.4 for the min in industrial and military. VIH had VCCI and that was changed to
VCCA.
1-22
The "Ease of Integration" section was updated.
1-i
The "Temperature Grade Offerings" section is new.
1-iii
The "Speed Grade Offerings" section is new.
1-iii
The "General Description" section was updated.
1-1
The "MultiPlex I/O Modules" section was updated.
1-7
The "User Security" section was updated.
1-8
Table 1-1 • Voltage Support of MX Devices was updated.
1-9
The "Power Dissipation" section was updated.
1-10
The "Static Power Component" section was updated.
1-10
The "Equivalent Capacitance" section was updated.
1-10
Figure 1-12 • Silicon Explorer II Setup with 42MX was updated.
1-12
Table 1-4 • Supported BST Public Instructions was updated.
1-14
Figure 1-13 • 42MX IEEE 1149.1 Boundary Scan Circuitry was updated.
1-14
Table 1-5 • Boundary Scan Pin Configuration and Functionality was updated.
1-15
The "Development Tool Support" section was updated.
1-16
R ev i si o n 1 1
3 -1
Datasheet Information
Revision
v6.0
(continued)
v5.1
v5.0
Changes
The Table 1-7 • Absolute Maximum Ratings for 42MX Devices* and the Table 1-6 •
Absolute Maximum Ratings for 40MX Devices* were updated.
1-16
The Table 1-9 • 5V TTL Electrical Specifications was updated.
1-18
The Table 1-13 • 3.3V LVTTL Electrical Specifications was updated.
1-20
In the "Mixed 5.0V/3.3V Electrical Specifications" section, Table 1-14 • Absolute
Maximum Ratings*, Table 1-15 • Recommended Operating Conditions, and
Table 1-16 • Mixed 5.0V/3.3V Electrical Specifications were updated.
1-21
Table 1-17 • DC Specification (5.0 V PCI Signaling)1 was updated.
1-23
Table 1-19 • DC Specification (3.3 V PCI Signaling)1 was updated.
1-24
The "Junction Temperature (TJ)" section, "Package Thermal Characteristics" section,
and the tables were updated.
1-26
Figure 1-16 • 40MX Timing Model* was updated.
1-27
Figure 1-18 • 42MX Timing Model (Logic Functions Using Quadrant Clocks) was
updated.
1-28
Figure 1-19 • 42MX Timing Model (SRAM Functions) was updated.
1-29
Figure 1-26 • Output Buffer Latches was updated.
1-32
Table 1-22 • 42MX Temperature and Voltage Derating Factors is new.
1-36
Table 1-23 • 40MX Temperature and Voltage Derating Factors is new.
1-36
The "Pin Descriptions" section was updated.
1-83
In the "PQ100" table, Pin 64 (42MX09 and 42MX16) has changed to LP.
2-10
In the "PQ160" table, Pin 61 (42MX09, 42MX16, and 42MX64) has changed to LP.
2-14
In the "PQ208" table, the following pins changed:
Pin 129 (42MX09, 42MX16, and 42MX64) has changed to LP.
Pin 198 (42MX09) has changed to I/O.
2-20
The n the "PQ240" table, Pin 91 (42MX36) has changed to LP.
2-27
In the "VQ100" table, Pin 62 (42MX09 and 42MX16) has changed to LP.
2-33
In the "TQ176" table, Pin 109 (42MX09 and 42MX16) has changed to LP.
2-35
In the "BG272" table, Pin K20 (42MX36) has changed to LP.
2-48
The "Low Power Mode" section was updated.
1-9
Footnote 8 in Table 1-9 • 5V TTL Electrical Specifications was updated.
1-18
Footnote 8 in Table 1-13 • 3.3V LVTTL Electrical Specifications was updated.
1-20
Because the changes in this data sheet are extensive and technical in nature, this
should be viewed as a new document. Please read it as you would a datasheet that is
published for the first time.
ALL
Note that the “Package Characteristics and Mechanical Drawings” section has been
eliminated from the datasheet. The mechanical drawings are now contained in a
separate document, Package Mechanical Drawings, available on the Microsemi SoC
Products Group website.
3- 2
Page
R ev isio n 1 1
40MX and 42MX FPGA Families
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has
been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and
"Datasheet Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general
product information. This brief gives an overview of specific device and family information.
Advance
This datasheet version contains initial estimated information based on simulation, other products,
devices, or speed grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the
general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more
detailed information and for specifications that do not differ between the two families.
R ev i si o n 1 1
3 -3
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
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5172136-11/5.12