Hanbit HMF2M32M4VGL-70 Flash-rom module 8mbyte (2mx32bit), 72pin-simm, 3.3v design Datasheet

HANBit
HMF2M32M4VGL
Flash-ROM Module 8MByte (2Mx32Bit), 72Pin-SIMM, 3.3V Design
Part No. HMF2M32M4VGL
GENERAL DESCRIPTION
The HMF2M32M4VGL is a high-speed flash read only memory (FROM) module containing 2,097,152 words organized in a
x32bit configuration. The module consists of four 2M x 8bit FROM mounted on a 72 -pin, single-sided, FR4-printed circuit
board.
Commands are written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the
device is similar to reading from 12.0V flash or EPROM devices.
Four chip enable inputs, (/WE0, /WE1, /WE2, /WE3) are used to enable the module’s 8 bits independently. Output enable
(/OE) and write enable (/WE) can set the memory input and output.
When FROM module is disable condition the module is becoming power standby mode, system designer can get low -power
design. All module components may be powered from a single + 3.3V DC power supply and all inputs and outputs are TTLcompatible.
PIN ASSIGNMENT
FEATURES
w Access time : 70, 80, 90, 120ns
PIN
Symbol
PIN
Symbol
PIN
Symbol
w High-density 8MByte design
1
Vss
25
DQ17
49
/BANKE0
w High-reliability, low-power design
2
NC
26
DQ18
50
A3
w Single + 3.3V ± 0.3V power supply
3
DQ0
27
DQ19
51
A4
w Easy memory expansion
4
DQ1
28
DQ20
52
A5
w All inputs and outputs are TTL-compatible
5
DQ2
29
DQ21
53
A6
6
DQ3
30
Vcc
54
A7
7
DQ4
31
DQ22
55
A8
32
DQ23
56
A9
w FR4-PCB design
w Low profile 72-pin SIMM
8
DQ5
w Minimum 1,000,000 write/erase cycle
9
DQ6
33
/WE2
57
A10
w Sectors erase architecture
10
Vcc
34
NC
58
A11
w Sector group protection
11
DQ7
35
DQ24
59
Vcc
w Temporary sector group unprotection
12
/WE0
36
DQ25
60
A12
13
/RY_BY
37
DQ26
61
A13
14
DQ8
38
DQ27
62
A14
15
DQ9
39
Vss
63
A15
16
DQ10
40
DQ28
64
A16
OPTIONS
MARKING
w Timing
70ns access
-70
17
DQ11
41
DQ29
65
A17
80ns access
-80
18
DQ12
42
DQ30
66
A18
90ns access
-90
19
DQ13
43
DQ31
67
A19
120ns access
-120
20
DQ14
44
/WE3
68
A20
21
DQ15
45
NC
69
A0
22
/WE1
46
/RESET
70
A1
23
NC
47
A2
71
NC
24
DQ16
48
/OE
72
Vss
w Packages
72-pin SIMM
URL : www.hbe.co.kr
REV,02(August,2002)
M
1
HANBit Electronics Co., Ltd.
HANBit
HMF2M32M4VGL
FUNCTIONAL BLOCK DIAGRAM
32
DQ0 - DQ31
20
A0 – A19
A0-19
DQ 0-7
/WE
/WE0
U1
/OE
/CE
RY-BY
/Reset
A0-20
DQ 8-15
/WE
/WE1
U2
/OE
/CE
RY-BY
/Reset
A0-20
DQ16-23
/WE2
/WE
U3
/OE
/CE
RY-BY
/Reset
A0-20
DQ24-31
/WE3
/WE
/OE
/OE
/BANK-E0
/CE
RY-BY
/RY_BY
/Reset
/Reset
URL : www.hbe.co.kr
REV,02(August,2002)
U4
2
HANBit Electronics Co., Ltd.
HANBit
HMF2M32M4VGL
TRUTH TABLE
MODE
/OE
/CE
/WE
/RESET
DQ ( /BYTE=L )
POWER
STANDBY
X
H
X
Vcc±0.3V
HIGH-Z
STANDBY
NOT SELECTED
H
L
H
H
HIGH-Z
ACTIVE
READ
L
L
H
H
DOUT
ACTIVE
WRITE or ERASE
X
L
L
H
DIN
ACTIVE
NOTE: X means don’t care
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN,OUT
-0.5V to Vcc+0.5V
Voltage with respect to ground Vcc
VCC
-0.5V to +4.0V
Storage Temperature
TSTG
-65oC to +150oC
Voltage with respect to ground all other pins
Operating Temperature
TA
-55oC to +125 oC
w Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device .
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
Vcc for ± 10% device Supply Voltages
Vcc
2.7V
Ground
VSS
0
TYP.
MAX
3.6V
0
0
DC AND OPERATING CHARACTERISTICS ( 0oC ≤ TA ≤ 70 oC )
PARAMETER
TEST CONDITIONS
SYMBO
L
MIN
TYP
MAX
UNI
T
Input Load Current
Vcc=Vcc max, V IN= Vss to Vcc
IL1
±1.0
µA
A9 Input Loda Current
Vcc=Vcc max, ; A9=12.5 V
IL1T
35
µA
Output Leakage Current
Vcc=Vcc max, V OUT= Vss to Vcc
IL0
±1.0
µA
/CE= VIL, /OE= VIH,
5MHz
Byte Mode
1MHz
Vcc Active Read Current (1)
9
16
2
4
ICC1
/CE= VIL, /OE= VIH,
5MHz
9
16
Word Mode
1MHz
2
4
µA
Vcc Active Write Current
/CE = VIL, /OE=VIH
ICC2
20
30
mA
/CE, /RESET=Vcc±0.3V
ICC3
0.2
5
mA
(Note2,3,4)
Vcc Standby Current(Note2)
URL : www.hbe.co.kr
REV,02(August,2002)
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HANBit Electronics Co., Ltd.
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HMF2M32M4VGL
Vcc Standby Current During
/RESET=Vss±0.3V
ICC4
0.2
5
mA
VCC5
0.2
5
V
-0.5
0.8
V
0.7×Vc
Vcc+0
Reset(Note2)
Automatic Sleep Mode(Note2,5)
VIH= Vcc ±0.3V;
VIL= Vss ±0.3V;
Input Low Voltage
VIL
Input High Voltage
VIH
V
.3
c
Voltage for Autoselect and
VCC = 3.3V
VID
IOL = 4.0mA, Vcc =Vcc min
VOL
11.5
12.5
V
0.45
V
Temporary Sector Unprotect
Output Low Voltage
0.85×Vc
IOH = -2.0mA, Vcc =Vcc min
V
Output High Voltage
c
IOH = -100µA, Vcc =Vcc min
Vcc-0.4
Low Vcc Lock-Out Voltage(Note
VLKO
2.3
2.5
V
4)
Notes
1.
The Icc Current listed is typically less than 2 ma/MHz,with /OE at VIH. Typical Vcc is 3.0V.
2.
Maximum Icc Specifications are tested with Vcc=Vccmax.
3.
Icc active while Embedded Erase of Embedded Program is in progress .
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
UNIT
MIN.
Sector Erase Time
-
Chip Erase Time
TYP.
MAX.
0.7
15
25
COMMENTS
sec
Excludes 00H programming
prior to erasure
sec
Byte Programming Time
-
9
300
µs
Chip Programming Time
-
18
54
sec
Excludes system-level
overhead
TSOP CAPACITANCE
PARAMETER
SYMBOL
CIN
PARAMETER
DESCRIPTION
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
TEST SETUP
MIN
MAX
UNIT
VIN = 0
6
7.5
pF
VOUT = 0
8.5
12
pF
VIN = 0
7.5
9
pF
o
Notes : Test conditions TA = 25 C, f=1.0 MHz.
URL : www.hbe.co.kr
REV,02(August,2002)
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HMF2M32M4VGL
AC CHARACTERISTICS
u Read Only Operations Characteristics
PARAMETER
SYMBOLS
Speed Options
DESCRIPTION
TEST SETUP
UNIT
JEDEC STANDARD
tAVAV
tRC
Read Cycle Time (Note 1)
-70R
-80
-90
-120
Min
70
80
90
120
ns
Max
70
80
90
120
ns
Max
70
80
90
120
ns
tAVQV
tACC
Address to Output Delay
/CE = V IL
/OE = VIL
tELQV
tCE
Chip Enable to Output Delay
/OE = VIL
tGLQV
tOE
Chip Enable to Output Delay
Max
30
30
35
35
ns
tEHQZ
tDF
Chip Enable to Output High-Z
Max
25
25
30
30
ns
tGHQZ
tDF
Output Enable to Output High-Z
Max
25
25
30
30
ns
Read
Min
0
Hold Time(Note 1)
Min
10
/Data Polling
Output Hold Time From Addresses,
/CE or /OE, Whichever Occurs First
Min
0
Output Enable
ns
Toggle and
tAXQX
tQH
Notes :
1. Not 100% tested.
2. See Figure 5 and Table 10 for test specifications.
ns
TEST SPECIFICATIONS
TEST CONDITION
70R, 80
Output load
90, 120
UNIT
100
pF
1TTL gate
Output load capacitance,CL (Including jig capacitance)
30
Input rise and fall times
5
ns
0.0-3.0
V
Input timing measurement reference levels
1.5
V
Output timing measurement reference levels
1.5
V
Input pulse levels
3.3V
2.7kΩ
IN3064
or Equivalent
Device
Under
Test
CL
6.2kΩ
Diodes = IN3064
or Equivalent
Note : CL = 100pF including jig capacitance
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REV,02(August,2002)
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HMF2M32M4VGL
u Erase/Program Operations
PARAMETER SYMBOLS
Speed Options
DESCRIPTION
UNIT
JEDEC
STANDARD
tAVAV
tWC
Write Cycle Time
Min
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
45
45
50
ns
tDVWH
tDS
Data Setup Time
Min
35
35
45
50
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHWL
tGHWL
Read Recover Time Before Write
Min
0
ns
tELWL
tCS
/CE Setup Time
Min
0
ns
tWHEH
tCH
/CE Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
30
tWHWH1
tWHWH1
tWHWH2
70R
80
90
120
70
80
90
120
0
35
35
ns
ns
35
50
ns
ns
Byte Programming
Byte
Typ
9
Operation
Word
Typ
11
Sector Erase Operation (Note1)
Typ
0.7
sec
tVCS
Vcc set up time
Min
50
µs
tRB
Recovery Time from RY//BY
Min
0
ns
Min
90
ns
tWHWH2
µs
Program/Erase Valid to RY//BY
tBUSY
Delay
Notes :
1.
Not 100% tested.
2.
See the “Erase and Programming Performance ” section for more information.
URL : www.hbe.co.kr
REV,02(August,2002)
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HMF2M32M4VGL
u Erase/Program Operations
Alternate /CE Controlled Writes
PARAMETER SYMBOLS
Speed Options
DESCRIPTION
UNIT
JEDEC
STANDARD
tAVAV
tWC
Write Cycle Time
Min
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
45
45
50
ns
tDVEH
tDS
Data Setup Time
Min
35
35
45
50
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recover Time Before Write
Min
0
ns
tWLEL
tWS
/WE Setup Time
Min
0
ns
tEHEH
tWH
/WE Hold Time
Min
0
ns
tELEH
tCP
/CE Pulse Width
Min
TEHEL
tCPH
/CE Pulse Width High
Min
30
ns
tWHWH1
tWHWH1
µs
tWHWH2
tWHWH2
-70R
-80
-90
120
70
80
90
120
0
35
35
Byte
Typ
9
Operation
Word
Typ
11
Typ
0.7
Sector Erase Operation
ns
35
Byte Programming
50
Notes :
1.
Not 100% tested.
2.
See the “Erase and Programming Performance ”section for more information.
URL : www.hbe.co.kr
REV,02(August,2002)
7
ns
HANBit Electronics Co., Ltd.
ns
sec
HANBit
HMF2M32M4VGL
u READ OPERATIONS TIMING
u RESET TIMING
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REV,02(August,2002)
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HANBit
HMF2M32M4VGL
u PROGRAM OPERATIONS TIMING
u CHIP/SECTOR ERASE OPERATION TIMINGS
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REV,02(August,2002)
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HANBit
HMF2M32M4VGL
u DATA# POLLING TIMES(DURING EMBEDDED ALGORITHMS)
u TOGGLE# BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
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REV,02(August,2002)
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HMF2M32M4VGL
u SECTOR PROTECT UNPROTECT TIMEING DIAGRAM
u ALTERNATE CE# CONTROLLED WRITE OPERATING TIMINGS
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REV,02(August,2002)
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HMF2M32M4VGL
PACKAGE DIMENSIONS
2.54 mm
0.25 mm MAX
MIN
1.27±0.08 mm
Gold: 1.04±0.10 mm
Solder: 0.914±0.10 mm
1.27
(Solder & Gold Plating)
ORDERING INFORMATION
Part Number
Density
Org.
Package
HMF2M32M4VGL-70
8MByte
2Mx 32Bit
72Pin -SIMM
HMF2M32M4VGL-80
8MByte
2Mx 32Bit
HMF2M32M4VGL-90
8MByte
HMF2M32M4VGL-120
8MByte
URL : www.hbe.co.kr
REV,02(August,2002)
Component
Vcc
SPEED
4EA
3.3V
70ns
72Pin -SIMM
4EA
3.3V
80ns
2Mx 32Bit
72Pin -SIMM
4EA
3.3V
90ns
2Mx 32Bit
72Pin -SIMM
4EA
3.3V
120ns
12
Number
HANBit Electronics Co., Ltd.
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