FEDL610Q428-04 Issue Date: May.15, 2015 ML610Q428/ML610Q429 8-bit Microcontroller with a Built-in LCD driver GENERAL DESCRIPTION This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask ROM and is most suitable for battery-driven applications. The on-chip debug function that is installed enables program debugging and programming. FEATURES • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system: 16-bit instructions − Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − On-Chip debug function − Minimum instruction execution time 30.5 µs (@32.768 kHz system clock) 0.24 4µs (@4.096 MHz system clock) • Internal memory − Internal 48KByte Flash ROM (24K×16 bits) (including unusable 1KByte TEST area) − Internal 3KByte Data RAM (3072×8 bits), 1KByte Display Allocation RAM (1024 x 8bit) − Internal 192-byte RAM for display • Interrupt controller − 2 non-maskable interrupt sources (Internal source: 1, External source: 1) − 27 maskable interrupt sources (Internal sources: 19, External sources: 8) • Time base counter − Low-speed time base counter ×1 channel Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) − High-speed time base counter ×1 channel • Watchdog timer − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timers − 8 bits × 2 channels (16-bit configuration available) • 1 kHz timer − 10 Hz/1 Hz interrupt function 1/34 FEDL610Q428-04 ML610Q428/ML610Q429 • PWM − Resolution 16 bits × 3 channel • Synchronous serial port − Master/slave selectable − LSB first/MSB first selectable − 8-bit length/16-bit length selectable − Timer interrupt is used as a serial clock and selection is possible • UART − TXD/RXD × 1 channel − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • I2C bus interface − Master function only − Fast mode (400 kbps@4MHｚ), standard mode (100 kbps@4MHｚ, 50kbps@500kHz) • Melody driver − Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz) − Tone length: 63 types − Tempo: 15 types − Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) • RC oscillation type A/D converter − 24-bit counter − Time division × 2 channels • Successive approximation type A/D converter − 12-bit A/D converter − Input × 2 channels • General-purpose ports − Non-maskable interrupt input port × 1 channel − Input-only port × 10 channels (including secondary functions) − Output-only port × 3 channels (including secondary functions) − Input/output port ML610Q428: 14 channels (including secondary functions) ML610Q429: 20 channels (including secondary functions) • LCD driver − Dot matrix can be supported. ML610Q428: 1392 dots max. (58 seg × 24 com), 1/1 to 1/24 duty ML610Q429: 512 dots max. (64 seg × 8 com) , 1/1 to 1/8 duty − 1/3 or 1/4 bias (built-in bias generation circuit) − Frame frequency selecable (approx. 32Hz, 64 Hz, 73 Hz, 85 Hz, and 102 Hz) − Bias voltage multiplying clock selectable (8 types) − Contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps) − LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable − Programmable display allocation function (available only when 1/1~1/8 duty is selected) 2/34 FEDL610Q428-04 ML610Q428/ML610Q429 • Reset − Reset through the RESET_N pin − Power-on reset generation when powered on − Reset when oscillation stop of the low-speed clock is detected − Reset by the watchdog timer (WDT) overflow • Power supply voltage detect function − Judgment voltages: One of 16 levels − Judgment accuracy: ±2% (Typ.) • Clock − Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock) Crystal oscillation (32.768 kHz) − High-speed clock: Built-in RC oscillation (2M/500kHz) Built-in PLL oscillation (8.192 MHz ±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock − Selection of high-speed clock mode by software: Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock • Power management − HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). − STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) − Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) − Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. • Guaranteed operating range − Operating temperature: −20°C to 70°C − Operating voltage: VDD = 1.1V to 3.6V 3/34 FEDL610Q428-04 ML610Q428/ML610Q429 • Product name – Supported Function The lien up to the ML610Q428and ML610Q429 is beiow. ROM type Operating temperature Product availability ML610Q428-xxxWA Flash ROM -20°C to +70°C Yes ML610Q429-xxxWA Flash ROM -20°C to +70°C Yes ROM type Operating temperature Product availability ML610Q428-xxxTB Flash ROM -20°C to +70°C Yes ML610Q429-xxxTB Flash ROM -20°C to +70°C Yes - Chip (Die) - -128-pin plastic TQFP - xxx: ROM code number (xxx of the blank product is NNN) Q:Flash ROM version WA: Chip TB: TQFP 4/34 FEDL610Q428-04 ML610Q428/ML610Q429 BLOCK DIAGRAM ML610Q428 Block Diagram Figure 1 show the block diagram of the ML610Q428. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST Instruction Decoder DSR/CSR EA PC Instruction Register Data-bus Program Memory (Flash) 48Kbyte BUS Controller INT 1 RAM 2048byte RESET & TEST Interrupt Controller INT 1 OSC VDDL VDDX INT 8 Power SSIO SCK0* SIN0* SOUT0* UART RXD0* TXD0* I2C SDA* SCL* INT 1 WDT INT 3 PWM ×3 TBC PWM0* to PWM2* INT 1 INT 1 RC-ADC ×2 VPP INT 1 LSCLK* OUTCLK* IN0* CS0* RS0* RT0* CRT0* RCM* IN1* CS1* RS1* RT1* LR SP XT0 XT1 OSC0* OSC1* ECSR1～3 ALU VDD VSS RESET_N ELR1～3 INT 1 INT 2 Melody 1kHzTC INT 5 8bit Timer ×2 Display Allocation RAM 1KByte BLD Display RAM 192Byte MD0* NMI P00 to P03 P10 to P11 GPIO P20 to P22 P30 to P35 P40 to P47 LCD Driver COM0 to COM23 LCD BIAS VL1, VL2, VL3, VL4 SEG0 to SEG57 C1, C2, C3, C4 Figure 1 ML610Q428 Block Diagram 5/34 FEDL610Q428-04 ML610Q428/ML610Q429 ML610Q429 Block Diagram Figure 2 show the block diagram of the ML610Q429. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST Instruction Decoder DSR/CSR EA PC Instruction Register Data-bus Program Memory (Flash) 48Kbyte BUS Controller INT 1 RAM 2048byte RESET & TEST Interrupt Controller INT 1 OSC VDDL VDDX INT 8 Power SSIO SCK0* SIN0* SOUT0* UART RXD0* TXD0* I2C SDA* SCL* INT 1 WDT INT 3 PWM ×3 TBC PWM0* to PWM2* INT 1 INT 1 RC-ADC ×2 VPP INT 1 LSCLK* OUTCLK* IN0* CS0* RS0* RT0* CRT0* RCM* IN1* CS1* RS1* RT1* LR SP XT0 XT1 OSC0* OSC1* ECSR1～3 ALU VDD VSS RESET_N ELR1～3 INT 1 INT 2 Melody 1kHzTC INT 9 8bit Timer ×2 Display Allocation RAM 1KByte BLD Display RAM 192Byte MD0* NMI P00 to P08 P10 to P11 GPIO P20 to P22 P30 to P35 P40 to P47 PA0 to PA5 LCD Driver COM0 to COM7 LCD BIAS VL1, VL2, VL3, VL4 SEG0 to SEG63 C1, C2, C3, C4 Figure 2 ML610Q429 Block Diagram 6/34 FEDL610Q428-04 ML610Q428/ML610Q429 PIN CONFIGURATION 96pin COM23 (NC) COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 ML610Q428 TQFP128 Pin Layout 65pin 64pin 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 97pin P20 P21 P22 P40 P41 VPP RESET_N P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 XT1 P42 P43 VL1 VL2 VL3 VL4 C1 C2 ML610Q428 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 128pin 1pin SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 33pin C3 (NC) C4 P00 P01 P02 P03 NMI VSS P10 (NC) P11 VDD COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 32pin (NC): No Connection Figure 3 ML610Q428 TQFP128 Pin Configuration 7/34 FEDL610Q428-04 ML610Q428/ML610Q429 96pin P07 (NC) P06 P05 P04 PA5 PA4 PA3 PA2 PA1 PA0 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 ML610Q429 TQFP128 Pin Layout 65pin 64pin 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 97pin P20 P21 P22 P40 P41 VPP RESET_N P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 XT1 P42 P43 VL1 VL2 VL3 VL4 C1 C2 ML610Q429 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 128pin 1pin SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 33pin C3 (NC) C4 P00 P01 P02 P03 NMI VSS P10 (NC) P11 VDD COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 32pin (NC): No Connection Figure 4 ML610Q429 TQFP128 Pin Configuration 8/34 FEDL610Q428-04 ML610Q428/ML610Q429 P20 P21 P22 P40 P41 VPP RESET_N P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 XT1 P42 P43 117 118 119 VL1 VL2 VL3 VL4 C1 C2 120 121 122 123 124 125 ZF8 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 ML610Q428 Chip Dimension 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Device Name "ZF8" Device Name "428" SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C3 C4 P00 P01 P02 P03 NMI VSS P10 P11 VDD COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 428 Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 2.99 mm × 3.11 mm 125 pins 80 µm 70 µm × 70 µm 350 µm VSS level Figure 5 ML610Q428 Chip Dimension Note: Figure 5 is an image figure of the order of PAD, and it differs from an actual image. Refer to the PAD coordinate for detailed arrangement. A chip angle can be checked by the distinguishing mark of three figures. 9/34 FEDL610Q428-04 ML610Q428/ML610Q429 P20 P21 P22 P40 P41 VPP RESET_N P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 ZF8 XT1 P42 P43 117 118 119 VL1 VL2 VL3 VL4 C1 C2 120 121 122 123 124 125 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 ML610Q429 Chip Dimension 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Device Name "ZF8" Device Name "428" SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C3 C4 P00 P01 P02 P03 NMI VSS P10 P11 VDD COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 428 Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 2.99 mm × 3.11 mm 125 pins 80 µm 70 µm × 70 µm 350 µm VSS level Figure 6 ML610Q429 Chip Dimension Note: Figure 6 is an image figure of the order of PAD, and it differs from an actual image. Refer to the PAD coordinate for detailed arrangement. A chip angle can be checked by the distinguishing mark of three figures. 10/34 FEDL610Q428-04 ML610Q428/ML610Q429 PIN LIST PAD No. Q429 Q428 Primary function Pin name Secondary function I/O Function Pin name Negative power supply 8,114 8,114 Vss pin Positive power supply 11,112 11,112 VDD pin Power supply pin for 113 113 VDDL internal logic (internally generated) Power supply pin for 115 115 VDDX low-speed oscillation (internally generated) Power supply pin for 99 99 VPP Flash ROM Power supply pin for 120 120 VL1 LCD bias (internally generated) Power supply pin for 121 121 VL2 LCD bias (internally generated) Power supply pin for 122 122 VL3 LCD bias (internally generated) Power supply pin for 123 123 VL4 LCD bias (internally generated) Capacitor connection 124 124 C1 pin for LCD bias generation Capacitor connection 125 125 C2 pin for LCD bias generation Capacitor connection 1 1 C3 pin for LCD bias generation Capacitor connection 2 2 C4 pin for LCD bias generation Input/output pin for 111 111 TEST I/O testing Reset input pin 100 100 RESET_N I Low-speed clock 116 116 XT0 I oscillation pin Low-speed clock 117 117 XT1 O oscillation pin Non-maskable interrupt 7 7 NMI I pin Input port, External 3 3 P00/EXI0 I interrupt 0 input Input port, External 4 4 P01/EXI1 I interrupt 1 input Input port, External P02/EXI2 interrupt 2, UART0 5 5 /RXD0 I receive, PWM2 /P2CK external clock input Tertiary function I/O Function Pin name I/O Function 6 6 P03/EXI3 I Input port, External interrupt 3 90 P04/EXI4 I/O Input port, External interrupt 4 91 P05/EXI5 I/O Input port, External interrupt 5 92 P06/EXI6 93 P07/EXI7 Input port, External interrupt 6 I/O Input port, External I/O 11/34 FEDL610Q428-04 ML610Q428/ML610Q429 PAD No. Q429 Q428 Primary function Pin name I/O P10 I Function interrupt 7 Input port Secondary function Pin name I/O Function OSC0 I High-speed oscillation OSC1 O High-speed oscillation 9 9 10 10 P11 I Input port 94 94 P20/LED0 O Output port 95 95 P21/LED1 O Output port 96 96 P22/LED2 O Output port 105 105 P30 I/O Input/output port 106 106 P31 I/O Input/output port 108 108 P32 I/O Input/output port 109 109 P33 I/O Input/output port 107 107 P34 I/O Input/output port 110 110 P35 I/O Input/output port 97 97 P40 I/O Input/output port 98 98 P41 I/O Input/output port SCL 118 118 P42 I/O Input/output port RXD0 119 119 P43 TXD0 101 101 P44/T02P 0CK IN1 I 102 102 P45/T13P 1CK CS1 O 103 103 P46/T46P 2CK I/O Input/output port Input/output port, Timer I/O 0/Timer 2/PWM0 external clock input Input/output port, Timer I/O 1/Timer 3/PWM1 external clock input Input/output port, I/O PWM2 external clock input RS1 O 104 1004 P47 I/O Input/output port RT1 O 84 PA0 I/O Input/output port 85 PA1 I/O Input/output port 86 PA2 I/O Input/output port 87 PA3 I/O Input/output port 88 PA4 I/O Input/output port 89 PA5 I/O Input/output port 12 12 COM0 O LCD common pin 13 13 COM1 O LCD common pin 14 14 COM2 O LCD common pin 15 15 COM3 O LCD common pin 16 16 COM4 O LCD common pin 17 17 COM5 O LCD common pin 18 18 COM6 O LCD common pin 19 19 COM7 O LCD common pin 78 COM8 O 79 COM9 O 80 COM10 81 Low-speed clock output High-speed clock OUTCLK O output MD0 O Melody output RC type ADC0 IN0 I oscillation input pin RC type ADC0 CS0 O reference capacitor connection pin RC type ADC0 RS0 O reference resistor connection pin RC type ADC0 resistor RT0 O sensor connection pin RC type ADC0 RCT0 O resistor/capacitor sensor connection pin RC type ADC RCM O oscillation monitor 2 SDA I/O I C data input/output LSCLK O Tertiary function Pin name I/O Function PWM2 O PWM2 output PWM2 O PWM2 output PWM0 O PWM0 output PWM1 O PWM1 output I SSIO data input SIN0 2 I/O I C clock input/output SCK0 I UART data input SOUT0 O SSIO data output O UART data output PWM0 O PWM0 output RC type ADC1 oscillation input pin SIN0 I SSIO0 data input SCK0 I/O SSIO0 synchronous clock SOUT0 O SSIO0 data output PWM1 O PWM1 output LCD common pin O LCD common pin COM11 O LCD common pin 82 COM12 O LCD common pin 83 COM13 O LCD common pin 84 COM14 O LCD common pin LCD common pin 85 COM15 O LCD common pin RC type ADC1 reference capacitor connection pin RC type ADC1 reference resistor connection pin RC type ADC1 resistor sensor connection pin I/O SSIO synchronous clock 12/34 FEDL610Q428-04 ML610Q428/ML610Q429 PAD No. Q429 Q428 Primary function Pin name I/O Function Secondary function Pin name I/O Function Tertiary function Pin name I/O Function LCD segment pin LCD segment pin O LCD segment pin SEG3 O LCD segment pin 24 SEG4 O LCD segment pin 25 SEG5 O LCD segment pin 26 26 SEG6 O LCD segment pin 27 27 SEG7 O LCD segment pin 28 28 SEG8 O LCD segment pin 29 29 SEG9 O LCD segment pin 30 30 SEG10 O LCD segment pin 31 31 SEG11 O LCD segment pin 32 32 SEG12 O LCD segment pin 33 33 SEG13 O LCD segment pin 34 34 SEG14 O LCD segment pin 35 35 SEG15 O LCD segment pin 36 36 SEG16 O LCD segment pin 37 37 SEG17 O LCD segment pin 38 38 SEG18 O LCD segment pin 39 39 SEG19 O LCD segment pin 40 40 SEG20 O LCD segment pin 41 41 SEG21 O LCD segment pin 42 42 SEG22 O LCD segment pin 43 43 SEG23 O LCD segment pin 44 44 SEG24 O LCD segment pin 45 45 SEG25 O LCD segment pin 46 46 SEG26 O LCD segment pin 47 47 SEG27 O LCD segment pin 48 48 SEG28 O LCD segment pin 49 49 SEG29 O LCD segment pin 50 50 SEG30 O LCD segment pin 51 51 SEG31 O LCD segment pin 52 52 SEG32 O LCD segment pin 53 53 SEG33 O LCD segment pin 54 54 SEG34 O LCD segment pin 55 55 SEG35 O LCD segment pin 56 56 SEG36 O LCD segment pin 57 57 SEG37 O LCD segment pin 58 58 SEG38 O LCD segment pin 59 59 SEG39 O LCD segment pin 60 60 SEG40 O LCD segment pin 61 61 SEG41 O LCD segment pin 62 62 SEG42 O LCD segment pin 63 63 SEG43 O LCD segment pin 64 64 SEG44 O LCD segment pin 86 COM16 O LCD common pin 87 COM17 O LCD common pin 88 COM18 O LCD common pin 89 COM19 O LCD common pin 90 COM20 O LCD common pin 91 COM21 O LCD common pin 92 COM22 O LCD common pin 93 COM23 O LCD common pin 20 20 SEG0 O 21 21 SEG1 O 22 22 SEG2 23 23 24 25 13/34 FEDL610Q428-04 ML610Q428/ML610Q429 PAD No. Q429 Q428 Primary function Pin name I/O Function Secondary function Pin name I/O Function Tertiary function Pin name I/O Function 65 65 SEG45 O LCD segment pin 66 66 SEG46 O LCD segment pin 67 67 SEG47 O LCD segment pin 68 68 SEG48 O LCD segment pin 69 69 SEG49 O LCD segment pin 70 70 SEG50 O LCD segment pin 71 71 SEG51 O LCD segment pin 72 72 SEG52 O LCD segment pin 73 73 SEG53 O LCD segment pin 74 74 SEG54 O LCD segment pin 75 75 SEG55 O LCD segment pin 76 76 SEG56 O LCD segment pin 77 77 SEG57 O LCD segment pin 78 SEG58 O LCD segment pin 79 SEG59 O LCD segment pin 80 SEG60 O LCD segment pin 81 SEG61 O LCD segment pin 82 SEG62 O LCD segment pin 83 SEG63 O LCD segment pin 14/34 FEDL610Q428-04 ML610Q428/ML610Q429 PIN DESCRIPTION Pin name I/O Description Primary/ Secondary/ Tertiary Logic — Negative — — — — Secondary Secondary — — Secondary — Secondary — Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive System Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected. XT0 I Crystal connection pin for low-speed clock. XT1 O A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL are connected across this pin and VSS as required. OSC0 I Crystal/ceramic connection pin for high-speed clock. OSC1 O A crystal or ceramic is connected to this pin (4.1 MHz max.). Capacitors CDH and CGH (see measuring circuit 1) are connected across this pin and VSS. This pin is used as the secondary function of the P10 pin(OSC0) and P11 pin(OSC1). LSCLK O Low-speed clock output pin. This pin is used as the secondary function of the P20 pin. OUTCLK O High-speed clock output pin. This pin is used as the secondary function of the P21 pin. General-purpose input port RESET_N I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P04-P07 I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. These pins are for the ML610Q429, but are not provided in the ML610Q428. P10-P11 I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose output port P20-P22 O General-purpose output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose input/output port P30-P35 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P40-P47 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. PA0-PA5 I/O General-purpose input/output port. These pins are for the ML610Q429, but are not provided in the ML610Q428. P00-P03 I 15/34 FEDL610Q428-04 ML610Q428/ML610Q429 Pin name Primary/ Secondary/ Tertiary Logic Secondary Positive Primary/Se condary Positive Secondary Positive Secondary Positive I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P41 or P45 pin. I Synchronous serial data input pin. This pin is used as the tertiary function of the P40 or P44 pin. O Synchronous serial data output pin. This pin is used as the tertiary function of the P42 or P46 pin. Tertiary — Tertiary Positive Tertiary Positive PWM0 output pin. This pin is used as the tertiary function of the P43 or P34 pin. PWM0 external clock input pin. This pin is used as the primary function of the P44 pin. PWM1 output pin. This pin is used as the tertiary function of the P47 or P35 pin. PWM1 external clock input pin. This pin is used as the primary function of the P45 pin. PWM2 output pin. This pin is used as the tertiary function of the P20 or P30 pin. PWM2 external clock input pin. This pin is used as the primary function of the P02 pin. Tertiary Positive Primary — Tertiary Positive Primary — Tertiary Positive Primary — External non-maskable interrupt input pin. An interrupt is generated on both edges. External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00-P07 pins. Primary Positive/ negative Positive/ negative External clock input pin used for Timer 0. This pin is used as the primary function of the P44 pin. External clock input pin used for Timer 1. This pin is used as the primary function of the P45 pin. Primary I/O UART TXD0 O RXD0 I Description UART data output pin. This pin is used as the secondary function of the P43 pin. UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. 2 I C bus interface 2 SDA I/O I C data input/output pin. This pin is used as the secondary function of the P40 pin. This pin has an NMOS open drain output. When using this pin as 2 a function of the I C, externally connect a pull-up resistor. 2 SCL O I C clock output pin. This pin is used as the secondary function of the P41 pin. This pin has an NMOS open drain output. When using this pin as a 2 function of the I C, externally connect a pull-up resistor. Synchronous serial (SSIO) SCK0 SIN0 SOUT0 PWM PWM0 O T0P0CK I PWM1 O T1P1CK I PWM2 O P2CK I External interrupt NMI I EXI0-7 I Primary Timer T0P0CK I T1P1CK I Melody MD0 O Melody/buzzer signal output pin. This pin is used as the secondary function of the P22 pin. LED drive LED0-2 O Nch open drain output pins to drive LED. Primary — — Secondary Positive/ negative Primary Positive/ negative 16/34 FEDL610Q428-04 ML610Q428/ML610Q429 Pin name I/O Description RC oscillation type A/D converter IN0 I Channel 0 oscillation input pin. This pin is used as the secondary function of the P30 pin. CS0 O Channel 0 reference capacitor connection pin. This pin is used as the secondary function of the P31 pin. RS0 O This pin is used as the secondary function of the P32 pin which is the reference resistor connection pin of Channel 0. RT0 O Resistor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P34 pin. CRT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P33 pin. RCM O RC oscillation monitor pin. This pin is used as the secondary function of the P35 pin. IN1 I Oscillation input pin of Channel 1. This pin is used as the secondary function of the P44 pin. CS1 O Reference capacitor connection pin of Channel 1. This pin is used as the secondary function of the P45 pin. RS1 O Reference resistor connection pin of Channel 1. This pin is used as the secondary function of the P46 pin. RT1 O Resistor sensor connection pin for measurement of Channel 1. This pin is used as the secondary function of the P47 pin. LCD drive signal COM0-7 O Common output pins. COM8-23 O Common output pins. These pins are for the ML610Q428, but are not provided in the ML610Q429. SEG0-57 O Segment output pin. SEG58-63 O Segment output pins. These pins are for the ML610Q429, but are not provided in the ML610Q428. LCD driver power supply VL1 — Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb, VL2 — Cc, and Cd (see measuring circuit 1) are connected between VSS and VL1, VL3 — VL2, VL3, and VL4, respectively. VL4 — C1 — Power supply pins for LCD bias (internally generated). Capacitors C12 C2 — and C34 (see measuring circuit 1) are connected between C1 and C2 and C3 — between C3 and C4, respectively. C4 — For testing TEST I/O Input/output pin for testing. A pull-down resistor is internally connected. Power supply VSS — VDD — VDDL — VDDX — VPP — Negative power supply pin. Positive power supply pin. Positive power supply pin (internally generated) for internal logic. Capacitors CL0 and CL1 (see measuring circuit 1) are connected between this pin and VSS. Plus-side power supply pin (internally generated) for low-speed oscillation. Capacitor Cx (see measuring circuit 1) is connected between this pin and VSS. Power supply pin for programming Flash ROM. A pull-up resistor is internally connected. Primary/ Secondary/ Tertiary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Logic — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 17/34 FEDL610Q428-04 ML610Q428/ML610Q429 TERMINATION OF UNUSED PINS Table 3 shows methods of terminating the unused pins. Table 3 Termination of Unused Pins Pin Recommended pin termination Open VPP VL1, VL2, VL3, VL4 Open C1, C2, C3, C4 RESET_N TEST NMI P00 to P07 P10 to P11 P20 to P22 P30 to P35 P40 to P47 PA0 to PA5 COM0 to 23 SEG0 to 63 Open Open Open Open VDD or VSS VDD Open Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. The main difference points of ML610Q428 and ML610Q429 Table 4 The main difference points of ML610Q428 and ML610Q429. Function PORT0 PORTA LCD COM LCD SEG ML610Q428 ML610Q429 P03 to P00 Nothing COM23 to COM0 SEG57 to SEG0 P07 to P00 PA5 to PA0 COM7 to COM0 SEG63 to SEG0 18/34 FEDL610Q428-04 ML610Q428/ML610Q429 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Parameter Symbol Condition Rating Unit VDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 2 VPP Ta = 25°C −0.3 to +9.5 V Power supply voltage 3 VDDL Ta = 25°C −0.3 to +3.6 V Power supply voltage 4 VDDX Ta = 25°C −0.3 to +3.6 V Power supply voltage 5 VL1 Ta = 25°C −0.3 to +1.75 V Power supply voltage 6 VL2 Ta = 25°C −0.3 to +3.5 V Power supply voltage 7 VL3 Ta = 25°C −0.3 to +5.25 V Power supply voltage 8 VL4 Ta = 25°C −0.3 to +7.0 V Power supply voltage 1 VIN Ta = 25°C −0.3 to VDD+0.3 V Output voltage VOUT Ta = 25°C −0.3 to VDD+0.3 V Output current 1 IOUT1 Port3–A, Ta = 25°C −12 to +11 mA Output current 2 IOUT2 Port2, Ta = 25°C −12 to +20 mA Power dissipation PD Ta = 25°C 122 mW Storage temperature TSTG −55 to +150 °C Input voltage RECOMMENDED OPERATING CONDITIONS (VSS = 0V) Parameter Symbol Condition Range Unit Operating temperature TOP −20 to +70 °C Operating voltage VDD 1.1 to 3.6 V Operating frequency (CPU) fOP Capacitor externally connected to VDDL pin Capacitor externally connected to VDDX pin CL0 CL1 VDD = 1.1 to 3.6V VDD = 1.3 to 3.6V VDD = 1.8 to 3.6V 30k to 36k 30k to 650k 30k to 4.2M 1.0±30% 0.1±30% CX 0.1±30% µF Capacitors externally connected to VL1, 2, 3, 4 pins Ca, b, c, d 1.0±30% µF Capacitors externally connected across C1 and C2 pins and across C3 and C4 pins C12, C34 1.0±30% µF Hz µF 19/34 FEDL610Q428-04 ML610Q428/ML610Q429 CLOCK GENERATION CIRCUIT OPERATING CONDITIONS (VSS = 0V) Rating Parameter Low-speed crystal oscillation frequency Recommended equivalent series resistance value of low-speed crystal oscillation Low-speed crystal oscillation *1 external capacitor High-speed crystal/ceramic oscillation frequency High-speed crystal oscillation external capacitor Symbol Condition Unit Min. Typ. Max. fXTL 32.768k Hz RL 40k Ω 0 CDL/CGL CL=6pF of crystal *2 oscillation CL=9pF of crystal oscillation CL=12pF of crystal oscillation 6 12 4.0M / 4.096M fXTH pF Hz CDH 24 pF CGH 24 *1 : The external CDL and CGL need to be adjusted in consideration of variation of internal loading capacitance CD and CG, and other additional capacitance such as PCB layout. *2 : When using a crystal oscillator CL = 6pF, there is a possibility that can not be adjusted by external CDL and CGL. 20/34 FEDL610Q428-04 ML610Q428/ML610Q429 OPERATING CONDITIONS OF FLASH ROM Parameter Operating temperature Symbol TOP VDD VDDL VPP CEP YDR Operating voltage Write cycles Data retention Condition At write/erase *1 At write/erase *1 At write/erase *1 At write/erase Range 0 to +40 2.75 to 3.6 2.5 to 2.75 7.7 to 8.3 80 10 (VSS = 0V) Unit °C V cycles years *1 : In addition the power supply to VDD pin and VPP pin, within the range 2.5V to 2.75V has to be supplied to VDDL pin when programming and eraseing Flash ROM. DC CHARACTERISTICS (1/5) Parameter 500kHz RC oscillation frequency 4 PLL oscillation frequency* (VDD = 1.1 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (1/5) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. Typ. Typ. Ta = 25°C 500 kHz VDD = −10% +10% 1.3 to fRC Ta = −20 to Typ. Typ. 3.6V 500 kHz +70°C −25% +25% LSCLK = 32.768kHz fPLL -2.5% 8.192 +2.5% MHz VDD = 1.8 to 3.6V Low-speed crystal oscillation 2 start time* TXTL 0.3 2 s 500kHz RC oscillation start time TRC 50 500 µs TXTH VDD = 1.8 to 3.6V ― 2 20 TPLL VDD = 1.8 to 3.6V ― 1 10 TSTOP 0.2 3 20 PRST 200 PNRST 0.3 TPOR 10 High-speed crystal oscillation 3 start time* PLL oscillation start time Low-speed oscillation stop detect *1 time Reset pulse width Reset noise elimination pulse width Power-on reset activation power rise time 1 ms µs ms *1: When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. *2 : Use 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=12pF). *3 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera). *4: 1024 clock average. [Reset pulse width] VIL1 RESET_N VIL1 PRST Reset pulse width (PRST) [Power-on reset activation power rise time] 0.9xVDD VDD 0.1xVDD TPOR Power-on reset activation power rise time (TPOR ) 21/34 FEDL610Q428-04 ML610Q428/ML610Q429 DC CHARACTERISTICS (2/5) Parameter VL1 voltage VL1 temperature deviation Symbol VL1 ∆VL1 VL1 voltage dependency ∆VL1 VL2 voltage VL2 VL3 voltage VL3 VL4 voltage VL4 LCD bias voltage generation time TBIAS (VDD = 1.1 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (2/5) Rating Measuring Condition Unit circuit Min. Typ. Max. CN4–0 = 00H 0.89 0.94 0.99 CN4–0 = 01H 0.91 0.96 1.01 CN4–0 = 02H 0.93 0.98 1.03 CN4–0 = 03H 0.95 1.00 1.05 CN4–0 = 04H 0.97 1.02 1.07 CN4–0 = 05H 0.99 1.04 1.09 CN4–0 = 06H 1.01 1.06 1.11 CN4–0 = 07H 1.03 1.08 1.13 CN4–0 = 08H 1.05 1.10 1.15 CN4–0 = 09H 1.07 1.12 1.17 CN4–0 = 0AH 1.09 1.14 1.19 CN4–0 = 0BH 1.11 1.16 1.21 CN4–0 = 0CH 1.13 1.18 1.23 CN4–0 = 0DH 1.15 1.20 1.25 CN4–0 = 0EH 1.17 1.22 1.27 CN4–0 = 0FH 1.19 1.24 1.29 VDD = 3.0V, V Tj = 25°C CN4–0 = 10H 1.21 1.26 1.31 CN4–0 = 11H 1.23 1.28 1.33 CN4–0 = 12H 1.25 1.30 1.35 CN4–0 = 13H 1.27 1.32 1.37 *1 CN4–0 = 14H 1.29 1.34 1.39 *1 CN4–0 = 15H 1.31 1.36 1.41 1 *1 CN4–0 = 16H 1.33 1.38 1.43 *1 CN4–0 = 17H 1.35 1.40 1.45 *1 CN4–0 = 18H 1.37 1.42 1.47 *1 CN4–0 = 19H 1.39 1.44 1.49 *1 CN4–0 = 1AH 1.41 1.46 1.51 *1 CN4–0 = 1BH 1.43 1.48 1.53 *1 CN4–0 = 1CH 1.45 1.50 1.55 *1 CN4–0 = 1DH 1.47 1.52 1.57 *1 CN4–0 = 1EH 1.49 1.54 1.59 *1 CN4–0 = 1FH 1.51 1.56 1.61 −1.5 mV/°C VDD = 1.3 to 3.6V 5 20 mV/V VDD = 3.0V, Tj = 25°C 300kΩ load (VL4−VSS) 1/3 bias VDD = 3.0V, 1/4 bias Tj = 25°C 300kΩ load 1/3 bias (VL4−VSS) 1/4 bias Typ. −10% Typ. −10% Typ. −10% VL1×2 VL1×2 VL1×3 VL1×3 VL1×4 Typ. +4% Typ. +4% Typ. +5% V 600 ms VDD = 3.0V *1: When using 1/4 bias, the VL1 voltage is set to typ. 1.32 V (same voltage as in CN4–0 = 13H). 22/34 FEDL610Q428-04 ML610Q428/ML610Q429 DC CHARACTERISTICS (3/5) Parameter BLD threshold voltage BLD threshold voltage temperature deviation Supply current 1 Supply current 2 Supply current 3 Supply current 4 Supply current 5 Supply current 6 Symbol (VDD = 1.1 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (3/5) Rating Measuring Condition Unit circuit Min. Typ. Max. Typ. −2% 1.35 1.4 1.45 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.7 2.9 Typ. +2% V 0 %/°C Ta = 25°C 0.15 0.50 Ta = -20 to +70°C 2.50 CPU: In HALT state (LTBC, RTC: Operating*3*5). High-speed oscillation: Stopped. LCD/BIAS circuits: Stopped. Ta = 25°C 0.5 1.3 Ta = -20 to +70°C 3.5 CPU: In 32.768kHz operating state.*1*3 High-speed oscillation: Stopped. LCD/BIAS circuits: Operating.*2 Ta = 25°C 5 7 Ta = -20 to +70°C 12 Ta = 25°C 70 85 Ta = -20 to +70°C 100 Ta = 25°C 0.4 0.5 Ta = -20 to +70°C 0.6 Ta = 25°C 0.8 1.0 Ta = -20 to +70°C 1.2 VBLD VDD = 1.35 to 3.6V ∆VBLD VDD = 1.35 to 3.6V IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 LD2–0 = 0H LD2–0 = 1H LD2–0 = 2H LD2–0 = 3H LD2–0 = 4H LD2–0 = 5H LD2–0 = 6H LD2–0 = 7H LD2–0 = 8H LD2–0 = 9H LD2–0 = 0AH LD2–0 = 0BH LD2–0 = 0CH LD2–0 = 0DH LD2–0 = 0EH LD2–0 = 0FH CPU: In STOP state. Low-speed/high-speed oscillation: stopped. CPU: In 500kHz CR operating state. LCD/BIAS circuits: Operating.*2*3 CPU: In 2MHz CR operating state. LCD/BIAS circuits: Operating.*2*3 CPU: In 4.096MHz operating state. PLL: In oscillating state. LCD/BIAS circuits: Operating. *2*3 VDD = 1.8 to 3.6V 1 µA µA µA µA mA mA *1 : CPU operating rate is 100% (No HALT state). *2 : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock: 1/128 LSCLK (256Hz) *3 : Use 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=12pF). *4 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera). *5 : Significant bits of BLKCON0~BLKCON4 registers are all “1”. 23/34 FEDL610Q428-04 ML610Q428/ML610Q429 DC CHARACTERISTICS (4/5) Parameter Output voltage 1 nd (P20–P22/2 function is selected) (P30–P36) (P40–P47) *1 (PA0–PA5) Output voltage 2 nd (P20–P22/2 function is Not selected) Output voltage 3 (P40–P41) Output voltage 4 (COM0–23) (SEG0–63) Output leakage (P20–P22) (P30–P35) (P40–P47) *1 (PA0–PA5) Symbol VOH1 VOL1 VOH2 Input current 1 (TEST) 0.3 IOH1 = −0.5mA, VDD = 1.8 to 3.6V VDD −0.5 VDD −0.3 VDD −0.3 IOH1 = -0.1mA, VDD = 1.3 to 3.6V VOL2 IOL2 = +5mA, VDD = 1.8 to 3.6V 0.5 VOL3 IOL3 = +3mA, VDD = 2.0 to 3.6V 2 (when I C mode is selected) 0.4 VOH4 IOH4 = −0.2mA, VL1=1.2V VL4 −0.2 VOMH4 IOMH4 = +0.2mA, VL1=1.2V VL3 +0.2 VOMH4S IOMH4S = −0.2mA, VL1=1.2V VL3 −0.2 VOM4 IOM4 = +0.2mA, VL1=1.2V VL2 +0.2 VOM4S IOM4S = −0.2mA, VL1=1.2V VL2 −0.2 VOML4 IOML4 = +0.2mA, VL1=1.2V VL1 +0.2 VOML4S IOML4S = −0.2mA, VL1=1.2V VL1 −0.2 VOL4 IOL4 = +0.2mA, VL1=1.2V 0.2 IOOH VOH = VDD (in high-impedance state) 1 IOOL IIL1 IIH1 IIL1 Input current 2 (NMI) (P00–P03) *1 (P04–P07) (P10–P11) IOL1 = +0.03mA, VDD = 1.1 to 3.6V IOH1 = -0.03mA, VDD = 1.1 to 3.6V IIH1 Input current 1 (RESET_N) (VDD = 1.1 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (4/5) Rating Measuring Condition Unit circuit Min. Typ. Max. VDD IOH1 = −0.5mA, VDD = 1.8 to 3.6V −0.5 VDD IOH1 = -0.1mA, VDD = 1.3 to 3.6V −0.3 VDD IOH1 = -0.03mA, VDD = 1.1 to 3.6V −0.3 IOL1 = +0.5mA, VDD = 1.8 to 3.6V 0.5 IOL1 = +0.1mA, VDD = 1.3 to 3.6V 0.5 −1 0 −600 −600 −600 20 10 2 -1 −300 −300 −300 300 300 300 1 −20 -10 -2 600 600 600 VDD = 1.8 to 3.6V 2 30 200 VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VDD = 1.8 to 3.6V VDD = 1.3 to 3.6V 0.2 0.01 −200 −200 30 30 −30 −30 200 200 −2 -0.2 VOL = VSS (in high-impedance state) VIH1 = VDD VDD = 1.8 to 3.6V VIL1 = VSS VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VDD = 1.8 to 3.6V VDD = 1.3 to 3.6V VIH1 = VDD VDD = 1.1 to 3.6V VIL1 = Vss IIH2 VIH2 = VDD (when pulled-down) IIL2 VIL2 = VSS (when pulled-up) V 2 µA 3 µA 4 24/34 FEDL610Q428-04 ML610Q428/ML610Q429 (P30–P35) (P40–P47) *1 (PA0–PA5) VDD = 1.1 to 3.6V −200 −30 -0.01 IIH2Z VIH2 = VDD (in high-impedance state) 1 IIL2Z VIL2 = VSS (in high-impedance state) −1 *1: ML610Q429 only DC CHARACTERISTICS (5/5) Parameter Input voltage 1 (RESET_N) (TEST) (NMI) (P00–P03) *1 (P04–P07) (P10–P11) (P31–P35) (P40–P43) (P45–P47) *1 (PA0–PA5) Input voltage 2 (P30, P44) Symbol (VDD = 1.1 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) (5/5) Rating Measuring Condition Unit circuit Min. Typ. Max. VDD = 1.3 to 3.6V 0.7 ×VDD VDD VDD = 1.1 to 3.6V 0.7 ×VDD VDD VDD = 1.3 to 3.6V 0 0.3 ×VDD VDD = 1.1 to 3.6V 0 0.2 ×VDD VIH2 0.7 ×VDD VDD VIL2 0 0.3 ×VDD f = 10kHz Vrms = 50mV Ta = 25°C 5 VIH1 VIL1 Input pin capacitance (NMI) (P00–P03) *1 (P04–P07) CIN (P10–P11) (P30–P35) (P40–P47) *1 (PA0–PA5) *1: ML610Q429 only V 5 pF 25/34 FEDL610Q428-04 ML610Q428/ML610Q429 MEASURING CIRCUITS MEASURING CIRCUIT 1 XT0 C4 XT1 C3 C2 C34 32.768kHz crystal CGH P10/OSC0 C12 C1 CDH CV: CL0: CL1: CX: Ca,Cb,Cc,Cd: C12,C34: CGH: CDH: P11/OSC1 4.096MHz crystal VDD VDDL VDDX VL1 VL2 VL3 VL4 VSS A CL1 CL0 CX Ca Cb Cc Cd CV 1µF 1µF 0.1µF 0.1µF 1µF 1µF 24pF 24pF 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (Made by KDS:DAISHINKU CORP.) 4.096MHz crystal: HC49SFWB (Kyocera) MEASURING CIRCUIT 2 (*2) VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 VL4 V VSS (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. 26/34 FEDL610Q428-04 ML610Q428/ML610Q429 MEASURING CIRCUIT 3 (*2) VIL Input pins RS1 Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 VL4 A VSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. MEASURING CIRCUIT 4 Input pins Output pins (*3) A VDD VDDL VDDX VL1 VL2 VL3 VL4 VSS *3: Measured at the specified output pins. VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 VL4 Waveform monitoring MEASURING CIRCUIT 5 VSS *1: Input logic circuit to determine the specified measuring conditions. 27/34 FEDL610Q428-04 ML610Q428/ML610Q429 AC CHARACTERISTICS (External Interrupt) (VDD = 1.1 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Symbol Condition Unit Min. Typ. Max. Parameter External interrupt disable period TNUL Interrupt: Enabled (MIE = 1), CPU: NOP operation System clock: 32.768kHz 76.8 106.8 µs P00–P07 (Rising-edge interrupt) tNUL P00–P07 (Falling-edge interrupt) tNUL NMI, P00–P07 (Both-edge interrupt) AC CHARACTERISTICS (UART) Parameter Transmit baud rate tNUL (VDD = 1.3 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Symbol Condition Unit Min. Typ. Max. tTBRT 1 BRT* 1 s 1 BRT* BRT* 1 BRT* s −3% +3% *1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H) and the UART mode register 0 (UA0MOD0). Receive baud rate tRBRT tTBRT TXD0* tRBRT RXD0* *: Indicates the secondary function of the port. 28/34 FEDL610Q428-04 ML610Q428/ML610Q429 AC CHARACTERISTICS (Synchronous Serial Port) Parameter Symbol (VDD = 1.3 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Condition Unit Min. Typ. Max. When high-speed oscillation is 10 µs not active When high-speed oscillation is 1 µs active (VDD = 1.8 to 3.6V) SCLK input cycle (slave mode) tSCYC SCLK output cycle (master mode) tSCYC tSW When high-speed oscillation is not active When high-speed oscillation is active (VDD = 1.8 to 3.6V) SCLK input pulse width (slave mode) SCLK* s 4 µs 1 0.4 1 SCLK* SCLK output pulse width tSW (master mode) ×0.4 SOUT output delay time tSD (slave mode) SOUT output delay time tSD (master mode) SIN input setup time tSS 80 (slave mode) SIN input setup time tSS 180 (master mode) SIN input tSH 80 hold time *1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1) 1 µs 1 SCLK* ×0.5 SCLK* ×0.6 s 180 ns 80 ns ns ns ns tSCYC tSW tSW SCLK0* tSD tSD SOUT0* tSS tSH SIN0* *: Indicates the secondary function of the port. 29/34 FEDL610Q428-04 ML610Q428/ML610Q429 AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz) (VDD = 1.8 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Symbol Condition Unit Min. Typ. Max. fSCL 0 100 kHz Parameter SCL clock frequency SCL hold time (start/restart condition) SCL ”L” level time SCL ”H” level time SCL setup time (restart condition) SDA hold time SDA setup time SDA setup time (stop condition) Bus-free time tHD:STA 4.0 µs tLOW tHIGH 4.7 4.0 µs µs tSU:STA 4.7 µs tHD:DAT tSU:DAT 0 0.25 3.45 µs µs tSU:STO 4.0 µs tBUF 4.7 µs AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz) (VDD = 1.8 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Symbol Condition Unit Min. Typ. Max. fSCL 0 400 kHz Parameter SCL clock frequency SCL hold time (start/restart condition) SCL ”L” level time SCL ”H” level time SCL setup time (restart condition) SDA hold time SDA setup time SDA setup time (stop condition) Bus-free time tHD:STA 0.6 µs tLOW tHIGH 1.3 0.6 µs µs tSU:STA 0.6 µs tHD:DAT tSU:DAT 0 0.1 0.9 µs µs tSU:STO 0.6 µs tBUF 1.3 µs Start condition Restart condition Stop condition P40/SDA P41/SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF 30/34 FEDL610Q428-04 ML610Q428/ML610Q429 AC CHARACTERISTICS (RC Oscillation A/D Converter) Parameter (VDD = 1.3 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Condition Unit Min. Typ. Max. Symbol RS0, RS1, RT0, RT0-1,RT1 fOSC1 Resistors for oscillation Oscillation frequency VDD = 1.5V CS0, CT0, CS1 ≥ 740pF Resistor for oscillation = 1kΩ Resistor for oscillation = 10kΩ Resistor for oscillation = 100kΩ RT0, RT0-1, RT1 = 1kHz RT0, RT0-1, RT1 = 10 kHz RT0, RT0-1, RT1 = 100 kHz Resistor for oscillation = 1kΩ Resistor for oscillation = 10kΩ Resistor for oscillation = 100kΩ RT0, RT0-1, RT1 = 1kHz RT0, RT0-1, RT1 = 10 kHz RT0, RT0-1, RT1 = 100 kHz fOSC2 fOSC3 Kf1 Kf2 Kf3 fOSC1 fOSC2 fOSC3 Kf1 Kf2 Kf3 RS to RT oscillation frequency ratio *1 VDD = 1.5V Oscillation frequency VDD = 3.0V RS to RT oscillation frequency ratio *1 VDD = 3.0V 1 209.4 41.29 4.71 5.567 0.99 0.104 407.3 49.76 5.04 8.006 0.99 0.100 330.6 55.27 5.97 5.982 1 0.108 435.1 64.16 7.06 6.225 1.01 0.118 486.7 59.28 5.993 8.210 1 0.108 594.6 72.76 7.04 8.416 1.01 0.115 kΩ kHz kHz kHz kHz kHz kHz *1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. fOSCX(RT0-1−CS0 oscillation) fOSCX(RS0−CS0 oscillation) , IN0 CS0 RCT0 (*1) VIL *1: Input logic circuit to determine the specified measuring conditions. VDDL fOSCX(RT1−CS1 oscillation) fOSCX(RS1−CS1 oscillation) VDDX RT0, RT0-1, RT1: 1kΩ /10kΩ/100kΩ RS0, RS1: 10kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF IN1 CS1 RS1 RT1 RCM VDD CV RT1 RT0 RS0 RS0 RT0 Input pins VIH , CVR1 RI0-1 CT0 CS0 CVR0 RS1 fOSCX(RT0−CS0 oscillation) fOSCX(RS0−CS0 oscillation) (x = 1, 2, 3) CS1 Kfx = Frequency measurement (fOSCX) VSS CL1 CL0 CX Note: - Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. - When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal. - Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have. 31/34 FEDL610Q428-04 ML610Q428/ML610Q429 PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 32/34 FEDL610Q428-04 ML610Q428/ML610Q429 REVISION HISTORY Document No. FEDL610Q428-01 FEDL610Q428-02 FEDL610Q428-03 FEDL610Q428-04 Date Feb.7.2011 Jun 7.2011 July.25.2014 May.15,2015 Page Previous Current Edition Edition – 3 All 3,18,19, 20,21,22, 23,26,27, 28,29 3,7 2,7 – 3 All 3,18,20, 21,22,23, 24,27,28, 29,30 4 2 3 4 - 19 19 20 21 22 30 31 2 2 - 4,8 Description Formally edition 1.0 Add the P version Change header and footer Delete the P version Delete package products Delete the metal option of only ML610Q429’s LCD driver Change from "Shipment" to " Product name – Supported Function " Add CLOCK GENERATION CIRCUIT OPERATING CONDITIONS Change "RESET" to "Reset pulse width (PRST)" and " Power-on reset activation power rise time (TPOR )". Correct the CGL’s value and the CDL’s value of DC CHARACTERISTICS (3/5)’s note No.3 Update Package Dimensions Corrected a typo. “100kbps@1MHz HSCLK” is corrected to 100kbps@4MHz HSCLK. Add the ML610Q429 package product 33/34 FEDL610Q428-04 ML610Q428/ML610Q429 Notes 1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing circuits for mass production. 4) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) The Products specified in this document are not designed to be radiation tolerant. 7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the recommended usage conditions and specifications contained herein. 10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Copyright 2011 – 2015 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/ 34/34