ON MC74VHC595 8-bit shift register with output storage register (3-state) Datasheet

MC74VHC595
8-- Bit Shift Register with
Output Storage Register
(3-- State)
The MC74VHC595 is an advanced high speed 8--bit shift register
with an output storage register fabricated with silicon gate CMOS
technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
The MC74VHC595 contains an 8--bit static shift register which
feeds an 8--bit storage register.
Shift operation is accomplished on the positive going transition of
the Shift Clock input (SCK). The output register is loaded with the
contents of the shift register on the positive going transition of the
Register Clock input (RCK). Since the RCK and SCK signals are
independent, parallel outputs can be held stable during the shift
operation. And, since the parallel outputs are 3--state, the VHC595 can
be directly connected to an 8--bit bus. This register can be used in
serial--to--parallel conversion, data receivers, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
•
•
•
•
•
•
•
•
•
•
•
High Speed: fmax = 185MHz (Typ) at VCC = 5V
Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 1.0V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
These devices are available in Pb--free package(s). Specifications herein
apply to both standard and Pb--free devices. Please see our website at
www.onsemi.com for specific Pb--free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
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MARKING DIAGRAMS
16
SOIC--16
D SUFFIX
CASE 751B
9
1
8
16
SOIC EIAJ--16
M SUFFIX
CASE 966
A
WL
YY
WW
A
WL
Y
WW
9
VHC595
ALYW
1
8
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Assembly Location
= Wafer Lot
= Year
= Work Week
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
MC74VHC595DR2
MC74VHC595DT
1
8
VHC
595
AWLYWW
TSSOP--16
DT SUFFIX
CASE 948F
Device
March, 2006 -- Rev. 4
1
16
MC74VHC595D
© Semiconductor Components Industries, LLC, 2006
9
VHC595
AWLYYWW
Package
Shipping
SOIC--16
48 Units/Rail
SOIC--16
2500 Units/Reel
TSSOP--16
96 Units/Rail
MC74VHC595DTEL TSSOP--16
2000 Units/Reel
MC74VHC595DTR2 TSSOP--16
2500 Units/Reel
MC74VHC595M
SOIC
EIAJ--16
50 Units/Rail
MC74VHC595MEL
SOIC
EIAJ--16
2000 Units/Reel
Publication Order Number:
MC74VHC595/D
MC74VHC595
PIN ASSIGNMENT
QB
1
16
VCC
QC
2
15
QA
QD
3
14
SI
QE
4
13
OE
QF
5
12
RCK
QG
6
11
SCK
QH
7
10
SCLR
GND
8
9
SQH
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2
MC74VHC595
LOGIC DIAGRAM
SERIAL
DATA
INPUT
SI
15
14
1
2
3
SHIFT
REGISTER
4
STORAGE
REGISTER
5
6
7
SCK
SCLR
RCK
OE
QA
QB
QC
PARALLEL
DATA
OUTPUTS
QD
QE
QF
QG
QH
11
9
10
SQH
12
13
IEC LOGIC SYMBOL
OE
RSK
SCLR
SCK
SI
13
12
10
11
14
EN3
C2
SRG8
R
C/1
1D
2D
3
15
1
2
3
4
5
6
2D
3
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3
7
9
QA
QB
QC
QD
QE
QF
QG
QH
SQH
SERIAL
DATA
OUTPUT
MC74VHC595
EXPANDED LOGIC DIAGRAM
OE
RCK
SI
13
12
14
D
Q
D
SRA
Q
15
QA
STRA
R
Q
D
D
SRB
Q
1
QB
STRB
R
Q
D
D
SRC
Q
2
QC
STRC
R
Q
D
D
SRD
Q
3
QD
STRD
PARALLEL
DATA
OUTPUTS
R
Q
D
D
SRE
Q
4
QE
STRE
R
Q
D
D
SRF
Q
5
QF
STRF
R
Q
D
D
SRG
Q
6
QG
STRG
R
Q
D
SCK
11
D
SRH
Q
7
QH
STRH
R
SCLR
10
9
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4
SQH
MC74VHC595
FUNCTION TABLE
Inputs
Resulting Function
Reset
(SCLR)
Serial
Input
(SI)
Shift
Clock
(SCK)
Reg
Clock
(RCK)
Output
Enable
(OE)
Shift
Register
Contents
Storage
Register
Contents
Serial
Output
(SQH)
Parallel
Outputs
(QA -- QH)
Clear shift register
L
X
X
L, H, ↓
L
L
U
L
U
Shift data into shift
register
H
D
↑
L, H, ↓
L
D→SRA;
SRN→SRN+1
U
SRG→SRH
U
Registers remains
unchanged
H
X
L, H, ↓
X
L
U
**
U
**
Transfer shift register
contents to storage
register
H
X
L, H, ↓
↑
L
U
SRN→STRN
*
SRN
Storage register remains
unchanged
X
X
X
L, H, ↓
L
*
U
*
U
Enable parallel outputs
X
X
X
X
L
*
**
*
Enabled
Force outputs into high
impedance state
X
X
X
X
H
*
**
*
Z
Operation
SR = shift register contents
D = data (L, H) logic level
inputs
STR = storage register contents U = remains unchanged
↓ = High--to--Low
* = depends on Reset and Shift Clock
↑ = Low--to--High
** = depends on Register Clock input
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
-- 20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
SOIC Packages†
TSSOP Package†
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute--maximum--rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: -- 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
5.5
V
DC Input Voltage
0
5.5
V
DC Output Voltage
0
VCC
V
-- 55
+ 125
_C
0
0
100
20
ns/V
VCC
DC Supply Voltage
Vin
Vout
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
VCC = 3.3V ±0.3V
VCC =5.0V ±0.5V
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5
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high--impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND ≤ (Vin or Vout) ≤ VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
MC74VHC595
The θJA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and
figure below.
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
117.8
419,300
TJ = 90 ° C
1,032,200
90
TJ = 100 ° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110° C
Time, Years
TJ = 120° C
Time, Hours
TJ = 130 ° C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
1
1
10
100
1000
TIME, YEARS
Figure 1. Failure Rate vs. Time
Junction Temperature
DC ELECTRICAL CHARACTERISTICS
Min
1.5
2.1
3.15
3.85
Symbol
Parameter
VIH
Minimum High--Level
Input Voltage
2.0
3.0
4.5
5.5
VIL
Maximum Low--Level
Input Voltage
2.0
3.0
4.5
5.5
VOH
Minimum High--Level
Output Voltage
VIN = VIH or VIL
VOL
Maximum Low--Level
Output Voltage
VIN = VIH or VIL
Test Conditions
TA = 25°C
VCC
(V)
Typ
TA = ≤ 85°C
Max
Min
1.5
2.1
3.15
3.85
0.59
0.9
1.35
1.65
VIN = VIH or VIL
IOH = -- 50 μA
2.0
3.0
4.5
1.9
2.9
4.4
VIN = VIH or VIL
IOH = --4 mA
IOH = --8 mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50 μA
2.0
3.0
4.5
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
Max
2.0
3.0
4.5
0.0
0.0
0.0
TA = ≤ 125°C
Min
Max
1.5
2.1
3.15
3.85
0.59
0.9
1.35
1.65
V
0.59
0.9
1.35
1.65
1.9
2.9
4.4
1.9
2.9
4.4
2.48
3.80
2.34
3.66
Unit
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
± 0.1
± 1.0
± 1.0
μA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
4.0
40.0
40.0
μA
IOZ
Three--State Output
Off--State Current
VIN = VIH or VIL
VOUT = VCC or
GND
5.5
± 0.25
± 2.5
± 2.5
μA
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6
MC74VHC595
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
fmax
tPLH,
tPHL
tPHL
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
CIN
COUT
Parameter
Min
Test Conditions
TA = ≤ 85°C
Typ
Max
Min
Max
TA = ≤ 125°C
Min
Max
Maximum Clock
Frequency (50%
Duty Cycle)
VCC = 3.3 ± 0.3 V
80
150
70
70
VCC = 5.0 ± 0.5 V
135
185
115
115
Propagation Delay,
SCK to SQH
VCC = 3.3 ± 0.3 V
CL = 15pF
CL = 50pF
8.8
11.3
13.0
16.5
1.0
1.0
15.0
18.5
1.0
1.0
15.0
18.5
VCC = 5.0 ± 0.5 V
CL = 15pF
CL = 50pF
6.2
7.7
8.2
10.2
1.0
1.0
9.4
11.4
1.0
1.0
9.4
11.4
VCC = 3.3 ± 0.3 V
CL = 15pF
CL = 50pF
8.4
10.9
12.8
16.3
1.0
1.0
13.7
17.2
1.0
1.0
13.7
17.2
VCC = 5.0 ± 0.5 V
CL = 15pF
CL = 50pF
5.9
7.4
8.0
10.0
1.0
1.0
9.1
11.1
1.0
1.0
9.1
11.1
VCC = 3.3 ± 0.3 V
CL = 15pF
CL = 50pF
7.7
10.2
11.9
15.4
1.0
1.0
13.5
17.0
1.0
1.0
13.5
17.0
VCC = 5.0 ± 0.5 V
CL = 15pF
CL = 50pF
5.4
6.9
7..4
9.4
1.0
1.0
8.5
10.5
1.0
1.0
8.5
10.5
VCC = 3.3 ± 0.3 V
RL = 1 kΩ
CL = 15pF
CL = 50pF
7.5
9.0
11.5
15.0
1.0
1.0
13.5
17.0
1.0
1.0
13.5
17.0
VCC = 5.0 ± 0.5 V
RL = 1 kΩ
CL = 15pF
CL = 50pF
4.8
8.3
8.6
10.6
1.0
1.0
10.0
12.0
1.0
1.0
10.0
12.0
VCC = 3.3 ± 0.3 V
RL = 1 kΩ
CL = 50pF
12.1
15.7
1.0
16.2
1.0
16.2
VCC = 5.0 ± 0.5 V
RL = 1 kΩ
CL = 50pF
7.6
10.3
1.0
11.0
1.0
11.0
Input Capacitance
4
10
Three--State Output
Capacitance (Output
in High--Impedance
State), QA--QH
6
Propagation Delay,
CPLR to SQH
Propagation Delay,
RCK to QA--QH
Output Enable Time,
OE to QA--QH
Output Disable Time,
OE to QA--QH
Unit
MHz
ns
ns
ns
ns
ns
10
10
pF
10
10
pF
Typical @ 25°C, VCC = 5.0V
87
CPD
Power Dissipation Capacitance (Note 1)
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD ¯ VCC ¯ fin + ICC. CPD is used to determine the no--load dynamic
power consumption; PD = CPD ¯ VCC2 ¯ fin + ICC ¯ VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.8
1.0
V
VOLV
Quiet Output Minimum Dynamic VOL
-- 0.8
-- 1.0
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
Characteristic
Symbol
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbol
tsu
tsu(H)
Parameter
TA = -- 40 to
85°C
TA = -- 55 to
125°C
Limit
Limit
Limit
Unit
TA = 25_C
VCC
V
Typ
Setup Time, SI to SCK
3.3
5.0
3.5
3.0
3.5
3.0
3.5
3.0
ns
Setup Time, SCK to RCK
3.3
5.0
8.0
5.0
8.5
5.0
8.5
5.0
ns
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7
MC74VHC595
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
VCC
V
Limit
Limit
Limit
Unit
Setup Time, SCLR to RCK
3.3
5.0
8.0
5.0
9.0
5.0
9.0
5.0
ns
Hold Time, SI to SCK
3.3
5.0
1.5
2.0
1.5
2.0
1.5
2.0
ns
th(L)
Hold Time, SCLR to RCK
3.3
5.0
0
0
0
0
1.0
1.0
ns
trec
Recovery Time, SCLR to SCK
3.3
5.0
3.0
2.5
3.0
2.5
3.0
2.5
ns
tw
Pulse Width, SCK or RCK
3.3
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
Pulse Width, SCLR
3.3
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
Symbol
tsu(L)
th
tw(L)
Parameter
Typ
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8
MC74VHC595
SWITCHING WAVEFORMS
tw
SCK
VCC
50%
GND
tw
SQH
GND
tPHL
1/fmax
tPLH
50% VCC
SQH
tPHL
trec
50% VCC
50%
VCC
50%
OE
GND
tPZL
tPHL
QA--QH
HIGH
IMPEDANCE
VCC
GND
VALID
tsu
VCC
50%
SCK
VCC
50%
GND
tsu(H)
GND
th
50%
RCK
VCC
50%
SCK or RCK
VOH --0.3V
Figure 5.
50%
SI
VOL +0.3V
tPHZ
50% VCC
Figure 4.
SCLR
HIGH
IMPEDANCE
50% VCC
QA--QH
50% VCC
GND
tPLZ
tPZH
QA--QH
GND
Figure 3.
VCC
tPLH
VCC
50%
SCK
Figure 2.
RCK
VCC
50%
SCLR
GND
tw
GND
Figure 6.
VCC
Figure 7.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 8.
Figure 9.
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9
MC74VHC595
TIMING DIAGRAM
SCK
SI
SCLR
RCK
OE
QA
QB
QC
QD
QE
QF
QG
QH
SQH
NOTE:
output is in a high--impedance state.
INPUT EQUIVALENT CIRCUIT
INPUT
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10
MC74VHC595
PACKAGE DIMENSIONS
SOIC--16
D SUFFIX
CASE 751B--05
ISSUE J
--A
-16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
1
--B
--
8
P 8 PL
0.25 (0.010)
M
B
M
G
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
R X 45°
C
--T
SEATING
-PLANE
D 16 PL
0.25 (0.010)
J
M
M
T
B
S
A
S
MILLIMETERS
MIN
MAX
9.80 10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
TSSOP--16
DT SUFFIX
CASE 948F--01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
K1
2X
L/2
16
9
J1
B
--U--
L
SECTION N--N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
--V--
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE --W--.
N
F
DETAIL E
--W--
C
0.10 (0.004)
--T-- SEATING
PLANE
D
G
DETAIL E
H
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11
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
-----1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
-----0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74VHC595
PACKAGE DIMENSIONS
SOIC EIAJ--16
M SUFFIX
CASE 966--01
ISSUE O
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
E HE
1
M_
L
8
Z
DETAIL P
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
-----2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
-----0.78
INCHES
MIN
MAX
-----0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
-----0.031
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MC74VHC595/D
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