DS78LS120 is OBSOLETE DS78LS120QML, DS78LS120 www.ti.com SNLS370C – SEPTEMBER 1999 – REVISED APRIL 2013 DS78LS120/DS78LS120QML Dual Differential Line Receiver (Noise Filtering and Fail-Safe) Check for Samples: DS78LS120QML, DS78LS120 FEATURES DESCRIPTION • The DS78LS120QML is a high performance, dual differential, TTL compatible line receiver for both balanced and unbalanced digital data transmission. The inputs are compatible with EIA, Federal and MIL standards. 1 2 • • • • • • • Meets EIA Standards RS232-C, RS422 and RS423, Federal Standards 1020, 1030 and MIL188-114 Input Voltage Range of ±15V (Differential or Common-mode) Separate Strobe Input for Each Receiver 5k Typical Input Impedance Optional 180Ω Termination Resistor 50mV Input Hysteresis 200mV Input Threshold Separate Fail-safe Mode The line receiver will discriminate a ±200 mV input signal over a common-mode range of ±10V and a ±300 mV signal over a range of ±15V. Circuit features include hysteresis and response control for applications where controlled rise and fall times and/or high frequency noise rejection are desirable. Threshold offset control is provided for failsafe detection, should the input be open or short. Each receiver includes an optional 180Ω terminating resistor and the output gate contains a logic strobe for time discrimination. The DS78LS120QML is specified over a −55°C to +125°C temperature range. Input specifications meet or exceed those of the popular DS7820 line receiver. Connection Diagram Figure 1. CDIP / CLGA See RETS Data Sheet See Package Number NFE0016A or NAD0016A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated DS78LS120 is OBSOLETE DS78LS120QML, DS78LS120 SNLS370C – SEPTEMBER 1999 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage 7V Input Voltage ±25V Strobe Voltage 7V Output Sink Current 50 mA −65°C to +150°C Storage Temperature Range Maximum Power Dissipation at 25°C (3) 1433 mV Lead Temperature (Soldering, 4 sec) (1) (2) (3) 260°C “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Derate CDIP package 9.6 mW/°C above 25°C. Operating Conditions Min Max Supply Voltage (VCC) 4.5 5.5 Units V Temperature (TA) −55 +125 °C Common-Mode Voltage (VCM) −15 +15 V Electrical Characteristics (1) (2) Symbol VTH Parameter Conditions Typ Max Units −7V ≤ VCM ≤ 7V Min 0.06 0.2 V −15 ≤ VCM ≤15V 0.06 0.3 V −7V ≤ VCM ≤7V −0.08 −0.2 V −15V ≤ VCM ≤ 15V −0.08 −0.3 V 0.47 0.7 V Differential Threshold Voltage IOUT = −400 μA, VOUT ≥ 2.5V Differential Threshold Voltage IOUT = 4 mA, VOUT ≤ 0.5V VTH Differential Threshold Voltage IOUT = −400 μA, VOUT ≥ 2.5V −7V ≤ VCM ≤ 7V VTL with Fail-Safe Offset = 5V IOUT = 4 mA, VOUT ≤ 0.5V −7V ≤ VCM ≤ 7V RIN Input Resistance −15V ≤ VCM ≤ 15V, 0V ≤ VCC ≤ 7V 4 5 RT Line Termination Resistance TA = 25°C 100 180 300 Ω RO Offset Control Resistance TA = 25°C 42 56 70 kΩ 2 3.1 mA 0 −0.5 mA −2 −3.1 mA 0.1 0.4 V −0.1 −0.4 VTL IIND −0.2 VCM = 10V Data Input Current (Unterminated) VCM = 0V 0V ≤ VCC ≤ 7V VCM = −10V IOUT = −400 μA, VOUT ≥ 2.5V, VTHB Input Balance (3) RS = 500Ω IOUT = 4 mA, VOUT ≤ 0.5V, RS = 500Ω −7V ≤ VCM 7V −7V ≤ VCM ≤ 7V VOH Logical “1” Output Voltage IOUT = −400 μA, VDIFF = 1V, VCC = 4.5V VOL Logical “0” Output Voltage IOUT = 4 mA, VDIFF = −1V, VCC = 4.5V ICC (1) (2) (3) 2 Power Supply Current 2.5 −0.42 V kΩ 3 V V 0.35 0.5 V VCC = 5.5V VCM = 15V 10 16 mA VDIFF = −0.5V, (Both Receivers) VCM = −15V 10 16 mA Unless otherwise specified min/max limits apply across the −55°C to +125°C temperature range for the DS78LS120QML. All typical values are for TA = 25°C, VCC = 5V and VCM = 0V. All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Refer to EIA-RS422 for exact conditions. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS78LS120QML DS78LS120 DS78LS120 is OBSOLETE DS78LS120QML, DS78LS120 www.ti.com SNLS370C – SEPTEMBER 1999 – REVISED APRIL 2013 Electrical Characteristics(1)(2) (continued) Symbol Typ Max Units (1) Logical “1” Strobe Input Current VSTROBE = 5.5V, VDIFF = 3V 1 100 μA (0) Logical “0” Strobe Input Current VSTROBE = 0V, VDIFF = −3V −290 −400 μA VIH Logical “1” Strobe Input Voltage VOL ≤ 0.5, IOUT = 4mA VIL Logical “0” Strobe Input Voltage VOH ≥ 2.5V, IOUT, = −400 μA IOS Output Short-Circuit Current VOUT = 0V, VCC = 5.5V, VSTROBE = 0V (4) IIN IIN (4) Parameter Conditions Min 2.0 1.12 V 1.12 0.8 V −30 −100 −170 mA Only one output at a time should be shorted. Switching Characteristics VCC = 5V, TA = 25°C Symbol Parameter Conditions tpd0(D) Differential Input to “0” Output tpd1(D) Differential Input to “1” Output tpd0(S) Strobe Input to “0” Output tpd1(S) Strobe Input to “1” Output Min Response Pin Open, CL = 15 pF, RL = 2 kΩ Typ Max Units 38 60 ns 38 60 ns 16 25 ns 12 25 ns AC Test Circuit and Switching Time Waveforms Includes probe and test fixture capacitance Figure 2. Differential and Strobe Input Signal Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection). Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS78LS120QML DS78LS120 Submit Documentation Feedback 3 DS78LS120 is OBSOLETE DS78LS120QML, DS78LS120 SNLS370C – SEPTEMBER 1999 – REVISED APRIL 2013 www.ti.com APPLICATION HINTS Figure 3. Balanced Data Transmission Figure 4. Unbalanced Data Transmission Figure 5. Logic Level Translator The DS78LS120QML may be used as a level translator to interface between ±12V MOS, ECL, TTL and CMOS. To configure, bias either input to a voltage equal to ½ the voltage of the input signal, and the other input to the driving gate. 4 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS78LS120QML DS78LS120 DS78LS120 is OBSOLETE DS78LS120QML, DS78LS120 www.ti.com SNLS370C – SEPTEMBER 1999 – REVISED APRIL 2013 LINE DRIVERS Line drivers which will interface with the DS78LS120QML are listed below. Balanced Drivers DS26LS31: Quad RS-422 Line Driver, Dual CMOS DS7830, DS8830: Dual TTL DS7831, DS8831: Dual TRI-STATE TTL DS7832, DS8832: Dual TRI-STATE TTL DS1691A, DS3691: Quad RS-423/Dual RS-422 TTL DS1692, DS3692: Quad RS-423/Dual TRI-STATE RS-422 TTL DS3487: Quad TRI-STATE RS-422 Unbalanced Drivers DS1488: Quad RS-232 DS75150: Dual RS-232 RESPONSE CONTROL AND HYSTERESIS In unbalanced (RS-232/RS-423) applications it is recommended that the rise time and fall time of the line driver be controlled to reduce cross-talk. Elimination of switching noise is accomplished in the DS78LS120QML by the 50 mV of hysteresis incorporated in the output gate. This eliminates the oscillations which may appear in a line receiver due to the input signal slowly varying about the threshold level for extended periods of time. High frequency noise which is superimposed on the input signal which may exceed 50 mV can be reduced in amplitude by filtering the device input. On the DS78LS120QML, a high impedance response control pin in the input amplifier is available to filter the input signal without affecting the termination impedance of the transmission line. Noise pulse width rejection vs the value of the response control capacitor is shown in Figure 6 and Figure 7. This combination of filters followed by hysteresis will optimize performance in a worse case noise environment. Figure 6. Noise Pulse Width vs Response Control Capacitor Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS78LS120QML DS78LS120 Submit Documentation Feedback 5 DS78LS120 is OBSOLETE DS78LS120QML, DS78LS120 SNLS370C – SEPTEMBER 1999 – REVISED APRIL 2013 www.ti.com Figure 7. TRANSMISSION LINE TERMINATION On a transmission line which is electrically long, it is advisable to terminate the line in its characteristic impedance to prevent signal reflection and its associated noise/cross-talk. A 180Ω termination resistor is provided in the DS78LS120QML line receiver. To use the termination resistor, connect pins 2 and 3 together and pins 13 and 14 together. The 180Ω resistor provides a good compromise between line reflections, power dissipation in the driver, and IR drop in the transmission line. If power dissipation and IR drop are still a concern, a capacitor may be connected in series with the resistor to minimize power loss. The value of the capacitor is recommended to be the line length (time) divided by 3 times the resistor value. Example: if the transmission line is 1,000 feet long, (approximately 1000 ns), and the termination resistor value is 180Ω, the capacitor value should be 1852 pF. For additional application details, refer to application notes AN-22 and AN-108. FAIL-SAFE OPERATION Communication systems require elements of a system to detect the presence of signals in the transmission lines, and it is desirable to have the system shut-down in a fail-safe mode if the transmission line is open or shorted. To facilitate the detection of input opens or shorts, the DS78LS120QML incorporates an input threshold voltage offset. This feature will force the line receiver to a specific logic state if presence of either fault is a condition. Given that the receiver input threshold is ±200 mV, an input signal greater than ±200 mV insures the receiver will be in a specific logic state. When the offset control input (pins 1 and 15) is connected to VCC = 5V, the input thresholds are offset from 200 mV to 700 mV, referred to the non-inverting input, or −200 mV to −700 mV, referred to the inverting input. Therefore, if the input is open or shorted, the input will be greater than the input threshold and the receiver will remain in a specified logic state. The input circuit of the receiver consists of a 5k resistor terminated to ground through 120Ω on both inputs. This network acts as an attenuator, and permits operation with common-mode input voltages greater than ±15V. The offset control input is actually another input to the attenuator, but its resistor value is 56k. The offset control input is connected to the inverting input side of the attenuator, and the input voltage to the amplifier is the sum of the inverting input plus 0.09 times the voltage on the offset control input. When the offset control input is connected to 5V the input amplifier will see VIN(INVERTING) +0.45V or VIN(INVERTING) +0.9V when the control input is connected to 10V. The offset control input will not significantly affect the differential performance of the receiver over its common-mode operating range, and will not change the input impedance balance of the receiver. It is recommended that the receiver be terminated (500Ω or less) to insure it will detect an open circuit in the presence of noise. The offset control can be used to insure fail-safe operation for unbalanced interface (RS-423) or for balanced interface (RS-422) operation. 6 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS78LS120QML DS78LS120 DS78LS120 is OBSOLETE DS78LS120QML, DS78LS120 www.ti.com SNLS370C – SEPTEMBER 1999 – REVISED APRIL 2013 For unbalanced operation, the receiver would be in an indeterminate logic state if the offset control input was open. Connecting the fail-safe offset pin to 5V, offsets the receiver threshold to 0.45V. The output is forced to a logic zero state if the input is open or shorted. Figure 8. Unbalanced RS-423 and RS-232 Fail-Safe Figure 9. Balanced RS-422 Fail-Safe Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS78LS120QML DS78LS120 Submit Documentation Feedback 7 DS78LS120 is OBSOLETE DS78LS120QML, DS78LS120 SNLS370C – SEPTEMBER 1999 – REVISED APRIL 2013 www.ti.com For balanced operation with inputs open or shorted, receiver C will be in an indeterminate logic state. Receivers A and B will be in a logic zero state allowing the NOR gate to detect the open or short condition. The strobe will disable receivers A and B and may therefore be used to sample the fail-safe detector. Another method of failsafe detection consists of filtering the output of NOR gate D so it would not indicate a fault condition when receiver inputs pass through the threshold region, generating an output transient. In a communications system, only the control signals are required to detect input fault conditions. Advantages of a balanced data transmission system over an unbalanced transmission system are: 1. High noise immunity 2. High data ratio 3. Long line lengths Truth Table (For Balanced Fail-Safe) Input Strobe A-Out B-Out C-Out D-Out 0 1 0 1 0 0 1 1 1 0 1 0 X 1 0 0 X 1 0 0 1 1 0 0 1 0 1 1 0 0 X 0 1 1 0 0 Schematic Diagram 8 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS78LS120QML DS78LS120 DS78LS120 is OBSOLETE DS78LS120QML, DS78LS120 www.ti.com SNLS370C – SEPTEMBER 1999 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ............................................................................................................ 8 Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS78LS120QML DS78LS120 Submit Documentation Feedback 9 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) DS78LS120J/883 ACTIVE Package Type Package Pins Package Drawing Qty CDIP NFE 16 25 Eco Plan Lead/Ball Finish (2) TBD MSL Peak Temp Op Temp (°C) Top-Side Markings (3) Call TI Call TI (4) -55 to 125 DS78LS120J/883 Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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