IXYS CPC7695BCTR Line card access switch Datasheet

CPC7695
Line Card Access Switch
INTEGRATED CIRCUITS DIVISION
Features
Description
• Improved switch dV/dt immunity of 1500V/s
• Drop-In Replacement for CPC7595
• Replaces CPC7585, and allows removal of
power-up control discrete components
• Enhanced Ringing Test Switch, SW8, breakdown
voltage
• TTL logic level inputs for 3.3V logic interfaces
• Smart logic for power-up / hot-plug state control
• Small 20-pin or 28-pin SOIC Package
• Monolithic IC reliability
• Low, matched, RON
• Eliminates the need for zero-cross switching
• Flexible switch timing for transition from Ringing
mode toTalk mode.
• Clean, bounce-free switching
• SLIC tertiary protection via integrated current
limiting, voltage clamping, and thermal shutdown
• 5V operation with power consumption <10.5 mW
• Intelligent battery monitor
The CPC7695 is a member of IXYS Integrated
Circuits Division’s third-generation Line Card Access
Switch (LCAS) family. This monolithic 10-pole line
card access switch is available in a 20-pin or 28-pin
SOIC package. It provides the necessary functions to
replace three 2-Form-C electromechanical relays on
analog line cards or combined voice and data line
cards found in central office, access, and PBX
equipment. The device contains solid state switches
for tip and ring line break, ringing injection, and test
access. The CPC7695 requires only a +5V supply and
provides stable start-up conditioning during system
power-up and for hot-plug insertion. Once active, the
inputs respond to traditional TTL logic levels, enabling
the CPC7695 to be used with 3.3V-only logic.
Ordering Information
CPC7695 part numbers are specified as shown here:
B - 28-pin SOIC delivered 29/Tube, 1000/Reel
Z - 20-pin SOIC delivered 40/Tube, 1000/Reel
Applications
•
•
•
•
•
•
•
•
•
Standard voice linecards
Integrated Voice and Data (IVD) linecards
Central office (CO)
Digital Loop Carrier (DLC)
PBX Systems
Digitally Added Main Line (DAML)
Fiber in the Loop (FITL)
Pair Gain System
Channel Banks
CPC7695 x x xx
TR - Add for Tape & Reel Version
A - With Protection SCR
B - Without Protection SCR
C - With Protection SCR and Additional Test State
TTESTin (TCHANTEST)
+5 VDC
TTESTout (TDROPTEST)
10
8 TRINGING
5
12 VDD
SW7
CPC7695
X
Tip
TLINE
7
X SW5 X SW3
X
X SW9
6 TBAT
SW1
Ring
Secondary
Protection
SLIC
SW2
RLINE 22
X
X SW10
X SW6 X SW4
SCR
Trip
Circuit
VREF
X
Switch
Control
Logic
SW8
19
RTESTout (RDROPTEST)
20 RRINGING
300Ω (min.)
VBAT
RTESTin (RCHANTEST)
DS-CPC7695-R01
RINGING
24
1
FGND
28
14 13
DGND
L
A
T
C
H
23 RBAT
17
16
15
18
INTESTin
INRINGING
INTESTout
LATCH
TSD
VBAT
NOTE 1: Pin assignments are for the 28-pin package.
NOTE 2: Block diagram shown with the optional protection SCR.
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1
CPC7695
INTEGRATED CIRCUITS DIVISION
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6.1 Break Switches: SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6.2 Ringing Return Switch: SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.6.3 Ringing Switch: SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6.4 TESTout Switches: SW5 and SW6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6.5 Ringing Test Return Switch: SW7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6.6 Ringing Test Switch: SW8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6.7 TESTin Switches: SW9 and SW10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.7 Digital I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.8 Voltage and Power Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.9 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.10 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.10.1 Truth Table for CPC7695xA and CPC7695xB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.10.2 Truth Table for CPC7695xC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 TSD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Under Voltage Switch Lock Out Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 Hot-Plug and Power-Up Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 VBAT Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Ringing To Talk State Switch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.1 Make-Before-Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.2 Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.3 Alternate Break-Before-Make Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.1 Current Limiting Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.2 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.3 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
16
17
17
17
17
18
18
18
18
18
19
20
20
20
21
21
21
21
22
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Mechanical Dimensions and PCB Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
23
23
24
25
2
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R01
CPC7695
INTEGRATED CIRCUITS DIVISION
1. Specifications
1.1 Package Pinout
1.2 Pinout
CPC7695B
28 VBAT
FGND 1
NC 2
27 NC
NC 3
26 NC
NC 4
25 NC
TTESTin 5
20 28
Pin Pin
23 RBAT
TLINE 7
22 RLINE
TRINGING 8
21 NC
20 RRINGING
NC 9
Description
1
FGND
2
NC
No connection
3
NC
No connection
4
NC
No connection
2
5
TTESTin
3
6
TBAT
Tip lead of the SLIC
4
7
TLINE
Tip lead of the line side
5
8
1
24 RTESTin
TBAT 6
Name
Fault ground
Tip lead of the TESTin bus
TRINGING Ringing generator return
TTESTout 10
19 RTESTout
NC 11
18 LATCH
6
10
VDD 12
17 IN TESTin
7
11
NC
No connection
TSD 13
16 INRINGING
8
12
VDD
+5V supply
15 INTESTout
9
13
TSD
Temperature shutdown pin
DGND 14
9
10 14
NC
Not connected
TTESTout Tip lead of the TESTout bus
DGND
Digital ground
11 15 INTESTout Logic control input
12 16 INRINGING Logic control input
CPC7695Z
FGND 1
TTESTin 2
19 RTESTin
TBAT 3
18 RBAT
TLINE 4
17 RLINE
INTESTin Logic control input
14 18
LATCH
15 19
RTESTout Ring lead of the TESTout bus
Data latch enable control input
16 20 RRINGING Ringing generator source
21
NC
No connection
17 22
RLINE
Ring lead of the line side
18 23
RBAT
Ring lead of the SLIC
19 24
RTESTin
Ring lead of the TESTin bus
TRINGING 5
16 RRINGING
25
NC
No connection
6
15 RTESTout
26
NC
No connection
NC 7
14 LATCH
27
NC
No connection
VDD 8
13 INTESTin
20 28
VBAT
Battery supply
TSD 9
12 INRINGING
DGND 10
11 INTESTout
TTESTout
R01
20 VBAT
13 17
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3
CPC7695
INTEGRATED CIRCUITS DIVISION
1.3 Absolute Maximum Ratings
Parameter
+5V power supply (VDD)
1.4 ESD Rating
Minimum Maximum
Unit
ESD Rating (Human Body Model)
1000V
-0.3
7
V
Battery Supply
-
-85
V
DGND to FGND separation
-5
+5
V
-0.3
VDD +0.3
V
Logic input to switch output
isolation
-
320
V
Switch open-contact
isolation (SW1, SW2, SW3,
SW5, SW6, SW7, SW8,
SW9, SW10)
-
320
V
Switch open-contact
isolation (SW4)
-
465
V
Operating relative humidity
5
95
%
Operating temperature
-40
+110
°C
Storage temperature
-40
+150
°C
Logic input voltage
1.5 General Conditions
Unless otherwise specified, minimum and maximum
values are production testing requirements.
Typical values are characteristic of the device at 25°C,
and are the result of engineering evaluations. They are
provided for informational purposes only, and are not
part of the manufacturing testing requirements.
Specifications cover the operating temperature range
TA = -40°C to +85°C. Also, unless otherwise specified
all testing is performed with VDD = +5VDC, logic low
input voltage is 0VDC and logic high input voltage is
+5VDC.
Absolute maximum electrical ratings are at 25°C
Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
4
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R01
CPC7695
INTEGRATED CIRCUITS DIVISION
1.6 Switch Specifications
1.6.1 Break Switches: SW1 and SW2
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW1 (differential) = TLINE to TBAT
VSW2 (differential) = RLINE to RBAT
All-Off state.
Off-State
Leakage Current
+25°C,
VSW (differential) = -320V to GND
VSW (differential) = +260V to -60V
0.1
+85°C,
VSW (differential) = -330V to GND
VSW (differential) = +270V to -60V
ISW
-
-40°C,
VSW (differential) = -310V to GND
VSW (differential) = +250V to -60V
0.3
0.1
ISW(on) = ±10mA, ±40mA,
RBAT and TBAT = -2V
On-Resistance
+25°C
RON
+85°C
-
-40°C
On-Resistance
Matching
Per SW1 & SW2 On-Resistance test
conditions.
14.5
-
20.5
28
10.5
-
0.15
0.55

RON
-
-
225
ISW
80
150
-
400
425
-
2.5
-
A
-
0.1
-
0.3
1
A
-
0.1
1500
2100
-
V/s

VSW (on) = ±10V
DC current limit
+25°C
+85°C
-40°C
Dynamic current limit
(t 0.5 s)
Break switches on, all other switches
off. Apply ±1kV 10x1000s pulse with
appropriate protection in place.
ISW
-
mA
Logic inputs = GND
Logic input to switch
output isolation
+25°C, VSW (TLINE, RLINE) = ±320V
+85°C, VSW (TLINE, RLINE) = ±330V
ISW
-40°C, VSW (TLINE, RLINE) = ±310V
Transient Immunity
R01
100VPP Square Wave, 100Hz
(Not production tested - limits are
guaranteed by design and quality
control sampling audits.)
dV/dt
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5
CPC7695
INTEGRATED CIRCUITS DIVISION
1.6.2 Ringing Return Switch: SW3
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW3 (differential) = TLINE to TRINGING
All-Off state.
Off-State
Leakage Current
+25°C,
VSW (differential) = -320V to GND
VSW (differential) = +260V to -60V
0.1
+85°C,
VSW (differential) = -330V to GND
VSW (differential) = +270V to -60V
ISW
-
-40°C,
VSW (differential) = -310V to GND
VSW (differential) = +250V to -60V
0.3
0.1
ISW(on) = ±0mA, ±10mA
On-Resistance
+25°C
RON
+85°C
-
-40°C
60
-
85
110
45
-

VSW (on) = ± 10V
DC current limit
+25°C
ISW
+85°C
-40°C
Dynamic current limit
(t 0.5 s)
Ringing switches on, all other switches
off. Apply ±1kV 10x1000s pulse with
appropriate protection in place.
ISW
-
120
70
85
-
210
-
2.5
-
mA
-
A
1
A
-
V/s
Logic inputs = GND
Logic input to switch
output isolation
+25°C, VSW (TRINGING, TLINE)= ±320V
+85°C, VSW (TRINGING, TLINE)= ±330V
0.1
ISW
-
-40°C, VSW (TRINGING, TLINE) = ±310V
Transient Immunity
6
100VPP Square Wave, 100Hz
(Not production tested - limits are
guaranteed by design and quality
control sampling audits.)
0.3
0.1
dV/dt
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1500
2100
R01
CPC7695
INTEGRATED CIRCUITS DIVISION
1.6.3 Ringing Switch: SW4
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW4 (differential) = RLINE to RRINGING
All-Off state.
Off-State
Leakage Current
+25°C
VSW (differential) = -255V to +210V
VSW (differential) = +255V to -210V
+85°C
VSW (differential) = -270V to +210V
VSW (differential) = +270V to -210V
0.05
ISW
-
-40°C
VSW (differential) = -245V to +210V
VSW (differential) = +245V to -210V
0.1
0.05
On-Resistance
ISW (on) = ±70mA, ±80mA
RON
-
10
15

On Voltage
ISW (on) = ± 1mA
VON
-
1.5
3
V
On-State
Leakage Current
Inputs set for ringing -Measure ringing
generator current to ground.
IRINGING
-
0.1
0.25
mA
Steady-State Current*
Inputs set for Ringing mode.
ISW
-
-
150
mA
Surge Current*
Ringing switches on, all other switches
off. Apply ±1kV 10x1000s pulse with
appropriate protection in place.
ISW
-
-
2
A
Release Current
SW4 transition from on to off.
IRINGING
-
450
-
A
1
A
-
V/s
Logic inputs = GND
Logic input to switch
output isolation
+25°C, VSW (RRINGING, RLINE)=±320V
+85°C, VSW (RRINGING, RLINE)=±330V
0.1
ISW
-
-40°C, VSW (RRINGING, RLINE)= ±310V
Transient Immunity
100VPP Square Wave, 100Hz
(Not production tested - limits are
guaranteed by design and quality
control sampling audits.)
0.3
0.1
dV/dt
1500
2100
*Secondary protection and current limiting must prevent exceeding this parameter.
R01
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7
CPC7695
INTEGRATED CIRCUITS DIVISION
1.6.4 TESTout Switches: SW5 and SW6
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW5 (differential) = TLINE to TTESTOUT
VSW6 (differential) = RLINE to RTESTOUT
All-Off state.
Off-State
Leakage Current
+25°C,
VSW (differential) = -320V to GND
VSW (differential) = +260V to -60V
0.1
+85°C
VSW (differential) = -330V to GND
VSW (differential) = +260V to -60V
ISW
-
-40°C
VSW (differential) = -310V to GND
VSW (differential) = +250V to -60V
0.3
0.1
ISW (on) = ±10mA, ±40mA
On-Resistance
+25°C
RON
+85°C
-
-40°C
35
-
50
70
26
-
140
-

VSW (on) = ±10V
DC current limit
-
+25°C
ISW
+85°C
-40°C
Dynamic current limit
(t 0.5 s)
Logic input to switch
output isolation
Test out switches on, all other switches
off. Apply ±1kV, 10x1000s pulse with
appropriate protection in place.
ISW
80
100
-
-
210
250
-
2.5
-
A
1
A
-
V/s
VSW5 (TTESTout, TLINE)
VSW6 (RTESTout, RLINE)
Logic inputs = GND
+25°C, VSW = ±320V
0.1
+85°C, VSW = ±330V
ISW
-
-40°C, VSW = ±310V
Transient Immunity
8
mA
0.3
0.1
100VPP Square Wave, 100Hz
(Not production tested - limits are
guaranteed by design and quality
control sampling audits.)
dV/dt
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1500
2100
R01
CPC7695
INTEGRATED CIRCUITS DIVISION
1.6.5 Ringing Test Return Switch: SW7
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW7 (differential) = TTESTin to
TRINGING
All-Off state.
Off-State
Leakage Current
+25°C,
VSW (differential) = -320V to GND
VSW (differential) = +260V to -60V
0.1
+85°C,
VSW (differential) = -330V to GND
VSW (differential) = +270V to -60V
ISW
-
-40°C,
VSW (differential) = -310V to GND
VSW (differential) = +250V to -60V
0.3
0.1
ISW (on) = ±10mA, ±40mA
On-Resistance
+25°C
RON
+85°C
-
-40°C
60
-
85
100
45
-

VSW (on) = ±10V
DC current limit
-
+25°C
ISW
+85°C
-40°C
120
60
80
-
210
-
mA
1
A
-
V/s
Logic inputs = GND
Logic input to switch
output isolation
+25°C, VSW(TRINGING, TTESTin)=±320V
+85°C, VSW(TRINGING, TTESTin)=±330V
0.1
ISW
-
-40°C, VSW(TRINGING, TTESTin)=±310V
Transient Immunity
R01
100VPP Square Wave, 100Hz
(Not production tested - limits are
guaranteed by design and quality
control sampling audits.)
0.3
0.1
dV/dt
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1500
2100
9
CPC7695
INTEGRATED CIRCUITS DIVISION
1.6.6 Ringing Test Switch: SW8
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW8 (differential) = RTESTin to
RRINGING
All-Off state.
Off-State
Leakage Current
+25°C,
VSW (differential) = -320V to GND
VSW (differential) = +320V to GND
0.1
+85°C
VSW (differential) = -330V to GND
VSW (differential) = +330V to GND
ISW
-
-40°C
VSW (differential) = -310V to GND
VSW (differential) = +310V to GND
0.3
0.1
ISW (on) = ±10mA, ±40mA
On-Resistance
+25°C
RON
+85°C
-
-40°C
35
-
50
70
26
-
140
-

VSW (on) = ±10V
DC current limit
-
+25°C
ISW
+85°C
-40°C
Dynamic current limit
(t 0.5 s)
Ringing test switches on, all other
switches off. Apply ±1kV, 10x1000s
pulse with appropriate protection in
place.
ISW
80
100
-
-
210
250
mA
-
2.5
-
A
1
A
-
V/s
VSW8 (RRINGING, RTESTin)
Logic inputs = GND
Logic input to switch
output isolation
+25°C, VSW = ±320V
0.1
+85°C, VSW = ±330V
ISW
-
-40°C, VSW = ±310V
Transient Immunity
10
0.3
0.1
100VPP Square Wave, 100Hz
(Not production tested - limits are
guaranteed by design and quality
control sampling audits.)
dV/dt
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1500
2100
R01
CPC7695
INTEGRATED CIRCUITS DIVISION
1.6.7 TESTin Switches: SW9 and SW10
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
1
A
VSW9 (differential) = TTESTin to TBAT
VSW10 (differential) = RTESTin to RBAT
All-Off state.
Off-state leakage
current
+25°C,
VSW (differential) = -320V to GND
VSW (differential) = +260V to -60V
0.1
+85°C,
VSW (differential) = -330V to GND
VSW (differential) =+270V to -60V
ISW
-
-40°C,
VSW (differential) = -310V to GND
VSW (differential) = +250V to -60V
0.3
0.1
ISW (on) = ±10mA, ±40mA
On-Resistance
+25°C
RON
+85°C
-
-40°C
35
-
50
70
26
-
160
-

VSW (on) = ±10V
DC current limit
-
+25°C
ISW
+85°C
-40°C
80
110
-
-
210
250
mA
Logic inputs = GND
Logic input to switch
output isolation
+25°C, VSW(TTESTin, RTESTin) = ±320V
+85°C, VSW(TTESTin, RTESTin) = ±330V
0.1
ISW
-
-40°C, VSW (TTESTin, RTESTin) = ±310V
Transient Immunity
R01
100VPP Square Wave, 100Hz
(Not production tested - limits are
guaranteed by design and quality
control sampling audits.)
0.3
1
A
-
V/s
0.1
dV/dt
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1500
2100
11
CPC7695
INTEGRATED CIRCUITS DIVISION
1.7 Digital I/O Electrical Specifications
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
Input voltage falling
VIL
0.8
1.1
-
Input voltage rising
VIH
-
1.7
2.0
Input leakage current,
INRINGING, INTESTin,
VDD = 5.5V, VBAT = -75V, VIH = 2.4V
and INTESTout Logic high
IIH
-
0.1
1
A
Input leakage current,
INRINGING, INTESTin,
VDD = 5.5V, VBAT = -75V, VIL = 0.4V
and INTESTout Logic low
IIL
-
0.1
1
A
Input leakage current,
LATCH Logic high
VDD = 4.5V, VBAT = -75V, VIH = 2.4V
IIH
10
19
-
A
Input leakage current,
LATCH Logic low
VDD = 5.5V, VBAT = -75V, VIL = 0.4V
IIL
-
47
125
A
Input leakage current,
TSD Logic high
VDD = 5.5V, VBAT = -75V, VIH = VDD
IIH
10
16
30
A
Input leakage current,
TSD Logic low
VDD = 5.5V, VBAT = -75V, VIL = 0.4V
IIL
10
16
30
A
Input Characteristics
Input voltage, Logic low
Input voltage, Logic high
V
Output Characteristics
Output voltage,
TSD Logic high
VDD = 5.5V, VBAT = -75V, ITSD = 10A
VTSD_off
2.4
VDD
-
V
Output voltage,
TSD Logic low
VDD = 5.5V, VBAT = -75V, ITSD = 1mA
(Not production tested - limits are
guaranteed by design and quality
control sampling audits.)
VTSD_on
-
0
0.4
V
12
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R01
CPC7695
INTEGRATED CIRCUITS DIVISION
1.8 Voltage and Power Specifications
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
VDD
-
VDD
4.5
5.0
5.5
V
VBAT1
-
VBAT
-19
-48
-72
V
Voltage Requirements
1
VBAT is used only for internal protection circuitry. If VBAT rises above -10V, the device will enter the All-Off state and will remain in the All-Off state until the battery
drops below -15V
Power Specifications
Power consumption
VDD = 5V, VBAT = -48V, VIH = 2.4V,
VIL = 0.4V, Measure IDD and IBAT
Talk and All-Off States
All other states
VDD current
-
IDD
-
IBAT
-
4.7
10.5
mW
5.2
10.5
mW
VDD = 5V, VBAT = -48V, VIH = 2.4V,
VIL = 0.4V
Talk and All-Off states
All other states
V = 5V, VBAT = -48V, VIH = 2.4V,
VBAT current in any state DD
VIL = 0.4V
R01
P
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0.9
2.0
1.0
2.0
4
10
mA
A
13
CPC7695
INTEGRATED CIRCUITS DIVISION
1.9 Protection Circuitry Electrical Specifications
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
2.8
3.5
Unit
Protection Diode Bridge
Forward Voltage drop,
continuous current
(50/60 Hz)
Apply ± DC current limit of break
switches
Forward Voltage drop,
surge current
Apply ± dynamic current limit of break
switches
VF
-
V
5
-
-
*
A
-
mA
-
mA
Protection SCR (CPC7695xA and CPC7695xC)
Surge current
Trigger current:
Current into VBAT pin.
SCR activates, +25°C
SCR activates, +85°C
SCR remains active, +25°C
Hold current: Current
through protection SCR SCR remains active, +85°C
Gate trigger voltage
IGATE = ITRIGGER§
Reverse leakage current VBAT = -48V
On-state voltage
0.5A, t = 0.5 s
2.0A, t = 0.5 s
ITRIG
-
150
80
-
220
110
145
VTBAT or
VRBAT
VBAT -4
-
VBAT -2
V
IVBAT
-
-
1.0
A
VTBAT or
VRBAT
-
-
V
TTSD_on
110
125
150
°C
TTSD_off
10
-
25
°C
IHOLD
-3
-5
Temperature Shutdown Specifications
Shutdown activation
temperature
Shutdown circuit
hysteresis
Not production tested - limits are
guaranteed by design and Quality
Control sampling audits.
*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.
§
VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate.
14
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R01
CPC7695
INTEGRATED CIRCUITS DIVISION
1.10 Truth Tables
1.10.1 Truth Table for CPC7695xA and CPC7695xB
TESTin
Switches
Break
Switches
Ringing
Test
Switches
Ringing
Switches
TESTout
Switches
0
Off
On
Off
Off
Off
0
1
Off
Off
Off
Off
On
On
Off
Off
Off
Off
On
Off
Off
Off
On
Off
Off
Off
On
Off
Off
Off
On
Off
Off
State
INRINGING
INTESTin
INTESTout
Talk
0
0
TESTout
0
Latch
TSD
TESTin
0
1
0
Simultaneous
TESTin and
TESTout
0
1
1
Ringing
1
0
0
Ringing
Generator
Test
1
1
0
Latched
X
X
X
1
1
0
1
0
Off
Off
Off
Off
Off
1
1
1
0
Off
Off
Off
Off
Off
X
X
X
X
Off
Off
Off
Off
Off
All-Off
1
0
Z1
Unchanged Unchanged Unchanged Unchanged Unchanged
0
Z = High Impedance. Because TSD has an internal pull up at this pin, it should be controlled with an open-collector or open-drain type device.
1.10.2 Truth Table for CPC7695xC
TESTin
Switches
Break
Switches
Ringing
Test
Switches
Ringing
Switches
TESTout
Switches
0
Off
On
Off
Off
Off
0
1
Off
Off
Off
Off
On
State
INRINGING
INTESTin
INTESTout
Talk
0
0
TESTout
0
Latch
TSD
TESTin
0
1
0
On
Off
Off
Off
Off
Simultaneous
TESTin and
TESTout
0
1
1
On
Off
Off
Off
On
Ringing
1
0
0
Off
Off
Off
On
Off
Ringing
Generator
Test
1
1
0
Off
Off
On
Off
Off
Simultaneous
TESTout and
Ringing
Generator
Test
1
1
1
Off
Off
On
Off
On
Latched
X
X
X
1
1
0
1
0
X
X
X
X
All-Off
1
0
Z1
Unchanged Unchanged Unchanged Unchanged Unchanged
0
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Z = High Impedance. Because TSD has an internal pull up at this pin, it should be controlled with an open-collector or open-drain type device.
R01
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15
CPC7695
INTEGRATED CIRCUITS DIVISION
2. Functional Description
2.1 Introduction
The CPC7695 has the following states:
• Talk. Loop break switches SW1 and SW2 closed, all
other switches open.
• Ringing. Ringing switches SW3 and SW4 closed, all
other switches open.
• TESTout. Testout switches SW5 and SW6 closed,
all other switches open.
• Ringing generator test. SW7 and SW8 closed, all
other switches open.
• TESTin. Testin switches SW9 and SW10 closed, all
other switches open.
• Simultaneous TESTin and TESTout. SW9, SW10,
SW5, and SW6 closed, all other switches open.
• Simultaneous TESTout and Ringing generator
test. SW5, SW6, SW7, and SW8 closed, all other
switches open (only on the xC and xD versions).
• All-Off. All switches open.
See “Truth Tables” on page 15 for more information.
The CPC7695 offers break-before-make and
make-before-break switching from the Ringing state to
theTalk state with simple TTL level logic input control.
Solid-state switch construction means no impulse
noise is generated when switching during ringing
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State-control is via TTL
logic-level input so no additional driver circuitry is
required. The linear line break switches SW1 and
SW2 have exceptionally low RON and excellent
matching characteristics. The ringing switch, SW4,
has a minimum open contact breakdown voltage of
465V at +25°C, sufficiently high with proper protection
to prevent breakdown in the presence of a transient
fault condition (i.e., prevent passing the transient on to
the ringing generator).
Integrated into the CPC7695 is an over-voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection to the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the current
limiting circuitry and hazardous potentials are diverted
away from the SLIC via the protection diode bridge or
the optional integrated protection SCR. Power-cross
potentials are also reduced by the current limiting and
thermal shutdown circuits.
16
To protect the CPC7695 from an overvoltage fault
condition, the use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the TLINE and RLINE terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
highly recommended. With proper selection of the
secondary protector, a line card using the CPC7695
will meet all relevant ITU, LSSGR, TIA/EIA and IEC
protection requirements.
The CPC7695 operates from a single +5V supply only.
This gives the device extremely low idle and active
power consumption with virtually any range of battery
voltage. The battery voltage used by the CPC7695
has a two fold function. For protection purposes it is
used as a fault condition current source by the internal
integrated protection circuitry. Secondly, it is used as a
reference so that in the event of battery voltage loss,
the CPC7695 will enter the All-Off state.
2.2 Start-up
The CPC7695 uses smart logic to monitor the VDD
supply. Any time VDD is below an internally set
threshold, the smart logic places the control logic into
the All-Off state. An internal pullup on the LATCH pin
locks the CPC7695 in the All-Off state following
start-up until the LATCH pin is pulled down to a logic
low. Prior to the assertion of a logic low at the LATCH
pin, the switch control inputs must be properly
conditioned.
2.3 Data Latch
The CPC7695 has an integrated transparent data
latch. Operation of the latch enable is controlled by
TTL logic input levels at the LATCH pin. Data input to
the latch are via the input pins, while the output of the
data latch are internal nodes used for state control.
When the LATCH enable control pin is at logic 0 the
data latch is transparent and the input data control
signals flow directly through the latch to the state
control circuitry. A change in input will be reflected by a
change in switch state. Whenever the LATCH enable
control pin is at logic 1, the latch is active and data is
locked. Subsequent input changes will not result in a
change to the control logic or affect the existing switch
state.
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CPC7695
INTEGRATED CIRCUITS DIVISION
Switches will remain in the state they were in when the
LATCH pin changes from logic 0 to logic 1 and will not
respond to changes in input as long as the latch is at
logic 1. However, neither the TSD input nor the TSD
output control functions are affected by the latch
function. Internal thermal shutdown control and
external “All-Off” control via TSD is not affected by the
state of the LATCH enable input.
2.4 TSD Pin Description
The TSD pin is a bidirectional I/O structure with an
internal pull up sourced from VDD. As an output, this
pin indicates the status of the thermal shutdown
circuitry. Typically, during normal operation, this pin will
be pulled up to VDD but under fault conditions that
create excess thermal loading the CPC7695 will enter
thermal shutdown and a logic low will be output.
As an input, the TSD pin can be utilized to place the
CPC7695 into the “All-Off” state by simply pulling the
input low via an open-collector type buffer. Using a
standard output having an active logic high drive
capability will need to sink the TSD pull-up current to
attain a logic low resulting in unnecessary power
consumption.
Use of a standard output buffer with an active high
drive capability, or tying TSD to VDD, will not disable the
thermal shutdown mechanism. The ability to enter
thermal shutdown during a fault condition is
independent of the connection at the TSD input.
The CPC7695’s internal pull up has a nominal value of
16A.
2.5 Under Voltage Switch Lock Out Circuitry
2.5.1 Overview
Smart logic in the CPC7695 now provides for switch
state control during both power-up and power-loss
transitions. An internal detector is used to evaluate the
VDD supply to determine when to de-assert the under
voltage switch lock out circuitry with a rising VDD and
when to assert the under voltage switch lock out
circuitry with a falling VDD. Any time unsatisfactory low
VDD conditions exist, the lock out circuit overrides user
R01
switch control by blocking the information at the
external input pins and conditioning internal switch
commands to the All-Off state. Upon restoration of
VDD, the switches will remain in the All-Off state until
the LATCH input is pulled low.
The rising VDD switch lock-out release threshold is
internally set to ensure all internal logic is properly
biased and functional before accepting external switch
commands at the inputs to control the switch states.
For a falling VDD event, the lock-out threshold is set to
assure proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed.
To facilitate hot plug insertion and system power-up
state control, the LATCH pin has an integrated weak
pull up resistor to the VDD power rail that will hold a
non-driven LATCH pin at a logic high state. This
enables board designers to use the CPC7695 with
FPGAs and other devices that provide high
impedance outputs during power-up and logic
configuration. The weak pull up allows a fan out of up
to 32 when the system’s LATCH control driver has a
logic low minimum sink capability of 4mA.
2.5.2 Hot-Plug and Power-Up Design Considerations
There are six possible start up scenarios that can
occur during power-up. They are:
1.
2.
3.
4.
5.
6.
All inputs defined at power-up & LATCH = 0
All inputs defined at power-up & LATCH = 1
All inputs defined at power-up & LATCH = Z
All inputs not defined at power-up & LATCH = 0
All inputs not defined at power-up & LATCH = 1
All inputs not defined at power-up & LATCH = Z
Under all of the start up situations listed above the
CPC7695 will hold all of it’s switches in the All-Off
state during power-up. When VDD requirements have
been satisfied the LCAS will complete it’s start up
procedure in one of three conditions.
For start up scenario 1, the CPC7695 will transition
from the All-Off state to the state defined by the inputs
when VDD is valid.
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17
CPC7695
INTEGRATED CIRCUITS DIVISION
For start up scenarios 2, 3, 5, and 6 the CPC7695 will
power up in the All-Off state and remain there until the
LATCH pin is pulled low. This allows for an indefinite
All-Off state for boards inserted into a powered system
but are not configured for service or boards that need
to wait for other devices to be configured first.
Start up scenario 4 will start up with all switches in the
All-Off state but upon the acceptance of a valid VDD
the LCAS will revert to any one of the legitimate states
listed in the truth tables and there after may randomly
change states based on input pin leakage currents
and loading. Because the LCAS state after power-up
can not be predicted with this start up condition it
should never be utilized.
On designs that do not wish to individually control the
LATCH pins of multi-port cards it is possible to bus
many (or all) of the LATCH pins together to create a
single board level input enable control.
2.6 VBAT Pin
2.6.1 Protection
available techniques are referred to as
make-before-break and break-before-make operation.
When the switch contacts of SW1 and SW2 are closed
(made) before the ringing switch contacts of SW3 and
SW4 are opened (broken), this is referred to as
make-before-break operation. Break-before-make
operation occurs when the ringing contacts of SW3
and SW4 are opened (broken) before the switch
contacts of SW1 and SW2 are closed (made). With
the CPC7695, make-before-break and
break-before-make operations can easily be
accomplished by applying the proper sequence of
logic-level inputs to the device.
The logic sequences for either mode of operation are
given in “Operation Logic Table (Ringing to Talk Transition):
Make-Before-Break” on page 19, “Operation Logic Table
(Ringing to Talk Transition): Break-Before-Make” on page 19
and “Alternate Operation Logic Table (Ringing to Talk
Transition): Break-Before-Make” on page 20. Logic states
and explanations are shown in “Truth Tables” on
page 15.
2.7.1 Make-Before-Break Operation
2.6.2 Battery Voltage Monitor
The CPC7695 also uses the VBAT pin to monitor
battery voltage. If the system battery voltage is lost,
the CPC7695 immediately enters the All-Off state. It
remains in this state until the system battery voltage is
restored. The device also enters the All-Off state if the
battery voltage rises more positive than about –10V
and remains in the All-Off state until the battery
voltage drops below –15 V. This battery monitor
feature draws a small current from the battery (less
than 1 A typical) and will add slightly to the device’s
overall power dissipation.
To use make-before-break operation, change the logic
inputs from the Ringing state directly to theTalk state.
Application of theTalk state opens the ringing return
switch, SW3, as the break switches SW1 and SW2
close. The ringing switch, SW4, remains closed until
the next zero-crossing of the ringing current. While in
the make-before-break state, ringing potentials in
excess of the CPC7695 internal protection circuitry
thresholds will be diverted away from the SLIC.
This monitor function performs properly if the
CPC7695 and SLIC share a common battery supply
origin. Otherwise, if battery is lost to the CPC7695 but
not to the SLIC, the VBAT pin will be internally biased
by the potential applied to the TBAT or RBAT pins via
the internal protection circuitry’s SCR trigger current
path.
2.7 Ringing To Talk State Switch Timing
The CPC7695 provides, when switching from the
Ringing state to theTalk state, the ability to control the
release timing of the ringing switches SW3 and SW4
relative to the state of the break switches SW1 and
SW2 using simple TTL logic-level inputs. The two
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INTEGRATED CIRCUITS DIVISION
Operation Logic Table (Ringing to Talk Transition): Make-Before-Break
State
Ringing
INRINGING INTESTin INTESTout
1
0
TSD
Latch
Timing
Ringing
Ringing
Break
Test
Return
Switch
Switches Switch
Switches
(SW4)
(SW3)
0
-
Off
On
On
Off
SW4 waiting for next
zero-current crossing to turn
off. Maximum time is one-half
of the ringing cycle. In this
transition state, current that is
limited to the break switch
DC current limit value will be
sourced from the ring node of
the SLIC.
On
Off
On
Off
Zero-cross current has
occurred
On
Off
Off
Off
MakeBeforeBreak
0
0
0
Talk
0
0
0
0
Z
2.7.2 Break-Before-Make Operation
Break-before-make operation of the CPC7695 can be
achieved using two different techniques.
The first method uses manipulation of the (INRINGING,
INTESTin, INTESTout) logic inputs as shown below in the
“Operation Logic Table (Ringing to Talk Transition):
Break-Before-Make” on page 19.
1. At the end of the Ringing state apply the All-Off
state (1,0,1). This releases the ringing return
switch (SW3) while the ringing switch (SW4)
remains active waiting for the next zero current
event.
2. Hold the All-Off state for at least one-half of a
ringing cycle to assure that a zero crossing event
occurs and that the ringing switch has opened.
3. Apply inputs for the next desired state. For
theTalk state, the inputs would be (0,0,0).
Break-before-make operation occurs when the ringing
switch opens before the break switches SW1 and
SW2 close.
Operation Logic Table (Ringing to Talk Transition): Break-Before-Make
State
Ringing
All-Off *
INRINGING INTESTin INTESTout Latch
1
1
0
0
TSD
Timing
Ringing
Ringing
Break
Test
Return
Switch
Switches Switch
Switches
(SW4)
(SW3)
0
-
Off
On
On
Off
1
Hold this state for at least
one-half of ringing cycle. SW4
waiting for zero current to turn off.
Off
Off
On
Off
0
Z
BreakBeforeMake *
1
0
1
Zero current has occurred. SW4
has opened
Off
Off
Off
Off
Talk
0
0
0
Break switches close.
On
Off
Off
Off
* For the CPC7695xA/B versions the input pattern (1,1,1) may also be used for the All-Off state.
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CPC7695
INTEGRATED CIRCUITS DIVISION
2.7.3 Alternate Break-Before-Make Operation
The second break-before-make method is also
available for use with all versions of the CPC7695. As
shown in “Truth Table for CPC7695xA and CPC7695xB” on
page 15 and “Truth Table for CPC7695xC” on page 15,
when pulled to a logic low the bidirectional TSD
interface disables all of the CPC7695 switches.
Although logically disabled, an active (closed) ringing
switch (SW4) will remain closed until the next current
zero crossing event.
As shown in the table “Operation Logic Table (Ringing to
Talk Transition): Break-Before-Make” on page 19, this
operation is similar to the one shown in “Alternate
Operation Logic Table (Ringing to Talk Transition):
Break-Before-Make” on page 20, except in the method
used to select the All-Off state and when the
INRINGING, INTESTin and INTESTout inputs are
reconfigured for theTalk state.
1. Pull TSD to a logic low to end the Ringing state.
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
2. Keep TSD low for at least one-half the duration of
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break before make state.
3. During the TSD low period, set the INRINGING,
INTESTin and INTESTout inputs to theTalk state
(0,0,0).
4. Release TSD allowing the internal pull-up to
activate the break switches.
When using TSD as an input, the two recommended
states are “0,” which overrides the logic inputs while
forcing an All-Off state, and “Z,” which allows switch
control via the logic input pins. This requires the use of
an open-collector or open-drain type buffer.
Alternate Operation Logic Table (Ringing to Talk Transition): Break-Before-Make
State
INRINGING INTESTin INTESTout Latch
Ringing
1
0
0
All-Off
1
0
1
0
X
BreakBeforeMake
0
0
0
Talk
0
0
0
0
Ringing
Ringing
Break
Test
Return
Switch
Switches Switch
Switches
(SW4)
(SW3)
TSD
Timing
Z
-
Off
On
On
Off
Hold this state for at least
one-half of ringing cycle. SW4
waiting for zero current to turn off.
Off
Off
On
Off
Zero current has occurred. SW4
has opened
Off
Off
Off
Off
Break switches close.
On
Off
Off
Off
0
Z
* For the CPC7695xA/B versions the input pattern (1,1,1) may also be used for the All-Off state.
2.8 Ringing Switch Zero-Cross Current Turn Off
After the application of a logic input to turn SW4 off,
the ringing switch is designed to delay the change in
state until the next zero-crossing. Once active, the
switch requires a zero-current crossing to turn off, and
therefore should not be used to switch a pure DC
signal. The switch will remain in the on state no matter
the logic input until the next zero crossing. These
switching characteristics will reduce and possibly
eliminate overall system impulse noise normally
associated with ringing switches. See IXYS Integrated
Circuits Division application note AN-144, Impulse Noise
20
Benefits of Line Card Access Switches for more
information. The attributes of ringing switch SW4 may
make it possible to eliminate the need for a zero-cross
switching scheme. A minimum impedance of 300 in
series with the ringing generator is recommended.
2.9 Power Supplies
Both a +5V supply and battery voltage are connected
to the CPC7695. Switch state control is powered
exclusively by the +5V supply. As a result, the
CPC7695 exhibits extremely low power consumption
during active and idle states.
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INTEGRATED CIRCUITS DIVISION
Although battery power is not used for switch control, it
is required to supply trigger current for the integrated
internal protection circuitry SCR during fault
conditions. This integrated SCR is designed to
activate whenever the voltage at TBAT or RBAT drops
2V to 4V below the applied voltage on the VBAT pin.
Because the battery supply at this pin is required to
source trigger current during negative overvoltage
fault conditions at tip and ring, it is important that the
net supplying this current be a low impedance path for
high speed transients such as lightning. This will
permit trigger currents to flow enabling the SCR to
activate and thereby prevent a fault induced negative
overvoltage event at the TBAT or RBAT nodes.
2.10 Protection
2.10.1 Current Limiting Function
If a lightning strike transient occurs when the device is
in theTalk state, the current is passed along the line to
the integrated protection circuitry and restricted by the
dynamic current limit response of the active switches.
During theTalk state when a 1000V 10x1000 S pulse
(GR-1089-CORE lightning) is applied to the line
though a properly clamped external protector, the
current seen at TLINE or RLINE will be a pulse with a
typical magnitude of 2.5A and a duration of less than
0.5 s.
If a power-cross fault occurs with the device in theTalk
state, the current is passed though the break switches
SW1 and SW2 on to the integrated protection circuit
but is limited by the dynamic DC current limit response
of the two break switches. The DC current limit
specified over temperature is between 80mA and
425mA, and the circuitry has a negative temperature
coefficient. As a result, if the device is subjected to
extended heating due to a power-cross fault condition,
the measured current into TLINE or RLINE will decrease
as the device temperature increases. If the device
temperature rises sufficiently, the thermal shutdown
mechanism will activate and the device will enter the
All-Off state.
2.10.2 Diode Bridge/SCR
The CPC7695 uses a combination of current limited
break switches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device and other associated circuitry from
damage during line transient events such as lightning.
During a positive transient condition, the fault current
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is conducted through the diode bridge to ground via
FGND. Voltage is clamped to a diode drop above
ground. During a negative transient of 2V to 4V more
negative than the voltage source at VBAT, the SCR
conducts and faults are shunted to FGND via the SCR.
Devices utilizing the diode bridge will steer negative
transients to VBAT.
In order for the SCR to crowbar or foldback, the SCR’s
on-voltage (see “Protection Circuitry Electrical
Specifications” on page 14) must be less than the
applied voltage at the VBAT pin. If the VBAT voltage is
less negative than the SCR on-voltage, or if the VBAT
supply is unable to source the trigger current, the SCR
will not crowbar.
For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to a diode
drop above ground and the fault current is directed to
ground. The negative cycle of the transient will cause
the SCR to conduct when the voltage exceeds the
VBAT reference voltage by two to four volts, steering
the fault current to ground.
Note: The CPC7695xB does not contain a protection
SCR but instead utilizes a diode bridge to clamp both
polarities of a fault transient. These diodes pass the
charge of negative fault potentials to the VBAT pin.
2.10.3 Thermal Shutdown
The thermal shutdown mechanism will activate when
the device die temperature reaches a minimum of
110°C, placing the device in the All-Off state
regardless of INRINGING, INTESTin and INTESTout logic
inputs. During thermal shutdown events the TSD pin
will output a logic low with a nominal 0V level. A logic
high is output from the TSD pin during normal
operation with a typical output level equal to VDD.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown mechanism will activate forcing the switches
to the All-Off state. At this point the current measured
into TLINE or RLINE will drop to zero. Once the device
enters thermal shutdown it will remain in the All-Off
state until the temperature of the die drops below the
deactivation level of the thermal shutdown circuit. This
permits the device to return to normal operation. If the
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CPC7695
INTEGRATED CIRCUITS DIVISION
transient has not passed, current will again flow up to
the value allowed by the dynamic DC current limiting
of the switches and heating will resume, reactivating
the thermal shutdown mechanism. This cycle of
entering and exiting the thermal shutdown mode will
continue as long as the fault condition persists. If the
magnitude of the fault condition is great enough, the
external secondary protector will activate shunting the
fault current to ground.
2.11 External Protection Elements
The CPC7695 requires only over voltage secondary
protection on the loop side of the device. The
integrated protection feature described above negates
the need for additional external protection on the SLIC
side. The secondary protector must limit voltage
transients to levels that do not exceed the breakdown
voltage or input-output isolation barrier of the
CPC7695. A foldback or crowbar type protector is
recommended to minimize stresses on the CPC7695.
Consult IXYS Integrated Circuits Division’s application
note, AN-100, Designing Surge and Power Fault Protection
Circuits for Solid State Subscriber Line Interfaces for
equations related to the specifications of external
secondary protectors, fused resistors and PTCs.
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3. Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
All Versions
MSL 1
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.
3.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020
must be observed.
Device
Maximum Temperature x Time
All Versions
260°C for 30 seconds
3.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
Pb
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CPC7695
INTEGRATED CIRCUITS DIVISION
3.5 Mechanical Dimensions and PCB Land Patterns
CPC7695Zx Package
Recommended PCB Land Pattern
12.757 ± 0.254
(0.502 ± 0.010)
1.27
(0.050)
PIN 20
10.312 ± 0.381
(0.406 ± 0.015)
7.493 ± 0.127
(0.295 ± 0.005)
9.40
(0.370)
2.00
(0.079)
PIN 1
0.406 ± 0.076
(0.016 ± 0.003)
1.270 TYP
(0.050 TYP)
0.60
(0.024)
45º
2.337 ± 0.051
(0.092 ± 0.002)
0.203 ± 0.102
(0.008 ± 0.004)
0.649 ± 0.102
(0.026 ± 0.004)
0.889 ± 0.178
(0.035 ± 0.007)
0.254 / +0.051 / -0.025
(0.010 / +0.002 / -0.001)
DIMENSIONS
mm
(inches)
NOTES:
1. Coplanarity = 0.1016 (0.004) max.
2. Leadframe thickness does not include solder plating (1000 microinch maximum).
CPC7695Bx Package
Recommended PCB Land Pattern
17.932 ± 0.254
(0.706 ± 0.010)
1.27
(0.050)
PIN 28
10.312 ± 0.381
(0.406 ± 0.015)
7.493 ± 0.127
(0.295 ± 0.005)
9.40
(0.370)
2.00
(0.079)
PIN 1
1.270 TYP
(0.050 TYP)
0.406 ± 0.076
(0.016 ± 0.003)
0.60
(0.024)
2.337 ± 0.051
(0.092 ± 0.002)
0.649 ± 0.102
(0.026 ± 0.004)
45º
0.203 ± 0.102
(0.008 ± 0.004)
0.889 ± 0.178
(0.035 ± 0.007)
NOTES:
1. Coplanarity = 0.1016 (0.004) max.
2. Leadframe thickness does not include solder plating (1000 microinch maximum).
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0.254 / +0.051 / -0.025
(0.010 / +0.002 / -0.001)
DIMENSIONS
mm
(inches)
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3.6 Tape and Reel Specifications
CPC7695ZxTR Tape & Reel
330.2 DIA.
(13.00 DIA)
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
W=24.00±0.3
(0.94)
B0=13.40±0.15
(0.53±0.006)
A0=10.75±0.15
(0.42±0.006)
K0=3.20±0.15
(0.126±0.006)
Embossed Carrier
P=12.00
(0.47)
Dimensions
mm
(inches)
K1=2.60±0.15
(0.10±0.006)
NOTE: Unless otherwise specified, all dimension tolerances per EIA-481
Embossment
CPC7695BxTR Tape & Reel
P=12.00
(0.472)
330.2 DIA.
(13.00 DIA)
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
A0=10.90
(0.429)
B0=18.30
(0.720)
W=24.00+0.03/-0
(0.945+0.001/-0.0
K0=3.20
(0.126)
K1=2.70
(0.106)
Embossed Carrier
Embossment
Dimensions
mm
(inches)
Notes:
1. Unless otherwise specified, all dimensional tolerances per EIA standard 481
2. Unless otherwise specified, all dimensions ±0.10 (0.004)
For additional information please visit www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed
or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability
whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical
harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes
to its products at any time without notice.
Specification: DS-CPC7695-R01
© Copyright 2013, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
6/10/2013
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