Cypress CY7C1440AV33-167AXC 36-mbit (1m x 36/2m x 18/512k x 72) pipelined sync sram Datasheet

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined Sync SRAM
Functional Description[1]
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200,167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.2 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Provide high-performance 3-1-1-1 access rate
Intel®
• User-selectable burst counter supporting
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Offered in JEDEC-standard 100-pin TQFP, 165-Ball
fBGA and 209-Ball fBGA packages
• Also available in lead-free packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM
integrates 1,048,576 x 36, 2,097,152 x 18 and 524,288 x 72
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and
CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWX and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
2.6
3.2
3.4
ns
Maximum Operating Current
475
425
375
mA
Maximum CMOS Standby Current
100
100
100
mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE3, CE2 are for TQFP and 165 fBGA package only.
Cypress Semiconductor Corporation
Document #: 38-05383 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 31, 2005
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Logic Block Diagram – CY7C1440AV33 (1 Mbit x 36)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
ADSC
ADSP
BWD
DQD ,DQPD
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE DRIVER
BWC
DQC ,DQPC
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE DRIVER
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
DQA ,DQPA
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Logic Block Diagram – CY7C1442AV33 (2 Mbit x 18)
A0, A1, A
ADDRESS
REGISTER
2 A[1:0]
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BWB
DQB,DQPB
WRITE DRIVER
DQB,DQPB
WRITE REGISTER
MEMORY
ARRAY
BWA
DQA,DQPA
WRITE DRIVER
DQA,DQPA
WRITE REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
E
BWE
GW
CE1
CE2
CE3
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document #: 38-05383 Rev. *B
Page 2 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Logic Block Diagram – CY7C1446AV33 (512K x 72)
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
Q1
BINARY
COUNTER
CLR
Q0
ADV
CLK
ADSC
ADSP
BWH
DQH, DQPH
WRITE DRIVER
DQH, DQPH
WRITE DRIVER
BWG
DQF, DQPF
WRITE DRIVER
DQG, DQPG
WRITE DRIVER
BWF
DQF, DQPF
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
BWE
DQE, DQPE
WRITE DRIVER
DQ
E, DQP
BYTE
“a”E
WRITE DRIVER
BWD
DQD, DQPD
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
BWC
DQC, DQPC
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
DQB, DQPB
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
OUTPUT
BUFFERS
E
DQA, DQPA
WRITE DRIVER
DQA, DQPA
WRITE DRIVER
ENABLE
REGISTER
OUTPUT
REGISTERS
PIPELINED
ENABLE
INPUT
REGISTERS
DQs
DQPA
DQPB
DQPC
DQPD
DQPE
DQPF
DQPG
DQPH
SLEEP
CONTROL
Document #: 38-05383 Rev. *B
Page 3 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Pin Configurations
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1442AV33
(2 Mbit x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05383 Rev. *B
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
MODE
A
A
A
A
A1
A0
NC / 72M
A
VSS
VDD
CY7C1440AV33
(1 Mbit x 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC / 72M
A
VSS
VDD
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP Pinout
Page 4 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Pin Configurations (continued)
165-ball fBGA
CY7C1440AV33 (1 Mbit x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
R
2
A
3
4
5
6
7
8
9
10
11
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC
A
CE2
BWD
BWA
CLK
GW
A
NC / 144M
NC
DQC
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VDD
OE
VSS
VDD
ADSP
DQPC
DQC
VDDQ
NC
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQB
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC / 72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
TCK
A
A
A
A
8
9
10
11
A
A0
CY7C1442AV33 (2 Mbit x 18)
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
A
3
4
5
6
CE1
CE2
BWB
NC
CE3
NC
A
NC
BWA
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
R
VDDQ
7
CLK
BWE
GW
ADSC
OE
ADV
ADSP
A
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VDDQ
NC
NC
A
NC / 144M
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
DQB
DQB
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC / 72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05383 Rev. *B
Page 5 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Pin Configurations (continued)
209-ball fBGA
CY7C1446AV33 (512K × 72)
1
2
3
A
DQG
DQG
B
DQG
DQG
BWSC
C
DQG
DQG
D
DQG
DQG
E
DQPG
F
DQC
G
DQC
H
4
6
7
8
9
10
11
CE3
A
DQB
DQB
ADSP ADSC
ADV
BWSG
NC
BW
A
BWSB
BWSF
DQB
DQB
BWSH
BWSD
NC
CE1
NC
BWSE
BWSA
DQB
DQB
VSS
NC
NC
OE
GW
NC
VSS
DQB
DQB
DQPC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPF
DQPB
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
J
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
K
NC
NC
CLK
NC
VSS
VSS
VSS
NC
NC
NC
NC
L
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
M
DQH
DQH
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQA
DQA
N
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
P
DQH
DQH
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQA
DQA
R
DQPD
DQPH
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
T
DQD
DQD
VSS
NC
NC
MODE
NC
NC
VSS
U
DQD
DQD
V
DQD
W
DQD
A
CE2
5
DQPA
DQPE
DQE
DQE
NC
A
A
A
A
A
A
DQE
DQE
DQD
A
A
A
A1
A
A
A
DQE
DQE
DQD
TMS
TDI
A
A0
A
TCK
DQE
DQE
TDO
Pin Definitions
Name
I/O
Description
A0, A1, A
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active.
A1: A0 are fed to the two-bit counter.
BWA, BWB,
BWC, BWD,
BWE, BWF,
BWG, BWH
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BWX and
BWE).
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
CE1
Document #: 38-05383 Rev. *B
Page 6 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Pin Definitions (continued)
I/O
Description
CE2[2]
Name
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external
address is loaded.
CE3[2]
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device. Not available for AJ package version. Not
connected for BGA. Where referenced, CE3 is assumed active throughout this document
for BGA. CE3 is sampled only when a new external address is loaded.
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted,
it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
InputAsynchronous
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPX
I/OSynchronous
VDD
Power Supply
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
Power supply inputs to the core of the device.
VSS
Ground
VSSQ
VDDQ
MODE
TDO
I/O Ground
Ground for the core of the device.
Ground for the I/O circuitry.
I/O Power Supply Power supply for the I/O circuitry.
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin should be disconnected. This pin is not available
on TQFP packages.
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
JTAGClock
NC
–
No Connects. Not internally connected to the die
NC/72M,
NC/144M,
NC/288M
–
No Connects. Not internally connected to the die. NC/72M, NC/144M and NC/288M are
address expansion pins are not internally connected to the die.
Document #: 38-05383 Rev. *B
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
Page 7 of 27
PRELIMINARY
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Functional Overview
then the Write operation is controlled by BWE and BWX
signals.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.6ns
(250-MHz device).
The
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
provides Byte Write capability that is described in the Write
Cycle Descriptions table. Asserting the Byte Write Enable
input (BWE) with the selected Byte Write (BWX) input, will
selectively write to only the desired bytes. Bytes not selected
during a Byte Write operation will remain unaltered. A
synchronous self-timed Write mechanism has been provided
to simplify the Write operations.
The
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
supports secondary cache in systems utilizing either a linear
or interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated
with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH,
Document #: 38-05383 Rev. *B
Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE,
and BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV input is ignored
during this cycle. If a global Write is conducted, the data
presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Burst Sequences
The
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
provides a two-bit wraparound counter, fed by A1: A0, that
implements either an interleaved or linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
Page 8 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
Sleep mode standby current
Test Conditions
Min.
ZZ > VDD – 0.2V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ Active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
Max.
Unit
100
mA
2tCYC
ns
2tCYC
ns
2tCYC
ns
0
ns
Truth Table [3, 4, 5, 6, 7, 8]
Operation
Add. Used
CE1
CE2
ZZ
ADSP
X
CE3
X
Deselect Cycle, Power Down
None
H
Deselect Cycle, Power Down
None
L
Deselect Cycle, Power Down
None
Deselect Cycle, Power Down
None
ADSC
ADV
WRITE OE CLK
DQ
L
X
L
X
X
X
L-H Tri-State
L
X
L
L
X
X
X
X
L-H Tri-State
L
X
H
L
L
X
X
X
X
L-H Tri-State
L
L
X
L
H
L
X
X
X
L-H Tri-State
L-H Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
X
X
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H Tri-State
WRITE Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H Tri-State
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05383 Rev. *B
Page 9 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Truth Table (continued)[3, 4, 5, 6, 7, 8]
Operation
Add. Used
CE1
CE2
ZZ
ADSP
ADSC
ADV
X
CE3
X
READ Cycle, Continue Burst
Next
X
READ Cycle, Continue Burst
Next
X
READ Cycle, Continue Burst
Next
READ Cycle, Continue Burst
Next
WRITE Cycle, Continue Burst
Next
X
X
WRITE Cycle, Continue Burst
Next
H
X
WRITE OE CLK
DQ
L
H
H
L
H
L
L-H
X
X
L
H
H
L
H
H
L-H Tri-State
H
X
X
L
X
H
L
H
L
L-H
H
X
X
L
X
H
L
H
H
L-H Tri-State
X
L
H
H
L
L
X
L-H
D
X
L
X
H
L
L
X
L-H
D
Q
Q
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H Tri-State
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H Tri-State
Q
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Truth Table for Read/Write[5,9,10]
Function (CY7C1440AV33)
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write Byte C – (DQC and DQPC)
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – (DQD and DQPD)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BWC
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BWB
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Truth Table for Read/Write[5, 9, 10]
Function (CY7C1442AV33)
Read
GW
H
BWE
H
BWB
X
BWA
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
H
L
H
L
Write Byte B – (DQB and DQPB)
Write Bytes B, A
H
L
L
H
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Notes:
9. BWx represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled
at the same time for any given write.
10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05383 Rev. *B
Page 10 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Truth Table for Read/Write[5, 9, 10]
Function ( CY7C1446AV33)
Read
Read
Write Byte x – (DQx and DQPx)
Write All Bytes
Write All Bytes
GW
BWE
BWx
H
H
H
H
L
H
L
L
L
X
X
All BW = H
L
All BW = L
X
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Access Port (TAP)
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with IEEE Standard 1149.1. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Clock (TCK)
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
TAP Controller State Diagram
1
TEST-LOGIC
RESET
RUN-TEST/
IDLE
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
0
0
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Document #: 38-05383 Rev. *B
Page 11 of 27
PRELIMINARY
TAP Controller Block Diagram
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection
Circuitry
TDO
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TMS
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
TAP CONTROLLER
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
Document #: 38-05383 Rev. *B
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
Page 12 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
EXTEST
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at , bit
#89 (for 165-FBGA package) or bit #138 (for 209-fBGA
package). When this scan cell, called the “extest output bus
tristate”, is latched into the preload register during the
“Update-DR” state in the TAP controller, it will directly control
the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable
the output buffers to drive the output bus. When LOW, this bit
will place the output bus into a High-Z condition.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
Document #: 38-05383 Rev. *B
UNDEFINED
Page 13 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
TAP AC Switching Characteristics Over the operating Range[11, 12]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
25
ns
tTL
TCK Clock LOW time
25
ns
50
ns
20
MHz
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
5
ns
0
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up to TCK Rise
5
ns
tTMSH
TMS hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ............................................... VSS to 3.3V
Input rise and fall times ...................... ..............................1ns
Input pulse levels................................................ .VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels ...........................................1.5V
Input timing reference levels................... ......................1.25V
Output reference levels...................................................1.5V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage...............................1.5V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
TDO
50Ω
TDO
Z O= 50Ω
20pF
Z O= 50Ω
20pF
Notes:
11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
12. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = ns.
Document #: 38-05383 Rev. *B
Page 14 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135 to 3.6V unless otherwise noted)[13]
Parameter
VOH1
Description
Test Conditions
Output HIGH Voltage
VOH2
Output HIGH Voltage
VOL1
Output LOW Voltage
VOL2
Output LOW Voltage
VIH
2.4
V
2.0
V
IOH = –100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
V
IOL = 8.0 mA
VDDQ = 3.3V
0.4
V
IOL = 1.0 mA
VDDQ = 2.5V
0.4
V
VDDQ = 3.3V
0.2
V
VDDQ = 2.5V
0.2
V
IOL = 100 µA
Input Load Current
Unit
IOH = –4.0 mA, VDDQ = 3.3V
Input LOW Voltage
IX
Max.
IOH = –1.0 mA, VDDQ = 2.5V
Input HIGH Voltage
VIL
Min.
VDDQ = 3.3V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
GND < VIN < VDDQ
Identification Register Definitions
CY7C1440AV33
(1 Mbit x 36)
Instruction Field
CY7C1442AV33
(2 Mbit x 18)
CY7C1446AV33
(512K x 72)
Description
Describes the version number.
Revision Number (31:29)
000
000
000
Device Depth (28:24)[14]
01011
01011
01011
000000
000000
000000
Architecture/Memory Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Reserved for Internal Use
Defines memory type and architecture
100111
010111
110111
00000110100
00000110100
00000110100
Defines width and density
1
1
1
Allows unique identification of
SRAM vendor.
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary Scan Order–165FBGA
89
89
–
Boundary Scan Order–209fBGA
–
–
138
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
Notes:
13. All voltages referenced to VSS (GND).
14. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05383 Rev. *B
Page 15 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Identification Codes (continued)
Instruction
Code
Description
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
165-Ball fBGA Boundary Scan Order [15,16]
165-Ball fBGA Boundary Scan Order (continued)[15,16]
CY7C1440AV33 (1 Mbit x 36),CY7C1442AV33 (2 Mbit x 18)
CY7C1440AV33 (1 Mbit x 36),CY7C1442AV33 (2 Mbit x 18)
BIT#
BALL ID
BIT#
BALL ID
BIT#
BALL ID
BIT#
BALL ID
G11
69
K1
1
N6
46
B5
24
2
47
F11
70
L1
48
A5
A4
25
3
N7
N10
26
E11
71
M1
4
P11
49
B4
27
D11
72
J2
G10
73
K2
5
P8
50
B3
28
6
R8
51
A3
29
F10
74
L2
E10
75
M2
7
R9
52
A2
30
8
P9
53
B2
31
D10
76
N1
C11
77
N2
9
P10
54
C2
32
10
R10
55
B1
33
A11
78
P1
B11
79
R1
11
R11
56
A1
34
12
H11
57
C1
35
A10
80
R2
B10
81
P3
13
N11
58
D1
36
14
M11
59
E1
37
A9
82
R3
B9
83
P2
15
L11
60
F1
38
16
K11
61
G1
39
C10
84
R4
A8
85
P4
17
J11
62
D2
40
18
M10
63
E2
41
B8
86
N5
A7
87
P6
19
L10
64
F2
42
20
K10
65
G2
43
B7
88
R6
B6
89
Internal
A6
21
J10
66
H1
44
22
H9
67
H3
45
23
H10
68
J1
Notes:
15. Balls that are NC (No Connect) are preset LOW.
16. Bit# 89 is preset HIGH.
Document #: 38-05383 Rev. *B
Page 16 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
209-Ball fBGA Boundary Scan Order
[15,17]
209-Ball fBGA Boundary Scan Order (continued) [15,17]
CY7C1446AV33 (512K x 72)
CY7C1446AV33 (512K x 72)
BIT#
BALL ID
BIT#
BALL ID
BIT#
1
W6
42
H11
36
F6
77
C5
43
H10
37
K8
78
D5
44
G11
38
K9
79
D4
K10
80
C4
2
3
V6
U6
BALL ID
BIT#
BALL ID
4
W7
45
G10
39
5
V7
46
F11
40
J11
81
A4
J10
82
B4
6
U7
47
F10
41
7
T7
48
E10
83
C3
111
L1
B3
112
M2
8
V8
49
E11
84
9
U8
50
D11
85
A3
113
M1
A2
114
N2
10
T8
51
D10
86
11
V9
52
C11
87
A1
115
N1
B2
116
P2
12
U9
53
C10
88
13
P6
54
B11
89
B1
117
P1
C2
118
R2
14
W11
55
B10
90
15
W10
56
A11
91
C1
119
R1
D2
120
T2
16
V11
57
A10
92
17
V10
58
C9
93
D1
121
T1
E1
122
U2
18
U11
59
B9
94
19
U10
60
A9
95
E2
123
U1
F2
124
V2
20
T11
61
D7
96
21
T10
62
C8
97
F1
125
V1
98
G1
126
W2
22
R11
63
B8
23
R10
64
A8
99
G2
127
W1
H2
128
T6
24
P11
65
D8
100
25
P10
66
C7
101
H1
129
U3
J2
130
V3
26
N11
67
B7
102
27
N10
68
A7
103
J1
131
T4
K1
132
T5
28
M11
69
D6
104
29
M10
70
G6
105
N6
133
U4
H6
C6
106
K3
134
V4
107
K4
135
5W
K6
136
5V
30
L11
71
31
L10
72
32
K11
73
B6
108
33
M6
74
A6
109
K2
137
5U
110
L2
138
Internal
34
L6
75
A5
35
J6
76
B5
Note:
17. Bit# 138 is preset HIGH.
Document #: 38-05383 Rev. *B
Page 17 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Range
Ambient
Temperature
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Commercial
0°C to +70°C
VDD
VDDQ
3.3V – 5%/+10% 2.5V – 5%
to VDD
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range[18, 19]
Parameter
Description
Test Conditions
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VDDQ = 3.3V, VDD = Max.., IOL = 8.0 mA
VIH
Input HIGH Voltage[18]
VDDQ = 3.3V
VIL
Input LOW Voltage[18]
IX
Input Load Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
Min.
3.135
3.6
V
3.135
VDD
V
VDDQ = 2.5V
2.375
2.625
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
2.0
V
V
V
0.4
V
0.4
V
2.0
VDD + 0.3V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
Input = VDD
30
Input = VSS
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
µA
µA
–30
5
µA
5
µA
4.0-ns cycle, 250 MHz
475
mA
5.0-ns cycle, 200 MHz
425
mA
6.0-ns cycle, 167 MHz
375
mA
4.0-ns cycle, 250 MHz
225
mA
5.0-ns cycle, 200 MHz
225
mA
6.0-ns cycle, 167 MHz
225
mA
All speeds
100
mA
Input = VDD
IOZ
µA
–5
Input Current of MODE Input = VSS
ISB1
Unit
VDDQ = 3.3V
VDDQ = 2.5V, VDD = Max.., IOL = 1.0 mA
Input Current of ZZ
Max.
–5
ISB2
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CE
VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V 5.0-ns cycle, 200 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
6.0-ns cycle, 167 MHz
200
mA
200
mA
200
mA
Automatic CE
Power-down
Current—TTL Inputs
110
mA
ISB4
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speeds
Shaded areas contain advance information.
Notes:
18. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
19. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD\
Document #: 38-05383 Rev. *B
Page 18 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Thermal Resistance[20]
Parameter
Description
Test Conditions
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA / JESD51.
100 TQFP
Package
165 BGA
Package
209 fBGA
Package
Unit
25.21
20.8
25.31
°C/W
2.28
3.2
4.48
°C/W
209 fBGA
Package
Unit
Capacitance[20]
Parameter
Description
100 TQFP
Package
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 2.5V
165 BGA
Package
6.5
5
5
pF
3
5
5
pF
5.5
7
7
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
10%
GND
5 pF
R = 351Ω
INCLUDING
JIG AND
SCOPE
VT = 1.5V
(a)
90%
10%
90%
≤ 1 ns
≤ 1 ns
(b)
(c)
2.5V I/O Test Load
2.5V
OUTPUT
R = 1667Ω
Z0 = 50Ω
5 pF
INCLUDING
JIG AND
SCOPE
VT = 1.25V
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
10%
90%
10%
90%
GND
R = 1538Ω
≤ 1 ns
≤ 1 ns
(b)
(c)
Switching Characteristics Over the Operating Range [25, 26]
250 MHz
Parameter
tPOWER
Description
VDD(Typical) to the first Access[21]
Min.
Max
200 MHz
Min.
Max.
167 MHz
Min.
Max
Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
5
6
ns
tCH
Clock HIGH
1.5
2.0
2.4
ns
tCL
Clock LOW
1.5
2.0
2.4
ns
Output Times
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
1.0
1.5
1.5
ns
tCLZ
Clock to Low-Z[22, 23, 24]
1.0
1.3
1.5
ns
2.6
3.2
3.4
ns
Notes:
20. Tested initially and after any design or process change that may affect these parameters.
21. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
22. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
23. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
24. This parameter is sampled and not 100% tested.
25. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
26. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05383 Rev. *B
Page 19 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[25, 26]
250 MHz
Parameter
Description
Min.
Max
tCHZ
Clock to High-Z
[22, 23, 24]
2.6
tOEV
OE LOW to Output Valid
2.6
[22, 23, 24]
tOELZ
OE LOW to Output Low-Z
tOEHZ
OE HIGH to Output High-Z[22, 23, 24]
0
200 MHz
Min.
Unit
3.0
3.4
ns
3.0
3.4
ns
3.4
ns
0
2.6
167 MHz
Max
Max.
Min.
0
3.0
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.2
1.4
1.5
ns
tADS
ADSC, ADSP Set-up Before CLK Rise
1.2
1.4
1.5
ns
tADVS
ADV Set-up Before CLK Rise
1.2
1.4
1.5
ns
tWES
GW, BWE, BWX Set-up Before CLK Rise
1.2
1.4
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.2
1.4
1.5
ns
tCES
Chip Enable Set-up Before CLK Rise
1.2
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.3
0.4
0.5
ns
tADVH
ADV Hold After CLK Rise
0.3
0.4
0.5
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.3
0.4
0.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.3
0.4
0.5
ns
Hold Times
Shaded areas contain advance information.
Document #: 38-05383 Rev. *B
Page 20 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Switching Waveforms
Read Cycle Timing[27]
t CYC
CLK
t
CH
t
ADS
t
CL
t
ADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
tCES
Deselect
cycle
tCEH
CE
tADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
Q(A1)
High-Z
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05383 Rev. *B
Page 21 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Switching Waveforms (continued)
Write Cycle Timing[27, 28]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
28. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document #: 38-05383 Rev. *B
Page 22 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[27, 29, 30]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BWX
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes:
29. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
30. GW is HIGH.
Document #: 38-05383 Rev. *B
Page 23 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing[32, 33]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
(MHz)
250
200
Ordering Code
CY7C1440AV33-250AXC
CY7C1442AV33-250AXC
Package
Name
Part and Package Type
Operating
Range
A101
Lead-Free 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1440AV33-250BZC
CY7C1442AV33-250BZC
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1446AV33-250BGC
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1440AV33-250BZXC
CY7C1442AV33-250BZXC
BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4
mm)
CY7C1446AV33-250BGXC
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1440AV33-200AXC
CY7C1442AV33-200AXC
CY7C1440AV33-200BZC
A101
Lead-Free 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1442AV33-200BZC
CY7C1446AV33-200BGC
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1440AV33-200BZXC
CY7C1442AV33-200BZXC
BB165C Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4
mm)
CY7C1446AV33-200BGXC
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
32. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
33. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05383 Rev. *B
Page 24 of 27
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
PRELIMINARY
Ordering Information (continued)
Speed
(MHz)
Ordering Code
167
Package
Name
Part and Package Type
Operating
Range
A101
Lead-Free 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1440AV33-167AXC
CY7C1442AV33-167AXC
CY7C1440AV33-167BZC
CY7C1442AV33-167BZC
BB165C 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1446AV33-167BGC
BB209A 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1440AV33-167BZXC
CY7C1442AV33-167BZXC
BB165C Lead-Free165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4
mm)
CY7C1446AV33-167BGXC
BB209A Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76 mm)
Package Diagrams
165-Ball FBGA (15 x 17 x 1.40 mm) BB165C
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45±0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
F
F
G
G
H
J
14.00
E
17.00±0.10
E
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
1.00
5.00
0.35
0.15 C
+0.05
-0.10
0.53±0.05
0.25 C
10.00
B
15.00±0.10
0.15(4X)
SEATING PLANE
1.40 MAX.
0.36
C
51-85165-*A
Document #: 38-05383 Rev. *B
Page 25 of 27
PRELIMINARY
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Package Diagrams (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) BB209A
51-85167-**
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05383 Rev. *B
Page 26 of 27
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document History Page
Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync
SRAM
Document Number: 38-05383
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
124437
03/04/03
CJM
New data sheet
*A
254910
See ECN
SYT
Part number changed from previous revision. New and old part number differ
by the letter "A”
Modified Functional Block diagrams
Modified switching waveforms
Added Boundary scan information
Added Footnote #14 (32-Bit Vendor ID Code changed)
Added IDD, IX and ISB values in the DC Electrical Characteristics
Added tPOWER specifications in Switching Characteristics table
Removed 119 PBGA package
Changed 165 FBGA package from BB165C (15 x 17 x 1.20 mm) to BB165
(15 x 17 x 1.40 mm)
Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A (14 x 22
x 1.76 mm)
*B
306335
See ECN
SYT
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209
FBGA on Page # 6
Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 Mhz
speed bin on the Switching Characteristics table on Page # 19
Changed ΘJA and ΘJC from TBD to 25.21 and 2.58 °C/W respectively for
TQFP Package on Pg # 19
Replaced ΘJA and ΘJC from TBD to respective Values for 165 BGA and 209
fBGA Packages on the Thermal Resistance Table
Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 fBGA
Packages .
Changed IDD from 450, 400 and 350 mA to 475, 425 and 375 mA for
frequencies of 250, 200 and 167 MHz respectively
Changed ISB1 from 190, 180 and 170 mA to 225 mA for frequencies of 250,
200 and 167 MHz respectively
Changed ISB2 from 80 to 100 mA
Changed ISB3 from 180, 170 and 160 mA to 200 mA for frequencies of 250,
200 and 167 MHz respectively
Changed ISB4 from 100 to 110 mA
Document #: 38-05383 Rev. *B
Page 27 of 27
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