Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD17556Q5B SLPS392B – MARCH 2013 – REVISED OCTOBER 2014 CSD17556Q5B 30 V N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • • 1 Product Summary Extremely Low Resistance Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5 mm × 6 mm Plastic Package TA = 25°C • • UNIT Drain-to-Source Voltage 30 V Qg Gate Charge Total (4.5 V) 30 nC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage 7.5 nC VGS = 4.5 V 1.5 mΩ VGS = 10 V 1.2 mΩ 1.4 V Ordering Information(1) Device Qty Media Package Ship CSD17576Q5B 2500 13-Inch Reel CSD17576Q5BT 250 13-Inch Reel SON 5 × 6 mm Plastic Package Tape and Reel 2 Applications • TYPICAL VALUE VDS Point of Load Synchronous Buck in Networking, Telecom, and Computing Systems Synchronous Rectification Active ORing and Hotswap Applications (1) For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings 3 Description TA = 25°C VALUE UNIT This 30 V, 1.2 mΩ, 5 × 6 mm NexFET™ power MOSFET is designed to minimize losses in synchronous rectification and other power conversion applications. VDS Drain-to-Source Voltage 30 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 100 Continuous Drain Current (Silicon limited), TC = 25°C 215 ID Continuous Drain Current(1) 34 A Pulsed Drain Current, TA = 25°C(1)(2) 400 A Power Dissipation(1) 3.1 Power Dissipation, TC = 25°C 191 TJ, Tstg Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 100 A, L = 0.1 mH, RG = 25 Ω 500 mJ Top View IDM S 8 1 D PD S S 7 2 3 D 6 D 5 D A W D G 4 (1) Typical RθJA = 40°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB (2) Max RθJC = 1.3°C/W, Pulse duration ≤100 μs, duty cycle ≤1% P0093-01 RDS(on) vs VGS Gate Charge 10 TC = 25°C Id = 30A TC = 125ºC Id = 30A 5 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) 6 4 3 2 1 0 0 2 4 6 8 10 VGS - Gate-to- Source Voltage (V) 12 G001 ID = 30A VDS =15V 8 6 4 2 0 0 10 20 30 40 50 Qg - Gate Charge (nC) 60 70 G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD17556Q5B SLPS392B – MARCH 2013 – REVISED OCTOBER 2014 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 Trademarks ............................................................... 7 6.2 Electrostatic Discharge Caution ................................ 7 6.3 Glossary .................................................................... 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q5B Package Dimensions ........................................ 8 Recommended PCB Pattern..................................... 9 Recommended Stencil Pattern ................................. 9 Q5B Tape and Reel Information ............................. 10 4 Revision History Changes from Revision A (October 2013) to Revision B Page • Increased max pulsed drain current to 400 A ....................................................................................................................... 1 • Updated pulsed drain current conditions ............................................................................................................................... 1 • Updated Figure 1 to a normalized RθJC curve ....................................................................................................................... 4 • Updated the SOA in Figure 10 .............................................................................................................................................. 6 • Updated the mechanical drawing and dimensions table to show previously unknown dimensions ...................................... 8 Changes from Original (March 2013) to Revision A • 2 Page Updated the dimensions table in the Mechanical Data Section to include DIM "H" values ................................................... 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD17556Q5B CSD17556Q5B www.ti.com SLPS392B – MARCH 2013 – REVISED OCTOBER 2014 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 μA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA RDS(on) Drain-to-Source On-Resistance gƒs Transconductance 30 1.15 V 1.4 1.65 V VGS = 4.5 V, IDS = 40 A 1.5 1.8 mΩ VGS = 10 V, IDS = 40 A 1.2 1.4 mΩ VDS = 15 V, IDS = 40 A 197 S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Series Gate Resistance Qg Gate Charge Total (4.5 V) 30 Qgd Gate Charge Gate-to-Drain Qgs Gate Charge Gate-to-Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tƒ Fall Time VGS = 0 V, VDS = 15 V, ƒ = 1 MHz VDS = 15 V, IDS = 40 A VDS = 15 V, VGS = 0 V VDS = 15 V, VGS = 4.5 V, IDS = 40 A,RG = 2 Ω 5400 7020 pF 1770 2310 pF 68 88 pF 0.7 1.4 Ω 39 nC 7.5 nC 11 nC 6.1 nC 48 nC 14 ns 26 ns 27 ns 12 ns DIODE CHARACTERISTICS VSD Diode Forward Voltage ISD = 40 A, VGS = 0 V Qrr Reverse Recovery Charge trr Reverse Recovery Time 0.8 VDD= 15 V, IF = 40 A, di/dt = 300 A/μs 1 V 68 nC 36 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC MIN TYP MAX RθJC Junction-to-Case Thermal Resistance (1) 1.3 RθJA Junction-to-Ambient Thermal Resistance (1) (2) 50 (1) (2) UNIT °C/W RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD17556Q5B 3 CSD17556Q5B SLPS392B – MARCH 2013 – REVISED OCTOBER 2014 GATE www.ti.com GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RθJA = 125°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) IDS - Drain-to-Source Current (A) 200 180 160 140 120 100 80 60 VGS =10V VGS =6V VGS =4.5V 40 20 0 0 0.1 0.2 0.3 0.4 VDS - Drain-to-Source Voltage (V) 0.5 G001 Figure 1. Transient Thermal Impedance Figure 2. Saturation Characteristics 4 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD17556Q5B CSD17556Q5B www.ti.com SLPS392B – MARCH 2013 – REVISED OCTOBER 2014 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 10 VDS = 5V 180 VGS - Gate-to-Source Voltage (V) IDS - Drain-to-Source Current (A) 200 160 140 120 100 80 60 TC = 125°C TC = 25°C TC = −55°C 40 20 0 0 1 2 3 4 VGS - Gate-to-Source Voltage (V) ID = 30A VDS =15V 8 6 4 2 0 5 0 10 20 30 40 50 Qg - Gate Charge (nC) G001 Figure 3. Transfer Characteristics VGS(th) - Threshold Voltage (V) C − Capacitance (pF) ID = 250uA 10000 1000 100 0 10 20 VDS - Drain-to-Source Voltage (V) 1.8 1.6 1.4 1.2 1 0.8 0.6 −75 30 −25 G001 Figure 5. Capacitance 25 75 125 TC - Case Temperature (ºC) 175 G001 Figure 6. Threshold Voltage vs Temperature 6 2.2 TC = 25°C Id = 30A TC = 125ºC Id = 30A 5 Normalized On-State Resistance RDS(on) - On-State Resistance (mΩ) G001 Figure 4. Gate Charge Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 4 3 2 1 0 70 2 100000 10 60 0 2 4 6 8 10 VGS - Gate-to- Source Voltage (V) 12 2 ID =30A 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 −75 G001 Figure 7. On-State Resistance vs Gate-to-Source Voltage VGS = 4.5V VGS = 10V −25 25 75 125 TC - Case Temperature (ºC) 175 G001 Figure 8. Normalized On-State Resistance vs Temperature Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD17556Q5B 5 CSD17556Q5B SLPS392B – MARCH 2013 – REVISED OCTOBER 2014 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 5000 TC = 25°C TC = 125°C 10 IDS - Drain-to-Source Current (A) ISD − Source-to-Drain Current (A) 100 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) Single Pulse Max RthetaJC = 1.3ºC/W 1 10 VDS - Drain-to-Source Voltage (V) 100 G001 Figure 10. Maximum Safe Operating Area (SOA) TC = 25ºC TC = 125ºC IDS - Drain- to- Source Current (A) IAV - Peak Avalanche Current (A) 1 300.0 100 0.1 TAV - Time in Avalanche (mS) 1 Silicon limited Package limited 250.0 200.0 150.0 100.0 50.0 0.0 −50 −25 G001 Figure 11. Single Pulse Unclamped Inductive Switching 6 DC 10 G001 Figure 9. Typical Diode Forward Voltage 1ms 10ms 100 0.1 0.1 1 300 10 0.01 10us 100us 1000 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs Temperature Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD17556Q5B CSD17556Q5B www.ti.com SLPS392B – MARCH 2013 – REVISED OCTOBER 2014 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD17556Q5B 7 CSD17556Q5B SLPS392B – MARCH 2013 – REVISED OCTOBER 2014 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q5B Package Dimensions K H D3 6 D1 4 5 e 6 4 3 3 5 D2 7 2 E 2 7 ө 1 8 1 8 L b (8x) c1 E1 d1 Top View d2 Bottom View Side View ө Front View DIM MILLIMETERS MIN NOM MAX A 0.80 1.00 1.05 b 0.36 0.41 0.46 c 0.15 0.20 0.25 c1 0.15 0.20 0.25 c2 0.20 0.25 0.30 D1 4.90 5.00 5.10 D2 4.12 4.22 4.32 D3 3.90 4.00 4.10 d 0.20 0.25 0.30 d1 0.085 TYP d2 0.319 0.369 0.419 E 4.90 5.00 5.10 E1 5.90 6.00 6.10 E2 3.48 3.58 3.68 e H 0.36 0.46 0.56 L 0.46 0.56 0.66 L1 0.57 0.67 0.77 θ 0° — — K 8 1.27 TYP 1.40 TYP Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD17556Q5B CSD17556Q5B www.ti.com SLPS392B – MARCH 2013 – REVISED OCTOBER 2014 7.2 Recommended PCB Pattern (0.175) 4.440 5 (0.028) 0.710 (0.043) 1.100 C L 4 (0.023) 0.590 1.270 (0.028) SYM C L (0.178) 4.520 1 8 0.560 (0.022) (0.136) 3.456 0.710 (0.028) (0.054) (0.039) 0.984 1.372 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 7.3 Recommended Stencil Pattern (0.020) 0.508 x4 (0.011) 0.286 (0.014) 0.350 (0.022) 0.562 x 4 (0.029) 0.746 x 8 2.186 (0.086) 4.318 (0.170) 0.300 (0.012) 1.270 (0.050) (0.030) 0.766 (0.051) 1.294 x8 (0.060) 1.525 1.270 (0.050) (0.042) 1.072 (0.259) 6.586 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD17556Q5B 9 CSD17556Q5B SLPS392B – MARCH 2013 – REVISED OCTOBER 2014 www.ti.com K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 7.4 Q5B Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN R 0.30 TYP A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified). 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket. 10 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD17556Q5B PACKAGE OPTION ADDENDUM www.ti.com 14-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD17556Q5B ACTIVE VSON-CLIP DNK 8 2500 Pb-Free (RoHS Exempt) CU SN Level-1-260C-UNLIM -55 to 150 CSD17556 CSD17556Q5BT ACTIVE VSON-CLIP DNK 8 250 Pb-Free (RoHS Exempt) CU SN Level-1-260C-UNLIM -55 to 150 CSD17556 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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