GSI GS74104TP-12I 1m x 4 4mb asynchronous sram Datasheet

GS74104TP/J
SOJ, TSOP
Commercial Temp
Industrial Temp
1M x 4
4Mb Asynchronous SRAM
Features
8, 10, 12, 15 ns
3.3 V VDD
Center VDD and VSS
SOJ 1M x 4-Pin Configuraton
• Fast access time: 8, 10, 12, 15 ns
• CMOS low power operation: 150/125/110/90 mA at
minimum cycle time.
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 32-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
Description
The GS74104 is a high speed CMOS Static RAM organized as
1,048,576 words by 4 bits. Static design eliminates the need for
external clocks or timing strobes. The GS operates on a single
3.3 V power supply and all inputs and outputs are TTL-compatible. The GS74104 is available in 400 mil SOJ and 400 mil
TSOP Type-II packages.
Pin Descriptions
Symbol
Description
A4
A3
A2
A1
A0
CE
DQ1
VDD
VSS
DQ2
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
400 mil SOJ
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A5
A6
A7
A8
A9
OE
DQ4
VSS
VDD
DQ3
A10
A11
A12
A13
A14
NC
TSOP-II 1M x 4-Pin Configuration
NC
1
44
NC
NC
43
42
NC
NC
2
3
A4
4
41
A5
A3
5
40
A6
A2
6
39
A7
NC
A0–A19
Address input
DQ1–DQ4
Data input/output
CE
Chip enable input
A1
7
38
A8
WE
Write enable input
A0
8
37
A9
OE
Output enable input
CE
9
36
OE
DQ1
10
35
+3.3 V power supply
VDD
11
44-pin
DQ4
VDD
34
VSS
Ground
12
400 mil TSOP II
33
VSS
VSS
DQ2
NC
No connect
WE
A19
Rev: 1.07 1/2001
32
VDD
DQ3
14
31
A10
15
30
A11
A18
16
29
A12
A17
17
28
A13
A16
18
27
A15
19
26
A14
NC
NC
20
25
NC
NC
21
24
NC
NC
22
23
NC
13
1/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
Block Diagram
A0
Address
Input
Buffer
Row
Decoder
Memory Array
Column
Decoder
A19
CE
WE
OE
I/O Buffer
Control
DQ1
DQ4
Truth Table
CE
OE
WE
DQ1 to DQ8
VDD Current
H
X
X
Not Selected
ISB1, ISB2
L
L
H
Read
L
X
L
Write
L
H
H
High Z
IDD
Note: X: “H” or “L”
Rev: 1.07 1/2001
2/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
Input Voltage
VIN
–0.5 to VDD +0.5
(≤ 4.6 V max.)
V
Output Voltage
VOUT
–0.5 to VDD +0.5
(≤ 4.6 V max.)
V
Allowable power dissipation
PD
0.7
W
Storage temperature
TSTG
–55 to 150
o
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage for -10/12/15
VDD
3.0
3.3
3.6
V
Supply Voltage for -8
VDD
3.135
3.3
3.6
V
Input High Voltage
VIH
2.0
—
VDD +0.3
V
Input Low Voltage
VIL
–0.3
—
0.8
V
Ambient Temperature,
Commercial Range
TAc
0
—
70
oC
Ambient Temperature,
Industrial Range
T AI
–40
—
85
o
C
Note:
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Rev: 1.07 1/2001
3/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
Capacitance
Parameter
Symbol
Test Condition
Max
Unit
Input Capacitance
CIN
VIN = 0 V
5
pF
Output Capacitance
COUT
VOUT = 0 V
7
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage
Current
IIL
VIN = 0 to VDD
– 1 uA
1 uA
Output Leakage
Current
ILO
Output High Z
VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH
IOH = –4mA
2.4
—
Output Low Voltage
VOL
ILO = +4mA
—
0.4 V
Rev: 1.07 1/2001
4/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
Power Supply Currents
Parameter
Symbol
Test Conditions
0 to 70°C
–40 to 85°C
8 ns
10 ns
12 ns
15 ns
10 ns
12 ns
15 ns
IDD (max)
CE ≤ VIL
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
150 mA
125 mA
110 mA
90 mA
135 mA
120 mA
100 mA
Standby
Current
ISB1 (max)
CE ≥ VIH
All other inputs
≥ VIH or ≤VIL
Min. cycle time
70 mA
65 mA
60 mA
55 mA
75 mA
70 mA
65 mA
Standby
Current
ISB2 (max)
CE ≥ VDD - 0.2V
All other inputs
≥ VDD - 0.2V or ≤ 0.2V
Operating
Supply
Current
30 mA
40 mA
AC Test Conditions
Output Load 1
Parameter
Conditions
Input high level
VIH = 2.4 V
Input low level
VIL = 0.4 V
50Ω
Input rise time
tr = 1 V/ns
VT = 1.4 V
Input fall time
tf = 1 V/ns
Input reference level
1.4 V
Output Load 2
Output reference level
1.4 V
3.3 V
Output load
Fig. 1& 2
DQ
Rev: 1.07 1/2001
589Ω
DQ
Note:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
5/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
30pF1
5pF1
434Ω
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
AC Characteristics
Read Cycle
Parameter
Symbol
Read cycle time
-8
-10
-12
-15
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tRC
8
—
10
—
12
—
15
—
ns
Address access time
tAA
—
8
—
10
—
12
—
15
ns
Chip enable access time (CE)
tAC
—
8
—
10
—
12
—
15
ns
Output enable to output valid (OE)
tOE
—
3.5
—
4
—
5
—
6
ns
Output hold from address change
tOH
3
—
3
—
3
—
3
—
ns
Chip enable to output in low Z (CE)
tLZ*
3
—
3
—
3
—
3
—
ns
Output enable to output in low Z (OE)
tOLZ*
0
—
0
—
0
—
0
---
ns
Chip disable to output in High Z (CE)
tHZ*
—
4
—
5
—
6
—
7
ns
Output disable to output in High Z (OE)
tOHZ*
—
3.5
—
4
—
5
—
6
ns
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH
tRC
Address
tAA
tOH
Data Out
Rev: 1.07 1/2001
Previous Data
Data valid
6/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
Read Cycle 2: WE = VIH
tRC
Address
tAA
CE
tAC
tHZ
tLZ
OE
tOE
Data Out
tOHZ
tOLZ
DATA VALID
High impedance
Write Cycle
Parameter
Symbol
Write cycle time
-8
-10
-12
-15
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tWC
8
—
10
—
12
—
15
—
ns
Address valid to end of write
tAW
5.5
—
7
—
8
—
10
—
ns
Chip enable to end of write
tCW
5.5
—
7
—
8
—
10
—
ns
Data set up time
tDW
4
—
5
—
6
—
7
—
ns
Data hold time
tDH
0
—
0
—
0
—
0
—
ns
Write pulse width
tWP
5.5
—
7
—
8
—
10
—
ns
Address set up time
tAS
0
—
0
—
0
—
0
—
ns
Write recovery time (WE)
tWR
0
—
0
—
0
—
0
—
ns
Write recovery time (CE)
tWR1
0
—
0
—
0
—
0
—
ns
Output Low Z from end of write
tWLZ*
3
—
3
—
3
—
3
—
ns
Write to output in High Z
tWHZ*
—
3.5
—
4
—
5
—
6
ns
* These parameters are sampled and are not 100% tested.
Rev: 1.07 1/2001
7/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
Write Cycle 1: WE control
tWC
Address
tAW
tWR
OE
tCW
CE
tAS
tWP
WE
tDW
Data In
tDH
DATA VALID
tWHZ
tWLZ
Data Out
HIGH IMPEDANCE
Write Cycle 2: CE control
tWC
Address
tAW
tWR1
OE
tAS
tCW
CE
tWP
WE
tDW
Data In
DATA VALID
Data Out
Rev: 1.07 1/2001
tDH
HIGH IMPEDANCE
8/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
32-Pin SOJ, 400 mil
Dimension in inch
L
D
e
A
A1
A
A2
1
GE
E
HE
c
y
B
B1
Detail A
Q
Dimension in mm
Symbol
min
nom
max
min
nom
max
A
—
—
0.146
—
—
3.70
A1
0.026
—
—
0.66
—
—
A2
0.105
0.110
0.115
2.67
2.80
2.92
B
0.013
0.017
0.021
0.33
0.43
0.53
B1
0.024
0.028
0.032
0.61
0.71
0.81
c
0.006
0.008
0.012
0.15
0.20
0.30
D
0.820
0.824
0.829
20.83
20.93
21.06
E
0.395
0.400
0.405
10.04
10.16
10.28
e
—
0.05
—
—
1.27
—
HE
0.430
0.435
0.440
10.93
11.05
11.17
GE
0.354
0.366
0.378
9.00
9.30
9.60
L
0.082
—
—
2.08
—
—
y
—
—
0.004
—
—
0.10
Q
o
o
—
10o
0
—
o
10
0
Note:
1. Dimension D& E do not include interlead flash.
2. Dimension B1 does not include dambar protrusion/intrusion.
3. Controlling dimension: inches
Rev: 1.07 1/2001
9/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
44-Pin, 400 mil TSOP-II
Dimension in inch
D
c
22
e
B
y
L
L1
A1
A
A2
1
A
HE
23
E
44
Detail A
Rev: 1.07 1/2001
Q
Dimension in mm
Symbol
min
nom
max
min
nom
max
A
—
—
0.047
—
—
1.20
A1
0.002
—
—
0.05
—
—
A2
0.037
0.039
0.041
0.95
1.00
1.05
B
0.01
0.014
0.018
0.25
0.35
0.45
c
—
0.006
—
—
0.15
—
D
0.721
0.725
0.729
18.31
18.41
18.51
E
0.396
0.400
0.404
10.06
10.16
10.26
e
—
0.031
—
—
0.80
—
HE
0.455
0.463
0.471
11.56
11.76
11.96
L
0.016
0.020
0.024
0.40
0.50
0.60
L1
—
0.031
—
—
0.80
—
y
—
—
0.004
—
—
0.10
Q
0o
—
5o
0o
—
5o
Note:
1. Dimension D& E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Controlling dimension: mm
10/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
Ordering Information
Part Number*
Package
Access Time
Temp. Range
GS74104TP-8
400 mil TSOP-II
8 ns
Commercial
GS74104TP-10
400 mil TSOP-II
10 ns
Commercial
GS74104TP-12
400 mil TSOP-II
12 ns
Commercial
GS74104TP-15
400 mil TSOP-II
15 ns
Commercial
GS74104TP-8I
400 mil TSOP-II
8 ns
Industrial
GS74104TP-10I
400 mil TSOP-II
10 ns
Industrial
GS74104TP-12I
400 mil TSOP-II
12 ns
Industrial
GS74104TP-15I
400 mil TSOP-II
15 ns
Industrial
GS74104J-8
400 mil SOJ
8 ns
Commercial
GS74104J-10
400 mil SOJ
10 ns
Commercial
GS74104J-12
400 mil SOJ
12 ns
Commercial
GS74104J-15
400 mil SOJ
15 ns
Commercial
GS74104J-8I
400 mil SOJ
8 ns
Industrial
GS74104J-10I
400 mil SOJ
10 ns
Industrial
GS74104J-12I
400 mil SOJ
12 ns
Industrial
GS74104J-15I
400 mil SOJ
15 ns
Industrial
Status
*
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:
GS74104TP-8T
Rev: 1.07 1/2001
11/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
GS74104TP/J
Revision History
Rev. Code: Old;
New
GS74104Rev1.05 1/2000K;Rev 6
2/2000L
74104_r1_06; 74104_r1_07
Rev: 1.07 1/2001
Types of Changes
Format or Content
Format/Content
Format
Page #/Revisions/Reason
• GSI Logo
• Updated format to comply with Technical Publications standard
• Specifically noted that numbers in Power Supply Currents table are worst
case scenario
• Corrected package reference on page 9 (replaced 300 mil diagram with 400
mil diagram)
12/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
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