TI1 CDCM61004 Four output, integrated vco, low-jitter clock generator Datasheet

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CDCM61004
SCAS871H – FEBRUARY 2009 – REVISED JANUARY 2016
CDCM61004 Four Output, Integrated VCO, Low-Jitter Clock Generator
1 Features
2 Applications
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Low-Jitter Clock Driver for High-End Datacom
Applications Including SONET, Ethernet, Fibre
Channel, Serial ATA, and HDTV
Cost-Effective High-Frequency Crystal Oscillator
Replacement
3 Description
The CDCM61004 is a highly versatile, low-jitter
frequency synthesizer capable of generating four lowjitter clock outputs, selectable between low-voltage
positive emitter coupled logic (LVPECL), low-voltage
differential signaling (LVDS), or low-voltage
complementary
metal
oxide
semiconductor
(LVCMOS) outputs, from a low-frequency crystal of
LVCMOS input for a variety of wireline and data
communication applications. The CDCM61004
features an onboard PLL that can be easily
configured solely through control pins. The overall
output random jitter performance is less than 1 ps,
RMS (from 10 kHz to 20 MHz), making this device a
perfect choice for use in demanding applications such
as SONET, Ethernet, Fibre Channel, and SAN. The
CDCM61004 is available in a small, 32-pin,
5-mm × 5-mm VQFN package.
Device Information(1)
PART NUMBER
CDCM61004
PACKAGE
BODY SIZE (NOM)
VQFN (32)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
CDCM61004 Block Diagram
RSTN
PR[1...0]
2
OD[2...0]
3
CDCM61004
PFD
Charge Pump
Loop Filter
Crystal/
LVCMOS
VCO
Feedback
Divider
Output Divider
•
One Crystal/LVCMOS Reference Input Including
24.8832 MHz, 25 MHz, and 26.5625 MHz
Input Frequency Range: 21.875 MHz to
28.47 MHz
On-Chip VCO Operates in Frequency Range of
1.75 GHz to 2.05 GHz
4x Output Available:
– Pin-Selectable Between LVPECL, LVDS, or
2-LVCMOS; Operates at 3.3 V
LVCMOS Bypass Output Available
Output Frequency Selectable by /1, /2, /3, /4, /6,
/8 from a Single Output Divider
Supports Common LVPECL/LVDS Output
Frequencies:
– 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
155.52 MHz, 156.25 MHz, 159.375 MHz,
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,
311.04 MHz, 312.5 MHz, 622.08 MHz,
625 MHz
Supports Common LVCMOS Output Frequencies:
– 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
155.52 MHz, 156.25 MHz, 159.375 MHz,
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz
Output Frequency Range: 43.75 MHz to
683.264 MHz (See Table 4)
Internal PLL Loop Bandwidth: 400 kHz
High-Performance PLL Core:
– Phase Noise typically at –146 dBc/Hz at
5-MHz Offset for 625-MHz LVPECL Output
– Random Jitter typically at 0.509 ps, RMS
( 10 kHz to 20 MHz) for 625-MHz LVPECL
Output
Output Duty Cycle Corrected to 50% (± 5%)
Low Output Skew of 30 ps on LVPECL Outputs
Divider Programming Using Control Pins:
– Two Pins for Prescaler/Feedback Divider
– Three Pins for Output Divider
– Two Pins for Output Select
Chip Enable Control Pin Available
3.3-V Core and I/O Power Supply
Industrial Temperature Range: –40°C to 85°C
5-mm × 5-mm, 32-pin, VQFN (RHB) Package
ESD Protection Exceeds 2 kV (HBM)
Prescaler
1
Output
Driver
LVPECL/
LVCMOS/
LVDS
Output
Driver
LVPECL/
LVCMOS/
LVDS
Output
Driver
LVPECL/
LVCMOS/
LVDS
Output
Driver
LVPECL/
LVCMOS/
LVDS
3.3 V
LVCMOS
CE
2
OS[1...0]
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCM61004
SCAS871H – FEBRUARY 2009 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
9
1
1
1
2
4
5
7
Absolute Maximum Ratings ..................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 9
Typical Output Phase Noise Characteristics ......... 10
Typical Output Jitter Characteristics ...................... 11
Crystal Characteristics ............................................ 11
Dissipation Ratings ................................................ 11
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 13
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Application ................................................ 26
11 Power Supply Recommendations ..................... 28
11.1 Power Considerations ........................................... 28
11.2 Thermal Management ........................................... 29
11.3 Power-Supply Filtering .......................................... 29
12 Layout................................................................... 30
12.1 Layout Guidelines ................................................. 30
12.2 Layout Example .................................................... 30
13 Device and Documentation Support ................. 31
13.1
13.2
13.3
13.4
13.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
14 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (May 2011) to Revision H
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Changed input capacitance, only typical. .............................................................................................................................. 6
•
Added Allowable Temperature Drift for Continuous PLL Lock parameter ............................................................................. 7
•
Changed on-chip load capacitance, only typical. ................................................................................................................. 11
•
Changed parisitic to parasitic. .............................................................................................................................................. 17
•
Added paragraph about temperature drift while locked. ..................................................................................................... 18
Changes from Revision F (February 2011) to Revision G
Page
•
Changed the On-Chip VCO section ..................................................................................................................................... 18
•
Changed Figure 15............................................................................................................................................................... 18
•
Moved the LVCMOS INPUT INTERFACE section prior to the Output Divider section........................................................ 18
Changes from Revision E (July 2010) to Revision F
Page
•
Changed Note 1 of the Pin Functions table From: Pullup and Pull-down see...To: Pullup refers to ..................................... 6
•
Deleted RPULLDOWN from the Table 1 table.............................................................................................................................. 6
•
Changed the text of Configuring the PLL, deleted the last sentence................................................................................... 16
•
Changed the On-Chip VCO section ..................................................................................................................................... 18
•
Changed the Output Buffer section ...................................................................................................................................... 19
•
Changed values in row 24.75 of Table 3.............................................................................................................................. 19
•
Changed the power dissipation equation From: 610.5 mW – 4 × 50 mW = 41.7 mW To: 617.1 mW – 4 × 50 mW =
2
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417.1 mW ............................................................................................................................................................................. 28
•
Deleted figure "Recommended PCB Layout for CDCM61001" from the Thermal Management section. Added text
"See the mechanical data at the end of the data sheet.." .................................................................................................... 29
Changes from Revision D (February 2010) to Revision E
Page
•
Added LVCMOS reference to first Features bullet ................................................................................................................. 1
•
Added reference to LVCMOS input in Description ................................................................................................................. 1
•
Added reference to LVCMOS inputs in XIN parameter of Pin Functions table...................................................................... 6
•
Changed name of Control Pin LVCMOS Input Characteristics section in Electrical Characteristics table ............................ 9
•
Changed description of Crystal Input Interface section........................................................................................................ 16
•
Changed description of LVCMOS Input Interface section.................................................................................................... 18
Changes from Revision C (July 2009) to Revision D
Page
•
Deleted references to Single-Ended and LVCMOS input throughout the document ............................................................. 1
•
Deleted fIN, ΔV/ΔT, and DutyREF parameters from Electrical Characteristics table.............................................................. 9
•
Added LVCMOS Input Interface section............................................................................................................................... 18
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5 Description (Continued)
The CDCM61004 is a high-performance, low-phase noise, fully-integrated voltage-controlled oscillator (VCO)
clock synthesizer with four universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS
compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS
bypass output clock is available in an output configuration which can help with crystal loading to achieve an
exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the
1.75 GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a lowfrequency crystal. The output share an output divider sourced from the VCO core. All device settings are
managed through a control pin structure, which has two pins that control the prescaler and feedback divider,
three pins that control the output divider, two pins that control the output type, and one pin that controls the
output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider)
are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates
a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividers are turned
off.
The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output
divider, and VCO frequency set fOUT with respect to fIN. For a configuration setting for common wireline and
datacom applications, see Table 3. For other applications, use Equation 1 to calculate the exact crystal oscillator
frequency required for the desired output.
Output Divider f
fIN =
Feedback Divider OUT
(1)
(
(
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and
prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also
through the use of control pins. CDCM61004 Block Diagram shows a high-level diagram of the CDCM61004.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C.
4
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6 Pin Configuration and Functions
OUTP2
OUTN2
VCC_OUT
OUTP3
OUTN3
VCC_OUT
PR1
PR0
RHB Package
32-Pin VQFN
Top View
32
31
30
29
28
27
26
25
VCC_OUT
1
24
NC
OUTN1
2
23
OSC_OUT
OUTP1
3
22
GND1
VCC_OUT
4
21
XIN
OUTN0
5
20
VCC_IN
OUTP0
6
19
REG_CAP1
CE
7
18
VCC_PLL1
NC
8
17
REG_CAP2
CDCM61004
9
10
11
12
13
14
15
16
VCC_VCO
OS1
OS0
RSTN
OD0
OD1
OD2
VCC_PLL2
Thermal Pad
(must be soldered to ground)
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Pin Functions
PIN
NAME
NO.
TYPE
DIRECTION (1)
DESCRIPTION
CE
7
Input
Pullup
GND1
22
Ground
—
Additional ground for device. (GND1 shorted on-chip to GND)
GND
Pad
Ground
—
Ground is on thermal pad. See Thermal Management
NC
8, 24
—
—
No connection
OD2, OD1,
OD0
15, 14, 13
Input
Pullup
Output divider control pins (see Table 6)
OS1, OS0
10, 11
Input
Pullup
Output type select control pin (see Table 7)
OSC_OUT
23
Output
—
Bypass LVCMOS output
OUTP0,
OUTN0
6, 5
Output
—
Differential output pair or two single-ended outputs
OUTP1,
OUTN1
3, 2
Output
—
Differential output pair or two single-ended outputs
OUTP2,
OUTN2
32, 31
Output
—
Differential output pair or two single-ended outputs
OUTP3,
OUTN3
29, 28
Output
—
Differential output pair or two single-ended outputs
PR1, PR0
26, 25
Input
Pullup
REG_CAP1
19
Output
—
Capacitor for internal regulator (connect to a 10-μF Y5V capacitor to
GND)
REG_CAP2
17
Output
—
Capacitor for internal regulator (connect to a 10-μF Y5V capacitor to
GND)
RSTN
Chip enable control pin (see Table 8)
Prescaler and Feedback divider control pins (see Table 5)
12
Input
Pullup
VCC_OUT
1, 4, 27, 30
Power
—
3.3-V supply for the output buffers
VCC_PLL1
18
Power
—
3.3-V supply for the PLL circuitry
VCC_PLL2
16
Power
—
3.3-V supply for the PLL circuitry
VCC_VCO
9
Power
—
3.3-V supply for the internal VCO
VCC_IN
20
Power
—
3.3-V supply for the input buffers
XIN
21
Input
—
Parallel resonant crystal or LVCMOS inputs
(1)
Device reset (active low) (see Table 9)
Pullup refers to internal input resistors; see Table 1, Pin Characteristics for typical values.
Table 1. Pin Characteristics
PARAMETER
CIN
Input capacitance
RPULLUP
Input pullup resistor
6
MIN
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TYP
MAX
UNIT
10
pF
150
kΩ
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
PARAMETER
MIN
MAX
UNIT
–0.5
4.6
V
VCC_OUT,
VCC_PLL1
Supply voltage (2)
VCC
VCC_PLL2
VCC_VCO
VCC_IN
VIN
Input voltage (3)
–0.5
VCC_IN + 0.5
V
VOUT
Output voltage range (3)
–0.5
VCC_OUT + 0.5
V
IN
Input current
–20
20
mA
IOUT
Output current
–50
50
mA
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All supply voltages must be supplied simultaneously.
Input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
NOM
MAX
VCC_OUT
Output supply voltage
3
3.3
3.6
V
VCC_PLL1
PLL supply voltage
3
3.3
3.6
V
VCC_PLL2
PLL supply voltage
3
3.3
3.6
V
VCC_VCO
On-chip VCO supply voltage
3
3.3
3.6
V
VCC_IN
Input supply voltage
3
3.3
3.6
V
TA
Ambient temperature
85
°C
|TCL|
Allowable temperature drift for continuous PLL lock (1)
100
°C
(1)
–40
UNIT
The maximum allowable temperature drift for continuous lock is how far the temperature can drift in either direction from the value it was
at the time when the On-Chip VCO was calibrated with the condition that the PLL stays in lock throughout the temperature drift. The
internal VCO calibration takes place at device start-up and when the device is reset using the RSTN pin. A more detailed description
can be found in On-Chip VCO and Start-Up Time Estimation.This implies the part will work over the entire frequency range, but if the
temperature drifts more than the maximum allowable temperature drift for continuous lock, then it is necessary to re-calibrate the VCO to
ensure the PLL stays in lock. Regardless of what temperature the part was initially calibrated at, the temperature can never drift outside
the ambient temperature range of –40 °C to 85 °C.
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7.4 Thermal Information
CDCM61004
THERMAL METRIC (1)
RHB (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
33.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
25.7
°C/W
RθJB
Junction-to-board thermal resistance
0.3
°C/W
ψJT
Junction-to-top characterization parameter
7.1
°C/W
ψJB
Junction-to-board characterization parameter
2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.12
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
At VCC = 3 V to 3.6 V and TA = –40°C to 85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CONTROL PIN LVCMOS INPUT CHARACTERISTICS
VIH
Input high voltage
VIL
Input low voltage
IIH
Input high current
IIL
Input low current
0.6 VCC
V
0.4 VCC
V
VCC = 3.6 V, VIL = 0 V
200
μA
VCC = 3 V, VIH = 3.6 V
–200
μA
21.875
28.47
MHz
43.75
250
MHz
LVCMOS OUTPUT CHARACTERISTICS (1) (See Figure 7 and Figure 8)
fOSC_OUT
Bypass output frequency
fOUT
Output frequency
VOH
Output high voltage
VCC = min to max, IOH = –100 μA
VOL
Output low voltage
VCC = min to max, IOL = 100 μA
tRJIT
RMS phase jitter
250 MHz (10 kHz to 20 MHz)
tSLEW-RATE
Output rise/fall slew rate
20% to 80%
ODC
Output duty cycle
tSKEW
Skew between outputs
ICC,
LVCMOS
Device current, LVCMOS
LVPECL OUTPUT CHARACTERISTICS
VCC –0.5
V
0.3
0.85 ps, RMS
2.4
V/ns
45%
fIN = 25 MHz, fOUT = 250 MHz, CL = 5 pF
(2)
V
55%
175
60
ps
205
mA
MHz
(See Figure 9 and Figure 10)
fOUT
Output frequency
VOH
Output high voltage
VOL
Output low voltage
|VOD|
Differential output voltage
tRJIT
RMS phase jitter
625 MHz (10 kHz to 20 MHz)
tR/tF
Output rise/fall time
20% to 80%
ODC
Output duty cycle
tSKEW
Skew between outputs
ICC,
LVPECL
Device current, LVPECL
43.75
683.264
VCC –1.18
VCC –0.73
V
VCC –2
VCC –1.55
V
0.6
1.23
V
0.77 ps, RMS
175
45%
fIN = 25 MHz, fOUT = 625 MHz
ps
55%
180
30
ps
215
mA
MHz
LVDS OUTPUT CHARACTERISTICS (3) (See Figure 11 and Figure 12)
fOUT
Output frequency
43.75
683.264
|VOD|
Differential output voltage
0.247
0.454
ΔVOD
VDD magnitude change
VOS
Common-mode voltage
ΔVOS
VOS magnitude change
tRJIT
RMS phase jitter
625 MHz (10 kHz to 20 MHz)
tR/tF
Output rise/fall time
20% to 80%
ODC
Output duty cycle
tSKEW
Skew between outputs
ICC, LVDS
Device current, LVDS
(1)
(2)
(3)
50
1.125
1.375
50
V
mV
0.73 ps, RMS
255
45%
fIN = 25 MHz, fOUT = 625 MHz
V
mV
ps
55%
150
40
ps
195
mA
Figure 7 and Figure 8 show DC and AC test setups, respectively. Jitter measurements made using 25-MHz quartz crystal inches.
Figure 9 and Figure 10 show DC and AC test setups, respectively. Jitter measurements made using 25-MHz quartz crystal inches.
Figure 11 and Figure 12 show DC and AC test setups, respectively. Jitter measurements made using 25-MHz quartz crystal inches.
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7.6 Typical Output Phase Noise Characteristics
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
250-MHz LVCMOS OUTPUT
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(See Figure 8)
phn100
Phase noise at 100-Hz offset
–95
dBc/Hz
phn1k
Phase noise at 1-kHz offset
–110
dBc/Hz
phn10k
Phase noise at 10-kHz offset
–117
dBc/Hz
phn100k
Phase noise at 100-kHz offset
–120
dBc/Hz
phn1M
Phase noise at 1-MHz offset
–135
dBc/Hz
phn10M
Phase noise at 10-MHz offset
–148
dBc/Hz
phn20M
Phase noise at 20-MHz offset
–148
dBc/Hz
tRJIT
RMS phase jitter from 10 kHz to 20 MHz
544
fs, RMS
tPJIT
Total period jitter
27.4
ps, PP
tSTARTUP
Start-up time, power supply ramp time of 1 ms,
final frequency accuracy of ±10 ppm
2.25
ms
–81
dBc/Hz
625-MHz LVPECL OUTPUT
(2)
(See Figure 10)
phn100
Phase noise at 100-Hz offset
phn1k
Phase noise at 1-kHz offset
–101
dBc/Hz
phn10k
Phase noise at 10-kHz offset
–109
dBc/Hz
phn100k
Phase noise at 100-kHz offset
–112
dBc/Hz
phn1M
Phase noise at 1-MHz offset
–129
dBc/Hz
phn10M
Phase noise at 10-MHz offset
–146
dBc/Hz
phn20M
Phase noise at 20-MHz offset
–146
dBc/Hz
tRJIT
RMS phase jitter from 10 kHz to 20 MHz
509
fs, RMS
tPJIT
Total period jitter
26.9
ps, PP
tSTARTUP
Start-up time, power supply ramp time of 1 ms,
final frequency accuracy of ±10 ppm
2.25
ms
625-MHz LVDS OUTPUT (3) (See Figure 12)
phn100
Phase noise at 100-Hz offset
–88
dBc/Hz
phn1k
Phase noise at 1-kHz offset
–102
dBc/Hz
phn10k
Phase noise at 10-kHz offset
–109
dBc/Hz
phn100k
Phase noise at 100-kHz offset
–112
dBc/Hz
phn1M
Phase noise at 1-MHz offset
–129
dBc/Hz
phn10M
Phase noise at 10-MHz offset
–146
dBc/Hz
phn20M
Phase noise at 20-MHz offset
–146
dBc/Hz
tRJIT
RMS phase jitter from 10 kHz to 20 MHz
510
fs, RMS
tPJIT
Total period jitter
27
ps, PP
tSTARTUP
Start-up time, power supply ramp time of 1 ms,
final frequency accuracy of ±10 ppm
(1)
(2)
(3)
10
2.25
ms
Figure 8 shows test setup and uses 25-MHz quartz crystal in, VCC = 3.3 V, and TA = 25°C.
Figure 10 shows test setup and uses 25-MHz quartz crystal in, VCC = 3.3 V, and TA = 25°C.
Figure 12 shows test setup and uses 25-MHz quartz crystal in, VCC = 3.3 V, and TA = 25°C.
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7.7 Typical Output Jitter Characteristics (1)
OUTPUT
FREQUENCY
(MHz)
INPUT (MHz)
62.5
(1)
LVCMOS OUTPUT
LVPECL OUTPUT
LVDS OUTPUT
tRJIT (fs, RMS)
tPJIT (psPP)
tRJIT (fs, RMS)
tPJIT (psPP)
tRJIT (fs, RMS)
tPJIT (psPP)
25
592
32.9
611
20.7
667
28.4
75
25
518
27.5
533
19.4
572
25.7
77.76
24.8832
506
29.2
526
20.9
567
26.9
100
25
507
24.5
510
20.7
533
26.5
106.25
26.5625
535
23.5
524
20.2
553
26.5
125
25
557
39.6
556
21.4
570
27.1
150
25
518
38.4
493
18.9
515
26.2
155.52
24.8832
498
36.9
486
19.8
502
26.7
156.25
25
510
37.7
503
20.7
518
26.5
159.375
26.5625
535
37.4
510
19.9
534
26.3
187.5
25
506
32.8
506
20.3
509
25.5
200
25
491
23.3
492
30
499
34.9
212.5
26.5625
520
47.8
509
30.8
530
37.3
250
25
544
27.4
541
21.4
550
27.5
311.04
24.8832
481
20.5
496
24.7
312.5
25
501
20.8
508
25.8
622.08
24.8832
492
27.2
500
27.2
625
25
515
26.9
509
27
Figure 8, Figure 10, and Figure 12 show LVCMOS, LVPECL, and LVDS test setups (respectively) using appropriate quartz crystal in,
VCC = 3.3 V, and TA = 25°C.
7.8 Crystal Characteristics
PARAMETER
MIN
Mode of oscillation
TYP
MAX
Fundamental
Frequency
MHz
21.875
28.47
Equivalent series resistance (ESR)
On-chip load capacitance
8
Drive level
UNIT
0.1
Maximum shunt capacitance
MHz
50
Ω
10
pF
1
mW
7
pF
7.9 Dissipation Ratings (1) (2)
TEST
CONDITIONS
PARAMETER
θJA
θJP
(1)
(2)
(3)
Thermal resistance, junction-to-ambient
(3)
0 LFM
Thermal resistance, junction-to-pad
VALUE
4 × 4 VIAS
ON PAD
UNIT
35
°C/W
4
°C/W
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).
Connected to GND with nine thermal vias (0.3-mm diameter).
θJP (junction-to-pad) is used for the VQFN package, because the primary heat flow is from the junction to the GND pad of the VQFN
package.
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7.10 Typical Characteristics
Over operating free-air temperature range (unless otherwise noted).
205
170
Output-divide-by-8
Output-divide-by-8
Output-divide-by-6
Output-divide-by-6
Output-divide-by-4
200
Output-divide-by-4
165
Output-divide-by-3
Output-divide-by-3
Output-divide-by-2
Output-divide-by-1
Supply Current (mA)
Supply Current (mA)
Output-divide-by-2
195
190
185
Output-divide-by-1
160
155
150
180
145
0
200
400
600
800
0
200
400
Output Frequency (MHz)
Figure 1. Typical Current Consumption for LVPECL Output
vs Output Frequency
175
0.76
Differential Output Voltage, VOD (V)
0.77
Supply Current (mA)
165
155
145
135
Output-divide-by-8
125
Output-divide-by-6
Output-divide-by-4
115
0.75
0.74
0.73
0.72
0.71
Output-divide-by-3
Output-divide-by-2
0.70
105
0
50
100
150
200
250
0
300
100
200
300
400
500
600
700
Output Frequency (MHz)
Output Frequency (MHz)
Figure 4. Typical LVPECL Differential Output Voltage vs
Output Frequency
Figure 3. Typical Current Consumption for LVCMOS Output
With 5-pF Load vs Output Frequency
0.42
3.30
0.40
3.25
Output Voltage, VOUT (V)
Differential Output Voltage, VDO (V)
800
Figure 2. Typical Current Consumption for LVDS Output vs
Output Frequency
185
0.38
0.36
0.34
0.32
3.20
3.15
3.10
3.05
0.30
3.00
0
100
200
300
400
500
600
700
50
100
Output Frequency (MHz)
150
200
250
Output Frequency (MHz)
Figure 5. Typical LVDS Differential Output Voltage vs
Output Frequency
12
600
Output Frequency (MHz)
Figure 6. Typical LVCMOS Output Voltage With 5-pF Load
vs Output Frequency
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8 Parameter Measurement Information
This section describes the function of each block for the CDCM61004. Figure 7 through Figure 13 illustrate how
the device should be set up for a variety of output configurations.
LVCMOS
5 pF
Figure 7. LVCMOS Output Loading During Device Test
Phase Noise
Analyzer
LVCMOS
Figure 8. LVCMOS AC Configuration During Device Test
Oscilloscope
LVPECL
50 W
50 W
VCC - 2V
Figure 9. LVPECL DC Configuration During Device Test
Phase Noise
Analyzer
LVPECL
150 W
150 W
50 W
Figure 10. LVPECL AC Configuration During Device Test
LVDS
100 W
Oscilloscope
Figure 11. LVDS DC Configuration During Device Test
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Parameter Measurement Information (continued)
Phase Noise
Analyzer
LVDS
50 W
Figure 12. LVDS AC Configuration During Device Test
VOH
Yx
VOD
VOL
Yx
80%
VOUTpp
20%
0V
tr
tf
Figure 13. Output Voltage and Rise and Fall Times
14
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9 Detailed Description
9.1 Overview
The CDCM61004 is a high-performance PLL that generates 4 copies of commonly used reference clocks with
less than 1 ps, RMS jitter from a low-cost crystal.
9.2 Functional Block Diagram
VCC_IN
VCC_PLL1
XO
LVCMOS
XIN
VCC_PLL2
Phase
Frequency
Detector
21.875 MHz
to 28 .47 MHz
VCC_VCO
VCC_VDD
VCC_OUT
Loop Filter
Charge
Pump
224 mA
400 kHz
¸15
FB_MUX
¸5
VCO
1.75 GHz
to 2.05 GHz
¸20
¸4
¸24
RSTN
¸3
Prescaler
Divider
¸25
Feedback
Divider
LVCMOS
¸1
PR1
DIV_MUX
PR0
¸2
LVPECL
OUTP[1...0]
¸3
4
¸4
LVDS
OUTN[1...0]
¸6
REG_CAP1
¸8
LVCMOS
Output
Divider
REG_CAP2
LVCMOS
OSC_OUT
CDCM61004
CE
GND1
OD2 OD1 OD0
OS1 OS0
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9.3 Feature Description
9.3.1 Phase-Locked Loop (PLL)
The CDCM61004 includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a crystal input
interface, which can also accept an LVCMOS signal, a phase frequency detector (PFD), a charge pump, an onchip loop filter, and prescaler and feedback dividers. Completing the CDCM61004 device are the output divider
and universal output buffer.
The PLL is powered by on-chip, low-dropout (LDO) linear voltage regulators. The regulated supply network is
partitioned such that the sensitive analog supplies are powered from separate LDOs rather than the digital
supplies which use a separate LDO regulator. These LDOs provide isolation for the PLL from any noise in the
external power-supply rail. The REG_CAP1 and REG_CAP2 pins should each be connected to ground by 10-μF
capacitors to ensure stability.
9.3.2 Configuring the PLL
The CDCM61004 permits PLL configurations to accommodate the various input and output frequencies listed in
Table 3 and Table 4. These configurations are accomplished by setting the prescaler divider, feedback divider
and output divider. The various dividers are managed by setting the device control pins as shown in Table 5 and
Table 6.
9.3.3 Crystal Input Interface
Fundamental mode is the recommended oscillation mode of operation for the input crystal and parallel
resonance is the recommended type of circuit for the crystal.
A crystal load capacitance refers to all capacitances in the oscillator feedback loop. It is equal to the amount of
capacitance seen between the terminals of the crystal in the circuit. For parallel resonant mode circuits, the
correct load capacitance is necessary to ensure the oscillation of the crystal within the expected parameters.
The CDCM61004 implements an input crystal oscillator circuitry, known as the Colpitts oscillator, and requires
one pad of the crystal to interface with the XIN pin; the other pad of the crystal is tied to ground. In this crystal
interface, it is important to account for all sources of capacitance when calculating the correct value for the
discrete capacitor component, CL, for a design.
The CDCM61004 has been characterized with 10-pF parallel resonant crystals. The input crystal oscillator stage
in the CDCM61004 is designed to oscillate at the correct frequency for all parallel resonant crystals with low-pull
capability and rated with a load capacitance that is equal to the sum of the onchip load capacitance at the XIN
pin (10-pF), crystal stray capacitance, and board parasitic capacitance between the crystal and XIN pin.
The normalized frequency error of the crystal, as a result of load capacitance mismatch, can be calculated as
Equation 2:
CS
CS
Df =
f
2(CL,R + CO) 2(CL,A + CO)
where
•
•
•
•
•
•
•
CS is the motional capacitance of the crystal,
C0 is the shunt capacitance of the crystal,
CL,R is the rated load capacitance for the crystal,
CL,A is the actual load capacitance in the implemented PCB for the crystal,
Δf is the frequency error of the crystal,
and f is the rated frequency of the crystal.
The first three parameters can be obtained from the crystal vendor.
(2)
To minimize the frequency error of the crystal to meet application requirements, the difference between the rated
load capacitance and the actual load capacitance should be minimized and a crystal with low-pull capability (low
CS) should be used.
16
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Feature Description (continued)
For example, if an application requires less than ±50-ppm frequency error and a crystal with less than ±50-ppm
frequency tolerance is picked, the characteristics are as follows: C0 = 7 pF, CS = 10 fF, and CL,R = 12 pF. In
order to meet the required frequency error, calculate CL,A using Equation 2 to be 17 pF. Subtracting CL,R from
CL,A, results in 5 pF; take care during printed-circuit-board (PCB) layout with the crystal and the CDCM61004 to
ensure that the sum of the crystal stray capacitance and board parasitic capacitance is less than the calculated 5
pF.
Good layout practices are fundamental to the correct operation and reliability of the oscillator. It is critical to
locate the crystal components very close to the XIN pin to minimize routing distances. Long traces in the
oscillator circuit are a very common source of problems. Do not route other signals across the oscillator circuit.
Also, make sure power and high-frequency traces are routed as far away as possible to avoid crosstalk and
noise coupling. Avoid the use of vias; if the routing becomes very complex, it is much better to use 0-Ω resistors
as bridges to go over other signals. Vias in the oscillator circuit should only be used for connections to the
ground plane. Do not share ground connections; instead, make a separate connection to ground for each
component that requires grounding. If possible, place multiple vias in parallel for each connection to the ground
plane. Especially in the Colpitts oscillator configuration, the oscillator is very sensitive to capacitance in parallel
with the crystal. Therefore, the layout must be designed to minimize stray capacitance across the crystal to less
than 5 pF total under all circumstances to ensure proper crystal oscillation. Be sure to consider both PCB and
crystal stray capacitance.
Table 2 lists several recommended crystals and the respective manufacturer of each.
Table 2. Recommended Crystal Manufacturers
MANUFACTURER
PART NUMBER
Vectron
VXC1-1133
Fox
218-3
Saronix
FP2650002
9.3.4 Phase Frequency Detector (PFD)
The PFD takes inputs from the input interface and the feedback divider and produces an output that depends on
the phase and frequency differences between the two inputs. The allowable range of frequencies at the PFD
inputs is 21.875 MHz to 28.47 MHz.
9.3.5 Charge Pump (CP)
The charge pump is controlled by the PFD, which dictates either to pump up or down to charge or discharge the
integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then converted to
a voltage that drives the control voltage node of the internal VCO through the on-chip loop filter. The charge
pump current is preset to 224 μA and cannot be changed.
9.3.6 On-Chip PLL Loop Filter
Figure 14 shows the on-chip active loop filter topology implemented in the device. This design corresponds to a
PLL bandwidth of 400 kHz for a PFD in the range of 21.875 MHz to 28.47 MHz, and a charge pump current of
224 μA.
473.5 pF
Charge Pump
Output
20 kW
15 kW
VCO Control
Figure 14. On-Chip PLL Loop Filter Topology
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9.3.7 Prescaler Divider and Feedback Divider
The VCO output is routed to the prescaler divider and then to the feedback divider. The prescaler divider and
feedback divider are set in tandem with each other, according to the control pin settings given in Table 5. The
allowable combinations of the two dividers ensure that the VCO frequency and the PFD frequency are within the
specified limits.
9.3.8 On-Chip VCO
The CDCM61004 includes an on-chip, LC oscillator-based VCO with low phase noise covering a frequency
range of 1.75 GHz to 2.05 GHz. The VCO must be calibrated to ensure proper operation over the valid device
operating conditions. This calibration requires that the PLL be set up properly to lock the PLL loop and that the
reference clock input be present. During the first device initialization after power-up, which occurs after the
Power-On-Reset is released (2.64 V or lower, over valid device operating conditions) or a device reset with the
RSTN pin, a VCO calibration sequence is initiated after 16,384 × Reference Input Clock Cycles. The VCO
calibration then takes about 20 µs over the allowable range of the reference clock input.
The VCO calibration can also be reinitiated with a pulse on the RSTN pin at any time after POR is released on
power-up; the RSTN pulse must be at least 100 ns wide.
For proper device operation, the reference input must be stable at the start of VCO calibration. Since inputs from
crystals or crystal oscillators can typically take up to 1-2ms to be stable, TI recommends to establish circuitry on
the RSTN pin that ensures device initialization including VCO calibration after a delay of greater than 5 ms
compared to the power-up ramp, as shown in Figure 15. A possible implementation of the delay circuitry on the
RSTN pin would be a 47-nF capacitor to GND, and this in tandem with the 150-kΩ on-chip pullup resistor
ensures the appropriate delay. The CE pin has an internal 150-kΩ pullup resistor and can be left unconnected or
pulled to high for proper device operation.
The device can operate at temperatures within the ambient temperature range TA. Within the ambient
temperature limits and after the point in time when the VCO calibrated, the absolute temperature drift must be
smaller than the maximum allowable temperature drift for continuous lock |TCL| for the PLL to stay in lock to an
appropriate input reference. When a larger absolute temperature drift has to be covered, the VCO needs to be
re-calibrated as described above.
tCE>0
3.3 V
Vtrigger(POR)
tRST = 5 ms
RSTN
CE
VIL, RST
VIH
Figure 15. Suggested Timing Recommendations
9.3.9 LVCMOS Input Interface
Alternately, the CDCM61004 can be operated with an external AC-coupled 2.5-V LVCMOS or DC-coupled 3.3-V
LVCMOS reference input applied to the XIN pin. For proper operation, the LVCMOS reference should be
available and fairly stable by the time the power supply voltages or the RSTN pin voltage on the CDCM61004
reaches 2.27 V. For more details about the LVCMOS input interface to the CDCM61004, see the application
report, Using LVCMOS Input to the CDM6100x (SCAA111), available on ti.com.
9.3.10 Output Divider
The output from the prescaler divider is also routed to the output divider. The output divider can be set with
control pins according to Table 6.
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9.3.11 Output Buffer
Each output buffer can be set to LVPECL or LVDS or 2x LVCMOS, according to Table 7. OSC_OUT is an
LVCMOS output that can be used to monitor proper loading of the input crystal to achieve the necessary crystal
frequency with the least error. The OSC_OUT turns on as soon as power is available and remains on during
deviec calibration. The output buffers are disabled during VCO calibration and are enabled only after calibration
is complete.
The output buffers on the CDCM61004 can also be disabled, along with other sections of the device, using the
CE pin according to Table 8.
9.4 Device Functional Modes
Table 3. Common Configuration
INPUT (MHz)
PRESCALER
DIVIDER
FEEDBACK
DIVIDER
VCO
FREQUENCY
(MHz)
OUTPUT
DIVIDER
OUTPUT
FREQUENCY
(MHz)
APPLICATION
25
4
20
2000
8
62.5
GigE
24.75
3
24
1782
8
74.25
HDTV
25
3
24
1800
8
75
SATA
24.8832
3
25
1866.24
8
77.76
SONET
25
3
24
1800
6
100
PCI express
26.5625
3
24
1912.5
6
106.25
Fibre channel
25
4
20
2000
4
125
GigE
25
3
24
1800
4
150
SATA
24.8832
3
25
1866.24
4
155.52
SONET
25
3
25
1875
4
156.25
10 GigE
26.5625
3
24
1912.5
4
159.375
10-G Fibre channel
25
5
15
1875
2
187.5
12 GigE
25
3
24
1800
3
200
PCI Express
26.5625
3
24
1912.5
3
212.5
4-G Fibre channel
25
4
20
2000
2
250
GigE
24.8832
3
25
1866.24
2
311.04
SONET
25
3
25
1875
2
312.5
XGMII
24.8832
3
25
1866.24
1
622.08
SONET
25
3
25
1875
1
625
10 GigE
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Table 4. Generic Configuration
INPUT FREQUENCY
RANGE (MHz)
PRESCALER
DIVIDER
FEEDBACK
DIVIDER
VCO FREQUENCY
RANGE (MHz)
OUTPUT DIVIDER
OUTPUT
FREQUENCY
RANGE (MHz)
21.875 to 25.62
4
20
1750 to 2050
8
54.6875 to 64.05
21.875 to 25.62
4
20
1750 to 2050
6
72.92 to 85.4
21.875 to 25.62
4
20
1750 to 2050
4
109.375 to 128.1
21.875 to 25.62
4
20
1750 to 2050
3
145.84 to 170.8
21.875 to 25.62
4
20
1750 to 2050
2
218.75 to 256.2
21.875 to 25.62
4
20
1750 to 2050
1
437.5 to 512.4
23.33 to 27.33
3
25
1750 to 2050
8
72.906 to 85.408
23.33 to 27.33
3
25
1750 to 2050
6
97.21 to 113.875
23.33 to 27.33
3
25
1750 to 2050
4
145.812 to 170.816
23.33 to 27.33
3
25
1750 to 2050
3
194.42 to 227.75
23.33 to 27.33
3
25
1750 to 2050
2
291.624 to 341.632
23.33 to 27.33
3
25
1750 to 2050
1
583.248 to 683.264
23.33 to 27.33
5
15
1750 to 2050
8
43.75 to 51.25
23.33 to 27.33
5
15
1750 to 2050
6
58.33 to 68.33
23.33 to 27.33
5
15
1750 to 2050
4
87.5 to 102.5
23.33 to 27.33
5
15
1750 to 2050
3
116.66 to 136.66
23.33 to 27.33
5
15
1750 to 2050
2
175 to 205
23.33 to 27.33
5
15
1750 to 2050
1
350 to 410
24.305 to 28.47
3
24
1750 to 2050
8
72.915 to 85.41
24.305 to 28.47
3
24
1750 to 2050
6
97.22 to 113.88
24.305 to 28.47
3
24
1750 to 2050
4
145.83 to 170.82
24.305 to 28.47
3
24
1750 to 2050
3
194.44 to 227.76
24.305 to 28.47
3
24
1750 to 2050
2
291.66 to 341.64
24.305 to 28.47
3
24
1750 to 2050
1
583.32 to 683.28
Table 5. Programmable Prescaler and Feedback Divider Settings
CONTROL INPUTS
20
PFD FREQUENCY
PR1
PR0
PRESCALER
DIVIDER
FEEDBACK
DIVIDER
MIN
MAX
0
0
3
24
24.305
28.47
0
1
5
15
23.33
27.33
1
0
3
25
23.33
27.33
1
1
4
20
21.875
25.62
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Table 6. Programmable Output Divider
CONTROL INPUTS
OUTPUT DIVIDER
OD2
OD1
OD0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
Reserved
1
0
1
6
1
1
0
Reserved
1
1
1
8
Table 7. Programmable Output Type
CONTROL INPUTS
OUTPUT TYPE
OS1
OS0
0
0
0
1
LVDS, OSC_OUT Off
1
0
LVPECL, OSC_OUT Off
1
1
LVPECL, OSC_OUT On
LVCMOS, OSC_OUT Off
Table 8. Output Enable
CONTROL INPUT
CE
OPERATING
CONDITION
OUTPUT
0
Power down
High-Z
1
Normal
Active
Table 9. Reset
CONTROL INPUT
RSTN
OPERATING
CONDITION
OUTPUT
0
Device reset
High-Z
0→1
PLL recalibration
High-Z
1
Normal
Active
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Start-Up Time Estimation
The CDCM61004 start-up time can be estimated based on the parameters defined in Table 10 and graphically
shown in Figure 16.
Table 10. Start-Up Time Dependencies
PARAMETER
DEFINITION
DESCRIPTION
FORMULA/METHOD OF
DETERMINATION
1
fREF
tREF
Reference clock period
The reciprocal of the applied reference
frequency in seconds.
tpul
Power-up time (low limit)
Power-supply rise time to low limit of Power
On Reset (POR) trip point
Time required for power
supply to ramp to 2.27 V
tpuh
Power-up time (high limit)
Power supply rise time to high limit of POR
trip point
Time required for power
supply to ramp to 2.64 V
trsu
Reference start-up time
After POR releases, the Colpits oscillator is
enabled. This start-up time is required for the
500 μs best-case and 800 μs
oscillator to generate the requisite signal
worst-case
levels for the delay block to be clocked by
the reference input.
tdelay
Delay time
Internal delay time generated from the
reference clock. This delay provides time for
the reference oscillator to stabilize.
tdelay= 16384 × tref
tVCO_CAL
VCO calibration time
VCO Calibration Time generated from the
reference clock. This process selects the
operating point for the VCO based on the
PLL settings.
tVCO_CAL= 550 × tref
tPLL_LOCK
PLL lock time
Based on the 400-kHz loop
Time required for PLL to lock within ±10 ppm
bandwidth, the PLL settles in
of fREF
5τ or 12.5 μs.
22
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Power Supply (V)
Power up
Reference
Startup
Delay
VCO Calibration
PLL Lock
2.64 V
2.27 V
tpul
trsu
Time (s)
tpuh
tVCO_CAL
tPLL_LOCK
tdelay
Figure 16. Start-up Time Dependencies
The CDCM61004 start-up time limits, tMAX and tMIN, can be calculated as follows in Equation 3 and Equation 4:
tMAX = tpuh + trsu + tdelay + tVCO_CAL + tPLL_LOCK
tMIN = tpul + trsu + tdelay + tVCO_CAL + tPLL_LOCK
(3)
(4)
10.1.2 Output Termination
The CDCM61004 is a 3.3-V clock driver with the following output options: LVPECL, LVDS, or LVCMOS.
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10.1.3 LVPECL Termination
The CDCM61004 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required
to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL is
50 Ω to (VCC–2) V, but this DC voltage is not readily available on most PCBs. Thus, a Thevenin equivalent circuit
is worked out for the LVPECL termination in both direct-coupled (DC) and ac-coupled (AC) cases, as shown in
Figure 17 and Figure 18. TI recommends placing all resistive components close to either the driver end or the
receiver end. If the supply voltage of the driver and receiver are different, ac-coupling is required.
130 W
130 W
VCC_OUT
VCC_OUT
CDCM61004
LVPECL
82 W
82 W
Figure 17. LVPECL Output DC Termination
VBB
CDCM61004
LVPECL
150 W
150 W
50 W
50 W
Figure 18. LVPECL Output AC Termination
24
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10.1.4 LVDS Termination
The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the
receiver end. Either direct-coupled termination or ac-coupled termination can be used for LVDS outputs, as
shown in Figure 19 and Figure 20. TI recommends placing all resistive components close to either the driver end
or the receiver end. If the supply voltage of the driver and the receiver are different, ac-coupling is required.
100 W
CDCM61004
LVDS
Figure 19. LVDS Output DC Termination
100 W
CDCM61004
LVDS
Figure 20. LVDS Output AC Termination
10.1.5 LVCMOS Termination
Series termination is a common technique used to maintain the signal integrity for LVCMOS drivers, if connected
to a receiver with a high-impedance input with a pullup or a pulldown resistor. For series termination, a series
resistor (RS) is placed close to the driver, as shown in Figure 21. The sum of the driver impedance and RS
should be close to the transmission line impedance, which is usually 50 Ω. Because the LVCMOS driver in the
CDCM61004 has an impedance of 30 Ω, RS is recommended to be 22 Ω to maintain proper signal integrity.
RS = 22 W
CDCM61004
LVCMOS
Figure 21. LVCMOS Output Termination
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10.1.6 Interfacing Between LVPECL and HCSL
Because the LVPECL common-mode voltage is different from the HCSL common-mode voltage, ac-coupled
termination is used. The 150-Ω resistor ensures proper biasing of the CDCM61004 LVPECL output stage, while
the 471-Ω and 56-Ω resistor network biases the HCSL receiver input stage, as shown in Figure 22.
471 W
471 W
VCC_OUT
VCC_OUT
0W
CDCM61004
HCSL
0W
150 W
150 W
56 W
56 W
Figure 22. LVPECL to HCSL Interface
10.2 Typical Application
Low-jitter PHY
ref clocks
PLL
25-MHz
crystal
1.875 GHz
CLK
Dist.
156.25 MHz (2x)
3.125G
PHY
156.25 MHz (2x)
1G
PHY
Figure 23. Ethernet Switch
10.2.1 Design Requirements
Consider a typical wired communications application, like a top-of-rack switch, which needs to clock 1-Gbps or
3.125-Gbps Ethernet PHYs. For such asynchronous systems, the reference input can be a crystal. In such
systems, the clocks are expected to be available upon power up without the need for any device-level
programming. An example of clock input and output requirements is shown below:
• Clock Input:
– 25-MHz crystal
• Clock Outputs:
– 2× 156.25 MHz clock for uplink 3.125 Gbps, LVPECL
– 2× 156.25 MHz clock for downlink 3.125 Gbps, LVPECL
The section below describes the detailed design procedure to generate the required output frequencies for the
above scenario using CDCM61004.
10.2.2 Detailed Design Procedure
Design of all aspects of the CDCM61004 is quite involved and software support is available to assist in part
selection and phase noise simulation. This design procedure will give a quick outline of the process.
1. Device Selection
– The first step is to calculate the VCO frequency given the required output frequency. The device must be
able to produce the VCO frequency that can be divided down to the required output frequency.
– The WEBENCH Clock Architect Tool from TI will aid in the selection of the right device that meets the
customer's output frequencies and format requirements.
26
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Typical Application (continued)
2. Device Configuration
– The WEBENCH Clock Architect Tool attempts to maximize the phase detector frequency, use smallest
dividers, and maximizes PLL bandwidth.
10.2.2.1 Device Selection
Use the WEBENCH Clock Architect Tool. Enter the required frequencies and formats into the tool. To use this
device, find a solution using the CDCM61004.
10.2.2.1.1 Calculation Using LCM
In this example, the valid VCO frequency for CDCM61004 is 1.875 GHz.
10.2.2.2 Device Configuration
For this example, when using the WEBENCH Clock Architect Tool, the reference would have been manually
entered as 25 MHz according to input frequency requirements. Enter the desired output frequencies and click on
Generate Solutions. Select CDCM61004 from the solution list.
From the simulation page of the WEBENCH Clock Architect Tool, it can be seen that to maximize phase detector
frequencies, the N divider is set to 25 and prescaler divider is set to 3. This results in a VCO frequency of
1.875 GHz. The output divider is set to 4. At this point the design meets all input and output frequency
requirements and it is possible to design a loop filter for system and simulate performance on the clock outputs.
Figure 24 shows the typical phase noise plot of the 156.25 MHz LVPECL output.
10.2.3 Application Curve
Figure 24. Typical Phase Noise Plot of 156.25 MHz LVPECL Output
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11 Power Supply Recommendations
11.1 Power Considerations
As a result of the different possible configurations of the CDCM61004, Table 11 is intended to provide enough
information on the estimated current consumption of the device. Unless otherwise noted, VCC = 3.3 V and
TA = 25°C.
Table 11. Estimated Block Power Consumption
BLOCK
Entire device,
core current
Output buffer
Divide circuitry
CURRENT CONSUMPTION
(mA)
IN-DEVICE POWER DISSIPATION
(mW)
Output off, no termination
resistors
65
214.5
LVPECL output, active mode
28
42.4
LVCMOS output pair, static
4.5
14.85
LVCMOS output pair,
transient, 'CL' load, 'f' MHz
output frequency
V × fOUT × (CL + 20 × 10–12) × 103
V2 × fOUT × (CL + 20 × 10–12) × 103
LVDS output, active mode
20
66
Divide enabled, divide = 1
5
16.5
Divide enabled, divide = 2
10
33
Divide enabled, divide = 3, 4
15
49.5
Divide enabled, divide = 6, 8
20
66
CONDITION
EXTERNAL
RESISTOR
POWER
DISSIPATION
(mW)
50
From Table 11, the current consumption can be calculated for any configuration. For example, the current for the
entire device with four LVPECL outputs in active mode can be calculated by adding up the following blocks: core
current, 4x LVPECL output buffer current, and the divide circuitry current. The overall in-device power
consumption can also be calculated by summing the in-device power dissipated in each of these blocks.
As an example scenario, let us consider the use case of a crystal input frequency of 25 MHz and device output
frequency of 312.5 MHz in LVPECL mode. For this case, the typical overall power dissipation can be calculated
as seen in Equation 5:
3.3 V × (65 + 4 × 28 + 10) mA = 617.1 mW
(5)
Because each LVPECL output has two external resistors and the power dissipated by these resistors is 50 mW,
the typical overall in-device power dissipation is as seen in Equation 6:
617.1 mW – 4 × 50 mW = 417.1 mW
(6)
When the LVPECL output is active, the average voltage is approximately 1.9 V on each output as calculated
from the LVPECL VOH and VOL specifications. Therefore, the power dissipated in each emitter resistor is
approximately (1.9 V)2/150Ω = 25 mW.
When the LVCMOS output is active and drives a load capacitance, CL, the overall LVCMOS output current
consumption is the sum of a static pre-driver current and a dynamic switching current (which is a function of the
output frequency and the load capacitance).
Let us consider another use case of a crystal input frequency of 26.5625 MHz and device output frequency of
212.5 MHz in LVCMOS mode and driving a 5-pF load capacitance with a typical signal swing of 3.18 V. For this
case, the typical overall power dissipation can be calculated as seen in Equation 7:
3.3 V × (65 + 15 + 4 × 21.4) mA = 546.48 mW
28
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11.2 Thermal Management
Power consumption of the CDCM61004 can be high enough to require attention to thermal management. For
reliability and performance reasons, the die temperature should be limited to a maximum of 125°C. That is, as an
estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125°C.
The device package has an exposed pad that provides the primary heat removal path as well as an electrical
grounding to the printed circuit board (PCB). To maximize the removal of heat from the package, a thermal land
pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the
package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.
Check the mechanical data at the end of the data sheet for land and via pattern examples.
11.3 Power-Supply Filtering
PLL-based frequency synthesizers are very sensitive to noise on the power supply, which can dramatically
increase the jitter of the PLL. This characteristic is especially true for analog-based PLLs. Thus, it is essential to
reduce noise from the system power supply, especially when jitter/phase noise is very critical to applications. A
PLL would have attenuated jitter as a result of power-supply noise at frequencies beyond the PLL bandwidth
because of attenuation by the loop response.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly use these bypass capacitors,
they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. TI
recommends adding as many high-frequency (for example, 0.1-μF) bypass capacitors as there are supply pins in
the package.
The CDCM61004 power-supply requirements can be grouped into two sets: the analog supply line and the
output/input supply line. The analog supply line consists of the following power-supply pins on the CDCM61004:
VCC_PLL1, VCC_PLL2, and VCC_VCO. These pins can be shorted together. The output/input supply line
consists of the VCC_OUT and the VCC_IN power-supply pins on the CDCM61004. These pins can be shorted
together. Inserting a ferrite bead between the analog supply line and the output/input supply line isolates the
high-frequency switching noises generated by the device input and outputs, preventing them from leaking into
the sensitive analog supply line. Choosing an appropriate ferrite bead with very low DC resistance is important
because it is imperative to provide adequate isolation between the sensitive analog supply line and the other
board supply lines, and to maintain a voltage at the analog power-supply pins of the CDCM61004 that is greater
than the minimum voltage required for proper operation.
Figure 25 shows a general recommendation for decoupling the power supply.
Board/
Output/Input
Supply
Analog
Supply
Ferrite Bead
C
10 mF
C
0.1 mF (x5)
C
10 mF
C
0.1 mF (x3)
Figure 25. Recommended Power-Supply Decoupling
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12 Layout
12.1 Layout Guidelines
The CDCM61004 is a high-performance device; therefore careful attention must be paid to device configuration
and printed circuit board layout with respect to power consumption. Observing good thermal layout practices
enables the thermal pad on the backside of the VQFN-32 package to provide a good thermal path between the
die contained within the package and the ambient air. This thermal pad also serves as the ground connection the
device; therefore, a low inductance connection to the ground plane is essential.
12.2 Layout Example
Figure 26 shows a general recommendation of PCB layout with the CDCM61004 that ensures good system-level
thermal reliability.
Back Side
Component Side
QFN-32
Solder Mask
Thermal Slug
(package bottom)
Internal
Ground
Plane
Internal
Power
Plane
Thermal
Dissipation
Pad (back side)
Thermal Vias
No Solder Mask
Figure 26. Recommended PCB Layout
30
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, see the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CDCM61004RHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCM
61004
CDCM61004RHBR/2801
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCM
61004
CDCM61004RHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCM
61004
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Oct-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCM61004RHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
CDCM61004RHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Oct-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCM61004RHBR
VQFN
RHB
32
3000
367.0
367.0
35.0
CDCM61004RHBT
VQFN
RHB
32
250
210.0
185.0
35.0
Pack Materials-Page 2
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Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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