Sanyo LC865632 8-bit single chip microcontroller Datasheet

Ordering number : ENN*6698
CMOS IC
LC865632/28/24/20/16/12/08A
8-Bit Single Chip Microcontroller
Preliminary
Overview
The LC865632A/28A/24A/20A/16A/12A/08A microcontrollers are 8-bit single chip microcontrollers with the following
on-chip functional blocks :
- CPU : Operable at a minimum bus cycle time of 0.5µs (microsecond)
- On-chip ROM maximum capacity : 32K bytes
- On-chip RAM capacity : 640 bytes (LC865632A/28A/24A)
: 512 bytes (LC865620A/16A/12A/08A)
- 16-bit timer/counter (or two 8-bit timers)
- 16-bit timer/ PWM (or two 8-bit timers)
- 8-channel × 8-bit AD converter
- Two 8-bit synchronous serial-interface circuits
- 13-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
(1) Read Only Memory (ROM)
(2) Random Access Memory (RAM)
: LC865632A
: LC865628A
: LC865624A
: LC865620A
: LC865616A
: LC865612A
: LC865608A
32512 × 8 bits
28672 × 8 bits
24576 × 8 bits
20480 × 8 bits
16384 × 8 bits
12288 × 8 bits
8192 × 8 bits
: LC865632A/28A/24A
: LC865620A/16A/12A/08A
640 × 8 bits
512 × 8 bits
(3) Bus Cycle Time / Instruction Cycle Time
The LC865632A/28A/24A/20A/16A/12A/08A are constructed to read ROM twice within one instruction cycle. It has
1.7 times more performance capability within the same instruction cycle compared to our 4-bit microcontrollers
(LC66000 series).
Bus cycle time indicates the speed to read ROM.
Bus cycle time
0.5µs
2.0µs
3.75µs
91.5µs
Ver.2.02
22599
cycle time
1.0µs
4.0µs
7.5µs
183µs
System clock oscillation
Ceramic resonator oscillation
Ceramic resonator oscillation
RC resonator oscillation
Crystal oscillation
Oscillation Frequency
6MHz
1.5MHz
800MHZ
32.568kHz
Voltage
4.5 - 6.0V
2.5 - 6.0V
2.5 - 6.0V
2.5 - 6.0V
91400 RM (IM) HK No.6698-1/20
LC865632/28/24/20/16/12/08A
(4) Ports
- Input / output ports
: 6 ports (42 terminals)
Input/output port programmable in nibble units
: 1 port (8 terminals)
(When the N-channel open drain output is selected, the data in a bit can be inputted.)
Input/output port programmable in a bit
: 5 ports (34 terminals)
Include 15V withstand N-channel open drain output port : 3 ports (18 terminals)
- Input ports
: 2 ports (13 terminals)
(5) AD converter
- 8 channels × 8-bit AD converters
(6) Serial-interface
- Two 8-bit serial-interface circuits
LSB first / MSB first function available
- Internal 8-bit baud-rate generator in common with two serial-interface circuits
(7) Timers
- Timer0
16-bit timer / counter
2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution of Timer is 1 tCYC. (tCYC : cycle time)
- Timer 1
16-bit timer / PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
In Mode 0 and Mode 1, the resolution of Timer and PWM is tCYC.
In Mode 2 and Mode 3, the resolution of Timer and PWM selectable ; tCYC or 1/2tCYC by program
- Base timer
Every 500ms overflow system for a clock application (using 32.568kHz crystal oscillation for Base timer clock)
Every 976µs, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.568kHz crystal oscillation for Base timer clock)
The Base timer clock selectable ; 32.568kHz crystal oscillation, System clock, and programmable prescaler output of
Timer 0
(8) Buzzer output
- The Buzzer sound frequency selectable ; 4KHz, 2KHz (using 32.568kHz crystal oscillation for Base timer clock)
(9) Remote control receiver circuit (Shares with the P73/INT3/T0IN terminal)
- Noise rejection function
- Switch polarity function
(10) Watchdog timer
- The watchdog timer is taken on RC outside
- Watchdog timer operation selectable : interrupt system, system reset
No.6698-2/20
LC865632/28/24/20/16/12/08A
(11) Interrupts system
- 13-sources 10-vectored interrupts :
1. External interrupt INT0 (include watchdog timer)
2. External interrupt INT1
3. External interrupt INT2, timer / counter T0L (Lower 8 bits)
4. External interrupt INT3, base timer
5. Timer / counter T0H (Upper 8-bit)
6. Timer T1L, Timer T1H
7. Serial interface SIO0
8. Serial interface SIO1
9. AD converter
10. Port 0
- Built-in interrupt priority control register
Microcontroller allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. It can specify
a low level or a high level interrupt priority from INT2/T0L through port 0 (i.e. the above interrupt number from three
through ten). It can also specify a low level or the highest level interrupt priority to INT0 and INT1.
(12) Real-time service operation
The Real-Time Service (RTS) functions the 4-byte data-transfer between the Special Function Registers at acknowledging
the interrupt request.
The RTS starts within 1 instruction cycle-time and completes within 5 instructions cycle-time after occurring the interrupt
request.
(13) Sub-routine stack levels
- 128 levels (Max.) : stack area included in RAM area
(14) Multiplication and division
- 16 bits × 8-bit (7 instruction cycle times)
- 16 bits ÷ 8-bit (7 instruction cycle times)
(15) Three oscillation circuits
- On-chip RC oscillation circuit using for the system clock
- On-chip CR oscillation circuit using for the system clock
- On-chip crystal oscillation circuit using for the system clock and for time-base clock
XT1 terminal can be used as P74
(16) Standby function
- HALT mode function
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This
operation mode can be released by the interrupt request signals or the initial system reset request signal.
- HOLD mode function
The HOLD mode is used to freeze all the oscillations ;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations.
• Reset terminal ( RES ) set to low level
• P70/INT0, P71/INT1 terminals set to assigned level (programmable)
• Input a Port 0 interrupt condition
(17) Factory shipment
• DIP64S, QFP64E delivery form
(18) Development support tools
- Evaluation (EVA) chip
- EPROM version
- One time version
- Emulator
: LC866098
: LC86E5632
: LC86P5632
: EVA86000 + ECB866600 (Evaluation chip board)
+ POD865000 (Pod for DIP64S)
+ POD865010 (Pod for QFP64E)
No.6698-3/20
LC865632/28/24/20/16/12/08A
Pin Assignment
•DIP64S
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/BUZ
P17/PWM
TEST1
RES
XT1/P74
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P70/INT0
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
P30
P31
P32
P33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P07
P06
P05
P04
P03
P02
P01
P00
P27
P26
P25
P24
P23
P22
P21
P20
VDDVPP
VSS
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P37
P36
P35
P34
Package Dimension
(unit : mm)
3071
SANYO : DIP-64S(750mil)
No.6698-4/20
LC865632/28/24/20/16/12/08A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P17/PWM
P16/BUZ
P15/SCK1
P14/SI1/SB1
P13/SO1
P12/SCK0
P11/SI0/SB0
P10/SO0
P07
P06
P05
P04
P03
P02
P01
P00
•QIP64E
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P27
P26
P25
P24
P23
P22
P21
P20
VDDVPP
VSS
P51
P50
P47
P46
P45
P44
P70/INT0
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
P30
P31
P32
P33
P34
P35
P36
P37
P40
P41
P42
P43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TEST1
RES
XT1/P74
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
Package Dimension
(unit : mm)
3159
SANYO : QIP-64E
No.6698-5/20
LC865632/28/24/20/16/12/08A
System Block Diagram
Interrupt Control
IR
Standby Control
PLA
ROM
RC
Clock
Generator
CF
PC
X’tal
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 7
C Register
Timer 0
Port 8
ALU
Timer 1
Port 2
ADC
Port 3
PSW
INT0 to 3
Noise Filtter
Port 4
RAR
Real Time Service
Port 5
RAM
RAM
(128 bytes)
Stack Pointer
Port 0
Watchdog Timer
No.6698-6/20
LC865632/28/24/20/16/12/08A
Pin Description
Pin name
VSS
VDD
VDDVPP*
PORT0
P00 - P07
I/O
I/O
PORT1
P10 - P17
I/O
PORT2
P20 - P27
PORT3
P30 - P37
I/O
PORT4
P40 - P47
I/O
PORT5
P50, P51
I/O
I/O
Function description
Power pin (–)
Power pin (+)
Power pin (+)
• 8-bit input/output port
• Input for port 0 interrupt
• Input/output in nibble units
• Input for HOLD release
• 8-bit input/output port
• Input/output can be specified in bit unit
• Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer1 output (PWM output)
• 8-bit input/output port
• Input/output in bit unit
• 8-bit input/output port
• Input/output in bit unit
• 15V withstand at N-channel open drain
output
• 8-bit input/output port
• Input/output in bit unit
• 15V withstand at N-channel open drain
output
• 2-bit input/output port
• Input/output in bit unit
• 15V withstand at N-channel open drain
output
Option
• Pull-up resistor :
Provided/Not provided
• Output form :
CMOS/N-channel open drain
• Output form :
CMOS/N-channel open drain
• Output form :
CMOS/N-channel open drain
• Pull-up resistor :
Provided/Not provided
• Output form :
CMOS/N-channel open drain
• Pull-up resistor :
Provided/Not provided
• Output form :
CMOS/N-channel open drain
• Pull-up resistor :
Provided/Not provided
• Output form :
CMOS/N-channel open drain
* Connect like the following figure to reduce noise into a VDD terminal.
Short-circuit the VDD terminal to the VDDVPP terminal.
Short-circuit the VSS terminal to the VSS terminal.
LSI
VDD
Power
Supply
VDDVPP
VSS
VSS
No.6698-7/20
LC865632/28/24/20/16/12/08A
Pin name
PORT7
I/O
P70
I/O
P71 - P74
I
PORT8
P80 - P87
I
RES
TEST1
I
Function description
Option
• 5-bit input port
• Pull-up resistor :
• Other pin functions
Provided/Not provided
P70 : INT0 input/HOLD release/N-channel
(P70,71,72,73)
Tr. output for watchdog timer
• P74 does not have Pull-up resistor
P71 : INT1 input/HOLD release input
option
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0
event input
P74 : Input pin XT1 for 32.768kHz crystal
oscillation
• Interrupt received form, vector address
rising falling rising
high
low
vector
&
level
level
falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
• 8-bit input port
• Pin description
AD input port (8 port pins)
Reset pin
-
O
• Test pin
Should be left unconnected
• Output fixed HIGH
I
• Input pin for 32.768kHz crystal oscillation
XT1/ P74
In case of non use, connect to VDD
• Other function : Input port P74
XT2
O
• Output pin for 32.768kHz crystal oscillation
• In case of non use, should be left
unconnected
CF1
I
Input pin for ceramic resonator oscillation
CF2
O
Output pin for ceramic resonator oscillation
* All of port options can be specified in bit unit.
* A state of pins at reset
Pin name
Input/output mode
Port 0
Input
Ports 70,71,72,73
Ports 1,2,3,4,5
Input
-
-
-
A state of pull-up resistor specified at pull-up option
Fixed pull-up resistor exist
Programmable pull-up resistor OFF
No.6698-8/20
LC865632/28/24/20/16/12/08A
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Parameter
Symbol
Supply voltage
Input voltage
VDDMAX
VI(1)
Input/output
voltage
VIO(1)
IOPH(1)
VDD,VDDVPP
•Ports 71,72,73, 74
•Port 8
• RES
•Ports 0,1,2
•Ports 3,4,5 at
CMOS output
option
Ports 3,4,5 at N-ch
open drain output
option
Ports 0,1,2,3,4,5
ΣIOAH(1)
ΣIOAH(2)
VIO(2)
High
level
output
current
Low
level
output
current
Peak
output
current
Total
output
current
Peak
output
current
Total
output
current
Maximum power
dissipation
Operating
temperature
range
Storage
temperature
range
Pins
Conditions
VDD=VDDVPP
VDD[V]
min.
-0.3
-0.3
Ratings
typ.
max.
+7.0
VDD+0.3
-0.3
VDD+0.3
-0.3
15
•CMOS output
•At each pin
-4
Ports 0,1
Ports 2,3,4,5
Total all pins
Total all pins
-20
-20
IOPL(1)
IOPL(2)
Ports 0,1,2,3,4,5
Port 70
At each pin
At each pin
20
15
ΣIOAL(1)
Ports 0,1
Port 70
Port 2
Ports 3,4,5
DIP64S
QFP64E
Total all pins
40
Total all pins
Total all pins
Ta=-30 to +70°C
Ta=-30 to +70°C
-30
40
80
670
420
+70
-65
+150
ΣIOAL(2)
ΣIOAL(3)
Pdmax(1)
Pdmax(2)
Topr
Tstg
unit
V
mA
mW
°C
No.6698-9/20
LC865632/28/24/20/16/12/08A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Parameter
Symbol
Pins
Operating
supply voltage
range
VDD(1)
Hold voltage
VHD
VDD
Input high
voltage
VIH(1)
Port 0 (Schmitt)
VIH(2)
•Ports 1,2
•Ports 72,73 (Schmitt)
•Port 70
(Port input/interrupt)
•Port 71
• RES (Schmitt)
Port 70
(Watchdog timer)
•Port 74
•Port 8
Ports 3,4,5 of
CMOS output
Ports 3,4,5 of open
drain output
Port 0 (Schmitt)
•Ports 1,2,3,4,5
•Ports 72,73 (Schmitt)
•Port 70
(Port input/interrupt)
•Port 71
• RES (Schmitt)
Port 70
(Watchdog timer)
•Port 74
•Port 8
VDD(2)
VIH(3)
VIH(4)
VIH(5)
VIH(6)
VIH(7)
Input low
voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
Operation
cycle time
VDD
Conditions
VDD[V]
0.98µs ≤ tCYC ≤
400µs
3.9µs ≤ tCYC ≤
400µs
RAMs and the
registers hold
voltage at HOLD
mode.
Output disable
2.5-6.0
Output disable
min.
4.5
Ratings
typ.
max.
6.0
2.5
6.0
2.0
6.0
VDD
2.5-6.0
0.4VDD
+0.9
0.75VDD
VDD
Output N-channel
Tr. OFF
2.5-6.0
0.75VDD
VDD
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Output disable
2.5-6.0
0.9VDD
VDD
2.7-6.0
0.75VDD
VDD
4.0-6.0
2.5-4.0
4.0-6.0
2.5-4.0
2.5-6.0
2.5-6.0
0.75VDD
0.8VDD
0.75VDD
0.8VDD
VSS
VSS
VDD
VDD
13.5
13.5
0.2VDD
0.25VDD
N-channel
Tr. OFF
2.5-6.0
VSS
0.25VDD
N-channel
Tr. OFF
Output N-channel
Tr. OFF
2.5-6.0
VSS
2.5-6.0
VSS
0.8VDD
-1.0
0.25VDD
4.5-6.0
2.5-6.0
0.98
3.9
400
400
Output disable
Output disable
Output disable
tCYC
unit
V
µs
Continue.
No.6698-10/20
LC865632/28/24/20/16/12/08A
Parameter
Symbol
Oscillation
FmCF(1)
frequency
range
(Note 1)
FmCF(2)
Oscillation
stabilizing
time period
(Note 1)
Pins
CF1, CF2
CF1, CF2
FmRC
FsXtal
XT1, XT2
tmsCF(1)
CF1, CF2
tmsCF(2)
CF1, CF2
tssXtal
XT1, XT2
Conditions
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
•1.5MHz
(ceramic resonator
oscillation)
•Refer to figure 1
RC oscillation
•32.768kHz
(crystal oscillation)
•Refer to figure 2
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•1.5MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•32.768kHz
(crystal oscillation)
•Refer to figure 3
VDD[V]
4.5-6.0
min.
2.5-6.0
2.5-6.0
2.5-6.0
4.5-6.0
Ratings
typ.
6
max.
unit
MHz
1.5
0.3
0.8
32.768
3.0
kHz
ms
4.5-6.0
2.5-6.0
4.5-6.0
2.5-6.0
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6698-11/20
LC865632/28/24/20/16/12/08A
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
Input high
current
Input low
current
Output high
voltage
Output low
voltage
Pull-up MOS
Tr. resistor
Hysteresis
voltage
Pin capacitance
Symbol
Pins
IIH(1)
Ports 3,4,5 of open
drain output
IIH(2)
•Port 0 without
pull-up MOS Tr.
•Ports 1,2,3,4,5
IIH(3)
•Ports 70,71,72,73
without pull-up
MOS Tr.
•Port 8
IIH(4)
IIL(1)
RES
•Ports 1,2,3,4,5
•Port 0 without
pull-up MOS Tr.
IIL(2)
•Ports 70,71,72,73
without pull-up
MOS Tr.
•Port 8
IIL(3)
VOH(1)
VOH(2)
VOL(1)
VOL(2)
VOL(3)
RES
VOL(4)
VOL(5)
Rpu
VHIS
CP
Ports 0,1,2,3,4,5 of
CMOS output
Ports 0,1,2,3,4,5
Port 70
•Ports 0,1,2,3,4,5
•Ports 70,71,72,73
•Ports 0,1,2,3,4,5
•Ports 70,71,72,73
• RES
All pins
Conditions
•Output disable
•VIN=13.5V
(including the offleak current of the
output Tr.)
•Output disable
•Pull-up MOS Tr.
OFF. VIN=VDD
(including the offleak current of the
output Tr.)
•VIN=VDD
VDD[V]
2.5-6.0
min.
1
2.5-6.0
1
2.5-6.0
2.5-6.0
-1
2.5-6.0
-1
VIN=VSS
IOH=-1.0mA
IOH=-0.1mA
IOL=10mA
IOL=1.6mA
•IOL=1.0mA
•The current of any
unmeasurement pin
is not over 1 mA.
IOL=1mA
IOL=0.5mA
VOH=0.9VDD
2.5-6.0
4.5-6.0
2.5-6.0
4.5-6.0
4.5-6.0
2.5-6.0
-1
VDD-1
VDD-0.5
•f=1MHz
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
max.
5
2.5-6.0
VIN=VDD
•Output disable
•Pull-up MOS
Tr. OFF. VIN=VSS
(including the offleak current of the
output Tr.)
•VIN=VSS
Output disable
Ratings
typ.
4.5-6.0
2.5-6.0
4.5-6.0
2.5-4.5
2.5-6.0
2.5-6.0
unit
µA
1
V
1.5
0.4
0.4
15
25
40
70
0.1VDD
10
0.4
0.4
70
150
kΩ
V
pF
No.6698-12/20
LC865632/28/24/20/16/12/08A
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V
Serial input
Input clock
Pins
tCKCY(1) SCK0,
SCK1
tCKL(1)
tCKCY(2) SCK0,
SCK1
tCKL(2)
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Data set up time
tICK
Data hold time
tCKI
Output delay time
(Serial clock is
external clock)
Serial output
Symbol
Output clock
Serial clock
Parameter
Output delay time
(Serial clock is
internal clock)
Conditions
Refer to figure 5.
tCKH(1)
tCKH(2)
tCKO(1)
tCKO(2)
•SI0,SI1
•SB0,SB1
•SO0,SO1
•SB0,SB1
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Refer to figure 5.
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5.
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Data hold from
SCK0,1
•Refer to figure 5.
VDD[V]
2.7-6.0
2.7-6.0
min.
2
1
2.7-6.0
1
2.7-6.0
2.7-6.0
2
4.5-6.0
2.7-6.0
4.5-6.0
0.1
0.4
0.1
2.7-6.0
0.4
2.7-6.0
4.5-6.0
2.7-6.0
max.
unit
tCYC
1/2
tCKCY
1/2
tCKCY
2.7-6.0
4.5-6.0
Ratings
typ.
µs
7/12
tCYC
+0.2
7/12
tCYC
+1
1/3
tCYC
+0.2
1/3
tCYC
+1
No.6698-13/20
LC865632/28/24/20/16/12/08A
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V
Parameter
High/low level
pulse width
Symbol
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
Pins
Conditions
VDD[V]
2.7-6.0
min.
1
Interrupt acceptable
2.7-6.0
2
•INT0, INT1
•INT2/T0IN
•INT3
INT3/T0IN
(The noise rejection
clock is selected to
1/1.)
INT3/T0IN
(The noise rejection
clock is selected to
1/16.)
•Interrupt acceptable
•Timer0-countable
Interrupt acceptable
2.7-6.0
32
RES
Reset acceptable
4.5-6.0
200
tPIL(4)
Ratings
typ.
max.
unit
tCYC
µs
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS=0V
Parameter
Symbol
Pins
Resolution
N
Absolute precision ET
(Note 2)
Conversion time
tCAD
Analog input
voltage range
Analog port
input current
VAIN
IAINH
IAINL
Conditions
AD conversion time =
16 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
(Note 3)
AN0 - AN7
VAIN=VDD
VAIN=VSS
Ratings
typ.
8
max.
unit
VDD[V]
4.5-6.0
4.5-6.0
min.
4.5-6.0
15.68
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
31.36
(tCYC=
0.98µs)
130.56
(tCYC=
4.08µs)
4.5-6.0
VSS
VDD
V
4.5-6.0
4.5-6.0
1
µA
-1
±1.5
bit
LSB
µs
(Note 2) Absolute precision excepts quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6698-14/20
LC865632/28/24/20/16/12/08A
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter
Current dissipation
during basic
operation
(Note 4)
Symbol
IDDOP(1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
Pins
VDD
Conditions
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•FmCF=1.5MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
Ratings
typ.
10
max.
20
4.5-6.0
2.7-4.5
3
1.5
7
5
4.5-6.0
2.7-4.5
1.0
0.6
3.5
3.0
4.5-6.0
2.7-4.5
50
25
150
75
VDD[V]
4.5-6.0
min.
unit
mA
µA
Continue.
No.6698-15/20
LC865632/28/24/20/16/12/08A
Parameter
Symbol
Current dissipation
IDDHALT(1)
in HALT mode
(Note 4)
Pins
VDD
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
Current dissipation
IDDHOLD(1) VDD
in HOLD mode
IDDHOLD(2)
(Note 4)
Conditions
•HALT mode
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•HALT mode
•FmCF=1.5MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•HALT mode
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•HALT mode
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
HOLD mode
Ratings
typ.
5
max.
10
4.5-6.0
2.7-4.5
2.2
0.8
4.6
2.5
4.5-6.0
2.7-4.5
800
400
2000
1500
4.5-6.0
2.7-4.5
35
11
140
56
4.5-6.0
0.05
30
2.7-4.5
0.02
20
VDD[V]
4.5-6.0
min.
unit
mA
µA
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6698-16/20
LC865632/28/24/20/16/12/08A
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type
Maker
Oscillator
C1
C2
Rf
12MHz ceramic resonator
Murata
CSA12.0MTZ
33pF
33pF
OPEN
oscillation
CSA12.0MTZ
39pF
30pF
OPEN
CST12.0MTW
on chip
OPEN
3MHz ceramic resonator
Murata
CSA3.00MG040
100pF
100pF
OPEN
oscillation
CST3.00MGW040
on chip
OPEN
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Rd
560Ω
0Ω
560Ω
1.5Ω
1.5Ω
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type
Maker
Oscillator
C3
C4
32.768kHz crystal oscillation
Kyocera
KF-38G-13P0200
18pF
18pF
Seiko Epson MC-306,C-002RX,32.768kHz
4pF
4pF
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.)
(Notes)
•Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to
the oscillation pins as possible with the shortest possible pattern length.
CF1
CF2
XT1
XT2
Rf
Rd
X’tal
C1
Figure 1
CF
C2
Main-clock circuit
Ceramic oscillation circuit
C3
C4
Figure 2
Sub-clock circuit
Crystal oscillation
No.6698-17/20
LC865632/28/24/20/16/12/08A
VDD
VDD limit
OV
Power supply
Reset time
RES
Interrnal RC
resonator
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution mode
< Reset time and oscillation stabilizing time. >
HOLD release signal
Valid
Interrnal RC
resonator
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Instruction execution mode
< HOLD release signal and oscillation stabilizing time. >
Figure 3
Oscillation stable time
No.6698-18/20
LC865632/28/24/20/16/12/08A
VDD
RRES
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has been over inferior limit of
supply voltage.
RES
CRES
Figure 4
Reset circuit
0.5VDD
<AC timing point>
tCKCY
tCKL
VDD
tCKH
SCK0
SCK1
1KΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
Figure 5
<Test load>
Serial input / output test condition
tPIL
Figure 6
tPIH
Pulse input timing condition
No.6698-19/20
LC865632/28/24/20/16/12/08A
memo:
PS No.6698-20/20