CDC536 www.ti.com SCAS378G – APRIL 1994 – REVISED JULY 2004 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS FEATURES • • • • • • • • • • • • • Low-Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Six Outputs One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency No External RC Network Required External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input Application for Synchronous DRAM, High-Speed Microprocessor Negative-Edge-Triggered Clear for Half-Frequency Outputs TTL-Compatible Inputs and Outputs Outputs Drive 50-Ω Parallel-Terminated Transmission Lines State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation Distributed VCC and Ground Pins Reduce Switching Noise Packaged in Plastic 28-Pin Shrink Small Outline Package DB OR DL PACKAGE (TOP VIEW) AVCC AGND CLKIN SEL OE GND 1Y1 VCC GND 1Y2 VCC GND 1Y3 VCC 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 AVCC AGND FBIN TEST CLR VCC 2Y1 GND VCC 2Y2 GND VCC 2Y3 GND DESCRIPTION The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50-W transmission line. The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN. The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock. Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-IIB is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1994–2004, Texas Instruments Incorporated CDC536 www.ti.com SCAS378G – APRIL 1994 – REVISED JULY 2004 Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of all outputs via OE. The CDC536 is characterized for operation from 0°C to 70°C. DETAILED DESCRIPTION OF OUTPUT CONFIGURATIONS The voltage-controlled oscillator (VCO) in the CDC536 has a frequency range of 100 MHz to 200 MHz, twice the operating frequency range of the CDC536 outputs. The output of the VCO is divided by two and by four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. The SEL0 and SEL1 inputs determine which of the two signals are buffered to each bank of device outputs. One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the frequency of this output matches that of the CLKIN signals. In the case that a VCO/2 output is wired to FBIN, the VCO must operate at twice the CLKIN frequency, resulting in device outputs that operate at the same or one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at the same or twice the CLKIN frequency. Output Configuration A Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to the FBIN input. The input frequency range for the CLKIN input is 50 MHz to 100 MHz when using output configuration A. Outputs configured as 1/2× outputs operate at half the CLKIN frequency, while outputs configured as 1× outputs operate at the same frequency as the CLKIN input. Table 1. Output Configuration A INPUTS OUTPUTS SEL 1/2× FREQUENCY 1× FREQUENCY L None All H 1Yn 2Yn Output Configuration B Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to FBIN. The input frequency range for the CLKIN input is 25 MHz to 50 MHz when using output configuration B. Outputs configured as 1× outputs operate at the CLKIN frequency, while outputs configured as 2× outputs operate at double the frequency of the CLKIN input. Table 2. Output Configuration B INPUTS 2× FREQUENCY L All None H 1Yn 2Yn SEL 2 OUTPUTS 1× FREQUENCY CDC536 www.ti.com SCAS378G – APRIL 1994 – REVISED JULY 2004 FUNCTIONAL BLOCK DIAGRAM OE 5 24 CLR FBIN 26 Phase-Lock Loop 3 CLKIN TEST SEL 2 2 25 4 7 10 13 22 19 16 1Y1 1Y2 1Y3 2Y1 2Y2 2Y3 3 CDC536 www.ti.com SCAS378G – APRIL 1994 – REVISED JULY 2004 FUNCTIONAL BLOCK DIAGRAM (continued) Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION CLKIN 3 I Clock input. CLKIN provides the clock signal to be distributed by the CDC536 clock-driver circuit. CLKIN is used to provide the reference signal to the integrated phase-lock loop that generates the clock output signals. CLKIN must have a fixed frequency and fixed phase in order for the phase-lock loop to obtain phase lock. Once the circuit is powered up and a valid CLKIN signal is applied, a stabilization time is required for the phase-lock loop to phase lock the feedback signal to its reference signal. CLR 24 I CLR is used for testing purposes only. Connect CLR to GND for normal operation. FBIN 26 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of the six clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to obtain zero phase delay between the FBIN and differential CLKIN inputs. OE 5 I Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE is high, all outputs are in the high-impedance state. Since the feedback signal for the phase-lock loop is taken directly from an output, placing the outputs in the high-impedance state interrupts the feedback loop; therefore, when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is required before the phase-lock loop obtains phase lock. SEL 4 I Output configuration select. SEL selects the output configuration for each output bank (e.g. 1×, 1/2×, or 2×).(see Tables 1 and 2). TEST 25 I TEST is used to bypass the phase-lock loop circuitry for factory testing of the device. When TEST is low, all outputs operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses the PLL circuitry. TEST should be grounded for normal operation. 1Y1-1Y3 7, 10, 13 O These outputs are configured by SEL to transmit one-half or one-fourth the frequency of the VCO. The relationship between the CLKIN frequency and the output frequency is dependent on SEL. The duty cycle of the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal. 2Y1-2Y3 22, 19, 16 O These outputs transmit one-half the frequency of the VCO. The relationship between the CLKIN frequency and the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty cycle of the Y output signals is nominally 50% independent of the duty cycle of the CLKIN signal. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, VCC Input voltage range, VI (see -0.5 V to 4.6 V (2)) -0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO(see (2)) -0.5 V to 5.5 V Current into any output in the low state, IO 64 mA Input clamp current, IIK(VI < 0) -20 mA Output clamp current, IOK(VO < 0) Maximum power dissipation at TA = 55°C (in still air) (see Operating free-air temperature range, TA Storage temperature range, Tstg (1) (2) (3) 4 -50 mA (3)): DB package 0.68 W DL package 0.7 W 0°C to 70°C -65°C to 150°C Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. CDC536 www.ti.com SCAS378G – APRIL 1994 – REVISED JULY 2004 RECOMMENDED OPERATING CONDITIONS (SEE (1) ) MIN MAX VCC Supply voltage 3 3.6 VIH High-level input voltage 2 VIL Low-level input voltage VI Input voltage IOH High-level output current IOL Low-level output current TA Operating free-air temperature (1) UNIT V V 0.8 0 0 V 5.5 V 32 mA 32 mA 70 °C Unused inputs must be held high or low. ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK MIN MAX II = -18 mA VCC = MIN to MAX (1), IOH = -100 µA VCC = 3 V, IOH = -32 mA VCC = 3 V, IOL = 100 µA 0.2 VCC = 3 V, IOL = 32 mA 0.5 VCC = 0 or MAX (1), VI = 3.6 V ±10 VCC = 3.6 V, VI = VCC or GND ±1 IOZH VCC = 3.6 V, VO = 3 V 10 µA IOZL VCC = 3.6 V, VO = 0 10 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND VOL II 1.2 UNIT VCC = 3 V, VOH (1) TA = 25°C TEST CONDITIONS VCC-0.2 V V 2 Outputs high 2 Outputs low 2 Outputs disabled 2 V µA mA Ci VI = VCC or GND 6 pF Co VO = VCC or GND 9 pF For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. TIMING REQUIREMENTS over recommended ranges of supply voltage and operating free-air temperature MIN fclock Clock frequency When VCO is operating at four times the CLKIN frequency 25 50 When VCO is operating at double the CLKIN frequency 50 100 40% 60% Input clock duty cycle Stabilization time (1) (1) MAX After SEL 50 After OE↓ 50 After power up 50 After CLKIN 50 UNIT MHz µs Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable. 5 CDC536 www.ti.com SCAS378G – APRIL 1994 – REVISED JULY 2004 SWITCHING CHARACTERISTICS over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Figure 2) PARAMETER FROM (INPUT) (1) and Figure 1 and TO (OUTPUT) MIN Y 45% 55% CLKIN↑ Y 500 +500 ps CLKIN↑ Y 200 ps 0.5 ns fmax MAX 100 Duty cycle tphase error (2) Jitter(pk-pk) UNIT MHz tsk(o) (2) tsk(pr) 1 ns tr 1.4 ns tf 1.4 ns (1) (2) The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. The propagation delay, tphase error, is dependent on the feedback path from any output to FBIN. The tphase error, tsk(o), and tsk(pk) specifications are only valid for equal loading of all outputs. PARAMETER MEASUREMENT INFORMATION 3V Input 1.5 V 1.5 V 0V tphase error From Output Under Test CL = 30 pF (see note A) 500 2V 0.8 V Output tr LOAD CIRCUIT FOR OUTPUTS 0.8 V VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES A. NOTES: . CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR≤ 100 MHz, ZO = 50 Ω, tr≤ 2.5 ns, tf≤ 2.5 ns. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 VOH 2V 1.5 V CDC536 www.ti.com SCAS378G – APRIL 1994 – REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION (continued) CLKIN tphase error 1 Outputs Operating at 1/2 CLKIN Frequency tphase error 2 tphase error 3 Outputs Operating at CLKIN Frequency A. B. tphase error 4 tphase error 7 tphase error 5 tphase error 8 tphase error 6 tphase error 9 NOTES: . Output skew, tsk(o), is calculated as the greater of: • The difference between the fastest and slowest of tphase error n (n = 1, 2, . . . 6) • The difference between the fastest and slowest of tphase error n (n = 7, 8, 9) Process skew, tsk(pr), is calculated as the greater of: • The difference between the maximum and minimum tphase identical operating conditions. • The difference between the maximum and minimum tphase identical operating conditions. error n (n = 1, 2, . . . 6) across multiple devices under error n (n = 7, 8, 9) across multiple devices under Figure 2. Skew Waveforms and Calculations 7 CDC536 www.ti.com SCAS378G – APRIL 1994 – REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION (continued) CLKIN tphase error 10 Outputs Operating at CLKIN Frequency tphase error 11 tphase error 12 tphase error 13 Outputs Operating at 2× CLKIN Frequency tphase error 14 tphase error 15 A. NOTES: . Output skew, tsk(o), is calculated as the greater of: B. Process skew, tsk(pr), is calculated as the greater of: • • The difference between the fastest and slowest of tphase error n (n = 10, 11, . . . 15) The difference between the maximum and minimum tphase under identical operating conditions. error n (n = 10, 11, . . . 15) across multiple devices Figure 3. Waveforms for Calculation of tsk(o) and tsk(pr) 8 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDC536DB ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC536DBG4 ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC536DBR ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC536DBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC536DL OBSOLETE SSOP DL 28 TBD Call TI Call TI CDC536DLR OBSOLETE SSOP DL 28 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDC536DBR Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.1 10.4 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC536DBR SSOP DB 28 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 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