LINER LTC1661 Micropower dual 10-bit dac in msop Datasheet

LTC1661
Micropower Dual
10-Bit DAC in MSOP
FEATURES
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DESCRIPTION
Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Board Space of an SO-8
Micropower: 60µA per DAC
Sleep Mode: 1µA for Extended Battery Life
Rail-to-Rail Voltage Outputs Drive 1000pF
Wide 2.7V to 5.5V Supply Range
Double Buffered for Independent or Simultaneous
DAC Updates
Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
Reference Input Has Constant Impedance over All
Codes (260kΩ Typ)—Eliminates External Buffers
3-Wire Serial Interface with Schmitt Trigger Inputs
Differential Nonlinearity: ≤±0.75LSB Max
APPLICATIONS
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Mobile Communications
Digitally Controlled Amplifiers and Attenuators
Portable Battery-Powered Instruments
Automatic Calibration for Manufacturing
Remote Industrial Devices
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
The LTC®1661 integrates two accurate, serially addressable, 10-bit digital-to-analog converters (DACs) in a single
tiny MS8 package. Each buffered DAC draws just 60µA
total supply current, yet is capable of supplying DC output
currents in excess of 5mA and reliably driving capacitive
loads up to 1000pF. Sleep mode further reduces total
supply current to a negligible 1µA.
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external
form factor. The double-buffered input logic provides
simultaneous update capability and can be used to write
to either DAC without interrupting sleep mode.
Ultralow supply current, power-saving sleep mode and
extremely compact size make the LTC1661 ideal for
battery-powered applications, while its straightforward
usability, high performance and wide supply range make
it an excellent choice as a general purpose converter.
For additional outputs and even greater board density,
please refer to the LTC1660 micropower octal DAC for
10‑bit applications. For 8-bit applications, please consult
the LTC1665 micropower octal DAC.
BLOCK DIAGRAM
VOUT A
GND
VCC
VOUT B
8
7
6
5
Differential Nonlinearity (DNL)
LATCH
LATCH
10-BIT
DAC A
LATCH
LATCH
0.75
0.60
10-BIT
DAC B
0.40
LSB
0.20
CONTROL
LOGIC
ADDRESS
DECODER
0
–0.20
–0.40
–0.60
SHIFT REGISTER
–0.75
1
2
3
4
CS/LD
SCK
DIN
REF
0
256
512
CODE
768
1023
1661 G02
1661 BD
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LTC1661
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VCC to GND............................................... –0.3V to 7.5V
Logic Inputs to GND ................................ –0.3V to 7.5V
VOUT A, VOUT B, REF to GND ............–0.3V to VCC + 0.3V
Maximum Junction Temperature...........................125°C
Storage Temperature Range................... –65°C to 150°C
Operating Temperature Range
LTC1661C................................................ 0°C to 70°C
LTC1661I............................................. –40°C to 85°C
Lead Temperature (Soldering, 10 sec).................. 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
CS/LD
SCK
DIN
REF
1
2
3
4
8
7
6
5
VOUT A
GND
VCC
VOUT B
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 150°C/W
CS/LD 1
8
VOUT A
SCK 2
7
GND
DIN 3
6
VCC
REF 4
5
VOUT B
N8 PACKAGE
8-LEAD PLASTIC DIP
TJMAX = 150°C, θJA = 100°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1661CMS8#PBF
LTC1661CMS8#TRPBF
LTDV
8-Lead Plastic MSOP
0°C to 70°C
LTC1661IMS8#PBF
LTC1661IMS8#TRPBF
LTDW
8-Lead Plastic MSOP
–40°C to 85°C
LTC1661CN8#PBF
LTC1661CN8#TRPBF
LTC1661CN8
8-Lead Plastic DIP
0°C to 70°C
LTC1661IN8#PBF
LTC1661IN8#TRPBF
LTC1661IN8
8-Lead Plastic DIP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Accuracy
l
10
Bits
1V ≤ VREF ≤ VCC – 0.1V (Note 2)
l
10
Bits
Resolution
Monotonicity
DNL
Differential Nonlinearity
1V ≤ VREF ≤ VCC – 0.1V (Note 2)
l
±0.1
±0.75
LSB
INL
Integral Nonlinearity
1V ≤ VREF ≤ VCC – 0.1V (Note 2)
l
±0.4
±2
LSB
VOS
Offset Error
Measured at Code 20
l
±5
±30
mV
VCC = 5V, VREF = 4.096V
l
VOS Temperature Coefficient
FSE
Full-Scale Error
±15
Full-Scale Error Temperature Coefficient
PSR
Power Supply Rejection
VREF = 2.5V
±1
µV/°C
±12
LSB
±30
µV/°C
0.18
LSB/V
1661fa
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LTC1661
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input
Input Voltage Range
Resistance
Active Mode
Reference Current
0
l
140
VCC
V
260
kΩ
l
15
Sleep Mode
l
0.001
1
5.5
V
120
95
1
195
154
3
µA
µA
µA
Capacitance
IREF
l
pF
µA
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
l
ICC
Supply Current
VCC = 5V (Note 3)
VCC = 5V (Note 3)
Sleep Mode (Note 3)
l
l
l
2.7
Short-Circuit Current Low
VOUT = 0V, VCC = VREF = 5V, Code = 1023
l
10
25
100
mA
Short-Circuit Current High
VOUT = VCC = VREF = 5V, Code = 0
l
7
19
120
mA
DC Performance
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
Voltage Output Settling Time
To ±0.5LSB (Notes 4, 5)
0.60
0.25
Capacitive Load Driving
V/µs
V/µs
30
µs
1000
pF
Digital I/O
VIH
Digital Input High Voltage
VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
l
l
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
l
l
0.8
0.6
V
V
ILK
Digital Input Leakage
VIN = GND to VCC
l
±10
µA
CIN
Digital Input Capacitance
(Note 6)
l
10
pF
TIMING CHARACTERISTICS
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
2.4
2.0
V
V
The l denotes the specifications which apply over the full operating temperature
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 4.5V to 5.5V
t1
DIN Valid to SCK Setup
l
40
ns
t2
DIN Valid to SCK Hold
l
0
ns
t3
SCK High Time
(Note 6)
l
30
ns
t4
SCK Low Time
(Note 6)
l
30
ns
t5
CS/LD Pulse Width
(Note 6)
l
80
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
30
ns
t7
CS/LD Low to SCK High
(Note 6)
l
20
ns
t9
SCK Low to CS/LD Low
(Note 6)
l
0
ns
CS/LD High to SCK Positive Edge
(Note 6)
l
20
SCK Frequency
Square Wave (Note 6)
l
t11
ns
16.7
MHz
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LTC1661
TIMING CHARACTERISTICS
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
The l denotes the specifications which apply over the full operating temperature
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 2.7V to 5.5V
t1
DIN Valid to SCK Setup
(Note 6)
l
60
ns
t2
t3
DIN Valid to SCK Hold
(Note 6)
SCK High Time
(Note 6)
l
0
ns
l
50
ns
t4
SCK Low Time
(Note 6)
t5
CS/LD Pulse Width
(Note 6)
l
50
ns
l
100
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
50
ns
t7
t9
CS/LD Low to SCK High
(Note 6)
l
30
ns
SCK Low to CS/LD Low
(Note 6)
l
0
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
30
ns
SCK Frequency
Square Wave (Note 6)
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defined from code 20 to code
1023 (full scale). See Applications Information.
10
MHz
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS,
i.e., codes k = 102 and k = 922.
Note 6: Guaranteed by design and not subject to test.
TIMING DIAGRAM
t1
t2
t3
t6
t4
SCK
t9
t11
DIN
A3
t5
A2
A1
X1
X0
t7
CS/LD
1661 TD
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LTC1661
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
0.60
0.40
0.5
0.20
LSB
1.0
0
1000
0
–0.20
–0.5
–1.0
–0.40
–1.5
–0.60
0
256
512
CODE
768
–0.75
1023
0
3.0
256
512
CODE
768
125°C
2.8
–55°C
2.0
200
2.4
4
6
8
10
–20
–10
SINK
0
10
IOUT (mA)
0.5
∆VOUT (LSB)
0.5
–0.5
–1.5
–1.5
–1
0
IOUT (mA)
–15 –12
30
SINK
–2.0
1
2
1661 G07
–8
SINK
–4
0
4
IOUT (mA)
8
–500
12 15
1661 G06
Large-Signal Step Response
5
VCC = VREF = 3V
CODE = 512
VCC = VREF = 5V
10% TO
CODE = 922
90% STEP
4
–0.5
–1.0
–2
20
0
–1.0
SOURCE
SOURCE
1.0
VOUT (V)
1.5
0
VCC = 2.7V
1.1
SOURCE
2.0
1.0
–2.0
1.4
Load Regulation
vs Output Current
1.0
10
VCC = 3V
1.5
1661 G05
VCC = VREF = 5V
CODE = 512
1.5
8
1.2
–30
Load Regulation
vs Output Current
2.0
1.6
1.3
VCC = 4.5V
2.0
|IOUT| (mA) (SINKING)
6
VCC = 3.6V
1.7
VCC = 5V
2.5
1661 G04
∆VOUT (LSB)
1.8
VOUT (V)
2.6
2.1
2
4
|IOUT| (mA) (Sourcing)
VREF = VCC
CODE = 512
1.9
2.2
0
2
Mid-Scale Output Voltage
vs Load Current
VCC = 5.5V
2.3
400
0
0
1661 G03
2.7
VOUT (V)
VOUT (mV)
1000
600
–55°C
400
0
1023
VREF = VCC
CODE = 512
2.9
25°C
25°C
600
Mid-Scale Output Voltage
vs Load Current
1400
800
800
1661 G02
Minimum VOUT vs Load Current
(Output Sinking)
VCC = 5V
CODE = 0
125°C
200
1661 G01
1200
VREF = 4.096V
∆VOUT < 1LSB
CODE = 1023
1200
VCC – VOUT (mV)
1.5
LSB
1400
0.75
2.0
–2.0
Minimum Supply Headroom vs
Load Current (Output Sourcing)
Differential Nonlinearity (DNL)
3
2
1
SOURCE
0
IOUT (µA)
SINK
500
1661 G08
0
CODE = 102
0
20
40
60
TIME (µs)
80
100
1661 G09
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LTC1661
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current
vs Logic Input Voltage
Supply Current vs Temperature
1.0
150
ALL DIGITAL INPUTS
SHORTED TOGETHER
130
SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
0.8
140
0.6
0.4
0.2
VREF = VCC
CODE = 1023
120
110
VCC = 5.5V
100
VCC = 4.5V
90
VCC = 3.6V
80
70
VCC = 2.7V
60
0
0
1
2
3
4
LOGIC INPUT VOLTAGE (V)
5
50
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1661 G10
1661 G11
PIN FUNCTIONS
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
DIN into the register. When CS/LD is pulled high, SCK is
disabled and the operation(s) specified in the control code,
A3-A0, is (are) performed. CMOS and TTL compatible.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
DIN (Pin 3): Serial Interface Data Input. Input word data on
the DIN pin is shifted into the 16-bit register on the rising
edge of SCK. CMOS and TTL compatible.
REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUT A, VOUT B (Pin 8, Pin 5): DAC Analog Voltage Outputs.
The output range is
 1023 
0 ≤ VOUTA,VOUTB ≤ VREF 
 1024 
VCC (Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
GND (Pin 7): System Ground.
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LTC1661
DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL =
∆VOUT – LSB
LSB
where ∆VOUT is the measured voltage difference between
two adjacent codes.
Full-Scale Error (FSE): The deviation of the actual full-scale
voltage from ideal. FSE includes the effects of offset and
gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (endpoint INL). Because the output cannot go
below zero, the linearity is measured between full scale
and the lowest code which guarantees the output will be
greater than zero. The INL error at a given input code is
calculated as follows:
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB =
VREF
1024
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
 Code 
VOUT – VOS – ( VFS – VOS ) 
 1023 
INL =
LSB
where VOUT is the output voltage of the DAC measured at
the given input code.
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LTC1661
OPERATION
Transfer Function
where k is the decimal equivalent of the binary DAC input
code D9-D0 and VREF is the voltage at REF (Pin 6).
By selecting the appropriate 4-bit control code (see Table 2)
it is possible to perform single operations, such as loading
one DAC or changing power-down status (sleep/wake).
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and wakes the part
up. The DACs can be loaded separately or together, but
the outputs are always updated together.
Power-On Reset
Register Loading Sequence
The LTC1661 positively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
See Figure 1. With CS/LD held low, data on the DIN input
is shifted into the 16-bit shift register on the positive edge
of SCK. The 4-bit control code, A3-A0, is loaded first, then
the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last. When
the full 16-bit Input word has been shifted in, CS/LD is
pulled high, causing the system to respond according to
Table 2. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
The transfer function for the LTC1661 is:
 k 
VOUT(DEAL) = 
V
 1024  REF
Power Supply Sequencing
The voltage at REF (Pin 4) must not ever exceed the
voltage at VCC (Pin 6) by more than 0.3V. Particular care
should be taken in the power supply turn-on and turnoff sequences to assure that this limit is observed. See
Absolute Maximum Ratings.
Serial Interface
See Table 1. The 16-bit Input word consists of the 4-bit
Control code, the 10-bit Input code and two don’t-care bits.
Table 1. LTC1661 Input Word
INPUT WORD
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
CONTROL CODE
INPUT CODE
DON’T
CARE
After the Input word is loaded into the register (see
Figure 1), it is internally converted from serial to parallel
format. The parallel 10-bit-wide input code data path is
then buffered by two latch registers.
The first of these, the input register, is used for loading
new input codes. The second buffer, the DAC register, is
used for updating the DAC outputs. Each DAC has its own
10‑bit input register and 10-bit DAC register.
Sleep Mode
DAC control code 1110b is reserved for the special sleep
instruction (see Table 2). In this mode, the digital parts
of the circuit stay active while the analog sections are
disabled; static power consumption is greatly reduced.
The reference input and analog outputs are set in a high
impedance state and all DAC settings are retained in
memory so that when Sleep mode is exited, the outputs
of DACs not updated by the wake command are restored
to their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110b (the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared
with new input codes during Sleep (control codes 0001b
and 0010b); then, a single command (1000b) can be used
both to wake the part and to update the output values.
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LTC1661
OPERATION
Table 2. DAC Control Functions
CONTROL
A3
A2
A1
A0
INPUT REGISTER
STATUS
DAC REGISTER
STATUS
0
0
0
0
No Change
No Update
No Change
No Operation. Power-Down Status Unchanged
(Part Stays in Wake or Sleep Mode)
0
0
0
1
Load DAC A
No Update
No Change
Load Input Register A with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
0
0
1
0
Load DAC B
No Update
No Change
Load Input Register B with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
0
0
1
1
Reserved
0
1
0
0
Reserved
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
No Change
Update Outputs
Wake
Load Both DAC Regs with Existing Contents of Input
Regs. Outputs Update. Part Wakes Up
1
0
0
1
Load DAC A
Update Outputs
Wake
Load Input Reg A. Load DAC Regs with New Contents
of Input Reg A and Existing Contents of Reg B. Outputs
Update. Part Wakes Up
1
0
1
0
Load DAC B
Update Outputs
Wake
Load Input Reg B. Load DAC Regs with Existing
Contents of Input Reg A and New Contents of Reg B.
Outputs Update. Part Wakes Up
1
0
1
1
Reserved
1
1
0
0
Reserved
1
1
0
1
No Change
No Update
Wake
Part Wakes Up. Input and DAC Regs Unchanged. DAC
Outputs Reflect Existing Contents of DAC Regs
1
1
1
0
No Change
No Update
Sleep
Part Goes to Sleep. Input and DAC Regs Unchanged.
DAC Outputs Set to High Impedance State
1
1
1
1
Load DACs A, B with
Same 10-Bit Code
Update Outputs
Wake
Load Both Input Regs. Load Both DAC Regs with New
Contents of Input Regs. Outputs Update. Part Wakes Up
SCK
DIN
1
A3
2
A2
3
A1
CONTROL CODE
4
A0
5
D9
6
D8
POWER-DOWN STATUS
(SLEEP/WAKE)
COMMENTS
7
D7
8
D6
9
D5
10
D4
11
D3
INPUT CODE
12
D2
13
D1
14
D0
15
X1
16
X0
DON’T CARE
INPUT WORD W0
CS/LD
(LTC1661
RESPONDS)
(SCK ENABLED)
1661 F01
Figure 1. Register Loading Sequence
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LTC1661
OPERATION
Voltage Outputs
Rail-to-Rail Output Considerations
Each of the rail-to-rail output amplifiers contained in the
LTC1661 can typically source or sink up to 5mA (VCC = 5V).
The outputs swing to within a few millivolts of either supply
when unloaded and have an equivalent output resistance of
85Ω (typical) when driving a load to the rails. The output
amplifiers are stable driving capacitive loads up to 1000pF.
In any rail-to-rail DAC, the output swing is limited to voltages within the supply range.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1µF
load can be successfully driven by inserting a 20Ω resistor in series with the VOUT pin. A 2.2µF load needs only a
10Ω resistor, and a 10µF electrolytic capacitor can be used
without any resistor (the equivalent series resistance of the
capacitor itself provides the required small resistance). In
any of these cases, larger values of resistance, capacitance
or both may be substituted for the values given.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 2c. No full-scale limiting
can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
INPUT CODE
(2c)
VREF = VCC
OUTPUT
VOLTAGE
0
512
INPUT CODE
(2a)
1023
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
INPUT CODE
(2b)
1661 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (2a) Overall Transfer Function (2b) Effect of Negative
Offset for Codes Near Zero Scale (2c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
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LTC1661
TYPICAL APPLICATIONS
5V
4
VH = 7.5V
(FROM MAIN
INPUT DAC)
6
8
DAC A
CS/LD
DIN
SCK
R1
5k
R2
50k
VA1 = 2.5V
1
LTC1661
U1
3
3
2
2
5
DAC B
10V
+
0.1µF
8
U3A
LT1368
5V
0.1µF
–
0.1µF
4
R3
50k
–5V
R4
5k
VH
0.1µF
VL
6
PIN
DRIVER
(1 0F N)
VOUT
LOGIC
DRIVE
5
DAC B
R5
50k
R6
5k
6
LTC1661
U2
5
2
8
DAC A
–
U3B
LT1368
VL′ = VL + ∆VL
7
+
0.1µF
VA1 = VA2 = 2.5V
VH′ = VH + R1 (VA1 – VB1)
R2
R7
50k
VA2 = 2.5V
7
7.5V 250mV
–2.5V 250mV
VB2
1
3
VH′ = VH + VH
1
VB1
4
FOR EACH U1 AND U2
CODE A CODE B ∆VH, ∆VL
512
1023
–250mV
512
512
0
512
0
250mV
0.1µF
R8
5k
VL′ = VL + R1 (VA2 – VB2)
R2
VL = –2.5V
(FROM MAIN
INPUT DAC)
FOR VALUES SHOWN,
∆VH, ∆VL ADJUSTMENT RANGE = ±250mV
∆VH, ∆VL STEP SIZE = 500µV
1661 F03
Figure 3. Pin Driver VH and VL Adjustment in ATE Applications
VIN ≥ 4.3V
0.1µF
0.1µF
6
2
LTC1258-4.1
4
4
1
4.096V
3
2
1
VCC
VOUTA
REF
8
0V TO 4.096V
(4mV/BIT)
5
T
0V TO 4.096V
(4mV/BIT)
DIN
LTC1661
SCK
CS/LD
VOUTB
GND
7
1661 F04
Figure 4. Using the LTC1258 and the LTC1661 In a Single Li-Ion Battery Application
1661fa
11
LTC1661
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
TYP
8
0.52
(.0205)
REF
7 6 5
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
1
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.65
(.0256)
BSC
MSOP (MS8) 0307 REV F
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
(
+.035
.325 –.015
+0.889
8.255
–0.381
)
.045 – .065
(1.143 – 1.651)
.065
(1.651)
TYP
.400*
(10.160)
MAX
.130 .005
(3.302 0.127)
8
7
6
5
1
2
3
4
.255 .015*
(6.477 0.381)
.100
(2.54)
BSC
.120
(3.048) .020
MIN
(0.508)
MIN
.018 .003
(0.457 0.076)
N8 1002
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
12
1661fa
LTC1661
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
11/10
Removed typical values from Timing Characteristics section
3, 4
1661fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
13
LTC1661
TYPICAL APPLICATION
Pin Driver VH and VL Adjustment in ATE Applications
5V
4
VH = 7.5V
(FROM MAIN
INPUT DAC)
6
8
DAC A
CS/LD
DIN
SCK
R2
50k
VA1 = 2.5V
1
LTC1661
U1
3
R1
5k
3
2
2
5
DAC B
10V
+
0.1µF
8
U3A
LT1368
5V
0.1µF
–
0.1µF
4
R3
50k
–5V
R4
5k
VH
0.1µF
VL
6
PIN
DRIVER
(1 0F N)
VOUT
LOGIC
DRIVE
5
DAC B
R5
50k
R6
5k
6
LTC1661
U2
5
2
8
DAC A
–
U3B
LT1368
7
VL′ = VL + ∆VL
+
0.1µF
VA1 = VA2 = 2.5V
R7
50k
VA2 = 2.5V
7
7.5V 250mV
–2.5V 250mV
VB2
1
3
VH′ = VH + VH
1
VB1
4
FOR EACH U1 AND U2
CODE A CODE B ∆VH, ∆VL
512
1023
–250mV
512
512
0
512
0
250mV
0.1µF
R8
5k
VL = –2.5V
(FROM MAIN
INPUT DAC)
VH′ = VH + R1 (VA1 – VB1)
R2
VL′ = VL + R1 (VA2 – VB2)
R2
FOR VALUES SHOWN,
∆VH, ∆VL ADJUSTMENT RANGE = ±250mV
∆VH, ∆VL STEP SIZE = 500µV
1661 F03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1446/LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448
Dual 12-Bit VOUT DAC in SO-8 Package
VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC
LTC1454/LTC1454L
Dual 12-Bit VOUT DACs in SO-16 Package with Added
Functionality
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1659
Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package
VCC: 2.7V to 5.5V
Low Power Multiplying VOUT DAC. Output Swings from GND to
REF. REF Input Can Be Tied to VCC
LTC1663
Single 10-Bit VOUT DAC in SOT-23 Package
VCC = 2.7V to 5.5V, Internal Reference, 60µA
LTC1665/LTC1660
Octal 8/10-Bit VOUT DAC in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
1661fa
14 Linear Technology Corporation
LT 1110 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 1999