ATMEL AT29C010A-90PI 1-megabit (128k x 8) 5-volt only flash memory Datasheet

Features
• Fast Read Access Time – 70 ns
• 5-volt Only Reprogramming
• Sector Program Operation
•
•
•
•
•
•
•
•
•
•
– Single Cycle Reprogram (Erase and Program)
– 1024 Sectors (128 Bytes/sector)
– Internal Address and Data Latches for 128 Bytes
Two 8K Bytes Boot Blocks with Lockout
Internal Program Control and Timer
Hardware and Software Data Protection
Fast Sector Program Cycle Time – 10 ms
DATA Polling for End of Program Detection
Low Power Dissipation
– 50 mA Active Current
– 100 µA CMOS Standby Current
Typical Endurance > 10,000 Cycles
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
1-Megabit
(128K x 8)
5-volt Only
Flash Memory
AT29C010A
Description
The AT29C010A is a 5-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 1 megabit of memory is organized as 131,072 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 70 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is
Pin Configurations
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PLCC Top View
A12
A15
A16
NC
VCC
WE
NC
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4
3
2
1
32
31
30
A0 - A16
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
Function
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
Pin Name
DIP Top View
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
Rev. 0394E–FLASH–11/02
1
less than 100 µA. The device endurance is such that any sector can typically be written
to in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29C010A does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29C010A is performed on a sector basis; 128 bytes of data are loaded
into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 128 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the sector and then program the
latched data using an internal control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle has been detected, a new
access for a read or program can begin.
Block Diagram
Device Operation
READ: The AT29C010A is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state whenever CE
or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
BYTE LOAD: Byte loads are used to enter the 128 bytes of a sector to be programmed
or the software codes for data protection. A byte load is performed by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The
address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE.
PROGRAM: The device is reprogrammed on a sector basis. If a byte of data within a
sector is to be changed, data for the entire sector must be loaded into the device. The
data in any byte that is not loaded during the programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the device, they are simultaneously
programmed during the internal programming period. After the first data byte has been
loaded into the device, successive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition on WE (or CE) within 150 ms
of the low to high transition of WE (or CE) of the preceding byte. If a high to low transition is not detected within 150 m s of the last low to high transition, the load period will
end and the internal programming period will start. A7 to A16 specify the sector address.
2
AT29C010A
0394E–FLASH–11/02
AT29C010A
The sector address must be valid during each high to low transition of WE (or CE). A0 to
A6 specify the byte address within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming operation has been initiated,
and for the duration of tWC, a read operation will effectively be a polling operation.
SOFTWARE DATA PROTECTION: A software controlled data protection feature is
available on the AT29C010A. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software
protection feature may be enabled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable the software data protection,
a series of three program commands to specific addresses with specific data must be
performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software
program commands must obey the sector program timing specifications. Once set, the
software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.
Once set, software data protection will remain active unless the disable command
sequence is issued.
After setting SDP, any attempt to write to the device without the 3-byte command
sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of CE or WE, whichever occurs
last. The data is latched by the first rising edge of CE or WE. The 128 bytes of data must
be loaded into each sector by the same procedure as outlined in the program section
under device operation.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT29C010A in the following ways: (a) VCC sense – if VCC is below 3.8V
(typical), the program function is inhibited; (b) V CC power on delay – once V CC has
reached the VCC sense level, the device will automatically time out 5 ms (typical) before
programming; (c) Program inhibit – holding any one of OE low, CE high or WE high
inhibits program cycles; and (d) Noise filter—pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part (i.e. using the device code), and
have the system software use the appropriate sector size for program operations. In this
manner, the user can have a common board design for 256K to 4-megabit densities
and, with each density’s sector size in a memory map, have the system software apply
the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.
DATA POLLING: The AT29C010A features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
3
0394E–FLASH–11/02
TOGGLE BIT: In addition to DATA polling the AT29C010A provides another method
for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte
software code. Please see Software Chip Erase application note for details.
BOOT BLOCK PROGRAMMING LOCKOUT: The AT29C010A has two designated
memory blocks that have a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. Each of
these blocks consists of 8K bytes; the programming lockout feature can be set independently for either block. While the lockout feature does not have to be activated, it can be
activated for either or both blocks.
These two 8K memory sections are referred to as boot blocks. Secure code which will
bring up a system can be contained in a boot block. The AT29C010A blocks are located
in the first 8K bytes of memory and the last 8K bytes of memory. The boot block programming lockout feature can therefore support systems that boot from the lower
addresses of memory or the higher addresses. Once the programming lockout feature
has been activated, the data in that block can no longer be erased or programmed; data
in other memory locations can still be changed through the regular programming methods. To activate the lockout feature, a series of seven program commands to specific
addresses with specific data must be performed. Please see Boot Block Lockout Feature Enable Algorithm.
If the boot block lockout feature has been activated on either block, the chip erase function will be disabled.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine
whether programming of either boot block section is locked out. See Software Product
Identification Entry and Exit sections. When the device is in the software product identification mode, a read from location 00002 will show if programming the lower address
boot block is locked out while reading location 1FFF2 will do so for the upper boot block.
If the data is FE, the corresponding block can be programmed; if the data is FF, the program lockout feature has been activated and the corresponding block cannot be programmed. The software product identification exit mode should be used to return to
standard operation.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
4
AT29C010A
0394E–FLASH–11/02
AT29C010A
DC and AC Operating Range
Operating
Temperature (Case)
AT29C010A-70
AT29C010A-90
AT29C010A-12
AT29C010A-15
0°C - 70°C
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
5V ± 10%
5V ± 10%
5V ± 10%
Com.
Ind.
5V ± 5%
VCC Power Supply
Note:
Not recommended for New Designs.
Operating Modes
Mode
Read
Program
(2)
5V Chip Erase
Standby/Write Inhibit
CE
OE
WE
Ai
I/O
VIL
VIL
VIH
Ai
DOUT
VIL
VIH
VIL
Ai
DIN
VIL
VIH
VIL
Ai
X
(1)
VIH
X
X
Program Inhibit
X
X
VIH
Program Inhibit
X
VIL
X
Output Disable
X
VIH
X
VIL
VIL
VIH
High Z
High Z
Product Identification
Hardware
A1 - A16 = VIL, A9 = VH,(3) A0 = VIL
Manufacturer Code(4)
A1 - A16 = VIL, A9 = VH,(3) A0 = VIH
Device Code(4)
Software(5)
Notes:
1.
2.
3.
4.
5.
A0 = VIL
Manufacturer Code(4)
A0 = VIH
Device Code(4)
X can be VIL or VIH.
Refer to AC Programming Waveforms.
VH = 12.0V ± 0.5V.
Manufacturer Code: 1F, Device Code: D5.
See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
ISB1
Min
Max
Units
VIN = 0V to VCC
10
mA
Output Leakage Current
VI/O = 0V to VCC
10
mA
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
0° - 40°C
30
mA
Com.
100
mA
Ind.
300
mA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ICC
VCC Active Current
f = 5 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
VOH2
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
2.0
V
0.45
V
5
0394E–FLASH–11/02
AC Read Characteristics
AT29C010A-70
Min
Max
AT29C010A-90
Min
Max
AT29C010A-12
Min
Max
Max
Units
120
150
ns
120
150
ns
0
70
ns
0
40
ns
Symbol
Parameter
tACC
Address to Output Delay
70
90
tCE(1)
CE to Output Delay
70
90
(2)
OE to Output Delay
0
35
0
40
0
50
(3)(4)
CE or OE to Output Float
0
25
0
25
0
30
Output Hold from OE, CE or
Address, whichever occurred first
0
tOE
tDF
tOH
Note:
0
0
AT29C010A-15
Min
0
ns
Not recommended for New Designs.
AC Read Waveforms(1)(2)(3)(4)
Notes:
6
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
AT29C010A
0394E–FLASH–11/02
AT29C010A
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
70 ns
90/120/150 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is canharacterized and is not 100% tested.
7
0394E–FLASH–11/02
AC Byte Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
90
ns
tDS
Data Set-up Time
35
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
100
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
8
AT29C010A
0394E–FLASH–11/02
AT29C010A
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
tWC
Write Cycle Time
10
ms
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
35
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
90
ns
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
150
100
ms
ns
Program Cycle Waveforms(1)(2)(3)
Notes:
1. A7 through A16 must specify the sector address during each high to low transition of WE (or CE).
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
9
0394E–FLASH–11/02
Software Data Protection Enable
Algorithm(1)
Software Data Protection Disable
Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA
TO
PAGE (128 BYTES)(4)
ENTER DATA
PROTECT STATE(2)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Notes:
1. Data Format: I/O7 - I/O0 (Hex); Address Format:
A14 - A0 (Hex).
2. Data Protect state will be activated at end of program cycle.
3. Data Protect state will be deactivated at end of program period.
4. 128 bytes of data MUST BE loaded.
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
LOAD DATA
TO
PAGE (128 BYTES)(4)
Software Protected Program Cycle Waveform(1)(2)(3)
Notes:
10
1. A7 through A16 must specify the sector address during each high to low transition of WE (or CE) after the software code
has been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
AT29C010A
0394E–FLASH–11/02
AT29C010A
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Max
OE to Output Delay
tWR
Write Recovery Time
Units
10
ns
10
ns
(2)
tOE
Notes:
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Min
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
0394E–FLASH–11/02
Software Product Identification
Entry(1)
Boot Block Lockout Feature Enable
Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
PAUSE 10 mS
LOAD DATA AA
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product Identification Exit(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 00
TO
ADDRESS 00000H(2)
LOAD DATA FF
TO
ADDRESS 1FFFFH(3)
PAUSE 20 mS
PAUSE 20 mS
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 10 mS
Notes:
12
EXIT PRODUCT
IDENTIFICATION
MODE(4)
1. Data Format: I/O7 - I/O0 (Hex); Address Format:
A14 - A0 (Hex).
2. A1 - A15 = VIL.
Manufacturer Code is read for A0 = VIL; Device
Code is read for A0 = VIH.
3. The device does not remain in identification mode
if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is D5.
Notes:
1. Data Format: I/O7 - I/O0 (Hex); Address Format:
A14 - A0 (Hex).
2. Lockout feature set on lower address boot block.
3. Lockout feature set on higher address boot block.
AT29C010A
0394E–FLASH–11/02
AT29C010A
NORMALIZED SUPPLY CURRENT
vs. TEMPERATURE
1.4
N
O
R
M
A
L
I
Z
E
D
1.3
1.2
1.1
1.0
I
0.9
C
C
0.8
-55
-25
5
35
65
95
125
TEMPERATURE (C)
NORMALIZED SUPPLY CURRENT
vs. ADDRESS FREQUENCY
1.1
N
O
R
M 1.0
A
L
I
0.9
Z
E
D
I
C
C
VCC = 5V
T = 25C
0.8
0.7
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
N
O
R
M 1.2
A
L
I
1.0
Z
E
D
I
C
C
0.8
0.6
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
13
0394E–FLASH–11/02
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
70
50
0.1
AT29C010A-70JC
AT29C010A-70PC
AT29C010A-70TC
32J
32P6
32T
Commercial
(0° to 70°C)
90
50
0.1
AT29C010A-90JC
AT29C010A-90PC
AT29C010A-90TC
32J
32P6
32T
Commercial
(0° to 70°C)
50
0.3
AT29C010A-90JI
AT29C010A-90PI
AT29C010A-90TI
32J
32P6
32T
Industrial
(-40° to 85°C)
50
0.1
AT29C010A-12JC
AT29C010A-12PC
AT29C010A-12TC
32J
32P6
32T
Commercial
(0° to 70°C)
50
0.3
AT29C010A-12JI
AT29C010A-12PI
AT29C010A-12TI
32J
32P6
32T
Industrial
(-40° to 85°C)
50
0.1
AT29C010A-15JC
AT29C010A-15PC
AT29C010A-15TC
32J
32P6
32T
Commercial
(0° to 70°C)
50
0.3
AT29C010A-15JI
AT29C010A-15PI
AT29C010A-15TI
32J
32P6
32T
Industrial
(-40° to 85°C)
120
150
Note:
Operation Range
Not recommended for New Designs.
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32P6
32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32-lead, Thin Small Outline Package (TSOP)
14
AT29C010A
0394E–FLASH–11/02
AT29C010A
Packaging Information
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E1
E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
3.175
–
3.556
A1
1.524
–
2.413
A2
0.381
–
–
D
12.319
–
12.573
D1
11.354
–
11.506
D2
9.906
–
10.922
E
14.859
–
15.113
E1
13.894
–
14.046
E2
12.471
–
13.487
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
32J
B
15
0394E–FLASH–11/02
32P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
MIN
NOM
MAX
A
–
–
4.826
A1
0.381
–
–
D
41.783
–
42.291
E
15.240
–
15.875
E1
13.462
–
13.970
B
0.356
–
0.559
B1
1.041
–
1.651
L
3.048
–
3.556
C
0.203
–
0.381
eB
15.494
–
17.526
SYMBOL
eB
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
e
NOTE
Note 1
Note 1
2.540 TYP
09/28/01
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
32P6
REV.
B
AT29C010A
0394E–FLASH–11/02
AT29C010A
32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
32T
B
17
0394E–FLASH–11/02
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0394E–FLASH–11/02
xM
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