MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3850 group (spec. H) is the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec. H) is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter. FEATURES ● Basic machine-language instructions ...................................... 71 ● Minimum instruction execution time .................................. 0.5 µs (at 8 MHz oscillation frequency) ● Memory size ROM ................................................................... 8K to 32K bytes RAM ................................................................. 512 to 1024 bytes ● Programmable input/output ports ............................................ 34 ● Interrupts ................................................. 14 sources, 14 vectors ● Timers ............................................................................. 8-bit ✕ 4 ● Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized) ● Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized) ● PWM ............................................................................... 8-bit ✕ 1 ● A-D converter ............................................... 10-bit ✕ 5 channels ● Watchdog timer ............................................................ 16-bit ✕ 1 ● Clock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) ●Power source voltage In high-speed mode .................................................. 4.0 to 5.5 V (at 8 MHz oscillation frequency) In middle-speed mode ............................................... 2.7 to 5.5 V (at 8 MHz oscillation frequency) In low-speed mode .................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency) ●Power dissipation In high-speed mode ..........................................................34 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................................ 60 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) ●Operating temperature range .................................... –20 to 85°C APPLICATION Office automation equipment, FA equipment, Household products, Consumer electronics, etc. PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 M38503M4H-XXXFP M38503M4H-XXXSP VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK P25/TxD P24/RxD P23 P22 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7) Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP) Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP) Fig. 1 M38503M4H-XXXFP/SP pin configuration 2 Fig. 2 Functional block diagram 20 AVSS VREF 2 3 A-D converter (10) Watchdog timer PWM (8) Reset Sub-clock Sub-clock input output XCIN XCOUT Main-clock output XOUT Clock generating circuit 19 Main-clock input XIN I/O port P4 4 5 6 7 8 P4(5) RAM ROM INT0– INT3 FUNCTIONAL BLOCK DIAGRAM I/O port P3 38 39 40 41 42 P3(5) 21 VSS PC H SI/O1(8) C P U 1 VCC PS PC L S CNTR0 22 23 24 25 26 27 28 29 I/O port P1 I/O port P2 P1(8) 9 10 11 12 13 1416 17 P2(8) XCIN XCOUT CNTR1 Prescaler Y(8) Prescaler X(8) I/O port P0 30 31 32 33 34 35 36 37 P0(8) Timer Y( 8 ) Timer X( 8 ) Timer 2( 8 ) Prescaler 12(8) X Y Timer 1( 8 ) 15 CNVSS A 18 RESET Reset input SI/O2(8) MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL BLOCK MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 1 Pin description Pin VCC, VSS Power source CNVSS CNVSS input RESET Reset input XIN Clock input XOUT Clock output I/O port P0 P10–P17 I/O port P1 Function except a port function •Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss. •This pin controls the operation mode of the chip. •Normally connected to VSS. •Reset input pin for active “L.” •Input and output pins for the clock generating circuit. •Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. •8-bit CMOS I/O port. P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04–P07 • Serial I/O2 function pin •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. P20/XCOUT P21/XCIN P22 P23 Functions Name •P10 to P17 (8 bits) are enabled to output large current for LED drive. •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. I/O port P2 •CMOS compatible input level. •P20, P21, P24 to P27: CMOS3-state output structure. P24/RxD P25/TxD • Sub-clock generating circuit I/O pins (connect a resonator) • Serial I/O1 function pin •P22, P23: N-channel open-drain structure. P26/SCLK • Serial I/O1 function pin/ Timer X function pin P27/CNTR0/ SRDY1 P30/AN0– P34/AN4 •8-bit CMOS I/O port with the same function as port P0. I/O port P3 •CMOS 3-state output structure. P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM • A-D converter input pin •CMOS compatible input level. •8-bit CMOS I/O port with the same function as port P0. I/O port P4 •CMOS compatible input level. • Timer Y function pin • Interrupt input pins •CMOS 3-state output structure. • Interrupt input pin • SCMP2 output pin • Interrupt input pin • PWM output pin 3 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product name M3850 3 M 4 H– XXX SP Package type SP : 42P4B FP : 42P2R-A/E SS : 42S1B-A ROM number Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. – : standard Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. H–: Partial specification changed version ROM/PROM/Flash memory size 9 : 36864 bytes 1 : 4096 bytes 2 : 8192 bytes A : 40960 bytes 3 : 12288 bytes B : 45056 bytes 4 : 16384 bytes C : 49152 bytes 5 : 20480 bytes D : 53248 bytes 6 : 24576 bytes E : 57344 bytes 7 : 28672 bytes F : 61440 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user’s ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M : Mask ROM version E : EPROM or One Time PROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes Fig. 3 Part numbering 4 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Packages Mitsubishi plans to expand the 3850 group (spec. H) as follows. 42P4B ......................................... 42-pin shrink plastic-molded DIP 42P2R-A/E ........................................... 42-pin plastic-molded SOP 42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version) Memory Type Support for mask ROM, One Time PROM, and flash memory versions. Memory Size Flash memory size ......................................................... 32 K bytes One Time PROM size ..................................................... 24 K bytes Mask ROM size ................................................... 8 K to 32 K bytes RAM size ............................................................... 512 to 1 K bytes Memory Expansion Plan ROM size (bytes) As of Feb. 2000 ROM exteranal Under development M38507M8/F8 32K 28K Mass production M38504M6/E6 24K 20K Mass production M38503M4H 16K 12K Mass production M38503M2H 8K 384 512 640 768 1152 896 1024 RAM size (bytes) 1280 1408 1536 2048 Products under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped. Fig. 4 Memory expansion plan 5 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Currently planning products are listed below. As of Feb. 2000 Table 2 Support products Product name M38503M2H-XXXSP M38503M2H-XXXFP M38503M4H-XXXSP M38503M4H-XXXFP M38504M6-XXXSP M38504E6-XXXSP M388504E6SP M388504E6SS M38504M6-XXXFP M38504E6-XXXFP M38504E6FP ROM size (bytes) ROM size for User in ( ) RAM size (bytes) 8192 (8062) 512 16384 (16254) 512 Package 42P4B 42P2R-A/E 424P4B 42P2R-A/E 424P4B 24576 (24446) 640 42S1B-A 42P2R-A/E Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) Table 3 3850 group (standard) and 3850 group (spec. H) corresponding products 3850 group (standard) 3850 group (spec. H) M38503M2-XXXFP/SP M38503M2H-XXXFP/SP M38503M4-XXXFP/SP M38503M4H-XXXFP/SP M38503E4-XXXFP/SP M38504M6-XXXFP/SP M38503E4FP/SP M38504E6-XXXFP/SP M38503E4SS M38504E6FP/SP M38504E6SS M38507M8-XXXFP/SP M38507F8FP/SP Table 4 Differences between 3850 group (standard) and 3850 group (spec. H) Serial I/O 3850 group (standard) 1: Serial I/O (UART or Clock-synchronized) A-D converter Large current port Unserviceable in low-speed mode 5: P13–P17 3850 group (spec. H) 2: Serial I/O1 (UART or Clock-synchronized) Serial I/O2 (Clock-synchronized) Serviceable in low-speed mode 8: P10–P17 Notes on differences between 3850 group (standard) and 3850 group (spec. H) (1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard). •Power source voltage Vcc = –0.3 to 6.5 V •CNVss input voltage VI = –0.3 to Vcc +0.3 V (2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group (spec. H). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.) (4) Fix bit 3 of the CPU mode register to “1”. (5) Be sure to perform the termination of unused pins. 6 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) [Stack Pointer (S)] The 3850 group (spec. H) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b0 b7 A Accumulator b0 b7 X Index register X b0 b7 Y b7 Index register Y b0 S b15 b7 PCH Stack pointer b0 Program counter PCL b7 b0 N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig. 5 740 Family CPU register structure 7 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER On-going Routine Interrupt request (Note) M (S) Execute JSR Push return address on stack M (S) (PCH) (S) (S) – 1 M (S) (PCL) (S) (S)– 1 (S) M (S) (S) M (S) (S) Subroutine POP return address from stack (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) (S) – 1 (PCL) Push return address on stack (S) – 1 (PS) Push contents of processor status register on stack (S) – 1 Interrupt Service Routine Execute RTS (S) (PCH) I Flag is set from “0” to “1” Fetch the jump vector Execute RTI Note: Condition for acceptance of an interrupt (S) (S) + 1 (PS) M (S) (S) (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) POP contents of processor status register from stack POP return address from stack Interrupt enable flag is “1” Interrupt disable flag is “0” Fig. 6 Register push and pop at interrupt generation and subroutine call Table 5 Push and pop instructions of accumulator or processor status register 8 Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. •Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. •Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. •Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. •Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. •Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. •Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. •Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. •Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 6 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction Z flag _ I flag D flag V flag SEI SED B flag _ T flag SEC SET _ N flag _ CLC _ CLI CLD _ CLT CLV _ 9 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16. b7 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to “1”. Port X C switch bit 0 : I/O port function (stop oscillating) 1 : X CIN–XCOUT oscillating function Main clock (X IN–XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(X IN)/2 (high-speed mode) 0 1 : φ = f(X IN)/8 (middle-speed mode) 1 0 : φ = f(X CIN)/2 (low-speed mode) 1 1 : Not available Fig. 7 Structure of CPU mode register 10 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) Address XXXX16 192 256 384 512 640 768 896 1024 1536 2048 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 000016 SFR area Zero page 004016 RAM 010016 XXXX16 Not used 0FF016 0FFF16 SFR area (Note) Not used YYYY16 ROM area Reserved ROM area ROM size (bytes) Address YYYY16 Address ZZZZ16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 (128 bytes) ZZZZ16 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page Reserved ROM area Note: Flash memory version only Fig. 8 Memory map diagram 11 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 Port P0 (P0) 002016 Prescaler 12 (PRE12) 000116 Port P0 direction register (P0D) 002116 Timer 1 (T1) 000216 Port P1 (P1) 002216 Timer 2 (T2) 000316 Port P1 direction register (P1D) 002316 Timer XY mode register (TM) 000416 Port P2 (P2) 002416 Prescaler X (PREX) 000516 Port P2 direction register (P2D) 002516 Timer X (TX) 000616 Port P3 (P3) 002616 Prescaler Y (PREY) 000716 Port P3 direction register (P3D) 002716 Timer Y (TY) 000816 Port P4 (P4) 002816 Timer count source selection register (TCSS) 000916 Port P4 direction register (P4D) 002916 000A16 002A16 000B16 002B16 Reserved ✽ 000C16 002C16 Reserved ✽ 000D16 002D16 Reserved ✽ 000E16 002E16 Reserved ✽ 000F16 002F16 Reserved ✽ 001016 003016 Reserved ✽ 003116 Reserved ✽ 001116 001216 Reserved ✽ 003216 001316 Reserved ✽ 003316 001416 Reserved ✽ 003416 A-D control register (ADCON) 001516 Serial I/O2 control register 1 (SIO2CON1) 003516 A-D conversion low-order register (ADL) 001616 Serial I/O2 control register 2 (SIO2CON2) 003616 A-D conversion high-order register (ADH) 001716 Serial I/O2 register (SIO2) 003716 Reserved ✽ 001816 Transmit/Receive buffer register (TB/RB) 003816 MISRG 001916 Serial I/O1 status register (SIOSTS) 003916 Watchdog timer control register (WDTCON) 001A16 Serial I/O1 control register (SIOCON) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART control register (UARTCON) 003B16 CPU mode register (CPUM) 001C16 Baud rate generator (BRG) 003C16 Interrupt request register 1 (IREQ1) 001D16 PWM control register (PWMCON) 003D16 Interrupt request register 2 (IREQ2) 001E16 PWM prescaler (PREPWM) 003E16 Interrupt control register 1 (ICON1) 001F16 PWM register (PWM) 003F16 Interrupt control register 2 (ICON2) ✽ Reserved : Do not write any data to this addresses, because these areas are reserved. Fig. 9 Memory map of special function register (SFR) 12 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 5 I/O port function Pin P00/SIN2 P01/SOUT2 P02/SCLK2 Name Input/Output Serial I/O2 function I/O Related SFRs Serial I/O2 control register CMOS compatible input level CMOS 3-state output P04–P07 Sub-clock generating circuit CPU mode register CMOS compatible input level N-channel open-drain output Port P2 Input/output, individual bits Ref.No. (1) (2) (3) (4) (5) Port P1 P20/XCOUT P21/XCIN P22 P23 Non-Port Function Port P0 P03/SRDY2 P10–P17 I/O Structure (6) (7) (8) Serial I/O1 function I/O Serial I/O1 control register (9) (10) Serial I/O1 function I/O Serial I/O1 control register (11) Serial I/O1 function I/O Timer X function I/O Serial I/O1 control register Timer XY mode register (12) A-D conversion input A-D control register (13) P40/CNTR1 Timer Y function I/O Timer XY mode register (14) P41/INT0 P42/INT1 External interrupt input Interrupt edge selection register (15) Interrupt edge selection register Serial I/O2 control register (16) Interrupt edge selection register PWM control register (17) P24/RxD P25/TxD P26/SCLK P27/CNTR0/SRDY1 P30/AN0– P34/AN4 P43/INT2/SCMP2 P44/INT3/PWM CMOS compatible input level CMOS 3-state output Port P3 Port P4 External interrupt input SCMP2 output External interrupt input PWM output 13 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Port P01 (1) Port P00 P01/SOUT2 P-channel output disable bit Direction register Data bus Serial I/O2 Transmit completion signal Serial I/O2 port selection bit Direction register Port latch Data bus Port latch Serial I/O2 input Serial I/O2 output (3) Port P02 (4) Port P03 P02/SCLK2 P-channel output disable bit SRDY2 output enable bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Direction register Data bus Data bus Port latch Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (6) Port P20 (5) Ports P04-P07,P1 Port XC switch bit Direction register Data bus Port latch Direction register Data bus Port latch Oscillator Port P21 (7) Port P21 Port XC switch bit Port XC switch bit (8) Ports P22,P23 Direction register Data bus Direction register Port latch Data bus Sub-clock generating circuit input Fig. 10 Port block diagram (1) 14 Port latch MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (10) Port P25 (9) Port P24 Serial I/O1 enable bit Receive enable bit P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register Direction register Port latch Data bus Port latch Data bus Serial I/O1 input Serial I/O1 output (11) Port P26 (12) Port P27 Pulse output mode Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch Port latch Data bus Pulse output mode Serial ready output Serial I/O1 clock output Timer output External clock input (13) Ports P30-P34 CNTR0 interrupt input (14) Port P40 Direction register Direction register Port latch Data bus Port latch Data bus Pulse output mode Timer output A-D converter input Analog input pin selection bit CNTR1 interrupt input (16) Port P43 Serial I/O2 I/O comparison signal control bit (15) Ports P41,P42 Direction register Data bus Port latch Interrupt input Direction register Data bus Port latch Serial I/O2 I/O comparison signal output Interrupt input Fig. 11 Port block diagram (2) 15 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (17) Port P44 PWM output enable bit Direction register Data bus Port latch PWM output Interrupt input Fig. 12 Port block diagram (3) 16 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS ■Notes Interrupts occur by 14 sources among 14 sources: six external, seven internal, and one software. When the active edge of an external interrupt (INT0–INT3, CNTR0, CNTR1) is set, the corresponding interrupt request bit may also be set. Therefore, take the following sequence: Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. 1. Disable the interrupt 2. Change the interrupt edge selection register (the timer XY mode register for CNTR0 and CNTR1) 3. Clear the interrupt request bit to “0” 4. Accept the interrupt. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. 17 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 8 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) Priority 1 Vector Addresses (Note 1) Low High FFFD16 FFFC16 Interrupt Request Generating Conditions Remarks At reset Non-maskable External interrupt (active edge selectable) INT0 2 FFFB16 FFFA16 At detection of either rising or falling edge of INT0 input Reserved 3 FFF916 FFF816 Reserved INT1 4 FFF716 FFF616 At detection of either rising or falling edge of INT1 input External interrupt (active edge selectable) INT2 5 FFF516 FFF416 At detection of either rising or falling edge of INT2 input External interrupt (active edge selectable) INT3/ Serial I/O2 6 FFF316 FFF216 At detection of either rising or falling edge of INT 3 input/ At completion of serial I/O2 data reception/transmission External interrupt (active edge selectable) Switch by Serial I/O2/INT3 interrupt source bit Reserved Timer X Timer Y Timer 1 Timer 2 7 8 FFF116 FFF016 Reserved FFEF16 9 FFED16 10 11 FFEB16 FFE916 FFEE16 FFEC16 FFEA16 FFE816 At timer X underflow At timer Y underflow At timer 1 underflow Serial I/O1 reception 12 FFE716 FFE616 At completion of serial I/O1 data reception Valid when serial I/O1 is selected Serial I/O1 transmission 13 FFE516 FFE416 At completion of serial I/O1 transfer shift or when transmission buffer is empty Valid when serial I/O1 is selected CNTR0 14 FFE316 FFE216 At detection of either rising or falling edge of CNTR0 input External interrupt (active edge selectable) CNTR1 15 FFE116 FFE016 At detection of either rising or falling edge of CNTR1 input External interrupt (active edge selectable) A-D converter BRK instruction 16 FFDF16 FFDE16 At completion of A-D conversion 17 FFDD16 FFDC16 At BRK instruction execution Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 18 STP release timer underflow At timer 2 underflow Non-maskable software interrupt MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 13 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit 0 : Falling edge active 1 : Rising edge active INT2 active edge selection bit INT3 active edge selection bit Serial I/O2 / INT3 interrupt source bit 0 : INT3 interrupt selected 1 : Serial I/O2 interrupt selected Not used (returns “0” when read) b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O1 reception interrupt request bit Serial I/O1 transmit interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit AD converter interrupt request bit Not used (returns “0” when read) INT0 interrupt request bit Reserved INT1 interrupt request bit INT2 interrupt request bit INT3 / Serial I/O2 interrupt request bit Reserved Timer X interrupt request bit Timer Y interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 b7 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit Reserved(Do not write “1” to this bit.) INT1 interrupt enable bit INT2 interrupt enable bit INT3 / Serial I/O2 interrupt enable bit Reserved(Do not write “1” to this bit.) Timer X interrupt enable bit Timer Y interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled b0 Interrupt control register 2 (ICON2 : address 003F16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O1 reception interrupt enable bit Serial I/O1 transmit interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 14 Structure of interrupt-related registers 19 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS Timer 1 and Timer 2 The 3850 group (spec. H) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. Timer X and Timer Y Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register. (1) Timer Mode The timer counts the count source selected by Timer count source selection bit. b0 b7 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bits b5b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop Fig. 15 Structure of timer XY mode register b7 b0 Timer count source selection register (TCSS : address 002816) (2) Pulse Output Mode The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach “0016”, the signal output from the CNTR0 (or CNTR1 ) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P27 ( or port P40) direction register to output mode. (3) Event Counter Mode Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 or CNTR1 pin. When the CNTR0 (or CNTR1) active edge selection bit is “0”, the rising edge of the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is “1”, the falling edge of the CNTR0 (or CNTR1) pin is counted. (4) Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts the selected signals by the count source selection bit while the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge selection bit is “1”, the timer counts it while the CNTR0 (or CNTR1) pin is at “L”. The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows. Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN) Not used (returns “0” when read) Fig. 16 Structure of timer count source selection register 20 ■Note When switching the count source by the timer 12, X and Y count source bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Data bus f(XIN)/16 (f(XCIN)/16 at low-speed mode) Prescaler X latch (8) f(XIN)/2 Pulse width (f(XCIN)/2 at low-speed mode) Timer X count source selection bit measurement mode Timer mode Pulse output mode Prescaler X (8) CNTR0 active edge selection “0” bit P27/CNTR0 Event counter mode “1” Timer X (8) To timer X interrupt request bit Timer X count stop bit To CNTR0 interrupt request bit CNTR0 active edge selection “1” bit “0” Q Toggle flip-flop T Q R Timer X latch write pulse Pulse output mode Port P27 latch Port P27 direction register Timer X latch (8) Pulse output mode Data bus f(XIN)/16 (f(XCIN)/16 at low-speed mode) Prescaler Y latch (8) f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit Pulse width measurement mode Timer mode Pulse output mode Prescaler Y (8) CNTR1 active edge selection bit “0” P40/CNTR1 Event counter mode “1” Port P40 direction register Timer Y (8) To timer Y interrupt request bit Timer Y count stop bit To CNTR1 interrupt request bit CNTR1 active edge selection “1” bit Q Toggle flip-flop T Q Port P40 latch Timer Y latch (8) “0” R Timer Y latch write pulse Pulse output mode Pulse output mode Data bus Prescaler 12 latch (8) f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XCIN) Prescaler 12 (8) Timer 1 latch (8) Timer 2 latch (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit Timer 12 count source selection bit To timer 1 interrupt request bit Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2 21 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O1 (1) Clock Synchronous Serial I/O Mode Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Clock synchronous serial I/O mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Data bus Serial I/O1 control register Address 001816 Receive buffer register Receive buffer full flag (RBF) Receive shift register P24/RXD Address 001A16 Receive interrupt request (RI) Shift clock Clock control circuit P26/SCLK XIN Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C16 BRG count source selection bit 1/4 P27/SRDY1 F/F Clock control circuit Falling-edge detector Shift clock P25/TXD Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register Transmit buffer register Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Address 001816 Data bus Fig. 18 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 19 Operation of clock synchronous serial I/O1 function 22 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Asynchronous Serial I/O (UART) Mode two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the Data bus Address 001816 P24/RXD Serial I/O1 control register Address 001A16 Receive buffer register OE Character length selection bit ST detector 7 bits Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 8 bits PE FE SP detector Clock control circuit UART control register Address 001B16 Serial I/O synchronous clock selection bit P26/SCLK XIN BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P25/TXD Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Character length selection bit Transmit buffer register Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 20 Block diagram of UART serial I/O1 23 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD TBE=0 TBE=1 ST D0 D1 SP TSC=1 ST D0 Receive buffer read signal SP D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode RBF=0 RBF=1 Serial input RXD ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 21 Operation of UART serial I/O1 function [Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 Status Register (SIOSTS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. 24 [Serial I/O1 Control Register (SIOCON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O1 status register (SIOSTS : address 001916) b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits b0 Serial I/O1 control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P27 pin operates as ordinary I/O pin 1: P27 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P24 to P27 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P24 to P27 operate as serial I/O1 pins) Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P25/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 22 Structure of serial I/O1 control registers 25 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O2 The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection bits (b2, b1, b0) of serial I/O2 control register 1. Regarding SOUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P0 1 /S OUT2 , P0 2 /S CLK2 P-channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 001716). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not set to “1” automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the SOUT2 pin does not go to high impedance after completion of data transfer. To cause the SOUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to “1” when SCLK2 is “H” after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to “0” and the SOUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the said bit is MSB first. For the remaining bits, the previously received data is shifted. At transmit operation using the clock synchronous serial I/O, the SCMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H” is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16). [Serial I/O2 Control Registers 1, 2 (SIO2CON1 / SIO2CON2)] 001516, 001616 The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 23. 26 b7 b0 Serial I/O2 control register 1 (SIO2CON1 : address 001516) Internal synchronous clock selection bits b2 b1 b0 0 0 0 0 1 1 0 0 1 1 1 1 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 output pin SRDY2 output enable bit 0: P03 pin is normal I/O pin 1: P03 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P01/SOUT2 ,P02/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode ) b7 b0 Serial I/O2 control register 2 (SIO2CON2 : address 001616) Optional transfer bits b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: 1 bit 1: 2 bit 0: 3 bit 1: 4 bit 0: 5 bit 1: 6 bit 0: 7 bit 1: 8 bit Not used ( returns "0" when read) Serial I/O2 I/O comparison signal control bit 0: P43 I/O 1: SCMP2 output SOUT2 pin control bit (P01) 0: Output active 1: Output high-impedance Fig. 23 Structure of Serial I/O2 control registers 1, 2 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal synchronous clock selection bit 1/8 XCIN “10” “00” “01” XIN 1/16 1/32 Divider Main clock division ratio selection bits (Note) Data bus 1/64 1/128 1/256 P03 latch Serial I/O2 synchronous clock selection bit “0” P03/SRDY2 SCLK2 SRDY2 Synchronous circuit “1” SRDY2 output enable bit “1” “0” External clock P02 latch Optional transfer bits (3) “0” P02/SCLK2 Serial I/O2 interrupt request Serial I/O counter 2 (3) “1” Serial I/O2 port selection bit P01 latch “0” P01/SOUT2 “1” Serial I/O2 port selection bit Serial I/O2 register (8) P00/SIN2 P43 latch “0” D P43/SCMP2/INT2 Q “1” Serial I/O2 I/O comparison signal control bit Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register. Fig. 24 Block diagram of Serial I/O2 Transfer clock (Note 1) Write-in signal to serial I/O2 register (Note 2) Serial I/O2 output SOUT2 D0 D1 . D2 D3 D4 D5 D6 D7 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion. Fig. 25 Timing chart of Serial I/O2 27 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SCMP2 SCLK2 SOUT2 SIN2 Judgement of I/O data comparison Fig. 26 SCMP2 output operation 28 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PULSE WIDTH MODULATION (PWM) PWM Operation The 3850 group (spec. H) has a PWM function with an 8-bit resolution, based on a signal that is the clock input X IN or that clock input divided by 2. When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pin also functions as port P44 . Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1) / f(XIN) = 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz,count source selection bit = “0”) Output pulse “H” term = PWM period ✕ m / 255 = 0.125 ✕ (n+1) ✕ m µs (when f(XIN) = 8 MHz,count source selection bit = “0”) 31.875 ✕ m ✕ (n+1) µs 255 PWM output T = [31.875 ✕ (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(X IN) = 8 MHz,count source selection bit = “0”) Fig. 27 Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch PWM register latch PWM prescaler PWM register Count source selection bit “0” XIN (XCIN at low-speed mode) 1/2 Port P44 “1” Port P44 latch PWM enable bit Fig. 28 Block diagram of PWM function 29 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 PWM control register (PWMCON : address 001D 16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) (f(XCIN) at low-speed mode) 1: f(XIN)/2 (f(XCIN)/2 at low-speed mode) Not used (return “0” when read) Fig. 29 Structure of PWM control register A B B = C T2 T C PWM output T PWM register write signal PWM prescaler write signal T T2 (Changes “H” term from “A” to “B”.) (Changes PWM period from “T” to “T2”.) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 30 PWM output timing when PWM register or PWM prescaler is changed ■Note The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin. The length of this “L” level output is as follows: 30 n+1 2 • f(XIN) sec (Count source selection bit = 0, where n is the value set in the prescaler) n+1 f(XIN) sec (Count source selection bit = 1, where n is the value set in the prescaler) MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 003516, 003616 b7 b0 AD control register (ADCON : address 0034 16) The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion. Analog input pin selection bits b2 b1 b0 0 0 0 0 1 [AD Control Register (ADCON)] 003416 The AD control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. 0 0 1 1 0 0: P30/AN0 1: P31/AN1 0: P32/AN2 1: P33/AN3 0: P34/AN4 Not used (returns “0” when read) A-D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns “0” when read) Comparison Voltage Generator Fig. 31 Structure of AD control register The comparison voltage generator divides the voltage between AVSS and VREF into 1024 and outputs the divided voltages. Channel Selector 10-bit reading (Read address 003616 before 003516) The channel selector selects one of ports P30/AN0 to P34/AN4 and inputs the voltage to the comparator. b7 b0 b9 b8 b7 b0 (Address 003616) Comparator and Control Circuit The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the A-D conversion registers. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion. When the A-D converter is operated at low-speed mode, f(X IN ) and f(XCIN) do not have the lower limit of frequency, because of the A-D converter has a built-in self-oscillation circuit. (Address 003516) b7 b6 b5 b4 b3 b2 b1 b0 Note : The high-order 6 bits of address 0036 16 become “0” at reading. 8-bit reading (Read only address 003516) b7 b0 (Address 003516) b9 b8 b7 b6 b5 b4 b3 b2 Fig. 32 Structure of A-D conversion registers Data bus AD control register (Address 0034 16) b7 b0 3 A-D interrupt request A-D control circuit Channel selector P30/AN0 P31/AN 1 P32/AN 2 P33/AN 3 P34/AN 4 Comparator A-D conversion high-order register (Address 0036 16) A-D conversion low-order register (Address 0035 16) 10 Resistor ladder VREF AV SS Fig. 33 Block diagram of A-D converter 31 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER WATCHDOG TIMER ●Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 0039 16) permits selecting a watchdog timer H count source. When this bit is set to “0”, the count source becomes the underflow signal of watchdog timer L. The detection time is set to 131.072 ms at f(XIN) = 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency. When this bit is set to “1”, the count source becomes the signal divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN) = 32 kHz frequency. This bit is cleared to “0” after reset. The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Standard Operation of Watchdog Timer When any data is not written into the watchdog timer control register (address 0039 16 ) after reset, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 003916) and an internal reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16 ) may be started before an underflow. When the watchdog timer control register (address 0039 16) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. ●Operation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 0039 16) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is “0”, the STP instruction is enabled. When this bit is “1”, the STP instruction is disabled, once the STP instruction is executed, an internal reset occurs. When this bit is set to “1”, it cannot be rewritten to “0” by program. This bit is cleared to “0” after reset. ●Initial value of watchdog timer At reset or writing to the watchdog timer control register (address 003916), each watchdog timer H and L is set to “FF16.” “FF16” is set when watchdog timer control register is written to. XCIN XIN “FF16” is set when watchdog timer control register is written to. “0” “10” Main clock division ratio selection bits (Note) Data bus Watchdog timer L (8) 1/16 “1” “00” “01” Watchdog timer H (8) Watchdog timer H count source selection bit STP instruction disable bit STP instruction Reset circuit RESET Internal reset Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig. 34 Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 0039 16) Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig. 35 Structure of Watchdog timer control register 32 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an "L" level for 2 µs or more. Then the RESET pin is returned to an "H" level (the power source voltage must be between 2.7 V and 5.5 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V. Poweron RESET Power source voltage 0V VCC Reset input voltage 0V (Note) 0.2VCC Note : Reset release voltage ; Vcc=2.7 V RESET VCC Power source voltage detection circuit Fig. 36 Reset circuit example XIN φ RESET RESETOUT Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN: 8 to 13 clock cycles Notes 1: The frequency relation of f(X IN) and f(φ) is f(XIN) = 2 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. 3: All signals except X IN and RESET are internals. Fig. 37 Reset sequence 33 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address Register contents (1) Port P0 (P0) 000016 0016 (34) MISRG 003816 (2) Port P0 direction register (P0D) 000116 0016 (35) Watchdog timer control register (WDTCON) 003916 0 0 1 1 1 1 1 1 (3) Port P1 (P1) 000216 0016 (36) Interrupt edge selection register (INTEDGE) 003A16 (4) Port P1 direction register (P1D) 000316 0016 (37) CPU mode register (CPUM) 003B16 0 1 0 0 1 0 0 0 (5) Port P2 (P2) 000416 0016 (38) Interrupt request register 1 (IREQ1) 003C16 0016 (6) Port P2 direction register (P2D) 000516 0016 (39) Interrupt request register 2 (IREQ2) 003D16 0016 (7) Port P3 (P3) 000616 0016 (40) Interrupt control register 1 (ICON1) 003E16 0016 (8) Port P3 direction register (P3D) 000716 0016 (41) Interrupt control register 2 (ICON2) 003F16 0016 (9) Port P4 (P4) 000816 0016 (42) Processor status register (PS) (10) Port P4 direction register (P4D) 000916 0016 (43) Program counter (PCH) FFFD16 contents (11) Serial I/O2 control register 1 (SIO2CON1) 001516 0016 (PCL) FFFC16 contents (12) Serial I/O2 control register 2 (SIO2CON2) 001616 0 0 0 0 0 1 1 1 (13) Serial I/O2 register (SIO2) 001716 X X X X X X X X (14) Transmit/Receive buffer register (TB/RB) 001816 X X X X X X X X (15) Serial I/O1 status register (SIOSTS) 001916 1 0 0 0 0 0 0 0 (16) Serial I/O1 control register (SIOCON) 001A16 (17) UART control register (UARTCON) 001B16 1 1 1 0 0 0 0 0 (18) Baud rate generator (BRG) 001C16 X X X X X X X X (19) PWM control register (PWMCON) 001D16 (20) PWM prescaler (PREPWM) 001E16 X X X X X X X X (21) PWM register (PWM) 001F16 X X X X X X X X (22) Prescaler 12 (PRE12) 002016 FF16 (23) Timer 1 (T1) 002116 0116 (24) Timer 2 (T2) 002216 0016 (25) Timer XY mode register (TM) 002316 0016 (26) Prescaler X (PREX) 002416 FF16 (27) Timer X (TX) 002516 FF16 (28) Prescaler Y (PREY) 002616 FF16 (29) Timer Y (TY) 002716 FF16 (30) Timer count source selection register (TCSS) 002816 0016 (31) A-D control register (ADCON) 003416 0 0 0 1 0 0 0 0 (32) A-D conversion low-order register (ADL) 003516 X X X X X X X X (33) A-D conversion high-order register (ADH) 003616 0 0 0 0 0 0 X X 0016 0016 Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 38 Internal status at reset 34 Address Register contents 0016 0016 X X X X X 1X X MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT (2) Wait mode The 3850 group (spec. H) has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between X IN and X OUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN divided by 16. Accordingly, set the timer 1 interrupt enable bit to “0” before executing the STP instruction. ■Note (2) High-speed mode The internal clock φ is half the frequency of XIN. When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. (3) Low-speed mode The internal clock φ is half the frequency of XCIN. ■Note If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3•f(XCIN). XCIN XCOUT Rf CCIN XIN XOUT Rd CCOUT CIN COUT (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1.” When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. Fig. 39 Ceramic resonator circuit XCIN Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit is “0,” the prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the oscillation stabilizing time set after STP instruction released bit is “1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. Either XIN or XCIN divided by 16 is input to the prescaler 12 as count source. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the oscillation is stable since a wait time will not be generated. XCOUT Rf XIN XOUT Open Rd External oscillation circuit CCIN CCOUT Vcc Vss Fig. 40 External clock input circuit 35 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [MISRG (MISRG)] 003816 b0 b7 MISRG (MISRG : address 003816) MISRG consists of three control bits (bits 1 to 3) for middle-speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. By setting the middle-speed mode automatic switch start bit to “1” while operating in the low-speed mode and setting the middlespeed mode automatic switch set bit to “1”, X IN oscillation automatically starts and the mode is automatically switched to the middle-speed mode. Oscillation stabilizing time set after STP instruction released bit 0: Automatically set “0116” to Timer 1, “FF16” to Prescaler 12 1: Automatically set nothing Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enable Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start Not used (return “0” when read) Note: When the mode is automatically switched from the low-speed mode to the middle-speed mode, the value of CPU mode register (address 003B16) changes. Fig. 41 Structure of MISRG XCOUT XCIN “0” “1” Port XC switch bit XOUT XIN Main clock division ratio selection bits (Note 1) Low-speed mode 1/2 1/4 Prescaler 12 1/2 High-speed or middle-speed mode FF16 Timer 1 0116 Reset or STP instruction (Note 2) Main clock division ratio selection bits (Note 1) Middle-speed mode Timing f (internal clock) High-speed or low-speed mode Main clock stop bit Q S R S Q STP instruction WIT instruction R Q S R STP instruction Reset Interrupt disable flag l Interrupt request Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b1) to “1”. 2: When bit 0 of MISRG = “0” Fig. 42 System clock generating circuit block diagram (Single-chip mode) 36 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset C “0 M4 CM ” ← “1 6 → ”← “1 ” → “0 ” ” “0 4 → M ” C ”← “0 “1 M6 → C ”← “1 Middle-speed mode (f(φ) = 1 MHz) CM7 = 0 CM6 = 1 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM7 = 0 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) C M6 “1” ←→ “0” C “0 M7 CM ” ← “1 6 → “1 ”← ” → “0 ” CM4 “1” ←→ “0” CM4 “1” ←→ “0” CM7 = 0 CM6 = 1 CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) High-speed mode (f(φ) = 4 MHz) C M6 “1” ←→ “0” High-speed mode (f(φ) = 4 MHz) CM7 = 0 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM7 “1” ←→ “0” Middle-speed mode (f(φ) = 1 MHz) CM5 “1” ←→ “0” Low-speed mode (f(φ)=16 kHz) CM7 = 1 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) Low-speed mode (f(φ)=16 kHz) CM7 = 1 CM6 = 0 CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : φ = f(XIN)/2 ( High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not available Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed mode. 5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed. (1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”. (2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. f indicates the internal clock. Fig. 43 State transitions of system clock 37 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register A-D Converter The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) in the middle/high-speed mode is at least on 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion. Interrupts Instruction Execution Time The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN frequency in high-speed mode. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to “1.” Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transmission is completed. When an external clock is used as synchronous clock in serial I/ O1 or serial I/O2, write transmission data to the transmit buffer register or serial I/O2 register while the transfer clock is “H.” 38 NOTES ON USAGE Differences between 3850 group (standard) and 3850 group (spec. H) (1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard). •Power source voltage Vcc = –0.3 to 6.5 V •CNVss input voltage VI = –0.3 to Vcc +0.3 V (2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group (spec. H). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.) (4) Fix bit 3 of the CPU mode register to “1”. (5) Be sure to perform the termination of unused pins. Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin) and between power source pin (V CC pin) and analog power source input pin (AV SS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1µF is recommended. MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS Table 7 Absolute maximum ratings Symbol VCC VI VI VI VI VO VO Pd Topr Tstg Parameter Conditions Power source voltage Input voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, VREF Input voltage Input voltage Input voltage Output voltage P22, P23 RESET, XIN CNVSS P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature All voltages are based on VSS. Output transistors are cut off. Ratings –0.3 to 6.5 Unit V –0.3 to VCC +0.3 V –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to VCC +0.3 V V V –0.3 to VCC +0.3 V –0.3 to 5.8 1000 (Note) –20 to 85 –40 to 125 V mW °C °C Ta = 25 °C Note : The rating becomes 300mW at the 42P2R-A/E package. Table 8 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter 8 MHz (high-speed mode) 8 MHz (middle-speed mode), 4 MHz (high-speed mode) VCC Power source voltage VSS VREF AVSS VIA VIH VIH VIL VIL VIL Power source voltage A-D convert reference voltage Analog power source voltage Analog input voltage AN0–AN4 “H” input voltage P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 “H” input voltage RESET, XIN, CNVSS “L” input voltage P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) Min. 4.0 2.7 Limits Typ. 5.0 5.0 0 2.0 Max. 5.5 5.5 “L” input voltage RESET, CNVSS “L” input voltage XIN “H” total peak output current “H” total peak output current “L” total peak output current (Note) “L” total peak output current (Note) “L” total peak output current “H” total average output current “H” total average output current “L” total average output current (Note) “L” total average output current (Note) “L” total average output current P00–P07, P10–P17, P30–P34 (Note) P20, P21, P24–P27, P40–P44 (Note) P00–P07, P30–P34 P10–P17 P20–P27,P40–P44 (Note) P00–P07, P10–P17, P30–P34 (Note) P20, P21, P24–P27, P40–P44 (Note) P00–P07, P30–P34 P10–P17 P20–P27,P40–P44 (Note) 0.8VCC 0.8VCC 0 0 0 V VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC V V V V V V V V V –80 –80 80 120 80 –40 –40 40 60 40 mA mA mA mA mA mA mA mA mA mA VCC 0 AVSS Unit Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 39 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 9 Recommended operating conditions (2) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) f(XIN) Parameter “H” peak output current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note 1) “L” peak output current (Note 1) P00–P07, P20–P27, P30–P34, P40–P44 “L” peak output current (Note 1) P10–P17 “H” average output current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note 2) “L” average output current (Note 2) P00–P07, P20–P27, P30–P34, P40–P44 “L” average output current (Note 2) P10–P17 Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3) Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3) Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50%. 40 Min. Limits Typ. Max. Unit –10 mA 10 20 mA mA –5 mA 5 15 8 4 mA mA MHz MHz MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 10 Electrical characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VOH VOL VOL Parameter “H” output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note) “L” output voltage P00–P07, P20–P27, P30–P34, P40–P44 “L” output voltage P10–P17 Test conditions IOH = –10 mA VCC = 4.0–5.5 V IOH = –1.0 mA VCC = 2.7–5.5 V IOL = 10 mA VCC = 4.0–5.5 V IOL = 1.0 mA VCC = 2.7–5.5 V IOL = 20 mA VCC = 4.0–5.5 V IOL = 10 mA VCC = 2.7–5.5 V Min. Typ. Max. Unit VCC–2.0 V VCC–1.0 V 2.0 V 1.0 V 2.0 V 1.0 V VT+–VT– Hysteresis CNTR0, CNTR1, INT0–INT3 0.4 V VT+–VT– Hysteresis RxD, SCLK ____________ Hysteresis RESET “H” input current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 ____________ “H” input current RESET, CNVSS “H” input current XIN “L” input current P00–P07, P10–P17, P20–P27 P30–P34, P40–P44 ____________ “L” input current RESET,CNVSS “L” input current XIN RAM hold voltage 0.5 V VT+–VT– IIH IIH IIH IIL IIL IIL VRAM 0.5 VI = VCC 5.0 VI = VCC VI = VCC VI = VSS 4 VI = VSS VI = VSS When clock stopped –4 5.0 –5.0 –5.0 2.0 5.5 V µA µA µA µA µA µA V Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 41 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 11 Electrical characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol ICC Parameter Power source current Test conditions High-speed mode f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” High-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” Middle-speed mode f(XIN) = 8 MHz f(XCIN) = stopped Output transistors “off” Middle-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = stopped Output transistors “off” Increment when A-D conversion is executed f(XIN) = 8 MHz All oscillation stopped (in STP state) Output transistors “off” 42 Ta = 25 °C Ta = 85 °C Min. Typ. Max. 6.8 13 1.6 Unit mA mA 60 200 µA 20 40 µA 20 55 µA 5.0 10.0 µA 4.0 7.0 mA 1.5 mA 800 µA 0.1 1.0 µA 10 µA MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 12 A-D converter characteristics (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted) Symbol Parameter Test conditions – – tCONV Resolution Absolute accuracy (excluding quantization error) Conversion time RLADDER IVREF Ladder resistor Reference power source input current II(AD) A-D port input current VREF “on” VREF “off” Limits Min. High-speed mode, Middle-speed mode Low-speed mode VREF = 5.0 V 50 Typ. 40 35 150 0.5 Max. 10 ±4 61 200 5.0 5.0 Unit bit LSB 2tc(XIN) µs kΩ µA µA 43 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS Table 13 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Limits Min. 2 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Table 14 Timing requirements (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART). 44 Limits Min. 2 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 15 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tv (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tv (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Parameter Test conditions Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Fig.44 Limits Min. Typ. tC(SCLK1)/2–30 tC(SCLK1)/2–30 Max. 140 –30 30 30 tC(SCLK2)/2–160 tC(SCLK2)/2–160 200 0 10 10 30 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”. 3: The XOUT pin is excluded. Table 16 Switching characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tv (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tv (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Fig.44 Limits Min. Typ. tC(SCLK1)/2–50 tC(SCLK1)/2–50 Max. 350 –30 50 50 tC(SCLK2)/2–240 tC(SCLK2)/2–240 400 0 20 20 50 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”. 3: The XOUT pin is excluded. 45 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Measurement output pin 100pF CMOS output Fig. 44 Circuit for measuring output switching characteristics 46 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER tC(CNTR) tWH(CNTR) CNTR0 CNTR1 tWL(CNTR) 0.8VCC 0.2VCC tWL(INT) tWH(INT) 0.8VCC INT0 to INT3 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN SCLK1 SCLK2 tf 0.2VCC tC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2) tWH(SCLK1), tWH(SCLK2) tr 0.8VCC 0.2VCC tsu(RxD-SCLK1), tsu(SIN2-SCLK2) RXD SIN2 th(SCLK1-RxD), th(SCLK2-SIN2) 0.8VCC 0.2VCC td(SCLK1-TXD), td(SCLK2-SOUT2) tv(SCLK1-TXD), tv(SCLK2-SOUT2) TXD SOUT2 Fig. 45 Timing diagram 47 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE 42P4B Plastic 42pin 600mil SDIP EIAJ Package Code SDIP42-P-600-1.78 Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy 22 1 21 E 42 e1 c JEDEC Code – Symbol L A1 A A2 D e b1 b2 b SEATING PLANE A A1 A2 b b1 b2 c D E e e1 L 42P2R-A/E Dimension in Millimeters Min Nom Max – – 5.5 0.51 – – – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° – 15° Plastic 42pin 450mil SSOP EIAJ Package Code SSOP42-P-450-0.80 JEDEC Code – Weight(g) 0.63 e b2 22 E HE e1 I2 42 Lead Material Alloy 42 Recommended Mount Pad F Symbol 1 21 A D G A2 e b L L1 y A1 A A1 A2 b c D E e HE L L1 z Z1 y c z Z1 48 Detail G Detail F b2 e1 I2 Dimension in Millimeters Min Nom Max 2.4 – – – – 0.05 – 2.0 – 0.4 0.3 0.25 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 – 0.8 – 12.23 11.93 11.63 0.7 0.5 0.3 – 1.765 – – 0.75 – – – 0.9 0.15 – – 0° – 10° – 0.5 – – 11.43 – – – 1.27 MITSUBISHI MICROCOMPUTERS 3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 42S1B-A Metal seal 42pin 600mil DIP EIAJ Package Code WDIP42-C-600-1.78 JEDEC Code – Weight(g) 1 21 e1 22 E 42 c D A1 L A A2 Symbol Z e b b1 SEATING PLANE A A1 A2 b b1 c D E e e1 L Z Dimension in Millimeters Min Nom Max 5.0 – – – – 1.0 3.44 – – 0.38 0.54 0.46 0.7 0.8 0.9 0.17 0.33 0.25 – – 41.1 – 15.8 – – – 1.778 – – 15.24 3.05 – – – – 3.05 49 HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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H) DATA SHEET Revision Description Rev. date 1.0 First Edition 000309 1.1 Font errors are revised. 000322 (1/1)