Cypress CY62157EV30 8 mbit (512k x 16) static ram Datasheet

CY62157EV30 MoBL®
8 Mbit (512K x 16) Static RAM
Features
■
TSOP I Package Configurable as 512K x 16 or 1M x 8 SRAM
■
High Speed: 45 ns
■
Temperature Ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■
Wide Voltage Range: 2.20V to 3.60V
■
Pin Compatible with CY62157DV30
■
Ultra Low Standby Power
❐ Typical standby current: 2 μA
❐ Maximum standby current: 8 μA (Industrial)
■
Ultra Low Active Power
❐ Typical active current: 1.8 mA at f = 1 MHz
■
Easy Memory Expansion with CE1, CE2, and OE Features
■
Automatic Power Down when Deselected
■
CMOS for Optimum Speed and Power
■
Available in Pb-free and non Pb-free 48-Ball VFBGA, Pb-free
44-Pin TSOP II and 48-Pin TSOP I Packages
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input or output pins (IO0
through IO15) are placed in a high impedance state when the
device is deselected (CE1HIGH or CE2 LOW), the outputs are
disabled (OE HIGH), Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or a write operation is active (CE1
LOW, CE2 HIGH and WE LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO0 through IO7) is written
into the location specified on the address pins (A0 through A18).
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the address
pins (A0 through A18).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO8 to IO15. See the Truth Table on page 10
for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Functional Description
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
Logic Block Diagram
512K × 16/1M x 8
RAM Array
SENSE AMPS
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
IO0–IO7
IO8–IO15
COLUMN DECODER
BYTE
BHE
WE
CE2
CE1
BHE
A11
A12
A13
A14
A15
A16
A17
A18
Power Down
Circuit
OE
BLE
CE2
CE1
BLE
Cypress Semiconductor Corporation
Document #: 38-05445 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 26, 2009
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CY62157EV30 MoBL®
Pin Configuration
Figure 1. 48-Ball VFBGA (Top View) [2]
Figure 2. 44-Pin TSOP II (Top View) [3]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
IO8
BHE
A3
A4
CE1
IO0
B
IO9
IO10
A5
A6
IO1
IO2
C
VSS
IO11
A17
A7
IO3
VCC
D
VCC
IO12
NC
A16
IO4
VSS
E
IO14
IO13
A14
A15
IO5
IO6
F
IO15
NC
A12
A13
WE
IO7
G
A18
A8
A9
A10
A11
NC
H
A4
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
A8
A9
A10
A11
A12
A13
Figure 3. 48-Pin TSOP I (512K x 16/1M x 8) (Top View) [2, 4]
A15
A14
A13
A12
A11
A10
A9
A8
NC
DNU
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
Vss
IO15/A19
IO7
IO14
IO6
IO13
IO5
IO12
IO4
Vcc
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
OE
Vss
CE1
A0
Product Portfolio
Power Dissipation
Product
CY62157EV30LL
Speed
(ns)
VCC Range (V)
Range
Operating ICC, (mA)
f = 1 MHz
Min
Typ [1]
Max
Ind’l/Auto-A
2.2
3.0
3.6
Auto-E
2.2
3.0
3.6
f = fmax
Standby, ISB2
(μA)
Typ [1]
Max
Typ [1]
Max
Typ [1]
Max
45
1.8
3
18
25
2
8
55
1.8
4
18
35
2
30
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
2. NC pins are not connected on the die.
3. The 44-TSOP II package has only one chip enable (CE) pin.
4. The BYTE pin in the 48-TSOP I package must be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOP I package can also be used as a 1M × 8
SRAM by tying the BYTE signal LOW. In the 1M x 8 configuration, Pin 45 is A19, while BHE, BLE and IO8 to IO14 pins are not used (DNU).
Document #: 38-05445 Rev. *F
Page 2 of 15
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CY62157EV30 MoBL®
DC Input Voltage [5, 6] ........... –0.3V to 3.9V (VCC max + 0.3V)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch Up Current ................................................... > 200 mA
Operating Range
Supply Voltage to Ground
Potential ............................... –0.3V to 3.9V (VCCmax + 0.3V)
DC Voltage Applied to Outputs
in High-Z State [5, 6] ............... –0.3V to 3.9V (VCCmax + 0.3V)
Ambient
Temperature
VCC [7]
CY62157EV30LL Ind’l/Auto-A –40°C to +85°C
2.2V to
3.6V
Device
Range
Auto-E
–40°C to +125°C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
45 ns (Ind’l/Auto-A)
Min
Typ
[1]
Max
55 ns (Auto-E)
Min
Typ [1]
Max
Unit
Output HIGH
Voltage
IOH = –0.1 mA
2.0
2.0
V
IOH = –1.0 mA, VCC > 2.70V
2.4
2.4
V
VOL
Output LOW
Voltage
IOL = 0.1 mA
VIH
Input HIGH
Voltage
VOH
VIL
Input LOW
Voltage
0.4
IOL = 2.1mA, VCC > 2.70V
0.4
0.4
V
0.4
V
VCC = 2.2V to 2.7V
1.8
VCC + 0.3
1.8
VCC + 0.3
V
VCC = 2.7V to 3.6V
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VCC = 2.2V to 2.7V
–0.3
0.6
–0.3
0.6
V
VCC = 2.7V to 3.6V
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage
Current
GND < VI < VCC
–1
+1
–4
+4
μA
IOZ
Output Leakage GND < VO < VCC, Output Disabled
Current
–1
+1
–4
+4
μA
ICC
VCC Operating
Supply Current
f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
f = 1 MHz
CMOS levels
ISB1
Automatic CE
Power Down
Current —
CMOS Inputs
ISB2 [8]
Automatic CE
Power Down
Current —
CMOS Inputs
18
25
18
35
1.8
3
1.8
4
mA
CE1 > VCC − 0.2V, CE2 < 0.2V
VIN > VCC – 0.2V, VIN < 0.2V)
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60V
2
8
2
30
μA
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
2
8
2
30
μA
Notes
5. VIL(min) = –2.0V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100 μs ramp time from 0 to Vcc(min) and 200 μs wait time after VCC stabilization.
8. Only chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE (48 TSOP I only) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs
can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05445 Rev. *F
Page 3 of 15
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CY62157EV30 MoBL®
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
Unit
10
pF
10
pF
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
ΘJA
Thermal Resistance Still Air, soldered on a 3 × 4.5 inch,
(Junction to Ambient) two-layer printed circuit board
ΘJC
Thermal Resistance
(Junction to Case)
BGA
TSOP I
TSOP II
Unit
72
74.88
76.88
°C/W
8.86
8.6
13.52
°C/W
Figure 4. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
30 pF
10%
GND
R2 Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Parameters
R1
R2
RTH
VTH
Document #: 38-05445 Rev. *F
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V TH
2.5V
16667
15385
8000
1.20
3.0V
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Page 4 of 15
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CY62157EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
Conditions
Min
VCC for Data Retention
ICCDR
tCDR
[8]
[9]
tR [10]
Data Retention Current
Typ [1] Max Unit
1.5
VCC= 1.5V, CE1 > VCC – 0.2V,
CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
Chip Deselect to Data
Retention Time
Operation Recovery Time
Ind’l/Auto-A
V
2
Auto-E
μA
5
30
0
ns
tRC
ns
Data Retention Waveform
Figure 5. Data Retention Waveform [11]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
CE1 or
BHE.BLE
or
CE2
Notes
10. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
11. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 38-05445 Rev. *F
Page 5 of 15
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CY62157EV30 MoBL®
Switching Characteristics
Over the Operating Range[12, 13]
Parameter
Description
45 ns (Ind’l/Auto-A)
Min
Max
55 ns (Auto-E)
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
45
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
45
55
ns
tDOE
OE LOW to Data Valid
22
25
ns
OE LOW to
LOW-Z[14]
tHZOE
OE HIGH to
High-Z[14, 15]
tLZCE
CE1 LOW and CE2 HIGH to Low-Z[14]
tLZOE
45
10
55
18
ns
20
10
18
ns
ns
20
CE1 LOW and CE2 HIGH to Power Up
tPD
CE1 HIGH and CE2 LOW to Power
Down
45
55
ns
tDBE
BLE/BHE LOW to Data Valid
45
55
ns
tLZBE
tHZBE
Write
BLE/BHE LOW to
BLE/BHE HIGH to
HIGH-Z[14, 15]
0
ns
tPU
Low-Z[14, 16]
0
ns
ns
5
10
15]
ns
10
5
CE1 HIGH and CE2 LOW to High-Z[14,
tHZCE
55
5
ns
10
18
ns
20
ns
Cycle[17]
tWC
Write Cycle Time
45
55
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
40
ns
tAW
Address Setup to Write End
35
40
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Setup to Write Start
0
0
ns
tPWE
WE Pulse Width
35
40
ns
tBW
BLE/BHE LOW to Write End
35
40
ns
tSD
Data Setup to Write End
25
25
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High-Z[14, 15]
tLZWE
[14]
WE HIGH to Low-Z
18
10
20
10
ns
ns
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4.
13. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
15. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
16. If both byte enables are toggled together, this value is 10 ns.
17. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
Document #: 38-05445 Rev. *F
Page 6 of 15
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CY62157EV30 MoBL®
Switching Waveforms
Figure 6 shows Address Transition Controlled read cycle waveforms.[18, 19]
Figure 6. Read Cycle No. 1
tRC
RC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 7 shows OE Controlled read cycle waveforms. [19, 20]
Figure 7. Read Cycle No. 2
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
ICC
tPU
50%
50%
ISB
Notes
18. The device is continuously selected. OE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH.
19. WE is HIGH for read cycle.
20. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05445 Rev. *F
Page 7 of 15
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CY62157EV30 MoBL®
Switching Waveforms (continued)
Figure 8 shows WE Controlled write cycle waveforms.[17, 21, 22]
Figure 8. Write Cycle No. 1
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA IO
NOTE 23
VALID DATA
tHZOE
Figure 9 shows CE1 or CE2 Controlled write cycle waveforms.[17, 21, 22]
Figure 9. Write Cycle No. 1
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
NOTE 23
tHD
VALID DATA
tHZOE
Notes
21. Data I/O is high impedance if OE = VIH.
22. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
23. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 38-05445 Rev. *F
Page 8 of 15
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CY62157EV30 MoBL®
Switching Waveforms (continued)
Figure 10 shows WE Controlled, OE LOW write cycle waveforms.[22]
Figure 10. Write Cycle No. 3
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA IO
NOTE 23
tHD
VALID DATA
tLZWE
tHZWE
Figure 11 shows BHE/BLE Controlled, OE LOW write cycle waveforms.[22]
Figure 11. Write Cycle No. 4
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA IO
NOTE 23
Document #: 38-05445 Rev. *F
tHD
VALID DATA
Page 9 of 15
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CY62157EV30 MoBL®
Truth Table
CE1
CE2
WE
OE
BHE
BLE
H
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
H
L
H
L
Inputs/Outputs
Mode
Power
High-Z
Deselect/Power Down
Standby (ISB)
X
High-Z
Deselect/Power Down
Standby (ISB)
H
H
High-Z
Deselect/Power Down
Standby (ISB)
L
L
L
Data Out (IO0–IO15)
Read
Active (ICC)
H
L
H
L
Data Out (IO0–IO7);
High-Z (IO8–IO15)
Read
Active (ICC)
H
H
L
L
H
High-Z (IO0–IO7);
Data Out (IO8–IO15)
Read
Active (ICC)
L
H
H
H
L
H
High-Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High-Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High-Z
Output Disabled
Active (ICC)
L
H
L
X
L
L
Data In (IO0–IO15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (IO0–IO7);
High-Z (IO8–IO15)
Write
Active (ICC)
L
H
L
X
L
H
High-Z (IO0–IO7);
Data In (IO8–IO15)
Write
Active (ICC)
Ordering Information
Speed
(ns)
45
55
Ordering Code
Package
Diagram
Package Type
CY62157EV30LL-45BVI
51-85150
48-ball Very Fine Pitch Ball Grid Array
CY62157EV30LL-45BVXI
51-85150
48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62157EV30LL-45ZSXI
51-85087
44-pin Thin Small Outline Package Type II (Pb-free)
CY62157EV30LL-45ZXI
51-85183
48-pin Thin Small Outline Package Type I (Pb-free)
CY62157EV30LL-45BVXA
51-85150
48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62157EV30LL-45ZSXA
51-85087
44-pin Thin Small Outline Package Type II (Pb-free)
CY62157EV30LL-45ZXA
51-85183
48-pin Thin Small Outline Package Type I (Pb-free)
CY62157EV30LL-55ZSXE
51-85087
44-pin Thin Small Outline Package Type II (Pb-free)
CY62157EV30LL-55ZXE
51-85183
48-pin Thin Small Outline Package Type I (Pb-free)
Operating
Range
Industrial
Automotive-A
Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Document #: 38-05445 Rev. *F
Page 10 of 15
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CY62157EV30 MoBL®
Package Diagrams
Figure 12. 48-Pin VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
0.55 MAX.
6.00±0.10
0.15(4X)
0.10 C
0.21±0.05
0.25 C
B
Document #: 38-05445 Rev. *F
1.00 MAX
0.26 MAX.
SEATING PLANE
C
51-85150-*D
Page 11 of 15
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CY62157EV30 MoBL®
Package Diagrams (continued)
Figure 13. 44-Pin TSOP II, 51-85087
51-85087-*A
Document #: 38-05445 Rev. *F
Page 12 of 15
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CY62157EV30 MoBL®
Package Diagrams (continued)
Figure 14. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183
DIMENSIONS IN INCHES[MM] MIN.
MAX.
JEDEC # MO-142
0.037[0.95]
0.041[1.05]
N
1
0.020[0.50]
TYP.
0.472[12.00]
0.007[0.17]
0.011[0.27]
0.002[0.05]
0.006[0.15]
0.724 [18.40]
0.047[1.20]
MAX.
SEATING PLANE
0.004[0.10]
0.787[20.00]
0.004[0.10]
0.008[0.21]
0.010[0.25]
GAUGE PLANE
0°-5°
Document #: 38-05445 Rev. *F
0.020[0.50]
0.028[0.70]
51-85183-*A
Page 13 of 15
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CY62157EV30 MoBL®
Document History Page
Document Title: CY62157EV30 MoBL®, 8 Mbit (512K x 16) Static RAM
Document Number: 38-05445
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
202940
AJU
See ECN
New Data Sheet
*A
291272
SYT
See ECN
Converted from Advance Information to Preliminary
Removed 48-TSOP I Package and the associated footnote
Added footnote stating 44 TSOP II Package has only one CE on Page # 2
Changed VCC stabilization time in footnote #7 from 100 μs to 200 μs
Changed ICCDR from 4 to 4.5 μA
Changed tOHA from 6 to 10 ns for both 35 and 45 ns Speed Bins
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed tHZOE, tHZBE and tHZWE from 12 and 15 ns to 15 and 18 ns for 35 and 45
ns Speed Bins respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for 35 and 45 ns Speed Bins
respectively
Changed tSCE, tAW and tBW from 25 and 40 ns to 30 and 35 ns for 35 and 45 ns Speed
Bins respectively
Changed tSD from 15 and 20 ns to 18 and 22 ns for 35 and 45 ns Speed Bins respectively
Added Lead-Free Package Information
*B
444306
NXR
See ECN
Converted from Preliminary to Final.
Changed ball E3 from DNU to NC
Removed redundant footnote on DNU.
Removed 35 ns speed bin
Removed “L” bin
Added 48 pin TSOP I package
Added Automotive product information.
Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28 mA
to 25 mA for test condition f = fax = 1/tRC.
Changed the ICC Max value from 2.3 mA to 3 mA for test condition f = 1MHz.
Changed the ISB1 and ISB2 Max value from 4.5 μA to 8 μA and Typ value from 0.9
μA to 2 μA respectively.
Modified ISB1 test condition to include BHE, BLE
Updated Thermal Resistance table.
Changed Test Load Capacitance from 50 pF to 30 pF.
Added Typ value for ICCDR .
Changed the ICCDR Max value from 4.5 μA to 5 μA
Corrected tR in Data Retention Characteristics from 100 μs to tRC ns.
Changed tLZOE from 3 to 5
Changed tLZCE from 6 to 10
Changed tHZCE from 22 to 18
Changed tLZBE from 6 to 5
Changed tPWE from 30 to 35
Changed tSD from 22 to 25
Changed tLZWE from 6 to 10
Added footnote #15
Updated the ordering Information and replaced the Package Name column with
Package Diagram.
*C
467052
NXR
See ECN
Modified Data sheet to include x8 configurability.
Updated the Ordering Information table
*D
925501
VKN
See ECN
Removed Automotive-E information
Added Preliminary Automotive-A information
Added footnote #10 related to ISB2 and ICCDR
Added footnote #15 related AC timing parameters
*E
1045801
VKN
See ECN
Converted Automotive-A specs from preliminary to final
Updated footnote #9
Document #: 38-05445 Rev. *F
Description of Change
Page 14 of 15
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CY62157EV30 MoBL®
Document Title: CY62157EV30 MoBL®, 8 Mbit (512K x 16) Static RAM
Document Number: 38-05445
Rev.
ECN No.
Orig. of
Change
Submission
Date
*F
2724889
NXR/AESA
06/26/09
Description of Change
Added Automotive-E information
Included -45ZXA/-55ZSXE/-55ZXE parts in the Ordering Information table
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© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05445 Rev. *F
Revised June 26, 2009
Page 15 of 15
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