ON MC100EP446FA 3.3v/5v 8â bit cmos/ecl/ttl data input parallel/serial converter Datasheet

MC10EP446, MC100EP446
3.3V/5V 8-Bit
CMOS/ECL/TTL Data Input
Parallel/Serial Converter
The MC10/100EP446 is an integrated 8−bit parallel to serial data
converter. The device is designed with unique circuit topology to
operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence
from parallel data into a serial data stream is from bit D0 to D7. The
parallel input pins D0−D7 are configurable to be threshold controlled by
CMOS, ECL, or TTL level signals. The serial data rate output can be
selected at internal clock data rate or twice the internal clock data rate
using the CKSEL pin.
Control pins are provided to reset (SYNC) and disable internal clock
circuitry (CKEN). In either CKSEL modes, the internal flip−flops are
triggered on the rising edge for CLK and the multiplexers are switched
on the falling edge of CLK, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
Additionally, VBB pin is provided for single−ended input condition.
The 100 Series devices contain temperature compensation network.
•
•
•
•
•
•
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MARKING DIAGRAM*
MCXXX
EP446
AWLYYWW
LQFP−32
FA SUFFIX
CASE 873A
1
XXX
A
WL
YY
WW
3.2 Gb/s Typical Data Rate Capability
Differential Clock and Serial Outputs
VBB Output for Single-ended Input Applications
32
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
Asynchronous Data Reset (SYNC)
PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −5.5 V
Open Input Default State
*For additional marking information, refer to
Application Note AND8002/D.
•
• Safety Clamp on Inputs
• Parallel Interface Can Support PECL, TTL or CMOS
 Semiconductor Components Industries, LLC, 2004
June, 2004 − Rev. 5
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
1
Publication Order Number:
MC10EP446/D
D1
D2
D3
D4
D5
D6
24
23
22
21
20
19
18
D7
D0
MC10EP446, MC100EP446
17
VCC
25
16
VEE
VCF
26
15
PCLK
VEF
27
14
PCLK
VEE
28
13
VCC
SYNC
29
12
SOUT
SYNC
30
11
SOUT
VBB2
31
10
VCC
VCC
32
9
VCC
2
3
4
5
6
7
CKSEL
CLK
CLK
VBB1
CKEN
CKEN
8
VEE
1
VCC
MC10EP446
MC100EP446
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. LQFP−32 Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
D0*−D7*
ECL, CMOS, or TTL Parallel Data Input
SOUT, SOUT
ECL Differential Serial Data Output
CLK*, CLK*
ECL Differential Clock Input
PCLK, PCLK
ECL Differential Parallel Clock Output
SYNC*, SYNC**
ECL Conversion Synchronizing Differential Input (Reset)***
CKSEL*
ECL Clock Input Selector
CKEN*, CKEN*
ECL Clock Enable Differential Input
VCF
ECL, CMOS, or TTL Input Selector
VEF
ECL Reference Mode Connection
VBB1, VBB2
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
* Pins will default LOW when left open.
**Pins will default HIGH when left open.
***The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK
initiates the conversion process synchronously on the next rising edge of CLK.
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2
MC10EP446, MC100EP446
Table 2. TRUTH TABLE
Function
HIGH
Pin
CKSEL
LOW
SOUT: PCLK = 8:1
CLK: SOUT = 1:1
SOUT: PCLK = 8:1
CLK: SOUT = 1:2
CLK
CLK
SOUT
SOUT
CKEN
Synchronously Disables Normal Parallel to Serial Conversion
Synchronously Enables Normal Parallel to Serial Conversion
SYNC
Asynchronously Resets Internal Flip−Flops*
Synchronous Enable
*The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiates
the conversion process synchronously on the next rising edge of CLK.
Table 3. INPUT VOLTAGE LEVEL SELECTION TABLE
Input Function
Connect To VCF Pin
ECL Mode
VEF Pin
Table 4. DATA INPUT OPERATING VOLTAGE TABLE
Power Supply
(VCC,VEE)
Data Inputs (D [0:7])
CMOS
TTL
PECL
NECL
CMOS Mode
No Connect
PECL
N/A
TTL Mode*
1.5 V 100 mV
NECL
N/A
N/A
N/A
*For TTL Mode, if no external voltage can be provided, the reference
voltage can be provided by connecting the appropriate resistor
between VCF and VEE pins.
Power Supply
Resistor Value 10% (Tolerance)
3.3 V
1.5 k
5.0 V
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3
MC10EP446, MC100EP446
D0
D
Q
CR
MUX
2:1
D
Q
CR
D4
D
Q
CR
MUX
2:1
D
Q
C R
D2
D
Q
C R
MUX
2:1
D
Q
CR
D6
D
Q
CR
D1
D
MUX
2:1
SOUT
SOUT
Q
CR
MUX
2:1
D
Q
CR
D5
D
Q
CR
MUX
2:1
D
Q
CR
D3
D
Q
CR
MUX
2:1
D
Q
CR
D7
D
Q
CR
÷2
÷2
÷2
CKEN
CKEN
CLK
CLK
D
Q
C R
CKSEL
SYNC
SYNC
VCC
VEE
VBB
VCF
VEF
Figure 2. Logic Diagram
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4
MUX
2:1
Control
Logic
PCLK
PCLK
MC10EP446, MC100EP446
Table 5. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
37.5 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity (Note 1)
Flammability Rating
Level 2
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
962 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
6
V
−6
V
6
−6
V
V
50
100
mA
mA
± 0.5
mA
VCC
PECL Mode Power Supply
VEE = 0 V
VEE
NECL Mode Power Supply
VCC = 0 V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
LQFP−32
LQFP−32
80
55
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
Standard Board
LQFP−32
12 to 17
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
VI ≤ VCC
VI ≥ VEE
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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5
MC10EP446, MC100EP446
Table 7. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
90
110
130
90
110
130
95
115
135
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 3)
2165
2290
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 3)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single−Ended)
CMOS
PECL
TTL
2000
2090
2000
3300
3300
3300
2000
2155
2000
3300
3300
3300
2000
2215
2000
3300
3300
3300
mV
Input LOW Voltage (Single−Ended)
CMOS
PECL
TTL
0
1365
0
800
1690
800
0
1460
0
800
1755
800
0
1490
0
800
1815
800
mV
VBB
Output Voltage Reference
1740
1940
1805
2005
1865
2065
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 4)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
VIL
1840
2.0
1905
150
0.5
1965
150
0.5
A
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
3. All loading with 50 to VCC − 2.0 V.
4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 8. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
90
110
130
90
110
130
95
115
135
mA
Output HIGH Voltage (Note 6)
3865
3950
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 6)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single−Ended)
CMOS
PECL
TTL
3500
3790
2000
5000
5000
5000
3500
3855
2000
5000
5000
5000
3500
3915
2000
5000
5000
5000
mV
Input LOW Voltage (Single−Ended)
CMOS
PECL
TTL
0
3065
0
1500
3390
800
0
3130
0
1500
3455
800
0
3190
0
1500
3915
800
mV
VBB
Output Voltage Reference
3440
3640
3505
3705
3565
3765
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 7)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
Symbol
Characteristic
IEE
Power Supply Current
VOH
VIL
3540
2.0
150
0.5
3605
150
0.5
0.5
3665
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
6. All loading with 50 to VCC − 2.0 V.
7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP446, MC100EP446
Table 9. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 8)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
90
110
130
90
110
130
95
115
135
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 9)
−1135
−1010
−885
−1070
−945
−820
−1010
−885
−760
mV
VOL
Output LOW Voltage (Note 9)
−1935
−1810
−1685
−1870
−1745
−1620
−1810
−1685
−1560
mV
VIH
Input HIGH Voltage (Single−Ended)
−1210
−885
−1145
−820
−1085
−760
mV
VIL
Input LOW Voltage (Single−Ended)
−1935
−1610
−1870
−1545
−1810
−1485
mV
VBB
Output Voltage Reference
−1560
−1360
−1495
−1295
−1435
−1235
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
−1460
VEE+2.0
0.0
−1395
VEE+2.0
150
0.5
0.0
−1335
VEE+2.0
150
0.5
A
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with VCC.
9. All loading with 50 to VCC − 2.0 V.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 10. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
90
110
130
90
110
130
95
115
135
mA
Output HIGH Voltage (Note 12)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 12)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single−Ended)
CMOS
PECL
TTL
2000
2075
2000
3300
3300
3300
2000
2075
2000
3300
3300
3300
2000
2075
2000
3300
3300
3300
mV
Input LOW Voltage (Single−Ended)
CMOS
PECL
TTL
0
1355
0
800
1675
800
0
1355
0
800
1675
800
0
1355
0
800
1675
800
mV
VBB
Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
Symbol
Characteristic
IEE
Power Supply Current
VOH
VIL
1875
2.0
150
0.5
1875
150
0.5
0.5
1875
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
12. All loading with 50 to VCC − 2.0 V.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP446, MC100EP446
Table 11. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
90
110
130
90
110
130
95
115
135
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 15)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 15)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single−Ended)
CMOS
PECL
TTL
3500
3775
2000
5000
5000
5000
3500
3775
2000
5000
5000
5000
3500
3775
2000
5000
5000
5000
mV
Input LOW Voltage (Single−Ended)
CMOS
PECL
TTL
0
3055
0
1500
3375
800
0
3055
0
1500
3375
800
0
3055
0
1500
3375
800
mV
VBB
Output Voltage Reference
3475
3675
3475
3675
3475
3675
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 16)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
VIL
3575
2.0
3575
150
0.5
3575
150
0.5
A
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
15. All loading with 50 to VCC − 2.0 V.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 12. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 17)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
90
110
130
90
110
130
95
115
135
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 18)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
VOL
Output LOW Voltage (Note 18)
−1945
−1820
−1695
−1945
−1820
−1695
−1945
−1820
−1695
mV
VIH
Input HIGH Voltage (Single−Ended)
−1225
−880
−1225
−880
−1225
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1945
−1625
−1945
−1625
−1945
−1625
mV
VBB
Output Voltage Reference
−1525
−1325
−1525
−1325
−1525
−1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
−1425
VEE+2.0
0.0
150
0.5
−1425
VEE+2.0
0.0
150
0.5
−1425
VEE+2.0
0.5
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17. Input and output parameters vary 1:1 with VCC.
18. All loading with 50 to VCC − 2.0 V.
19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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MC10EP446, MC100EP446
Table 13. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
−40°C
Min
Typ
CKSEL High
CKSEL Low
3.2
1.6
3.4
1.7
Propagation Delay to Output Differential
CKSEL = 0
CLK TO SOUT,
CLK TO PCLK
650
700
750
800
775
850
875
950
(Figure 3)
(Figure 4)
(Figure 5)
−375
200
70
(Figure 3)
−525
0
75
Symbol
fmax
tPLH,
tPHL
Characteristic
th
tpw
Max
Min
Typ
3.2
1.6
3.4
1.7
850
900
700
750
800
850
975
1050
825
900
925
1000
−425
140
40
−400
200
70
−575
−550
0
75
85°C
Max
Min
Typ
Max
3.2
1.6
3.4
1.7
900
950
725
775
850
900
975
1025
ps
1025
1100
875
950
1000
1075
1125
1200
ps
−450
140
40
−450
200
70
−500
140
40
ps
−600
−600
0
75
−650
ps
Unit
Maximum Frequency
(Figure 14)
CKSEL = 1
tS
25°C
CLK TO SOUT,
CLK TO PCLK
Setup Time
D to CLK+
SYNC− to CLK−
CKEN+ to CLK−
Hold Time
D to CLK+
SYNC− to CLK−
CLK− to CKEN−
(Figure 5)
Minimum Pulse Width (Note 22)
Data (D0−D7)
SYNC
CKEN
tJITTER
Random Clock Jitter (RMS)
fmax Typ
VPP
Input Differential Voltage Swing
(Note 21)
tr
tf
Output Rise/Fall Times
(20% − 80%)
45
150
200
145
SOUT
45
150
200
145
0.2
<1
150
800
1200
50
100
150
GHz
45
ps
150
200
145
0.2
<1
150
800
1200
70
120
170
0.2
<1
ps
150
800
1200
mV
90
140
190
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC − 2.0 V.
21. VPP(min) is the minimum input swing for which AC parameters are guaranteed.
22. The minimum pulse width is valid only if the setup and hold times are respected.
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MC10EP446, MC100EP446
CLK
Data
Valid
Data
Setup Time
ts
th
+ 0 −
Figure 3. Setup and Hold Time for Data
SYNC
CLK
SYNC
ts
CLK
CKEN
tS
CLK
Figure 4. Setup Time for SYNC
th
Figure 5. Setup and Hold Time for CKEN
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MC10EP446, MC100EP446
APPLICATION INFORMATION
The MC10/100EP446 is an integrated 8:1 parallel to serial
converter. An attribute for EP446 is that the parallel inputs
D0–D7 (Pins 17 – 24) can be configured to accept either
CMOS, ECL, or TTL level signals by a combination of
interconnects between VEF (Pin 27) and VCF (Pin 26) pins.
For CMOS input levels, leave VEF and VCF open. For ECL
operation, short VCF and VEF (Pins 26 and 27). For TTL
operation, connect a 1.5 V supply reference to VCF and leave
the VEF pin open. The 1.5 V reference voltage to VCF pin can
be accomplished by placing a 1.5 k or 500 between VCF
and VEE for 3.3 V or 5.0 V power supplies, respectively.
Note: all pins requiring ECL voltage inputs must have a
50 terminating resistor to VTT (VTT = VCC – 2.0 V).
The CKSEL input (Pin 2) is provided to enable the user to
select the serial data rate output between internal clock data
rate or twice the internal clock data rate. For CKSEL LOW
operation, the time from when the parallel data is latched to when the data is seen on the SOUT is on the falling edge
of the 7th clock cycle plus internal propagation delay
(Figure 6). Note the PCLK switches on the falling edge of
CLK.
Number of Clock Cycles from Data Latch to SOUT
1
2
3
4
5
6
7
CLK
D0
D0−1
D0−2
D0−3
D0−4
D1
D1−1
D1−2
D1−3
D1−4
D2
D2−1
D2−2
D2−3
D2−4
D3
D3−1
D3−2
D3−3
D3−4
D4
D4−1
D4−2
D4−3
D4−4
D5
D5−1
D5−2
D5−3
D5−4
D6
D6−1
D6−2
D6−3
D6−4
D7
D7−1
D7−2
D7−3
D7−4
Data Latched
Data Latched
CKSEL
PCLK
Figure 6. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW
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D6−2
D5−2
D4−2
D3−2
D2−2
D0−2
D1−2
D7−1
D6−1
Data Latched
D5−1
D4−1
D3−1
D2−1
D1−1
SOUT
D0−1
Data Latched
MC10EP446, MC100EP446
Similarly, for CKSEL HIGH operation, the time from when the parallel data is latched to when the data is seen on the
SOUT is on the rising edge of the 14th clock cycle plus internal propagation delay (Figure 7). Furthermore, the PCLK switches
on the rising edge of CLK.
Number of Clock Cycles from Data Latch to SOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
D0
D0−1
D0−2
D0−3
D1
D1−1
D1−2
D1−3
D2
D2−1
D2−2
D2−3
D3
D3−1
D3−2
D3−3
D4
D4−1
D4−2
D4−3
D5
D5−1
D5−2
D5−3
D6
D6−1
D6−2
D6−3
D7
D7−1
D7−2
D7−3
CKSEL
PCLK
Figure 7. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL HIGH
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D1−2
D0−2
D7−1
D6−1
D5−1
D4−1
D3−1
D2−1
SOUT
D1−1
Data Latched
Data Latched
D0−1
Data Latched
MC10EP446, MC100EP446
The device also features a differential SYNC input (Pins 29 and 30), which asynchronously reset all internal flip–flops and
clock circuitry on the rising edge of SYNC. The release of SYNC is a synchronous process, which ensures that no runt serial
data bits are generated. The falling edge of the SYNC followed by a falling edge of CLK initiates the start of the conversion
process on the next rising edge of CLK (Figures 8 and 9). As shown in the figures below, the device will start to latch the parallel
input data after the a falling edge of SYNC , followed by the falling edge CLK , on the next rising of edge of CLK for
CKSEL LOW
SYNC
(Synchronous ENABLE)
Number of Clock Cycles from Data Latch to SOUT
1
SYNC
(Asynchronous RESET)
SYNC
3
4
5
6
7
D0
D0−1
D0−2
D0−3
D0−4
D1
D1−1
D1−2
D1−3
D1−4
D2
D2−1
D2−2
D2−3
D2−4
D3
D3−1
D3−2
D3−3
D3−4
D4
D4−1
D4−2
D4−3
D4−4
D5
D5−1
D5−2
D5−3
D5−4
D6
D6−1
D6−2
D6−3
D6−4
D7
D7−1
D7−2
D7−3
D7−4
SOUT
CKSEL
PCLK
Figure 8. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW and SYNC
SYNC
CLK
Figure 9. Synchronous Release of SYNC for CKSEL LOW
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D5−2
D4−2
D3−2
D2−2
D1−2
D0−2
D7−1
D6−1
Data Latched
D5−1
Data Latched
D4−1
Data Latched
D0−1
D1−1
D2−1
D3−1
Data Latched
D6−2
CLK
2
MC10EP446, MC100EP446
For CKSEL HIGH, as shown in the timing diagrams below, the device will start to latch the parallel input data after the falling
edge of SYNC , followed by the falling edge CLK , on the second rising edge of CLK (Figures 10 and 11).
SYNC
(Synchronous ENABLE)
Number of Clock Cycles from Data Latch to SOUT
SYNC
(Asynchronous RESET)
CLK
SYNC
1
2
3
4
5
6
7
8
9
10 11 12 13 14
D0
D0−1
D0−2
D0−3
D0−4
D1
D1−1
D1−2
D1−3
D1−4
D2
D2−1
D2−2
D2−3
D2−4
D3
D3−1
D3−2
D3−3
D3−4
D4
D4−1
D4−2
D4−3
D4−4
D5
D5−1
D5−2
D5−3
D5−4
D6
D6−1
D6−2
D6−3
D6−4
D7
D7−1
D7−2
D7−3
D7−4
Data Latched
SOUT
CKSEL
PCLK
Figure 10. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL HIGH and SYNC
SYNC
CLK
Figure 11. Synchronous Release of SYNC for CKSEL HIGH
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D1−2
D0−2
D7−1
D6−1
D5−1
D4−1
D3−1
D2−1
D1−1
Data Latched
D0−1
Data Latched
MC10EP446, MC100EP446
The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN will
suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the
falling edge of CLK will suspend all activities. The falling edge of CKEN followed by the falling edge of CLK will resume
all activities (Figure 12).
Internal Clock
Disabled
Internal Clock
Enabled
CLK
CKEN
SOUT
D0−1
D1−1
D2−1
D3−1
D4−1
D5−1
PCLK
CKSEL
Figure 12. Timing Diagram with CKEN with CKSEL HIGH
The differential PCLK output (Pins 14 and 15) is a word
framer and can help the user synchronize the serial data
output, SOUT (Pins 11 and 12), in their applications.
Furthermore, PCLK can be used as a trigger for input
parallel data (Figure 13).
An internally generated voltage supply, the VBB pin, is
available to this device only. For single–ended input
conditions, the unused differential input is connected to VBB
as a switching reference voltage. VBB may also rebias AC
coupled inputs. When used, decouple VBB and VCC via a
0.01 F capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open. Also, both
outputs of the differential pair must be terminated (50 to
VTT) even if only one output is used.
CLK
RESET
CLK
SYNC
Pattern Generator
Data Format Logic
(FPGA, ASIC)
PARALLEL
DATA INPUT
PARALLEL
DATA OUTPUT
TRIGGER
EP446
SOUT
PCLK
Figure 13. PCLK as Trigger Application
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SERIAL DATA
MC10EP446, MC100EP446
800
CKSEL High
700
VOUTpp (mV)
CKSEL Low
600
500
400
300
200
100
0
0
500
1000
1500
2000
2500
3000
3500
INPUT CLOCK FREQUENCY (MHz)
Figure 14. Typical VOUTPP versus Input Clock Frequency, 25C
Figure 15. SOUT System Jitter Measurement
(Condition: 3.4 GHz input frequency, CKSEL HIGH, BEOFE32 bit pattern on SOUT
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MC10EP446, MC100EP446
Zo = 50 Q
D
Receiver
Device
Driver
Device
Zo = 50 Q
D
50 50 VTT
VTT = VCC − 2.0 V
Figure 16. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
Shipping†
Package
MC10EP446FA
LQFP−32
250 Units / Tray
MC10EP446FAR2
LQFP−32
2000 / Tape & Reel
MC100EP446FA
LQFP−32
250 Units / Tray
MC100EP446FAR2
LQFP−32
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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MC10EP446, MC100EP446
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPS I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1642/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC10EP446, MC100EP446
PACKAGE DIMENSIONS
A
32
A1
−T−, −U−, −Z−
LQFP
FA SUFFIX
32−LEAD PLASTIC PACKAGE
CASE 873A−02
ISSUE B
4X
25
0.20 (0.008) AB T−U Z
1
AE
−U−
−T−
B
P
V
17
8
BASE
METAL
DETAIL Y
V1
ÉÉ
ÉÉ
ÉÉ
ÉÉ
−Z−
9
S1
4X
0.20 (0.008) AC T−U Z
F
S
8X
M
J
R
D
DETAIL AD
G
SECTION AE−AE
−AB−
C E
−AC−
H
W
K
X
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT
INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.250
(0.010) PER SIDE. DIMENSIONS A AND
B DO INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE
−AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER
MAY VARY FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
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MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12 REF
0.090
0.160
0.400 BSC
1
5
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12 REF
0.004
0.006
0.016 BSC
1
5
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Q
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
M
N
9
0.20 (0.008)
DETAIL Y
AC T−U Z
AE
B1
MC10EP446, MC100EP446
ECLinPS is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 81−3−5773−3850
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For additional information, please contact your
local Sales Representative.
MC10EP446/D
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