AD AD5307BRU-REEL 2.5 v to 5.5 v, 400 mua, quad voltage output Datasheet

2.5 V to 5.5 V, 400 μA, Quad Voltage Output,
8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5307/AD5317/AD5327
FEATURES
GENERAL DESCRIPTION
AD5307: 4 buffered 8-bit DACs in 16-lead TSSOP
A version: ±1 LSB INL; B version: ±0.625 LSB INL
AD5317: 4 buffered 10-bit DACs in 16-lead TSSOP
A version: ±4 LSB INL; B version: ±2.5 LSB INL
AD5327: 4 buffered 12-bit DACs in 16-lead TSSOP
A version: ±16 LSB INL; B version: ±10 LSB INL
Low power operation: 400 μA @ 3 V, 500 μA @ 5 V
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power down to 90 nA @ 3 V, 300 nA @ 5 V (LDAC pin)
Double-buffered input logic
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC pin)
Asynchronous clear facility (CLR pin)
Low power, SPI®-, QSPI™-, MICROWIRE™-, and DSPcompatible 3-wire serial interface
SDO daisy-chaining option
On-chip rail-to-rail output buffer amplifiers
Temperature range of −40°C to +105°C
The AD5307/AD5317/AD53271 are quad 8-,10-,12-bit buffered
voltage-output DACs in 16-lead TSSOP that operate from single
2.5 V to 5.5 V supplies and consume 400 μA at 3 V. Their onchip output amplifiers allow the outputs to swing rail-to-rail with
a slew rate of 0.7 V/μs. The AD5307/AD5317/AD5327 utilize
versatile 3-wire serial interfaces that operate at clock rates up to
30 MHz; these parts are compatible with standard SPI, QSPI,
MICROWIRE, and DSP interface standards.
The references for the four DACs are derived from two reference
pins (one per DAC pair). These reference inputs can be configured
as buffered or unbuffered inputs. Each part incorporates a poweron reset circuit, ensuring that the DAC outputs power up to 0 V
and remain there until a valid write to the device takes place.
There is also an asynchronous active low CLR pin that clears all
DACs to 0 V. The outputs of all DACs can be updated simultaneously using the asynchronous LDAC input. Each part
contains a power-down feature that reduces the current
consumption of the device to 300 nA @ 5 V (90 nA @ 3 V). The
parts can also be used in daisy-chaining applications using the
SDO pin.
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
All three parts are offered in the same pinout, allowing users to
select the amount of resolution appropriate for their application
without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFAB
AD5307/AD5317/AD5327
GAIN-SELECT
LOGIC
LDAC
SCLK
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
VOUTA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTB
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
VOUTC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
VOUTD
INTERFACE
LOGIC
SYNC
DIN
POWER-ON
RESET
DCEN
LDAC CLR
POWER-DOWN
LOGIC
VREFCD
PD
GND
02067-001
SDO
Figure 1.
1
Protected by U.S. Patent No. 5,969,657; other patents pending.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD5307/AD5317/AD5327
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Shift Register .................................................................... 17
Applications....................................................................................... 1
Control Bits ................................................................................. 17
General Description ......................................................................... 1
Low Power Serial Interface ....................................................... 18
Functional Block Diagram .............................................................. 1
Daisy Chaining ........................................................................... 18
Revision History ............................................................................... 2
Double-Buffered Interface ........................................................ 18
Specifications..................................................................................... 3
Load DAC Input (LDAC).......................................................... 18
AC Characteristics........................................................................ 5
Power-Down Mode .................................................................... 18
Timing Characteristics ................................................................ 5
Microprocessor Interfacing....................................................... 19
Absolute Maximum Ratings............................................................ 7
Applications..................................................................................... 20
ESD Caution.................................................................................. 7
Typical Application Circuit....................................................... 20
Pin Configuration and Function Descriptions............................. 8
Driving VDD from the Reference Voltage ................................ 20
Typical Performance Characteristics ............................................. 9
Bipolar Operation....................................................................... 20
Terminology .................................................................................... 13
Opto-Isolated Interface for Process-Control Applications... 21
Transfer Function ........................................................................... 14
Decoding Multiple AD5307/AD5317/AD5327 Devices....... 21
Functional Description .................................................................. 15
AD5307/AD5317/AD5327 as Digitally Programmable
Window Detectors ..................................................................... 21
Digital-to-Analog Section ......................................................... 15
Resistor String ............................................................................. 15
DAC Reference Inputs ............................................................... 15
Output Amplifier........................................................................ 16
Power-On Reset .......................................................................... 16
Daisy Chaining ........................................................................... 22
Power Supply Bypassing and Grounding................................ 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
Serial Interface ................................................................................ 17
REVISION HISTORY
3/06—Rev. B to Rev. C
Changes to Table 3............................................................................ 5
Changes to Ordering Guide .......................................................... 25
10/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Bipolar Operation Section ........................................ 21
Changes to Ordering Guide .......................................................... 25
8/03—Rev. 0 to Rev. A
Added A Version ................................................................Universal
Changes to Features ..........................................................................1
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings........................................6
Changes to Ordering Guide .............................................................6
Changes to TPC 21......................................................................... 12
Added Octals section to Table II .................................................. 20
Updated Outline Dimensions....................................................... 21
Rev. C | Page 2 of 28
AD5307/AD5317/AD5327
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND, CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter 2
DC PERFORMANCE 3 , 4
AD5307
Resolution
Relative Accuracy
Differential Nonlinearity
Min
A Version 1
Typ
Max
Min
B Version
Typ
Max
Unit
8
±0.15
±0.02
±1
±0.25
8
±0.15
±0.02
±0.625
±0.25
Bits
LSB
LSB
AD5317
Resolution
Relative Accuracy
Differential Nonlinearity
10
±0.5
±0.05
±4
±0.5
10
±0.5
±0.05
±2.5
±0.5
Bits
LSB
LSB
AD5327
Resolution
Relative Accuracy
Differential Nonlinearity
12
±2
±0.2
±16
±1
12
±2
±0.2
±10
±1
Bits
LSB
LSB
Offset Error
±5
±60
±5
±60
mV
Gain Error
±0.3
±1.25
±0.3
±1.25
% FSR
Lower Dead Band 5
10
60
10
60
mV
Upper Dead Band
10
60
10
60
mV
Offset Error Drift 6
−12
−12
Gain Error Drift
−5
−5
−60
200
−60
200
DC Power Supply Rejection Ratio
DC Crosstalk
DAC REFERENCE INPUTS
VREF Input Range
1
0.25
VREF Input Impedance (RDAC)
Reference Feedthrough
Channel-to-Channel Isolation
OUTPUT CHARACTERISTICS
Minimum Output Voltage 7
Maximum Output Voltage
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD
VDD
1
0.25
>10
ppm of
FSR/°C
ppm of
FSR/°C
dB
mV
VDD
VDD
>10
V
V
MΩ
74
90
74
90
kΩ
37
45
37
45
kΩ
−90
−75
−90
−75
dB
dB
0.001
0.001
V
VDD −
0.001
0.5
25
16
2.5
VDD −
0.001
0.5
25
16
2.5
V
Ω
mA
mA
μs
5
5
μs
Rev. C | Page 3 of 28
Conditions/Comments
Guaranteed monotonic by design
over all codes
Guaranteed monotonic by design
over all codes
Guaranteed monotonic by design
over all codes
VDD = 4.5 V, gain = 2; see Figure 29
and Figure 30
VDD = 4.5 V, gain = 2; see Figure 29
and Figure 30
See Figure 29, lower dead band
exists only if offset error is negative
See Figure 30, upper dead band
exists only if VREF = VDD and offset
plus gain error is positive
∆VDD = ±10%
RL = 2 kΩ to GND or VDD
Buffered reference mode
Unbuffered reference mode
Buffered reference mode and
power-down mode
Unbuffered reference mode,
0 V to VREF output range
Unbuffered reference mode,
0 V to 2 VREF output range
Frequency = 10 kHz
Frequency = 10 kHz
A measure of the minimum drive
capability of the output amplifier
A measure of the maximum drive
capability of the output amplifier
VDD = 5 V
VDD = 3 V
Coming out of power-down mode,
VDD = 5 V
Coming out of power-down mode,
VDD = 3 V
AD5307/AD5317/AD5327
Parameter 2
LOGIC INPUTS
Input Current
Input Low Voltage, VIL
Min
A Version 1
Typ
Max
Min
±1
0.8
0.6
0.5
±1
0.8
0.6
0.5
Input High Voltage, VIH
(Excluding DCEN)
1.7
1.7
Input High Voltage, VIH
(DCEN)
2.4
2.4
2.1
2.0
2.1
2.0
Pin Capacitance
LOGIC OUTPUT (SDO)
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
Floating State Leakage Current
Floating State Output Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode) 8
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
B Version
Typ
Max
3
0.4
VDD = 3 V ± 10%
VDD = 2.5 V
V
V
ISINK = 2 mA
ISOURCE = 2 mA
V
V
ISINK = 2 mA
ISOURCE = 2 mA
±1
μA
pF
DCEN = GND
DCEN = GND
5.5
V
0.4
0.4
0.4
VDD −
0.5
±1
3
2.5
3
5.5
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
VDD = 2.5 V to 5.5 V; TTL and
1.8 V CMOS compatible
V
V
pF
VDD − 1
VDD −
0.5
mA
V
V
V
V
Conditions/Comments
VDD = 5 V ± 10%
3
VDD − 1
Unit
2.5
500
400
900
750
500
400
900
750
μA
μA
0.3
0.09
1
1
0.3
0.09
1
1
μA
μA
1
VIH = VDD and VIL = GND
All DACs in unbuffered mode; in
buffered mode, extra current is
typically x mA per DAC, where
x = 5 mA + VREF/RDAC
VIH = VDD and VIL = GND
Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.
See the Terminology section.
3
DC specifications tested with the outputs unloaded, unless otherwise noted.
4
Linearity is tested using a reduced code range: AD5307 (Code 8 to Code 255); AD5317 (Code 28 to Code 1023); AD5327 (Code 115 to Code 4095).
5
This corresponds to x codes, where x = deadband voltage/LSB size.
6
Guaranteed by design and characterization; not production tested.
7
For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus
gain error must be positive.
8
Interface inactive. All DACs active. DAC outputs unloaded.
2
Rev. C | Page 4 of 28
AD5307/AD5317/AD5327
AC CHARACTERISTICS
VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
2, 3
Parameter
Output Voltage Settling Time
AD5307
AD5317
AD5327
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
SDO Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
A, B Versions 1
Min
Typ
Max
Unit
6
7
8
0.7
12
0.5
4
0.5
1
3
200
−70
μs
μs
μs
V/μs
nV-s
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
8
9
10
Conditions/Comments
VREF = VDD = 5 V
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 to 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
1 LSB change around major carry
Daisy-chain mode; SDO load is 10 pF
VREF = 2 V ± 0.1 V p-p; unbuffered mode
VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz
1
Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.
Guaranteed by design and characterization; not production tested.
3
See the Terminology section.
2
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter 1, 2 ,
A, B Versions
Limit at TMIN, TMAX
Unit
Conditions/Comments
33
13
13
13
5
4.5
5
50
20
20
20
0
20
25
5
8
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width
SCLK falling edge to LDAC rising edge
CLR pulse width
SCLK falling edge to LDAC falling edge
SCLK rising edge to SDO valid (VDD = 3.6 V to 5.5 V)
SCLK rising edge to SDO valid (VDD = 2.5 V to 3.5 V)
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13 4, 5
t14
t15
t16
1
Guaranteed by design and characterization; not production tested.
All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3
See Figure 3 and Figure 4.
4
This is measured with the load circuit of Figure 2. t13 determines maximum SCLK frequency in daisy-chain mode.
5
Daisy-chain mode only.
2
Rev. C | Page 5 of 28
AD5307/AD5317/AD5327
2mA
VOH (MIN)
CL
50pF
2mA
02067-002
TO OUTPUT
PIN
IOL
IOH
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
t1
SCLK
t4
t8
t2
t3
t7
SYNC
t6
t5
DB15
DIN
DB0
t9
t12
LDAC1
t10
LDAC2
t11
CLR
02067-003
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 3. Serial Interface Timing Diagram
t1
SCLK
t8
t3
t4
t14
t2
SYNC
t15
t16
t5
DIN
t9
t6
DB0
DB15
INPUT WORD FOR DAC N
DB15'
DB0'
INPUT WORD FOR DAC (N+1)
t13
DB0
DB15
SDO
UNDEFINED
INPUT WORD FOR DAC N
Figure 4. Daisy-Chaining Timing Diagram
Rev. C | Page 6 of 28
02067-004
LDAC
AD5307/AD5317/AD5327
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter 1
VDD to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input Voltage to GND
VOUTA − VOUTD to GND
Operating Temperature Range
Industrial (A, B Versions)
Storage Temperature Range
Junction Temperature (TJ max)
16-Lead TSSOP
Power Dissipation
θJA Thermal Impedance
Reflow Soldering
Peak Temperature
Time at Peak Temperature
1
Ratings
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
150.4°C/W
220°C
10 sec to 40 sec
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 7 of 28
AD5307/AD5317/AD5327
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLR 1
16
SDO
LDAC 2
15
SYNC
14
SCLK
VDD
3
AD5307/
AD5317/
AD5327
DIN
TOP VIEW
VOUTB 5 (Not to Scale) 12 GND
13
VOUTC 6
11
VOUTD
VREFAB 7
10
PD
VREFCD 8
9
DCEN
02067-005
VOUTA 4
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No.
1
2
Mnemonic
CLR
LDAC
3
VDD
4
5
6
7
VOUTA
VOUTB
VOUTC
VREFAB
8
VREFCD
9
DCEN
10
PD
11
12
13
VOUTD
GND
DIN
14
SCLK
15
SYNC
16
SDO
Description
Active Low Control Input. Loads all 0s to all input and DAC registers. Therefore, the outputs also go to 0 V.
Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this
pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous
update of all DAC outputs. Alternatively, this pin can be tied permanently low.
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Reference Input Pin for DAC A and DAC B. It can be configured as a buffered or unbuffered input to each or both of
the DACs, depending on the state of the BUF bits in the serial input words to DAC A and DAC B. It has an input range
of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.
Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to each or both of
the DACs, depending on the state of the BUF bits in the serial input words to DAC C and DAC D. It has an input range
of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.
Enables the Daisy-Chaining Option. It should be tied high if the part is being used in a daisy chain, and tied low if it is
being used in standalone mode.
Active Low Control Input. It acts like a hardware power-down option. All DACs go into power-down mode when this
pin is tied low. The DAC outputs go into a high impedance state, and the current consumption of the part drops to
300 nA @ 5 V (90 nA @ 3 V).
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. These devices each have a 16-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input. The DIN input buffer is powered down after each write cycle.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at rates of up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers
on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the
following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and
the write sequence is ignored by the device.
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in
the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the
falling edge of the clock.
Rev. C | Page 8 of 28
AD5307/AD5317/AD5327
TYPICAL PERFORMANCE CHARACTERISTICS
0.3
1.0
TA = 25°C
VDD = 5V
TA = 25°C
VDD = 5V
0.2
DNL ERROR (LSB)
INL ERROR (LSB)
0.5
0
0.1
0
–0.1
–0.5
0
50
100
150
200
–0.3
250
02067-009
–1.0
02067-006
–0.2
0
50
100
Figure 6. AD5307 INL
250
800
1000
0.6
TA = 25°C
VDD = 5V
2
TA = 25°C
VDD = 5V
0.4
1
DNL ERROR (LSB)
0
–1
0
–0.2
–0.4
02067-007
–2
0.2
0
200
400
600
900
–0.6
1000
02067-010
INL ERROR (LSB)
200
Figure 9. AD5307 DNL
3
–3
150
CODE
CODE
0
200
400
CODE
600
CODE
Figure 7. AD5317 INL
Figure 10. AD5317 DNL
1.0
12
TA = 25°C
VDD = 5V
TA = 25°C
VDD = 5V
8
DNL ERROR (LSB)
0
–4
0
–0.5
–12
0
1000
2000
3000
–1.0
4000
02067-011
–8
02067-008
INL ERROR (LSB)
0.5
4
0
1000
2000
CODE
CODE
Figure 11. AD5327 DNL
Figure 8. AD5327 INL
Rev. C | Page 9 of 28
3000
4000
AD5307/AD5317/AD5327
0.2
0.50
TA = 25°C
VDD = 5V
MAX INL
0
0.25
ERROR (% FSR)
MAX DNL
ERROR (LSB)
TA = 25°C
VREF = 2V
0.1
0
GAIN ERROR
–0.1
–0.2
–0.3
MIN INL
0
1
2
3
4
–0.6
5
02067-015
–0.5
02067-012
MIN INL
–0.50
OFFSET ERROR
–0.4
–0.25
0
1
2
VREF (V)
Figure 12. AD5307 INL Error and DNL Error vs. VREF
5
6
5
VDD = 5V
VREF = 3V
MAX INL
0.3
5V SOURCE
4
0.2
3V SOURCE
MAX DNL
0.1
VOUT (V)
ERROR (LSB)
4
Figure 15. Offset Error and Gain Error vs. VDD
0.5
0.4
3
VDD (V)
0
–0.1
MIN DNL
3
2
–0.2
–0.3
1
–0.5
–40
0
40
80
0
120
0
1
TEMPERATURE (°C)
2
3
4
5
6
SINK/SOURCE CURRENT (mA)
Figure 13. AD5307 INL Error and DNL Error vs. Temperature
Figure 16. VOUT Source and Sink Current Capability
600
1.0
VDD = 5V
VREF = 2V
500
0.5
TA = 25°C
VDD = 5V
VREF = 2V
400
IDD (µA)
GAIN ERROR
0
300
OFFSET ERROR
200
–0.5
–1.0
–40
0
40
80
120
0
02067-017
100
02067-014
ERROR (% FSR)
3V SINK
5V SINK
02067-016
02067-013
MIN INL
–0.4
ZERO SCALE
FULL SCALE
CODE
TEMPERATURE (°C)
Figure 17. Supply Current vs. DAC Code
Figure 14. AD5307 Offset Error and Gain Error vs. Temperature
Rev. C | Page 10 of 28
AD5307/AD5317/AD5327
600
–40°C
+25°C
500
TA = 25°C
VDD = 5V
VREF = 5V
IDD (µA)
400
CH1
+105°C
VOUTA
300
200
SCLK
2.5
3.0
3.5
4.0
4.5
5.0
CH2
02067-021
0
02067-018
100
5.5
VDD (V)
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
Figure 21. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
Figure 18. Supply Current vs. Supply Voltage
0.5
TA = 25°C
VDD = 5V
VREF = 2V
0.4
IDD (µA)
CH1
0.3
VDD
–40°C
0.2
+25°C
+105°C
0
2.5
3.0
3.5
4.0
4.5
5.0
CH2
5.5
VDD (V)
CH1 2.00V, CH2 200mV, TIME BASE = 200µs/DIV
Figure 22. Power-On Reset to 0 V
Figure 19. Power-Down Current vs. Supply Voltage
800
VOUTA
02067-022
02067-019
0.1
DECREASING
TA = 25°C
TA = 25°C
VDD = 5V
VREF = 2V
700
IDD (µA)
INCREASING
CH1
600
VDD = 5V
VOUTA
500
VDD = 3V
DECREASING
300
0
1
2
02067-020
INCREASING
3
4
CH2
PD
02067-023
400
5
VLOGIC (V)
CH1 500MV, CH2 5.00V, TIME BASE = 1µs/DIV
Figure 20. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing
and Decreasing
Rev. C | Page 11 of 28
Figure 23. Exiting Power-Down to Midscale
AD5307/AD5317/AD5327
0.02
VDD = 5V
TA = 25°C
02067-024
FREQUENCY
FULL-SCALE ERROR (V)
VDD = 5V
350
400
450
500
IDD (µA)
550
0.01
0
–0.01
–0.02
600
02067-027
VDD = 3V
0
1
2
3
4
5
6
VREF (V)
Figure 27. Full-Scale Error vs. VREF
Figure 24. IDD Histogram with VDD = 3 V and VDD = 5 V
2.50
1mV/DIV
VOUT (V)
2.49
2.47
1µs/DIV
150ns/DIV
Figure 25. AD5327 Major-Code Transition Glitch Energy
Figure 28. DAC-to-DAC Crosstalk
10
0
–10
(dB)
–20
–30
–40
02067-026
–50
–60
10
100
1k
10k
02067-028
02067-025
2.48
100k
1M
10M
FREQUENCY (Hz)
Figure 26. Multiplying Bandwidth (Small-Signal Frequency Response)
Rev. C | Page 12 of 28
AD5307/AD5317/AD5327
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSB from a straight line
passing through the endpoints of the DAC transfer function.
Figure 6 through Figure 8 show plots of typical INL vs. code.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Figure 9 through Figure 11 show plots of
typical DNL vs. code.
Offset Error
Offset error is a measure of the deviation in the output voltage
from 0 V when zero-code is loaded to the DAC (see Figure 29
and Figure 30.) It can be negative or positive. It is expressed in
millivolts.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic from
the ideal expressed as a percentage of the full-scale range.
Offset Error Drift
Offset error drift is a measure of the change in offset error
with changes in temperature. It is expressed in (ppm of fullscale range)/°C.
Gain Error Drift
Gain error drift is a measure of the change in gain error
with changes in temperature. It is expressed in (ppm of fullscale range)/°C.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. It is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It is
measured in decibels. VREF is held at 2 V, and VDD is varied ±10%.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC while monitoring
another DAC. It is expressed in microvolts.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal at
the DAC output to the reference input when the DAC output is not
being updated (that is, LDAC is high). It is expressed in decibels.
Channel-to-Channel Isolation
Channel-to-channel isolation is the ratio of the amplitude of the
signal at the output of one DAC to a sine wave on the reference
input of another DAC. It is measured in decibels.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-s and is measured when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but it is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-s and is measured with a
full-scale change on the digital input pins, that is, from all 0s to
all 1s or vice versa.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another DAC.
It is measured in standalone mode and is expressed in nV-s.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping LDAC
high, and then pulsing LDAC low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC low while monitoring the output of another DAC. The
energy of the glitch is expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth, and the
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference for
the DAC, and the THD is a measure of the harmonics present
on the DAC output. It is measured in decibels.
Rev. C | Page 13 of 28
AD5307/AD5317/AD5327
TRANSFER FUNCTION
GAIN ERROR
+
OFFSET ERROR
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
ERROR
DAC CODE
ACTUAL
IDEAL
LOWER
DEAD BAND
CODES
AMPLIFIER
FOOTROOM
02067-029
NEGATIVE
OFFSET
ERROR
Figure 29. Transfer Function with Negative Offset
GAIN ERROR
+
OFFSET ERROR
UPPER
DEADBAND
CODES
OUTPUT
VOLTAGE
POSITIVE
OFFSET
ERROR
DAC CODE
FULL SCALE
Figure 30. Transfer Function with Positive Offset (VREF = VDD)
Rev. C | Page 14 of 28
02067-030
ACTUAL
IDEAL
AD5307/AD5317/AD5327
FUNCTIONAL DESCRIPTION
The AD5307/AD5317/AD5327 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits respectively. Each contains four output buffer amplifiers
and is written to via a 3-wire serial interface. They operate from
single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers
provide rail-to-rail output swing with a slew rate of 0.7 V/μs.
DAC A and DAC B share a common reference input, VREFAB.
DAC C and DAC D share a common reference input, VREFCD.
Each reference input can be buffered to draw virtually no
current from the reference source, or can be unbuffered to give
a reference input range of 0.25 V to VDD. The devices have a
power-down mode in which all DACs can be completely turned
off with a high impedance output.
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a resistorstring DAC followed by an output buffer amplifier. The voltage
at the VREF pin provides the reference voltage for the
corresponding DAC. Figure 31 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
DAC REFERENCE INPUTS
There is a reference pin for each pair of DACs. The reference
inputs are buffered but can also be individually configured as
unbuffered. The advantage with the buffered input is the high
impedance it presents to the voltage source driving it. However,
if the unbuffered mode is used, the user can have a reference
voltage as low as 0.25 V and as high as VDD, because there is no
restriction due to headroom and footroom of the reference
amplifier.
R
R
VREF × D
2
R
TO OUTPUT
AMPLIFIER
N
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 255 for AD5307 (8 bits).
0 to 1023 for AD5317 (10 bits).
0 to 4095 for AD5327 (12 bits).
N is the DAC resolution.
VREFAB
BUF
REFERENCE
BUFFER
RESISTOR
STRING
R
Figure 32. Resistor String
If there is a buffered reference in the circuit (for example, REF192),
there is no need to use the on-chip buffers of the AD5307/AD5317/
AD5327. In unbuffered mode, the input impedance is still large
at typically 90 kΩ per reference input for 0 V to VREF mode and
45 kΩ or 0 V to 2 VREF mode.
VOUTA
OUTPUT
BUFFER AMPLIFIER
02067-031
DAC
REGISTER
R
The buffered/unbuffered option is controlled by the BUF bit in
the data-word. The BUF bit setting applies to whichever DAC is
selected.
GAIN MODE
(GAIN = 1 OR 2)
INPUT
REGISTER
The resistor string section is shown in Figure 32. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
02067-032
VOUT =
RESISTOR STRING
Figure 31. Single DAC Channel Architecture
Rev. C | Page 15 of 28
AD5307/AD5317/AD5327
OUTPUT AMPLIFIER
POWER-ON RESET
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on the value of VREF, GAIN, offset error, and gain error.
The AD5307/AD5317/AD5327 are each provided with a poweron reset function so that they power up in a defined state. The
power-on state is
If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V
to VREF.
•
Normal operation
•
Reference inputs unbuffered
•
0 V to VREF output range
•
Output voltage set to 0 V
If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 VREF. Because of clamping, however, the maximum output
is limited to VDD − 0.001 V.
The output amplifier is capable of driving a load of 2 kΩ to GND
or VDD in parallel with 500 pF to GND or VDD. The source and
sink capabilities of the output amplifier can be seen in Figure 16.
The slew rate is 0.7 V/μs, with a half-scale settling time to
±0.5 LSB (at eight bits) of 6 μs.
Both input and DAC registers are filled with 0s until a valid
write sequence is made to the device. This is particularly useful
in applications where it is important to know the state of the
DAC outputs while the device is powering up.
Rev. C | Page 16 of 28
AD5307/AD5317/AD5327
SERIAL INTERFACE
The AD5307/AD5317/AD5327 are controlled over versatile 3-wire
serial interfaces that operate at clock rates of up to 30 MHz and
are compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.
The AD5327 uses all 12 bits of DAC data; the AD5317 uses
10 bits and ignores the 2 LSBs. The AD5307 uses eight bits and
ignores the last four bits. The data format is straight binary, with
all 0s corresponding to 0 V output and all 1s corresponding to
full-scale output (VREF − 1 LSB).
INPUT SHIFT REGISTER
The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can be transferred
into the device only while SYNC is low. To start the serial data
transfer, SYNC should be taken low, observing the minimum
SYNC to SCLK falling edge set-up time, t4. After SYNC goes
low, serial data is shifted into the device’s input shift register on
the falling edges of SCLK for 16 clock pulses. In standalone
mode (DCEN = 0), any data and clock pulses after the 16th
falling edge of SCLK are ignored, and no further serial data
transfer can occur until SYNC is taken high and low again.
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in
Figure 3. The 16-bit word consists of four control bits followed
by 8, 10, or 12 bits of DAC data, depending on the device type.
Data is loaded MSB first (Bit 15), and the first two bits
determine whether the data is for DAC A, DAC B, DAC C, or
DAC D. Bit 13 and Bit 12 control the operating mode of the
DAC. Bit 13 is GAIN, which determines the output range of the
part. Bit 12 is BUF, which controls whether the reference inputs
are buffered or unbuffered.
SYNC can be taken high after the falling edge of the 16th SCLK
pulse, observing the minimum SCLK falling edge to SYNC
rising edge time, t7.
Table 6. Address Bits for the AD53x7
A1 (Bit 15)
0
0
1
1
A0 (Bit 14)
0
1
0
1
DAC Addressed
DAC A
DAC B
DAC C
DAC D
After the end of serial data transfer, data is automatically transferred from the input shift register to the input register of the
selected DAC. If SYNC is taken high before the 16th falling
edge of SCLK, the data transfer is aborted and the DAC input
registers are not updated.
CONTROL BITS
GAIN controls the output range of the addressed DAC.
When data has been transferred into the input register of a DAC,
the corresponding DAC register and DAC output can be updated
by taking LDAC low. CLR is an active low, asynchronous clear
that clears the input registers and DAC registers to all 0s.
0: output range of 0 V to VREF.
1: output range of 0 V to 2 VREF.
BUF controls whether reference of the addressed DAC is
buffered or unbuffered.
0: unbuffered reference.
1: buffered reference.
A1
BIT 0
(LSB)
A0 GAIN BUF
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
DATA BITS
02067-033
BIT 15
(MSB)
Figure 33. AD5307 Input Shift Register Contents
A1
BIT 0
(LSB)
A0 GAIN BUF
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
DATA BITS
02067-034
BIT 15
(MSB)
Figure 34. AD5317 Input Shift Register Contents
A1
BIT 0
(LSB)
A0 GAIN BUF D11 D10
D9
D8
D7
D6
D5
D4
D3
DATA BITS
Figure 35. AD5327 Input Shift Register Contents
Rev. C | Page 17 of 28
D2
D1
D0
02067-035
BIT 15
(MSB)
AD5307/AD5317/AD5327
LOW POWER SERIAL INTERFACE
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC. The SCLK and DIN input buffers
are powered down on the rising edge of SYNC.
DAISY CHAINING
For systems that contain several DACs, or where the user
wishes to read back the DAC contents for diagnostic purposes,
the SDO pin can be used to daisy-chain several devices together
and provide serial readback.
By connecting the DCEN (daisy-chain enable) pin high, the
daisy-chain mode is enabled. It is tied low in the case of
standalone mode. In daisy-chain mode, the internal gating on
SCLK is disabled. The SCLK is continuously applied to the
input shift register when SYNC is low. If more than 16 clock
pulses are applied, the data ripples out of the shift register and
appears on the SDO line. This data is clocked out on the rising
edge of SCLK and is valid on the falling edge. By connecting
this line to the DIN input on the next DAC in the chain, a
multi-DAC interface is constructed. Each DAC in the system
requires 16 clock pulses; therefore, the total number of clock
cycles must equal 16N, where N is the total number of devices
in the chain. When the serial transfer to all devices is complete,
SYNC should be taken high. This prevents any further data
from being clocked into the input shift register.
A continuous SCLK source can be used if SYNC is held low for
the correct number of clock cycles. Alternatively, a burst clock
containing the exact number of clock cycles can be used and
SYNC can be taken high some time later.
When the transfer to all input registers is complete, a common
LDAC signal updates all DAC registers and all analog outputs
are updated simultaneously.
DOUBLE-BUFFERED INTERFACE
The AD5307/AD5317/AD5327 DACs have double-buffered
interfaces consisting of two banks of registers: input registers
and DAC registers. The input registers are connected directly to
the input shift register and the digital code is transferred to the
relevant input register on completion of a valid write sequence.
The DAC registers contain the digital code used by the resistor
strings.
Access to the DAC registers is controlled by the LDAC pin.
When the LDAC pin is high, the DAC registers are latched and
the input registers can change state without affecting the
contents of the DAC registers. When LDAC is brought low,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them.
The double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to three of the input registers individually and then, by bringing
LDAC low when writing to the remaining DAC input register,
all outputs update simultaneously.
These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been updated
since the last time LDAC was brought low. Normally, when LDAC
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5307/AD5317/AD5327,
the DAC register updates only if the input register has changed
since the last time the DAC register was updated, thereby removing
unnecessary digital crosstalk.
LOAD DAC INPUT (LDAC)
LDAC transfers data from the input registers to the DAC
registers and therefore updates the outputs. Use of the LDAC
function enables double buffering of the DAC data, GAIN, and
BUF. There are two LDAC modes: synchronous and asynchronous.
Synchronous Mode
In this mode, the DAC registers are updated after new data is
read from on the falling edge of the 16th SCLK pulse. LDAC
can be tied permanently low or pulsed as in Figure 3.
Asynchronous Mode
In this mode, the outputs are not updated at the same time that
the input registers are written to. When LDAC goes low, the DAC
registers are updated with the contents of the input register.
POWER-DOWN MODE
The AD5307/AD5317/AD5327 have low power consumption,
typically dissipating 1.2 mW with a 3 V supply and 2.5 mW with
a 5 V supply. Power consumption can be further reduced when
the DACs are not in use by putting them into power-down mode,
which is selected by taking the PD pin low.
When the PD pin is high, all DACs work normally with a typical
power consumption of 500 μA at 5 V (400 μA at 3 V). However,
in power-down mode, the supply current falls to 300 nA at 5 V
(90 nA at 3 V) when all DACs are powered down. Not only does
the supply current drop, but the output stage is also internally
switched from the output of the amplifier, making it an open
circuit. This has the advantage that the output is three-state
while the part is in power-down mode and provides a defined
input condition for whatever is connected to the output of the
DAC amplifier. The output stage is illustrated in Figure 36.
The bias generator, output amplifiers, resistor string, and all
other associated linear circuitry are shut down when the powerdown mode is activated. However, the contents of the registers
are unaffected when in power-down. In fact, it is possible to
load new data to the input registers and DAC registers during
power-down. The DAC outputs update as soon as PD goes high.
Rev. C | Page 18 of 28
AD5307/AD5317/AD5327
68HC11/68L111
AMPLIFIER
PC7
SYNC
SCK
SCLK
MOSI
VOUT
DIN
02067-036
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 38. 68HC11/68L11-to-AD5307/AD5317/AD5327 Interface
80C51/80L51-to-AD5307/AD5317/AD5327 Interface
Figure 36. Output Stage During Power-Down
MICROPROCESSOR INTERFACING
ADSP-2101/ADSP-2103-toAD5307/AD5317/AD5327 Interface
Figure 37 shows a serial interface between the AD5307/AD5317/
AD5327 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT transmit
alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is
programmed through the SPORT control register and should be
configured as follows: internal clock operation, active low framing,
16-bit word length. Transmission is initiated by writing a word
to the Tx register after SPORT is enabled. The data is clocked
out on each rising edge of the DSP’s serial clock and clocked
into the AD5307/AD5317/AD5327 on the falling edge of the
DAC’s SCLK.
TFS
DT
SCLK
AD5307/
AD5317/
AD53271
AD5307/
AD5317/
AD53271
80C51/80L511
SYNC
DIN
P3.3
SYNC
SCLK
TxD
SCLK
RxD
DIN
1ADDITIONAL PINS OMITTED FOR CLARITY.
02067-037
ADSP-2101/
ADSP-21031
Figure 39 shows a serial interface between the AD5307/AD5317/
AD5327 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5307/AD5317/AD5327, and RxD drives the serial data
line of the part. The SYNC signal is again derived from a bitprogrammable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5307/AD5317/
AD5327, P3.3 is taken low. The 80C51/80L51 transmits data only
in 8-bit bytes; therefore, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data LSB first. The AD5307/AD5317/AD5327 require
their data with the MSB as the first bit received. The
80C51/80L51 transmit routine should take this into account.
Figure 37. ADSP-2101/ADSP-2103-to-AD5307/AD5317/AD5327 Interface
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. 80C51/80L51-to-AD5307/AD5317/AD5327 Interface
68HC11/68L11-to-AD5307/AD5317/AD5327 Interface
Figure 38 shows a serial interface between the AD5307/AD5317/
AD5327 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5307/AD5317/
AD5327, and the MOSI output drives the serial data line (DIN)
of the DAC. The SYNC signal is derived from a port line (PC7).
The set-up conditions for correct operation of this interface are as
follows: The 68HC11/68L11 should be configured so that its CPOL
bit is 0 and its CPHA bit is 1. When data is being transmitted to the
DAC, the SYNC line is taken low (PC7). With this configuration,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes, with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to
the AD5307/AD5317/AD5327, PC7 is left low after the first
eight bits are transferred and a second serial write operation
is performed to the DAC. PC7 is taken high at the end of this
procedure.
02067-039
POWER-DOWN
CIRCUITRY
MICROWIRE-to-AD5307/AD5317/AD5327 Interface
Figure 40 shows an interface between the AD5307/AD5317/
AD5327 and a MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock, SK, and is
clocked into the AD5307/AD5317/AD5327 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.
Rev. C | Page 19 of 28
AD5307/
AD5317/
AD53271
MICROWIRE1
CS
SYNC
SK
SCLK
SO
DIN
1ADDITIONAL PINS OMITTED FOR CLARITY.
02067-040
RESISTOR
STRING DAC
AD5307/
AD5317/
AD53271
02067-038
The time to exit power-down is typically 2.5 μs for VDD = 5 V
and 5 μs when VDD = 3 V. This is the time from the rising edge
of PD to when the output voltage deviates from its power-down
voltage. See Figure 23 for a plot.
Figure 40. MICROWIRE-to-AD5307/AD5317/AD5327 Interface
AD5307/AD5317/AD5327
APPLICATIONS
TYPICAL APPLICATION CIRCUIT
BIPOLAR OPERATION
The AD5307/AD5317/AD5327 can be used with a wide range
of reference voltages and offer full, one-quadrant multiplying
capability over a reference range of 0.25 V to VDD. More typically,
these devices are used with a fixed precision reference voltage.
Suitable references for 5 V operation are the AD780 and REF192
(2.5 V references). For 2.5 V operation, a suitable external reference would be the AD589, a 1.23 V band gap reference. Figure 41
shows a typical setup for the AD5307/AD5317/AD5327 when
using an external reference.
The AD5307/AD5317/AD5327 are designed for single-supply
operation, but a bipolar output range is also possible using the
circuit shown in Figure 42. This circuit provides an output
voltage range of 5 V. Rail-to-rail operation at the amplifier
output is achievable by using an AD820 or an OP295 as the
output amplifier.
The output voltage for any input code can be calculated as
follows:
⎡ (REFIN × D / 2 N )× (R1 + R2) ⎤
VOUT = ⎢
⎥ − REFIN × (R2 / R1)
R1
⎦⎥
⎣⎢
VDD = 2.5V TO 5.5V
10µF
0.1µF
VOUT
EXT
REF
1µF
VREF AB
VOUTA
VREF CD
VOUTB
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
REFIN is the reference voltage input.
AD5307/AD5317/
AD5327
AD780/REF192
WITH VDD = 5V
OR AD589 WITH
VDD = 2.5V
SCLK
VOUTC
DIN
SYNC
When REFIN = 5 V, R1 = R2 = 10 kΩ,
VOUTD
GND
02067-041
SERIAL
INTERFACE
VOUT = (10 × D/2N) − 5 V
Figure 41. AD5307/AD5317/AD5327 Using a 2.5 V External Reference
R1
10kΩ
+6V TO +16V
DRIVING VDD FROM THE REFERENCE VOLTAGE
10µF
If an output range of 0 V to VDD is required when the reference
inputs are configured as unbuffered, the simplest solution is to
connect the reference input to VDD. Because this supply can be
noisy and not very accurate, the AD5307/AD5317/AD5327 can
be powered from the reference voltage, for example, from a 5 V
reference such as the REF195, which outputs a steady supply
voltage. The typical current required from the REF195 with no
load on the DAC outputs is 500 μA supply current and ≈112 μA
into the reference inputs (if unbuffered). When the DAC
outputs are loaded, the REF195 also needs to supply the current
to the loads. The total current required with a 10 kΩ load on
each output is
R2
10kΩ
+5V
0.1µF
±5V
VDD VOUTA
AD5307/AD5317/
AD5327
VIN
REF195
VOUT
GND
612 μA + 4 (5 V/10 kΩ) = 2.6 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 5.2 ppm (26 μV) for the 2.6 mA
current drawn from it. This corresponds to a 0.0013 LSB error
at eight bits and a 0.021 LSB error at 12 bits.
Rev. C | Page 20 of 28
+5V
1µF
VREF AB
VREF CD
AD820/
OP295
–5V
VOUTB
VOUTC
VOUTD
GND
DIN SCLK SYNC
SERIAL
INTERFACE
Figure 42. Bipolar Operation with the AD5307/AD5317/AD5327
02067-042
VIN
AD5307/AD5317/AD5327
AD5307
The AD5307/AD5317/AD5327 each have a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process-control and industrial applications. Due to noise, safety
requirements, or distance, it may be necessary to isolate the
AD5307/AD5317/AD5327 from the controller. This can easily
be achieved by using opto-isolators capable of providing isolation
in excess of 3 kV. The actual data rate achieved can be limited
by the type of optocouplers chosen. The serial loading structure
of the AD5307/AD5317/AD5327 makes them ideally suited for
use in opto-isolated applications. Figure 43 shows an opto-isolated
interface to the AD5307/AD5317/AD5327 where DIN, SCLK,
and SYNC are driven from optocouplers. The power supply to
the part should also be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator
provides the 5 V supply required for the AD5307/AD5317/
AD5327.
10µF
0.1µF
10kΩ
SCLK
VDD
VREF AB
VREF CD
AD5307
VDD
10kΩ
SYNC
VOUTA
SYNC
VDD
VCC
ENABLE
CODED
ADDRESS
1G 74HC139
1A
AD5307
1Y0
1Y1
1Y2
1Y3
1B
DGND
AD5307
AD5307
Figure 44. Decoding Multiple AD5307 Devices in a System
AD5307/AD5317/AD5327 AS DIGITALLY
PROGRAMMABLE WINDOW DETECTORS
5V
0.1µF
VREF
VOUTD
10µF
VIN
1kΩ
DIN
DIN
SCLK
02067-043
GND
SYNC
FAIL
VDD
VREF AB
AD5307/
AD5317/
SYNC AD5327
1/2
CMP04
SCLK
GND
VOUTB
Figure 45. Window Detection
The SYNC pin on the AD5307/AD5317/AD5327 can be used in
applications to decode a number of DACs. In this application,
all DACs in the system receive the same serial clock and serial
data, but the SYNC to only one of the devices is active at any
given time, allowing access to four channels in this 16-channel
system. The 74HC139 is used as a 2-to-4 line decoder to address
any of the DACs in the system. To prevent timing errors, the
enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 44 shows a
diagram of a typical setup for decoding multiple AD5307
devices in a system.
Rev. C | Page 21 of 28
PASS
PASS/FAIL
DIN
Figure 43. AD5307 in an Opto-Isolated Interface
DECODING MULTIPLE
AD5307/AD5317/AD5327 DEVICES
1kΩ
VOUTA
VREF CD
10kΩ
DCEN
VOUTA
VOUTB
VOUTC
VOUTD
SYNC
DIN
SCLK
VOUTC
DIN
VOUTA
VOUTB
VOUTC
VOUTD
SYNC
DIN
SCLK
VOUTB
VDD
VOUTA
VOUTB
VOUTC
VOUTD
SYNC
DIN
SCLK
A digitally programmable upper/lower limit detector using two of
the DACs in the AD5307/AD5317/AD5327 is shown in Figure 45.
The upper and lower limits for the test are loaded to DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the VIN input is not within the programmed window,
an LED indicates the fail condition. Similarly, DAC C and DAC D
can be used for window detection on a second VIN signal.
VDD
SCLK
DIN
SYNC
DIN
SCLK
1/6 74HC05
02067-045
5V
REGULATOR
POWER
VOUTA
VOUTB
VOUTC
VOUTD
SCLK
02067-044
OPTO-ISOLATED INTERFACE FOR
PROCESS-CONTROL APPLICATIONS
AD5307/AD5317/AD5327
DAISY CHAINING
POWER SUPPLY BYPASSING AND GROUNDING
For systems that contain several DACs, or where the user
wishes to read back the DAC contents for diagnostic purposes,
the SDO pin can be used to daisy-chain several devices together
and provide serial readback. Figure 4 shows the timing diagram
for daisy-chain applications. The daisy-chain mode is enabled
by connecting DCEN high (see Figure 46).
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5307/AD5317/AD5327 are mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5307/AD5317/AD5327
are in a system where multiple devices require an AGND-toDGND connection, the connection should be made at one
point only. The star ground point should be established as close
as possible to the device. The AD5307/AD5317/AD5327 should
have ample supply bypassing of 10 μF in parallel with 0.1 μF on
the supply located as close to the package as possible, ideally right
up against the device. The 10 μF capacitors are the tantalum bead
type. The 0.1 μF capacitor should have low effective series
resistance (ESR) and low effective series inductance (ESI), such
as is typical of the common ceramic types that provide a low
impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
68HC111
MOSI
AD53071
DIN
SCK
SCLK
PC7
SYNC
PC6
LDAC
DCEN
SDO
MISO
DIN
AD53071
SCLK
SYNC
LDAC
DCEN
SDO
DIN
AD53071
SCLK
SYNC
DCEN
SDO
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. AD5307 in Daisy-Chain Mode
02067-046
LDAC
The power supply lines of the AD5307/AD5317/AD5327 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Components, such as clocks, with fast switching signals should be
shielded with digital ground to avoid radiating noise to other
parts of the board, and they should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces
on opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board. A
microstrip technique is by far the best, but it is not always
possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, and signal
traces are placed on the solder side.
Rev. C | Page 22 of 28
AD5307/AD5317/AD5327
Table 7. Overview of AD53xx Serial Devices 1
Part No.
SINGLES
AD5300
AD5310
AD5320
AD5301
AD5311
AD5321
DUALS
AD5302
AD5312
AD5322
AD5303
AD5313
AD5323
QUADS
AD5304
AD5314
AD5324
AD5305
AD5315
AD5325
AD5306
AD5316
AD5326
AD5307
AD5317
AD5327
OCTALS
AD5308
AD5318
AD5328
1
Resolution
No. of DACs
DNL
Interface
Settling Time (μs)
Package
Pin
8
10
12
8
10
12
1
1
1
1
1
1
±0.25
±0.5
±1.0
±0.25
±0.5
±1.0
SPI
SPI
SPI
2-Wire
2-Wire
2-Wire
4
6
8
6
7
8
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
6, 8
6, 8
6, 8
6, 8
6, 8
6, 8
8
10
12
8
10
12
2
2
2
2
2
2
±0.25
±0.5
±1.0
±0.25
±0.5
±1.0
SPI
SPI
SPI
SPI
SPI
SPI
6
7
8
6
7
8
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
8
8
8
16
16
16
8
10
12
8
10
12
8
10
12
8
10
12
4
4
4
4
4
4
4
4
4
4
4
4
±0.25
±0.5
±1.0
±0.25
±0.5
±1.0
±0.25
±0.5
±1.0
±0.25
±0.5
±1.0
SPI
SPI
SPI
2-Wire
2-Wire
2-Wire
2-Wire
2-Wire
2-Wire
SPI
SPI
SPI
6
7
8
6
7
8
6
7
8
6
7
8
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
10
10
10
10
10
10
16
16
16
16
16
16
8
10
12
8
8
8
±0.25
±0.5
±1.0
SPI
SPI
SPI
6
7
8
TSSOP
TSSOP
TSSOP
16
16
16
Visit www.analog.com/support/standard_linear/selection_guides/AD53xx.html for more information.
Table 8. Overview of AD53xx Parallel Devices
Part No.
SINGLES
AD5330
AD5331
AD5340
AD5341
DUALS
AD5332
AD5333
AD5342
AD5343
QUADS
AD5334
AD5335
AD5336
AD5344
Resolution
DNL
VREF Pin
Settling Time (μs)
BUF
8
10
12
12
±0.25
±0.5
±1.0
±1.0
1
1
1
1
6
7
8
8
•
8
10
12
12
±0.25
±0.5
±1.0
±1.0
2
2
2
1
6
7
8
8
8
10
10
12
±0.25
±0.5
±0.5
±1.0
2
2
4
4
6
7
7
8
Additional Pin Functions
GAIN
HBEN
CLR
•
•
•
•
•
•
•
•
•
•
Package
Pin
•
•
•
•
•
TSSOP
TSSOP
TSSOP
TSSOP
20
20
24
20
•
•
•
•
•
TSSOP
TSSOP
TSSOP
TSSOP
20
24
28
20
•
•
•
TSSOP
TSSOP
TSSOP
TSSOP
24
24
28
28
•
•
•
Rev. C | Page 23 of 28
AD5307/AD5317/AD5327
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.65
BSC
0.30
0.19
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. C | Page 24 of 28
0.75
0.60
0.45
AD5307/AD5317/AD5327
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD5307ARU
AD5307ARU-REEL7
AD5307ARUZ1
AD5307ARUZ-REEL71
AD5307BRU
AD5307BRU-REEL
AD5307BRU-REEL7
AD5307BRUZ1
AD5307BRUZ-REEL1
AD5307BRUZ-REEL71
AD5317ARU
AD5317ARU-REEL7
AD5317ARUZ1
AD5317BRU
AD5317BRU-REEL
AD5317BRU-REEL7
AD5317BRUZ1
AD5317BRUZ-REEL1
AD5317BRUZ-REEL71
AD5327ARU
AD5327ARU-REEL7
AD5327ARUZ1
AD5327BRU
AD5327BRU-REEL
AD5327BRU-REEL7
AD5327BRUZ1
AD5327BRUZ-REEL1
AD5327BRUZ-REEL71
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
1
Z = Pb-free part.
Rev. C | Page 25 of 28
AD5307/AD5317/AD5327
NOTES
Rev. C | Page 26 of 28
AD5307/AD5317/AD5327
NOTES
Rev. C | Page 27 of 28
AD5307/AD5317/AD5327
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02067–0–3/06(C)
Rev. C | Page 28 of 28