ETC1 BC352239A Bluecore 3-multimedia external Datasheet

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Device Features
! Fully Qualified Bluetooth system
Single Chip Bluetooth® v1.2 System
! Bluetooth v1.2 Specification Compliant
! Kalimba DSP Open Platform Co-Processor
Production Information Data Sheet For
! Full Speed Bluetooth Operation with Full
Piconet Support
BC352239A
! Scatternet Support
November 2004
! Low Power 1.8V Operation
! 7 x 7mm 120-ball VFBGA Package
! Minimum External Components
! Integrated 1.8V regulator
! Dual UART Ports
! 16-bit Stereo Audio CODEC
! I2S and SPDIF Interfaces
! RoHS Compliant
General Description
Applications
BlueCore3-Multimedia External is a single chip
radio and baseband IC for Bluetooth 2.4GHz
systems.
!
Stereo Headphones
!
Automotive Hands-Free Kits
BC352239A interfaces to 8Mbit of external Flash
memory. When used with the CSR Bluetooth
software stack, it provides a fully compliant
Bluetooth system to v1.2 of the specification for
data and voice communications.
!
Echo Cancellation
!
High Performance Telephony Headsets
!
Enhanced Audio Applications
!
A/V Profile Support
RAM
External Memory
FLASH
BlueCore3-Multimedia External has been designed to
reduce the number of external components required,
ensuring that production costs are minimised.
SPI
Baseband
DSP
UART/USB
2.4
GHz
Radio
RF IN
The device incorporates auto-calibration and built-in
self-test (BIST) routines to simplify development, type
approval and production test. All hardware and device
firmware is fully compliant with the Bluetooth v1.2
Specification.
I/O
RF OUT
PIO
MCU
Audio In/Out
Kalimba DSP
BlueCore3-Multimedia External contains the Kalimba
DSP, an open platform digital signal processor (DSP) coprocessor supporting enhanced audio applications.
PCM / I2S / SPDIF
XTAL
BlueCore3-Multimedia External System
Architecture
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Contents
Contents
Status Information ................................................................................................................................................ 7
Advance Information ............................................................................................................................................ 7
Production Information ........................................................................................................................................ 7
Life Support Policy and Use in Safety-Critical Applications ............................................................................. 7
RoHS Compliance ................................................................................................................................................. 7
Trademarks, Patents and Licenses ..................................................................................................................... 7
1
Key Features .................................................................................................................................................. 8
2
7 x 7 VFBGA Package Information ............................................................................................................... 9
2.1
BlueCore3-Multimedia External Pinout Diagram................................................................................ 9
2.2
Device Terminal Functions .............................................................................................................. 10
3
Electrical Characteristics ............................................................................................................................ 15
4
Radio Characteristics .................................................................................................................................. 22
4.1
4.2
4.3
4.4
4.5
4.6
Temperature +20°C ......................................................................................................................... 22
4.1.1 Transmitter ................................................................................................................................. 22
4.1.2 Receiver ..................................................................................................................................... 23
Temperature -40°C .......................................................................................................................... 24
4.2.1 Transmitter ................................................................................................................................. 24
4.2.2 Receiver ..................................................................................................................................... 24
Temperature -25°C .......................................................................................................................... 25
4.3.1 Transmitter ................................................................................................................................. 25
4.3.2 Receiver ..................................................................................................................................... 25
Temperature +85°C ......................................................................................................................... 26
4.4.1 Transmitter ................................................................................................................................. 26
4.4.2 Receiver ..................................................................................................................................... 26
Temperature +105°C ....................................................................................................................... 27
4.5.1 Transmitter ................................................................................................................................. 27
4.5.2 Receiver ..................................................................................................................................... 27
Power Consumption ........................................................................................................................ 28
5
Device Diagram ............................................................................................................................................ 29
6
Description of Functional Blocks ............................................................................................................... 30
6.1
6.3
RF Receiver..................................................................................................................................... 30
6.1.1 Low Noise Amplifier ................................................................................................................... 30
6.1.2 Analogue to Digital Converter .................................................................................................... 30
RF Transmitter................................................................................................................................. 30
6.2.1 IQ Modulator .............................................................................................................................. 30
6.2.2 Power Amplifier .......................................................................................................................... 30
6.2.3 Auxiliary DAC ............................................................................................................................. 30
RF Synthesiser ................................................................................................................................ 30
6.4
Clock Input and Generation ............................................................................................................. 30
6.5
Baseband and Logic ........................................................................................................................ 31
6.5.1 Memory Management Unit ......................................................................................................... 31
6.5.2 Burst Mode Controller ................................................................................................................ 31
6.5.3 Physical Layer Hardware Engine DSP....................................................................................... 31
6.5.4 RAM ........................................................................................................................................... 31
6.5.5 Kalimba DSP RAM..................................................................................................................... 31
6.5.6 External Memory Driver ............................................................................................................. 32
6.5.7 USB............................................................................................................................................ 32
6.5.8 Synchronous Serial Interface ..................................................................................................... 32
6.5.9 UART ......................................................................................................................................... 32
Microcontroller ................................................................................................................................. 32
6.6.1 Programmable I/O...................................................................................................................... 32
6.2
6.6
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Pre-Production Information.................................................................................................................................. 7
Contents
6.7
Kalimba DSP ................................................................................................................................... 33
6.8
7
Audio Interface................................................................................................................................. 34
6.8.1 Audio Input and Output .............................................................................................................. 34
6.8.2 Digital Audio Interface ................................................................................................................ 34
CSR Bluetooth Software Stacks ................................................................................................................. 35
8
7.2
BlueCore HCI Stack ........................................................................................................................ 35
7.1.1 Key Features of the HCI Stack - Standard Bluetooth Functionality ............................................ 36
7.1.2 Key Features of the HCI Stack - Extra Functionality .................................................................. 37
Stand-Alone BlueCore3-Multimedia External and Kalimba DSP Applications ................................. 38
7.3
Host-Side Software.......................................................................................................................... 39
7.4
Device Firmware Upgrade ............................................................................................................... 39
7.5
BCHS Software................................................................................................................................ 39
7.6
Additional Software for Other Embedded Applications .................................................................... 39
7.7
CSR Development Systems ............................................................................................................ 39
Device Terminal Descriptions..................................................................................................................... 40
8.1
8.2
8.3
8.4
8.5
8.6
8.7
RF Ports .......................................................................................................................................... 40
8.1.1 TX_A and TX_B ......................................................................................................................... 40
8.1.2 Transmit Port Impedances for 7 x 7 VFBGA Package (2.4-2.5GHz vs. Temperature)............... 41
8.1.3 Receive Port Impedances for 7 x 7 VFBGA Package (2.4-2.5GHz vs. Temperature)................ 44
8.1.4 Transmit S Parameters .............................................................................................................. 45
8.1.5 Balanced Receive S Parameters ............................................................................................... 46
8.1.6 Single-Ended Input (RF_IN) ....................................................................................................... 47
8.1.7 Transmit RF Power Control for Class 1 Applications (TX_PWR) ............................................... 47
8.1.8 Control of External RF Components .......................................................................................... 48
External Reference Clock Input (XTAL_IN) ..................................................................................... 49
8.2.1 External Mode ............................................................................................................................ 49
8.2.2 XTAL_IN Impedance in External Mode ...................................................................................... 49
8.2.3 Clock Timing Accuracy............................................................................................................... 49
8.2.4 Clock Start-Up Delay.................................................................................................................. 50
8.2.5 Input Frequencies and PS Key Settings..................................................................................... 51
Crystal Oscillator (XTAL_IN, XTAL_OUT) ....................................................................................... 52
8.3.1 XTAL Mode ................................................................................................................................ 52
8.3.2 Load Capacitance ...................................................................................................................... 53
8.3.3 Frequency Trim .......................................................................................................................... 53
8.3.4 Transconductance Driver Model ................................................................................................ 54
8.3.5 Negative Resistance Model ....................................................................................................... 54
8.3.6 Crystal PS Key Settings ............................................................................................................. 54
8.3.7 Crystal Oscillator Characteristics ............................................................................................... 55
Off-Chip Program Memory............................................................................................................... 58
8.4.1 Minimum Flash Specification ..................................................................................................... 59
8.4.2 Common Flash Interface............................................................................................................ 60
8.4.3 Memory Timing .......................................................................................................................... 61
UART Interface ................................................................................................................................ 63
8.5.1 UART Bypass............................................................................................................................. 65
8.5.2 UART Configuration While RESET is Active.............................................................................. 65
8.5.3 UART Bypass Mode................................................................................................................... 65
8.5.4 Current Consumption in UART Bypass Mode ............................................................................ 65
USB Interface .................................................................................................................................. 66
8.6.1 USB Data Connections .............................................................................................................. 66
8.6.2 USB Pull-Up Resistor................................................................................................................. 66
8.6.3 Power Supply ............................................................................................................................. 66
8.6.4 Self-Powered Mode.................................................................................................................... 67
8.6.5 Bus-Powered Mode.................................................................................................................... 68
8.6.6 Suspend Current ........................................................................................................................ 69
8.6.7 Detach and Wake_Up Signalling................................................................................................ 69
8.6.8 USB Driver ................................................................................................................................. 69
8.6.9 USB 1.1 Compliance.................................................................................................................. 70
8.6.10 USB 2.0 Compatibility ................................................................................................................ 70
Serial Peripheral Interface ............................................................................................................... 70
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7.1
Contents
8.11
TCXO Enable OR Function ............................................................................................................. 97
8.12
9
RESET and RESETB ...................................................................................................................... 97
8.12.1 Pin States on Reset ................................................................................................................... 98
8.12.2 Status after Reset ...................................................................................................................... 98
8.13
Power Supply................................................................................................................................... 99
8.13.1 Voltage Regulator ...................................................................................................................... 99
8.13.2 Sequencing ................................................................................................................................ 99
8.13.3 Sensitivity to Disturbances ......................................................................................................... 99
Typical Audio CODEC Performance......................................................................................................... 100
9.1
Output............................................................................................................................................ 100
10 Application Schematic............................................................................................................................... 108
11 Package Dimensions ................................................................................................................................. 109
11.1
7 x 7 VFBGA 120-Ball Package .................................................................................................... 109
12 Solder Profiles............................................................................................................................................ 110
12.1
Solder Re-flow Profile for Devices with Lead-Free Solder Balls .................................................... 110
13 Ordering Information ................................................................................................................................. 111
13.1
BlueCore3-Multimedia External ..................................................................................................... 111
14 Contact Information ................................................................................................................................... 112
15 Document References ............................................................................................................................... 113
Acronyms and Definitions................................................................................................................................ 114
Record of Changes ........................................................................................................................................... 116
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8.7.1 Instruction Cycle......................................................................................................................... 70
8.7.2 Writing to BlueCore3-Multimedia External ................................................................................. 71
8.7.3 Reading from BlueCore 3-Multimedia External .......................................................................... 71
8.7.4 Multi Slave Operation................................................................................................................. 71
8.8
Stereo Audio Interface ..................................................................................................................... 72
8.8.1 Stereo CODEC Setup ................................................................................................................ 73
8.8.2 ADC ........................................................................................................................................... 73
8.8.3 ADC Sample Rate Selection and Warping................................................................................. 73
8.8.4 ADC Gain ................................................................................................................................... 73
8.8.5 DAC ........................................................................................................................................... 75
8.8.6 DAC Sample Rate Selection and Warping................................................................................. 75
8.8.7 DAC Gain ................................................................................................................................... 75
8.8.8 Mono Operation ......................................................................................................................... 76
8.8.9 PCM CODEC Interface .............................................................................................................. 77
8.8.10 PCM Interface Master/Slave ...................................................................................................... 78
8.8.11 Long Frame Sync....................................................................................................................... 79
8.8.12 Short Frame Sync ...................................................................................................................... 79
8.8.13 Multi Slot Operation.................................................................................................................... 80
8.8.14 GCI Interface.............................................................................................................................. 80
8.8.15 Slots and Sample Formats ......................................................................................................... 81
8.8.16 Additional Features .................................................................................................................... 81
8.8.17 PCM Timing Information ............................................................................................................ 82
8.8.18 PCM Slave Timing ..................................................................................................................... 84
8.8.19 PCM_CLK and PCM_SYNC Generation.................................................................................... 86
8.8.20 PCM Configuration..................................................................................................................... 87
8.8.21 Digital Audio Bus........................................................................................................................ 89
8.8.22 IEC 60958 Interface ................................................................................................................... 92
8.8.23 Audio Input Stage....................................................................................................................... 93
8.8.24 Microphone Input ....................................................................................................................... 94
8.8.25 Line Input ................................................................................................................................... 94
8.8.26 Output Stage .............................................................................................................................. 95
8.9
I/O Parallel Ports.............................................................................................................................. 95
8.9.1 PIO Defaults for BTv1.2 HCI Level Bluetooth Stack................................................................... 96
8.10
I2C Interface..................................................................................................................................... 96
Contents
List of Figures
Figure 2.1: BlueCore3-Multimedia External Device Pinout ..................................................................................... 9
Figure 5.1: BlueCore3-Multimedia External Device Diagram ................................................................................ 29
Figure 6.1: Kalimba DSP Interface to Internal Functions ...................................................................................... 33
Figure 7.1: BlueCore HCI Stack ............................................................................................................................ 35
Figure 7.2: Kalimba DSP Stack............................................................................................................................. 38
Figure 8.1: Circuit TX/RX_A and TX/RX_B ........................................................................................................... 40
Figure 8.2: TX_A Output at Power Setting 35 ....................................................................................................... 41
Figure 8.3: TX_A Output at Power Setting 50 ....................................................................................................... 41
Figure 8.4: TX_A Output at Power Setting 63 ....................................................................................................... 42
Figure 8.5: TX_B Output at Power Setting 35 ....................................................................................................... 42
Figure 8.6: TX_B Output at Power Setting 50 ....................................................................................................... 43
Figure 8.7: TX_B Output at Power Setting 63 ....................................................................................................... 43
Figure 8.8: RX_A Balanced Receive Input Impedance ......................................................................................... 44
Figure 8.9: RX_B Balanced Receive Input Impedance ......................................................................................... 44
Figure 8.10: First Stage of ADC Analogue Amplifier Block Diagram ..................................................................... 74
Figure 8.11: BlueCore3-Multimedia External as PCM Interface Master ................................................................ 78
Figure 8.12: BlueCore3-Multimedia External as PCM Interface Slave .................................................................. 78
Figure 8.13: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................... 79
Figure 8.14: Short Frame Sync (Shown with 16-bit Sample) ................................................................................ 79
Figure 8.15: Multi Slot Operation with Two Slots and 8-bit Companded Samples ................................................ 80
Figure 8.16: GCI Interface..................................................................................................................................... 80
Figure 8.17: 16-Bit Slot Length and Sample Formats ........................................................................................... 81
Figure 8.18: PCM Master Timing Long Frame Sync ............................................................................................. 83
Figure 8.19: PCM Master Timing Short Frame Sync............................................................................................. 83
Figure 8.20: PCM Slave Timing Long Frame Sync ............................................................................................... 85
Figure 8.21: PCM Slave Timing Short Frame Sync .............................................................................................. 85
Figure 8.22: Digital Audio Interface Modes ........................................................................................................... 89
Figure 8.23: Digital Audio Interface Slave Timing ................................................................................................. 90
Figure 8.24: Digital Audio Interface Master Timing ............................................................................................... 91
Figure 8.25: Example Circuit for SPDIF Interface with Coaxial Output ................................................................. 92
Figure 8.26: Example Circuit for SPDIF Interface with Coaxial Input .................................................................... 92
Figure 8.27: Example Circuit for SPDIF Interface with Optical Output .................................................................. 93
Figure 8.28: Example Circuit for SPDIF Interface with Optical Input ..................................................................... 93
Figure 8.29: Microphone Biasing (Left Channel Shown) ....................................................................................... 94
Figure 8.30: Differential Input (Left Channel Shown) ............................................................................................ 94
Figure 8.31: Single Ended Input (Left Channel Shown) ........................................................................................ 94
Figure 8.32: Speaker Output (Left Channel Shown) ............................................................................................. 95
Figure 8.33: Example EEPROM Connection ........................................................................................................ 96
Figure 8.34: Example TXCO Enable OR Function ................................................................................................ 97
Figure 10.10.1: Relative Level of 2nd Harmonic to Fundamental, PL = 600Ω....................................................... 100
Figure 10.10.2: Relative Level of 3rd Harmonic to Fundamental, PL = 600Ω ...................................................... 101
Figure 10.10.3: Relative Level of 2nd Harmonic to Fundamental, PL = 32Ω......................................................... 102
Figure 10.10.4: Relative Level of 3rd Harmonic to Fundamental, PL = 32Ω ......................................................... 103
Figure 10.10.5: Relative Level of 2nd Harmonic to Fundamental, PL = 22Ω......................................................... 104
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Figure 6.2: Audio Interface .................................................................................................................................... 34
Contents
Figure 10.10.6: Relative Level of 3rd Harmonic to Fundamental, PL = 22Ω ......................................................... 105
Figure 10.10.7: Noise Floor................................................................................................................................. 106
Figure 10.10.8: THD+N ....................................................................................................................................... 107
Figure 11.11.1: Application Circuit for Radio Characteristics Specification with 7 x 7 VFBGA Package ............. 108
Figure 12.12.1: BlueCore3-Multimedia External 120-Ball VFBGA Package Dimensions.................................... 109
List of Tables
Table 6.1: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface .................................... 34
Table 8.1: Transmit S Parameters ........................................................................................................................ 45
Table 8.2: Balanced Receiver S Parameters ........................................................................................................ 46
Table 8.3: DAC Digital Gain Rate Selection.......................................................................................................... 75
Table 8.4: DAC Analogue Gain Settings ............................................................................................................... 76
Table 8.5: PCM Master Timing.............................................................................................................................. 82
Table 8.6: PCM Slave Timing................................................................................................................................ 84
Table 8.7: PSKEY_PCM_CONFIG32 Description................................................................................................. 87
Table 8.8: PSKEY_PCM_LOW_JITTER_CONFIG Description ............................................................................ 88
Table 8.9: Digital Audio Interface Slave Timing .................................................................................................... 90
Table 8.10: Digital Audio Interface Master Timing................................................................................................. 91
Table 8.11: PIO Defaults....................................................................................................................................... 96
Table 8.12: Pin States of BlueCore3-Multimedia External on Reset ..................................................................... 98
List of Equations
Equation 8.1: Output Voltage with Load Current ≤ 10mA...................................................................................... 47
Equation 8.2: Output Voltage with No Load Current ............................................................................................. 47
Equation 8.3: Load Capacitance ........................................................................................................................... 53
Equation 8.4: Trim Capacitance ............................................................................................................................ 53
Equation 8.5: Frequency Trim ............................................................................................................................... 53
Equation 8.6: Pullability......................................................................................................................................... 53
Equation 8.7: Transconductance Required for Oscillation .................................................................................... 54
Equation 8.8: Equivalent Negative Resistance ..................................................................................................... 54
Equation 8.9: Baud Rate ....................................................................................................................................... 64
Equation 8.10: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock .......................... 86
Equation 8.11: PCM_SYNC Frequency Relative to PCM_CLK ............................................................................ 86
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Figure 13.13.1: Typical Lead-Free Re-flow Solder Profile................................................................................... 110
Status Information
Status Information
The status of this Data Sheet is Production Information.
CSR Product Data Sheets progress according to the following format:
Information for designers concerning CSR product in development. All values specified are the target values of
the design. Minimum and maximum values specified are only given as guidance to the final specification limits
and must not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pre-Production Information
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not
be considered as the final values.
All electrical specifications may be changed by CSR without notice.
Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
Life Support Policy and Use in Safety-Critical Applications
CSR’s products are not authorised for use in life-support or safety-critical applications. Use in such applications is
done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.
RoHS Compliance
BlueCore3-Multimedia External devices meet the requirements of Directive 2002/95/EC of the European
Parliament and of the Council on the Restriction of Hazardous Substance (RoHS).
Trademarks, Patents and Licenses
BlueCore™, BlueLab™, Casira™, CompactSira™ and MicroSira™ are trademarks of CSR.
Bluetooth® and the Bluetooth logos are trademarks owned by Bluetooth SIG Inc, USA and are licensed to CSR.
Windows®, Windows 98™, Windows 2000™, Windows XP™ and Windows NT™ are registered trademarks of
the Microsoft Corporation.
I2C™ and I2S are registered trademarks of the Philips Corporation and SPDIF is the registered trademark of the
Sony Corporation and Philips Corporation.
All other product, service and company names are trademarks, registered trademarks or service marks of their
respective owners.
The publication of this information does not imply that any license is granted under any patent or other rights
owned by CSR Ltd.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.
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Advance Information
Key Features
1
Key Features
Radio
Kalimba DSP
! Common TX/RX terminal simplifies external
! DSP co-processor, 32MIPs, 24-bit fixed point DSP
! BIST minimises production test time. No external
trimming is required in production
core
! Single cycle MAC; 24 x 24-bit multiply and 56-bit
accumulator
! Full RF reference designs available
! 32-bit instruction word, dual 24-bit data memory
! Bluetooth v1.2 Specification compliant
! 4Kword program memory, 2 x 8Kword data
memory
Transmitter
! +6dBm RF transmit power with level control from
on-chip 6-bit DAC over a dynamic range >30dB
! Class 2 and Class 3 support without the need for
an external power amplifier or TX/RX switch
! Class1 support using external power amplifier, with
RF power controlled by an internal 8-bit DAC
! Flexible interfaces to BlueCore3 subsystem
Baseband and Software
! External 8Mbit Flash for complete system solution
! Internal 32Kbyte RAM, allows full speed data
transfer, mixed voice and data, and full piconet
operation
! Logic for forward error correction, header error
Receiver
! Integrated channel filters
! Digital demodulator for improved sensitivity and
co-channel rejection
control, access code correlation, CRC,
demodulation, encryption bit stream generation,
whitening and transmit pulse shaping
! Transcoders for A-law, µ-law and linear voice from
! Real time digitised RSSI available on HCI interface
host and A-law, µ-law and CVSD voice over air
! Fast AGC for enhanced dynamic range
Physical Interfaces
Synthesiser
! Synchronous serial interface up to 4Mbaud for
! Fully integrated synthesiser requires no external
VCO, varactor diode, resonator or loop filter
! Compatible with crystals between 8 and 32MHz (in
multiples of 250kHz) or an external clock
! Accepts 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44,
19.68, 19.8 and 38.4MHz TCXO frequencies for
GSM and CDMA devices with sinusoidal or logic
level signals
system debugging
! UART interface with programmable baud rate up to
1.5Mbaud with an optional bypass mode
! Full speed USB v1.1 interface supports OHCI and
UHCI host interfaces
! Bi-directional serial programmable audio interface
supporting PCM, I2S and SPDIF formats
! Optional I2C™ compatible interface
Auxiliary Features
Stereo Audio CODEC
! Crystal oscillator with built-in digital trimming
! 16-bit resolution, standard sample rates of 8kHz,
! Power management includes digital shut down and
wake up commands with an integrated low power
oscillator for ultra-low power Park/Sniff/Hold mode
! ‘Clock request’ output to control an external clock
! On-chip linear regulator; 1.8V output from a
2.2-4.2V input
11.025kHz, 16kHz, 22.05kHz, 32kHz, 44.1kHz and
48kHz (DAC only)
! Dual ADC and DAC for stereo audio
! Integrated amplifiers for driving microphone and
speakers with minimum external components
! Compatible with Kalimba DSP
! Power-on-reset cell detects low supply voltage
! Arbitrary power supply sequencing permitted
! 8-bit ADC and DAC available to applications
Bluetooth Stack
CSR’s Bluetooth Protocol Stack runs on the on-chip
MCU in a variety of configurations:
! Standard HCI (UART or USB)
Package Options
! 120-ball VFBGA, 7 x 7 x 1mm, 0.5mm pitch
! Fully embedded RFCOMM
! Customised builds with embedded application code
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matching; eliminates external antenna switch
7 x 7 VFBGA Package Information
2
7 x 7 VFBGA Package Information
2.1
BlueCore3-Multimedia External Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
C
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
D
D1
D2
D3
D11
D12
D13
E
E1
E2
E3
E11
E12
E13
F
F1
F2
F3
F11
F12
F13
G
G1
G2
G3
G11
G12
G13
H
H1
H2
H3
H11
H12
H13
J
J1
J2
J3
J11
J12
J13
K
K1
K2
K3
K11
K12
K13
L
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
M
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
Figure 2.1: BlueCore3-Multimedia External Device Pinout
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Orientation from top of device
7 x 7 VFBGA Package Information
2.2
Device Terminal Functions
Ball
Pad Type
Description
AUX_DAC
D2
Analogue
Voltage DAC output
PIO[0]/RXEN
C1
Bi-directional with
programmable strength
internal pull-up/down
Control output for external Tx/Rx switch (if
fitted)
PIO[1]/TXEN
B1
Bi-directional with
programmable strength
internal pull-up/down
Control output for external PA (If fitted)
RF_IN
E1
Analogue
Single ended receiver input
TX_A
G1
Analogue
Transmitter output/switched receiver input
TX_B
F1
Analogue
Complement of TX_A
Synthesiser and
Oscillator
Ball
Pad Type
Description
XTAL_IN
N1
Analogue
For crystal or external clock input
XTAL_OUT
N2
Analogue
Drive for crystal
USB and UART
Ball
Pad Type
Description
UART_TX
J12
CMOS output, tri-state, with
weak internal pull-up
UART data output
UART_RX
K11
CMOS input with weak
internal pull-down
UART data input
UART_RTS
L12
CMOS output, tri-state, with
weak internal pull-up
UART request to send active low
UART_CTS
K12
CMOS input with weak
internal pull-down
UART clear to send active low
USB_DP
L13
Bi-directional
USB data plus with selectable internal
1.5kΩ pull-up resistor
USB_DN
K13
Bi-directional
USB data minus
Ball
Pad Type
Description
PCM_OUT
G13
CMOS output, tri-state, with
weak internal pull-down
Synchronous data output
PCM_IN
J11
CMOS input, with weak
internal pull-down
Synchronous data input
PCM_SYNC
H11
Bi-directional with weak
internal pull-down
Synchronous data sync
PCM_CLK
H13
Bi-directional with weak
internal pull-down
Synchronous data clock
PCM Interface
(1)
Note:
(1)
Pin names may be redefined dependent on chosen interface; see Table 6.1.
BC352239A-ds-001Pc
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Radio
7 x 7 VFBGA Package Information
Ball
Pad Type
Description
PIO[11]
A3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[10]
B3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[9]
C3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[8]
D3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
G11
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line or
programmable frequency clock output
F13
Bi-directional with
programmable strength
internal pull-up/down
PIO line or clock request output to enable
external clock for external clock line
F11
Bi-directional with
programmable strength
internal pull-up/down
PIO line or chip detaches from USB when
this input is high
F12
Bi-directional with
programmable strength
internal pull-up/down
PIO or USB on (input senses when VBUS is
high, wakes BlueCore3-Multimedia
External)
B2
Bi-directional with
programmable strength
internal pull-up/down
PIO or output goes high to wake up PC
when in USB mode or clock request input
from host controller
PIO[2]/CLK_REQ
C2
Bi-directional with
programmable strength
internal pull-up/down
PIO or external clock request
AIO[0]
N3
Bi-directional
Programmable input/output line
AIO[1]
L4
Bi-directional
Programmable input/output line
AIO[2]
M4
Bi-directional
Programmable input/output line
AIO[3]
N4
Bi-directional
Programmable input/output line
Test and Debug
Ball
Pad Type
Description
RESET
B12
CMOS input with weak
internal pull-down
Reset if high. Input debounced so must be
high for >5ms to cause a reset
RESETB
E12
CMOS input with weak
internal pull-up
Reset if low. Input debounced so must be
low for >5ms to cause a reset
SPI_CSB
C11
CMOS input with weak
internal pull-up
Chip select for Synchronous Serial Interface
active low
SPI_CLK
C13
CMOS input with weak
internal pull-down
Serial Peripheral Interface clock
SPI_MOSI
D12
CMOS input with weak
internal pull-down
Serial Peripheral Interface data input
SPI_MISO
B13
CMOS output, tri-state, with
weak internal pull-down
Serial Peripheral Interface data output
TEST_EN
B11
CMOS input with strong
internal pull-down
For test purposes only (leave unconnected)
PIO[7]/UART_RX(1)/
CLK_OUT
PIO[6]/CLK_REQ/
UART_CTS
(1)
PIO[5]/USB_DETACH/
UART_RTS
(1)
PIO[4]/USB_ON/
(1)
UART_TX
PIO[3]/USB_WAKE_UP/
HOST_CLK_REQ
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PIO Port
7 x 7 VFBGA Package Information
CODEC
Ball
Pad Type
Description
AUDIO_IN_P_RIGHT
L3
Analogue
Microphone input positive (right side)
AUDIO_IN_N_RIGHT
M3
Analogue
Microphone input negative (right side)
AUDIO_IN_P_LEFT
J3
Analogue
Microphone input positive (left side)
K3
Analogue
Microphone input negative (left side)
AUDIO_OUT_N_RIGHT
L2
Analogue
Speaker output negative (right side)
AUDIO_OUT_P_RIGHT
M2
Analogue
Speaker output positive (right side)
AUDIO_OUT_N_LEFT
L1
Analogue
Speaker output negative (left side)
AUDIO_OUT_P_LEFT
M1
Analogue
Speaker output positive (left side)
External Memory
Address Interface
Ball
Pad Type
Description
A[18]
N9
CMOS output, tri-state
Address line
A[17]
M8
CMOS output, tri-state
Address line
A[16]
A11
CMOS output, tri-state
Address line
A[15]
M12
CMOS output, tri-state
Address line
A[14]
N12
CMOS output, tri-state
Address line
A[13]
L11
CMOS output, tri-state
Address line
A[12]
M11
CMOS output, tri-state
Address line
A[11]
N11
CMOS output, tri-state
Address line
A[10]
L10
CMOS output, tri-state
Address line
A[9]
M10
CMOS output, tri-state
Address line
A[8]
N10
CMOS output, tri-state
Address line
A[7]
N8
CMOS output, tri-state
Address line
A[6]
L7
CMOS output, tri-state
Address line
A[5]
M7
CMOS output, tri-state
Address line
A[4]
M6
CMOS output, tri-state
Address line
A[3]
L5
CMOS output, tri-state
Address line
A[2]
M5
CMOS output, tri-state
Address line
A[1]
N5
CMOS output, tri-state
Address line
A[0]
C4
CMOS output, tri-state
Address line
BC352239A-ds-001Pc
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AUDIO_IN_N_LEFT
7 x 7 VFBGA Package Information
Ball
Pad Type
Description
D[15]
A10
Bi-directional with weak
internal pull-down
Data line
D[14]
C10
Bi-directional with weak
internal pull-down
Data line
D[13]
B9
Bi-directional with weak
internal pull-down
Data line
D[12]
A8
Bi-directional with weak
internal pull-down
Data line
D[11]
C8
Bi-directional with weak
internal pull-down
Data line
D[10]
B7
Bi-directional with weak
internal pull-down
Data line
D[9]
A6
Bi-directional with weak
internal pull-down
Data line
D[8]
B5
Bi-directional with weak
internal pull-down
Data line
D[7]
B10
Bi-directional with weak
internal pull-down
Data line
D[6]
A9
Bi-directional with weak
internal pull-down
Data line
D[5]
C9
Bi-directional with weak
internal pull-down
Data line
D[4]
B8
Bi-directional with weak
internal pull-down
Data line
D[3]
A7
Bi-directional with weak
internal pull-down
Data line
D[2]
B6
Bi-directional with weak
internal pull-down
Data line
D[1]
A5
Bi-directional with weak
internal pull-down
Data line
D[0]
C5
Bi-directional with weak
internal pull-down
Data line
External Memory
Interface
Ball
Pad Type
Description
REB
A4
CMOS output, tri-state with
internal weak pull-up
Read enable for external memory (active
low)
WEB
L9
CMOS output, tri-state with
internal weak pull-up
Write enable for external memory (active
low)
CSB
B4
CMOS output, tri-state with
internal weak pull-up
Chip select for external memory (active low)
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External Memory Data
Interface
7 x 7 VFBGA Package Information
Ball
Pad Type
Description
VREG_IN
N7
VDD/Regulator input
Linear regulator input
VDD_RADIO
H2
D1
VDD/Regulator sense
Positive supply for RF circuitry
VDD_LO
J2
VDD
Positive supply for local oscillator circuitry
VDD_CORE
C7
E13
L8
VDD
Positive supply for internal digital circuitry
VDD_ANA
K2
VDD/Regulator output
Positive supply for analogue circuitry and
1.8V regulated output. For optimum
performance, regulator decoupling and
loads should be connected to this ball
VDD_ANA
N6
VDD/Regulator output
Positive supply for analogue circuitry and
1.8V regulated output
VDD_MEM
A13
N13
VDD
Positive supply for external memory, AIO
and extended PIO ports
VDD_PADS
D11
VDD
Positive supply for all other digital
Input/Output ports (3)
VDD_PIO
A2
VDD
Positive supply for PIO and AUX DAC(2)
VDD_USB
M13
VDD
Positive supply for UART/USB ports
VSS_RADIO
E2 F2
E3
H1
G2
G3
VSS
Ground connections for RF circuitry
VSS_LO
J1
VSS
Ground connection for local oscillator
VSS_CORE
C6
E11
M9
VSS
Ground connections for internal digital
circuitry
VSS_ANA
H3
K1 L6
VSS
Ground connections for analogue circuitry
VSS_PADS
A1
A12
J13
VSS
Ground connections for digital Input/Output
ports
VSS
F3
VSS
Ground connection for internal package
shield
Notes:
(1)
Transparent UART port maps directly to main UART port.
(2)
Positive supply for PIO[3:0] and PIO[11:8].
(3)
Positive supply for SPI/PCM ports and PIO[7:4].
Unconnected
Terminals
BC352239A-ds-001Pc
Ball
Description
C12, D13, G12, H12
Leave unconnected
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Power Supplies and
Control
Electrical Characteristics
3
Electrical Characteristics
Absolute Maximum Ratings
Minimum
Maximum
Storage Temperature
-40°C
+150°C
Supply Voltage: VDD_RADIO, VDD_LO, VDD_ANA
and VDD_CORE
-0.4V
2.2V
Supply Voltage: VDD_MEM, VDD_PADS, VDD_PIO
and VDD_USB
-0.4V
3.7V
Supply Voltage: VREG_IN
-0.4V
5.6V
VSS-0.4V
VDD+0.4V
Minimum
Maximum
-40°C
+105°C
-25°C
+85°C
Supply Voltage: VDD_RADIO, VDD_LO, VDD_ANA
and VDD_CORE
1.7V
1.9V
Supply Voltage: VDD_MEM, VDD_PADS, VDD_PIO
and VDD_USB
1.7V
3.6V
Supply Voltage: VREG_IN
2.2V
4.2V(2)
Other Terminal Voltages
Recommended Operating Conditions
Operating Condition
Operating Temperature Range
Guaranteed RF performance range
(1)
Notes:
(1)
Typical figures are given for RF performance between -40°C and +105°C.
(2)
The device will operate without damage with VREG_IN as high as 5.6V, however the RF performance is
not guaranteed above 4.2V.
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Rating
Electrical Characteristics
Input/Output Terminal Characteristics
Linear Regulator
Minimum
Typical
Maximum
Unit
Output Voltage (Iload = 70 mA)
1.70
1.78
1.85
V
Temperature Coefficient
Normal Operation
-
+250
ppm/°C
-
-
1
mV rms
Load Regulation (Iload < 100 mA)
-
-
50
mV/A
-
-
50
µs
140
-
-
mA
(1)(3)
Settling Time
Maximum Output Current
Minimum Load Current
5
-
-
µA
Input Voltage
-
-
4.2(6)
V
Dropout Voltage (Iload = 70 mA)
-
-
350
mV
25
35
50
µA
4
7
10
µA
1.5
2.5
3.5
µA
Quiescent Current (excluding Ioad, Iload < 1mA)
Low Power Mode(4)
Quiescent Current (excluding Ioad, Iload < 100µA)
(5)
Disabled Mode
Quiescent Current
Notes:
For optimum performance the VDD_ANA ball adjacent to VREG_IN should be used for regulator ouput.
(1)
Regulator output connected to 47nF pure and 4.7µF 2.2Ω ESR capacitors.
(2)
Frequency range 100Hz to 100kHz.
(3)
1mA to 70mA pulsed load.
(4)
Low power mode is entered and exited automatically when the chip enters/leaves Deep Sleep mode.
(5)
Regulator is disabled when VREG_IN is either open circuit or driven to the same voltage as VDD_ANA.
(6)
Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to
damage the rest of BlueCore3, but output regulation and other specifications are no longer guaranteed
at input voltages in excess of 4.2V.
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-250
Output Noise(1)(2)
Electrical Characteristics
Input/Output Terminal Characteristics (Continued)
Digital Terminals
Minimum
Typical
Maximum
Unit
Input Voltage Levels
2.7V ≤ VDD ≤ 3.0V
-0.4
-
+0.8
V
1.7V ≤ VDD ≤ 1.9V
-0.4
-
+0.4
V
0.7VDD
-
VDD+0.4
V
-
-
0.2
V
-
-
0.4
V
VDD-0.2
-
-
V
VDD-0.4
-
-
V
Strong pull-up
-100
-40
-10
µA
Strong pull-down
+10
+40
+100
µA
Weak pull-up
-5.0
-1.0
-0.2
µA
Weak pull-down
+0.2
+1.0
+5.0
µA
I/O pad leakage current
-1
0
+1
µA
CI Input Capacitance
1.0
-
5.0
pF
VIH input logic level high
Output Voltage Levels
VOL output logic level low,
(lo = 4.0mA), 2.7V ≤ VDD ≤ 3.0V
VOL output logic level low,
(lo = 4.0mA), 1.7V ≤ VDD ≤ 1.9V
VOH output logic level high,
(lo = -4.0mA), 2.7V ≤ VDD ≤ 3.0V
VOH output logic level high,
(lo = -4.0mA), 1.7V ≤ VDD ≤ 1.9V
Input and Tri-state Current with:
BC352239A-ds-001Pc
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VIL input logic level low
Electrical Characteristics
Input/Output Terminal Characteristics (Continued)
USB Terminals
Minimum
VDD_USB for correct USB operation
Typical
3.1
Maximum
Unit
3.6
V
VIL input logic level low
-
-
0.3VDD_USB
V
VIH input logic level high
0.7VDD_USB
-
-
V
VSS_PADS < VIN < VDD_USB(1)
-1
1
5
µA
CI Input capacitance
2.5
-
10.0
pF
VOL output logic level low
0.0
-
0.2
V
VOH output logic level high
2.8
-
VDD_USB
V
Minimum
Typical
Maximum
Unit
1.40
1.50
1.60
V
Input leakage current
Output Voltage levels
To correctly terminated USB Cable
Input/Output Terminal Characteristics (Continued)
Power-on reset
VDD_CORE falling threshold
VDD_CORE rising threshold
1.50
1.60
1.70
V
Hysteresis
0.05
0.10
0.15
V
Minimum
Typical
Maximum
Unit
Input/Output Terminal Characteristics (Continued)
Crystal Oscillator
(4)
Crystal frequency
8.0
-
32.0
MHz
(5)
5.0
6.2
8.0
pF
-
0.1
-
pF
Transconductance
2.0
-
-
mS
Negative resistance(6)
870
1500
2400
Ω
Digital trim range
(5)
Trim step size
External Clock
Input frequency(7)
7.5
-
40.0
MHz
0.2
-
VDD_ANA
V pk-pk
Allowable jitter
-
-
15
ps rms
XTAL_IN input impedance
-
-
-
kΩ
XTAL_IN input capacitance
-
7
-
pF
(8)
Clock input level
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Input threshold
Electrical Characteristics
Input/Output Terminal Characteristics (Continued)
Auxiliary ADC
Resolution
(LSB size = VDD_ANA/255)
Typical
Maximum
Unit
-
-
8
Bits
0
-
VDD_ANA
V
Accuracy
INL
-1
-
1
LSB
(Guaranteed monotonic)
DNL
0
-
1
LSB
Offset
-1
-
1
LSB
-0.8
-
0.8
%
Input Bandwidth
-
100
-
kHz
Conversion time
-
2.5
-
µs
-
-
700
Samples/s
Gain Error
(2)
Sample rate
Input/Output Terminal Characteristics (Continued)
Auxiliary DAC
Resolution
Average output step size(3)
Minimum
Maximum
Unit
-
-
8
Bits
12.5
14.5
17.0
mV
Output Voltage
Voltage range (IO=0mA)
Typical
monotonic
(3)
VSS_PADS
-
VDD_PIO
V
-10.0
-
+0.1
mA
Minimum output voltage (IO=100mA)
0.0
-
0.2
V
Maximum output voltage (IO=10mA)
VDD_PIO-0.3
-
VDD_PIO
V
Current range
-1
-
+1
µA
-220
-
+120
mV
Integral non-linearity(3)
-2
-
+2
LSB
Settling time (50pF load)
-
-
10
µs
High Impedance leakage current
Offset
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_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
Input voltage range
Minimum
Electrical Characteristics
Input/Output Terminal Characteristics (Continued)
Stereo Audio CODEC
Minimum
Typical
Maximum
Unit
-
4
-
mV rms
Input full scale at minimum gain
-
400
-
mV rms
Gain resolution
-
3
-
dB
Distortion at 1kHz
-
-74
dB
Input referenced rms noise in 15kHz bandwidth
-
8
-
µV rms
3dB Bandwidth
-
17
-
kHz
Input impedance
-
20
-
kΩ
THD+N (microphone input) @ 30mV rms input
-
-66
-
dB
Resolution
-
-
16
bits
Input sample rate
8
-
44.1
kHz
Fsample = 8kHz
-
84
-
dB
Fsample = 11.025kHz
-
83
-
dB
Fsample = 16kHz
-
84
-
dB
Fsample = 22.050kHz
-
83
-
dB
Fsample = 32kHz
-
80
-
dB
Fsample = 44.1kHz
-
74
-
dB
21.5
dB
Input Stage/Microphone Amplifier
Analogue to Digital Converter
Signal / (Noise + Distortion), 0 - Fsample /2, with full
scale 1kHz tone
Digital Gain
-24
Digital to Analogue Converter
Resolution
-
-
16
bits
Output sample rate
8
-
48
kHz
Gain Resolution
-
3
-
dB
Fsample = 8kHz
-
79
-
dB
Fsample = 11.025kHz
-
78
-
dB
Fsample = 16kHz
-
79
-
dB
Fsample = 22.050kHz
-
88
-
dB
Fsample = 32kHz
-
90
-
dB
Fsample = 44.1kHz
-
90
-
dB
Fsample = 48kHz
-
89
-
dB
-24
-
21.5
dB
Signal / (Noise + Distortion), 0 – 20 kHz, with full
scale 1kHz tone
Digital Gain
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_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
Input full scale at maximum gain
Electrical Characteristics
Input/Output Terminal Characteristics (Continued)
Output Stage/Loudspeaker Driver
Output power into 32Ω
Output current drive (at full scale swing)
(9)
(9)
Typical
Maximum
Unit
-
30
-
mW pk
-
2.0
-
V pk-pk
10
20
40
mA
Output full scale current (at reduced swing)
-
75
-
mA
Distortion and noise (relative to full scale), THD
-
-75
-
dBc
16
-
O.C.
Ω
-
-
500
pF
Allowed Load: resistive
Allowed Load: capacitive
Notes:
VDD_CORE, VDD_RADIO, VDD_LO and VDD_ANA are at 1.8V unless shown otherwise.
VDD_PADS, VDD_PIO and VDD_USB are at 3.0V unless shown otherwise.
The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT.
Current drawn into a pin is defined as positive, current supplied out of a pin is defined as negative.
(1)
Internal USB pull-up disabled.
(2)
Access of ADC is through VM function and therefore sample rate given is achieved as part of this
function.
(3)
Specified for an output voltage between 0.2V and VDD_PIO -0.2V.
(4)
Integer multiple of 250kHz.
(5)
The difference between the internal capacitance at minimum and maximum settings of the internal
digital trim.
(6)
XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF.
(7)
Clock input can be any frequency between 8 and 40MHz in steps of 250kHz plus CDMA/3G TCXO
frequencies of 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz.
(8)
Clock input can either be sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or
above VDD_ANA a DC blocking capacitor is required between the signal and XTAL_IN.
(9)
For specified THD. Much greater current can be supplied by the loudspeaker driver with compromised
THD.
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Page 21 of 116
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
Output voltage full scale swing
Minimum
Radio Characteristics
4
Radio Characteristics
Temperature +20°C
4.1.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = +20°C
Maximum RF transmit power(1)(2)(3)
(1)(2)
RF power control range
Min
Typ
Max
Bluetooth
Specification
Unit
-
6.5
-
-6 to +4(4)
dBm
-
35
-
≥16
dB
RF power range control resolution
-
0.5
-
-
dB
20dB bandwidth for modulated carrier
-
800
-
≤1000
kHz
Adjacent channel transmit power F=F0 ± 2MHz(5)
-
-40
-
≤-20
dBm
(5)
Adjacent channel transmit power F=F0 ± 3MHz
-
-45
-
≤-40
dBm
∆f1avg “Maximum Modulation”
-
165
-
140<f1avg<175
kHz
∆f2max “Minimum Modulation”
-
145
-
115
kHz
∆f1avg/∆f2avg
-
0.9
-
≥0.80
-
Initial carrier frequency tolerance
-
10
-
±75
kHz
Drift Rate
-
8
-
≤20
kHz/ 50µs
Drift (single slot packet)
-
9
-
≤25
kHz
Drift (five slot packet)
-
10
-
≤40
kHz
Frequency (GHz)
Min
Typ
Max
Specification
Unit
0.925-0.960
-
-143
-
Integrated in
200kHz bandwidth
dBm/Hz
1.570-1.580
-
-138
-
Integrated in 1MHz
bandwidth
dBm/Hz
1.805-1.880
-
-131
-
Integrated in
200kHz bandwidth
dBm/Hz
1.930-1.990
-
-135
-
Integrated in 30kHz
bandwidth
dBm/Hz
1.930-1.990
-
-135
-
Integrated in
200kHz bandwidth
dBm/Hz
1.930-1.990
-
-137
-
Integrated in
1.2MHz bandwidth
dBm/Hz
2.110-2.170
-
-132
-
Integrated in
1.2MHz bandwidth
dBm/Hz
2.110-2.170
-
-135
-
Integrated in 5MHz
bandwidth
dBm/Hz
Emissions
Emitted power in cellular
bands measured at chip
terminals
Output power ≤4dBm
Notes:
(1)
Results are referenced to the single ended port of the baun.
(2)
Measured according to the Bluetooth v1.2 specification.
(3)
The firmware maintains the transmit power to be within the Bluetooth v1.2 specification limits.
(4)
Class 2 RF transmit power range, Bluetooth v1.2 specification.
(5)
Measured at F0 = 2441MHz.
BC352239A-ds-001Pc
© Cambridge Silicon Radio Limited 2004
Production Information
Page 22 of 116
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
4.1
Radio Characteristics
4.1.2
Receiver
Radio Characteristics
VDD = 1.8V
Temperature = +20°C
Min
Typ
Max
2.402
-
-83
-
Sensitivity at 0.1% BER for all
packet types
Bluetooth
Specification
Unit
dBm
≤-70
2.441
-
-85
-
2.480
-
-83
-
-
3
-
≥-20
dBm
Maximum received signal at 0.1% BER
dBm
dBm
-
8
-
≤11
dB
(1)(2)
-
-4
-
≤0
dB
(1)(2)
-
-3
-
≤0
dB
C/I co-channel
Adjacent channel selectivity C/I F=F0 +1MHz
Adjacent channel selectivity C/I F=F0 -1MHz
(1)(2)
Adjacent channel selectivity C/I F=F0 +2MHz
-
-38
-
≤-30
dB
Adjacent channel selectivity C/I F=F0 -2MHz(1)(2)
-
-21
-
≤-20
dB
Adjacent channel selectivity C/I F≥F0 +3MHz(1)(2)
-
-45
-
≤-40
dB
-
-45
-
≤-40
dB
-
-20
-
≤-9
dB
-
-30
-
≥-39
dBm
-
-140
-
-
dBm/Hz
Frequency
(GHz)
Min
Typ
Max
Modulation
Units
Continuous power in cellular
bands required to block
Bluetooth reception (for
Bluetooth sensitivity of
-67dBm with 0.1% BER)
0.824-0.849(5)
-
2
-
GSM
dBm
0.880-0.915
-
7
-
GSM
dBm
1.710-1.785
-
6
-
GSM
dBm
1.850-1.910
-
5
-
GSM
dBm
Measured at chip terminals
1.920-1.980
-
-6
-
W_CDMA
dBm
Adjacent channel selectivity C/I F≤F0 –5MHz
Adjacent channel selectivity C/I F=FImage
(1)(2)
(1)(2)
Maximum level of intermodulation interferers
(3)
(4)
Spurious output level
Blocking
Continuous power in cellular
bands required to block
Bluetooth reception (for
sensitivity of -80dBm with
0.1% BER) measured at chip
terminals
(5)
0.824-0.849
-
-5
-
GSM
dBm
0.880-0.915
-
-4
-
GSM
dBm
1.710-1.785
-
-3
-
GSM
dBm
1.850-1.910
-
-4
-
GSM
dBm
1.920-1.980
-
-14
-
W_CDMA
dBm
Notes:
Results shown are referenced to the single ended port of the RF balun.
(1)
Up to five exceptions are allowed in v1.2 of the Bluetooth specification. BlueCore3-Multimedia External
is guaranteed to meet the C/I performance as specified by the Bluetooth specification v1.2.
(2)
Measured at F = 2441MHz.
(3)
Measured at f1-f2 = 5MHz. Measurement is performed in accordance with Bluetooth RF test
RCV/CA/05/c. i.e. wanted signal at -64dBm.
(4)
Actual figure is below -140dBm/Hz except for discrete tones at multiples of 800MHz.
(5)
| 3fBlocking – fBluetooth | > 4MHz.
BC352239A-ds-001Pc
© Cambridge Silicon Radio Limited 2004
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Page 23 of 116
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
Frequency
(GHz)
Radio Characteristics
4.2
Temperature -40°C
4.2.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = -40°C
Typ
Max
Bluetooth
Specification
Unit
Maximum RF transmit power(1)
-
8
-
-6 to +4(2)
dBm
RF power control range
-
35
-
≥16
dB
RF power range control resolution
-
0.5
-
-
dB
20dB bandwidth for modulated carrier
-
800
-
≤1000
kHz
Adjacent channel transmit power F=F0 ±2MHz(3) (4)
-
-40
-
≤-20
dBm
(3) (4)
Adjacent channel transmit power F=F0 ±3MHz
-
-45
-
≤-40
dBm
∆f1avg “Maximum Modulation”
-
165
-
140<∆f1avg<175
kHz
∆f2max “Minimum Modulation”
-
145
-
115
kHz
∆f2avg / ∆f1avg
-
0.9
-
≥0.80
-
Initial carrier frequency tolerance
-
10
-
±75
kHz
Drift Rate
-
8
-
≤20
kHz/50µs
Drift (single slot packet)
-
9
-
≤25
kHz
Drift (five slot packet)
-
10
-
≤40
kHz
Notes:
(1)
BlueCore3-Multimedia External firmware maintains the transmit power to be within the Bluetooth
specification v1.2 limits.
(2)
Class 2 RF transmit power range, Bluetooth specification v1.2.
(3)
Measured at F0 = 2441MHz.
(4)
Up to three exceptions are allowed in v1.2 of the Bluetooth specification.
4.2.2
Receiver
Radio Characteristics
VDD = 1.8V
Sensitivity at 0.1% BER for all packet
types
Maximum received signal at 0.1% BER
BC352239A-ds-001Pc
Temperature = -40°C
Frequency
(GHz)
Min
Typ
Max
2.402
-
-85.0
-
2.441
-
-88.0
-
2.480
-
-85
-
-
1
-
© Cambridge Silicon Radio Limited 2004
Production Information
Bluetooth
Specification
Unit
≤-70
dBm
≥-20
dBm
Page 24 of 116
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
Min
Radio Characteristics
4.3
Temperature -25°C
4.3.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = -25°C
Typ
Max
Bluetooth
Specification
Unit
Maximum RF transmit power(1)
-
7
-
-6 to +4(2)
dBm
RF power control range
-
35
-
≥16
dB
RF power range control resolution
-
0.5
-
-
dB
20dB bandwidth for modulated carrier
-
800
-
≤1000
kHz
Adjacent channel transmit power F=F0 ±2MHz(3) (4)
-
-40
-
≤-20
dBm
(3) (4)
Adjacent channel transmit power F=F0 ±3MHz
-
-45
-
≤-40
dBm
∆f1avg “Maximum Modulation”
-
165
-
140<∆f1avg<175
kHz
∆f2max “Minimum Modulation”
-
145
-
115
kHz
∆f2avg / ∆f1avg
-
0.9
-
≥0.80
-
Initial carrier frequency tolerance
-
10
-
±75
kHz
Drift Rate
-
8
-
≤20
kHz/50µs
Drift (single slot packet)
-
9
-
≤25
kHz
Drift (five slot packet)
-
10
-
≤40
kHz
Notes:
(1)
BlueCore-Multimedia External firmware maintains the transmit power to be within the Bluetooth
specification v1.2 limits.
(2)
Class 2 RF transmit power range, Bluetooth specification v1.2.
(3)
Measured at F0 = 2441MHz.
(4)
Up to three exceptions are allowed in v1.2 of the Bluetooth specification.
4.3.2
Receiver
Radio Characteristics
VDD = 1.8V
Sensitivity at 0.1% BER for all packet
types
Maximum received signal at 0.1% BER
BC352239A-ds-001Pc
Temperature = -25°C
Frequency
(GHz)
Min
Typ
Max
2.402
-
-84.5
-
2.441
-
-86.5
-
2.480
-
-84.5
-
-
1
-
© Cambridge Silicon Radio Limited 2004
Production Information
Bluetooth
Specification
Unit
≤-70
dBm
≥-20
dBm
Page 25 of 116
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
Min
Radio Characteristics
4.4
Temperature +85°C
4.4.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = +85°C
Typ
Max
Bluetooth
Specification
Unit
Maximum RF transmit power(1)
-
3
-
-6 to +4(2)
dBm
RF power control range
-
35
-
≥16
dB
RF power range control resolution
-
0.5
-
-
dB
20dB bandwidth for modulated carrier
-
800
-
≤1000
kHz
Adjacent channel transmit power F=F0 ±2MHz(3) (4)
-
-40
-
≤-20
dBm
(3) (4)
Adjacent channel transmit power F=F0 ±3MHz
-
-45
-
≤-40
dBm
∆f1avg “Maximum Modulation”
-
165
-
140<∆f1avg<175
kHz
∆f2max “Minimum Modulation”
-
140
-
115
kHz
∆f2avg / ∆f1avg
-
0.9
-
≥0.80
-
Initial carrier frequency tolerance
-
10
-
±75
kHz
Drift Rate
-
8
-
≤20
kHz/50µs
Drift (single slot packet)
-
9
-
≤25
kHz
Drift (five slot packet)
-
10
-
≤40
kHz
Notes:
(1)
BlueCore3-Multimedia External firmware maintains the transmit power to be within the Bluetooth
specification v1.2 limits.
(2)
Class 2 RF transmit power range, Bluetooth specification v1.2.
(3)
Measured at F0 = 2441MHz.
(4)
Up to three exceptions are allowed in v1.2 of the Bluetooth specification.
4.4.2
Receiver
Radio Characteristics
VDD = 1.8V
Sensitivity at 0.1% BER for all packet
types
Maximum received signal at 0.1% BER
BC352239A-ds-001Pc
Temperature = +85°C
Frequency
(GHz)
Min
Typ
Max
2.402
-
-80
-
2.441
-
-83
-
2.480
-
-80
-
-
5
-
© Cambridge Silicon Radio Limited 2004
Production Information
Bluetooth
Specification
Unit
≤-70
dBm
≥-20
dBm
Page 26 of 116
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
Min
Radio Characteristics
4.5
Temperature +105°C
4.5.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = +105°C
Typ
Max
Bluetooth
Specification
Unit
Maximum RF transmit power(1)
-
1
-
-6 to +4(2)
dBm
RF power control range
-
35
-
≥16
dB
RF power range control resolution
-
0.5
-
-
dB
20dB bandwidth for modulated carrier
-
800
-
≤1000
kHz
Adjacent channel transmit power F=F0 ±2MHz(3) (4)
-
-403
-
≤-20
dBm
(3) (4)
Adjacent channel transmit power F=F0 ±3MHz
-
-45
-
≤-40
dBm
∆f1avg “Maximum Modulation”
-
165
-
140<∆f1avg<175
kHz
∆f2max “Minimum Modulation”
-
135
-
115
kHz
∆f2avg / ∆f1avg
-
0.9
-
≥0.80
-
Initial carrier frequency tolerance
-
10
-
±75
kHz
Drift Rate
-
8
-
≤20
kHz/50µs
Drift (single slot packet)
-
9
-
≤25
kHz
Drift (five slot packet)
-
10
-
≤40
kHz
Notes:
(1)
BlueCore3-Multimedia External firmware maintains the transmit power to be within the Bluetooth
specification v1.2 limits.
(2)
Class 2 RF transmit power range, Bluetooth specification v1.2.
(3)
Measured at F0 = 2441MHz.
(4)
Up to three exceptions are allowed in v1.2 of the Bluetooth specification.
4.5.2
Receiver
Radio Characteristics
VDD = 1.8V
Sensitivity at 0.1% BER for all packet
types
Maximum received signal at 0.1% BER
BC352239A-ds-001Pc
Temperature = +105°C
Frequency
(GHz)
Min
Typ
Max
2.402
-
-80
-
2.441
-
-82
-
2.480
-
-80
-
-
5
-
© Cambridge Silicon Radio Limited 2004
Production Information
Bluetooth
Specification
Unit
≤-70
dBm
≥-20
dBm
Page 27 of 116
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
Min
Radio Characteristics
4.6
Power Consumption
Typical Average Current Consumption
VDD=1.8V
Temperature = +20°C
Output Power = +4dBm
Average
Unit
SCO connection HV3 (30ms interval Sniff Mode) (Slave)
21
mA
SCO connection HV3 (30ms interval Sniff Mode) (Master)
21
mA
SCO connection HV3 (No Sniff Mode) (Slave)
28
mA
SCO connection HV1 (Slave)
42
mA
SCO connection HV1 (Master)
42
mA
ACL data transfer 115.2kbps UART no traffic (Master)
5
mA
ACL data transfer 115.2kbps UART no traffic (Slave)
22
mA
ACL data transfer 720kbps UART (Master or Slave)
45
mA
ACL data transfer 720kbps USB (Master or Slave)
45
mA
ACL connection, Sniff Mode 40ms interval, 38.4kbps UART
3.2
mA
ACL connection, Sniff Mode 1.28s interval, 38.4kbps UART
0.45
mA
Parked Slave, 1.28s beacon interval, 38.4kbps UART
0.55
mA
Standby Mode (Connected to host, no RF activity)
47.0
µA
Reset (RESET high or RESETB low)
15.0
µA
Minimum (NOP)
0.25
mA/MIPS
Maximum (MAC)
0.65
mA/MIPS
0.15
mA/MIPS
0.85
mA
1.4
mA
8
mA
DSP
DSP core (including PM memory access)
DSP memory access (DM1 or DM2)
CODEC
Microphone inputs and ADC / channel
(1)
DAC and loudspeaker driver, no signal / channel
Digital audio processing subsystem
Note:
(1)
Power consumption increase is >5% for maximum signal.
BC352239A-ds-001Pc
© Cambridge Silicon Radio Limited 2004
Production Information
Page 28 of 116
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
Mode
BC352239A-ds-001Pc
PA
RF Synthesiser
+45
Tune
Fref
/ N/N+1
Loop
Filter
RF
Synthesiser
Microcontroller
Digital Signal
Processor
Event
Timer
Interrupt
Controller
RISC
Microcontroller
Programmable I/O
Kalimba DSP
D[15:0]
-45
DAC
RAM
Memory
Management
Unit
Registers
Audio
Port
Interface
RESETB
PIO[1]/TXEN
AUX
DAC
XTAL_IN
RF Transmitter
RF_A
IQ MOD
VDD_MEM1
AUX_DAC
TX_A
RF_B
VDD_ANA2
TX_B
VREG_IN
VDD_RADIO
Physical
Layer
Hardware
Engine
A[18:0]
ADC
CSB
External Memory I nterface
REB
RF Receiver
VDD_ANA1
RSSI
VDD_LO
Dem odulator
Mem ory
Mapped
Control
Status
TEST_EN
IQ DEMOD
VDD_CORE
Burst
Mode
Controller
UART_TX
UART_RX
UART_RTS
UART_CTS
UART
Audio Interface
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
Synchronous
Serial
Interface
PCM_OUT / SPDIF_O UT / SD_O UT
PCM_IN / SPDIF_IN / SD_IN
PCM_SYNC / WS
PCM_CLK / SCK
AUDIO_IN_P_LEFT
AUDIO_IN_N_LEFT
AUDIO_IN_P_RIGHT
AUDIO_IN_N_RIG HT
AUDIO_OUT_P_LEFT
AUDIO_OUT_N_LEFT
AUDIO_OUT_P_RIGHT
AUDIO_OUT_N_RIG HT
PCM &
Digital
Audio
Interface
Stereo
Audio
CODEC
S/PDIF
Interface
USB_DP
USB_DN
USB
Baseband and Logic
VDD_PADS
LNA
Out
VDD_USB
RF_IN
Clock
G ener ation
VREG
VDD_PIO
Sense
5
RESET
WEB
VSS_PADS
PIO [2]/CLK_REQ
PIO [3]/USB_WAKE_UP/HOST_CLK_REQ
PIO [4]/USB_ON/UART_TX
PIO [5]/USB_DETACH/UART_RTS
PIO [6]/CLK_REQ /UART_CTS
© Cambridge Silicon Radio Limited 2004
Production Information
PIO [7]/UART_RX/ CLK_OUT
PIO [8]
PIO [9]
PIO [10]
PIO [11]
AIO[0]
AIO[1]
AIO[2]
AIO[3]
VSS_CORE
VSS_LO
VSS_ANA
VSS_PIO
VSS_RADIO
VSS
XTAL_OUT
Figure 5.1: BlueCore3-Multimedia External Device Diagram
Page 29 of 116
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
PIO[0]/RXEN
In
Device Diagram
Device Diagram
Description of Functional Blocks
6
6.1
Description of Functional Blocks
RF Receiver
6.1.1
Low Noise Amplifier
The Low Noise Amplifier (LNA) can be configured to operate in single-ended or differential mode. Single-ended
mode is used for Class 1 Bluetooth operation; differential mode is used for Class 2 operation.
6.1.2
Analogue to Digital Converter
The Analogue to Digital Converter (ADC) is used to implement fast Automatic Gain Control (AGC). The ADC
samples the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is
changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This
improves the dynamic range of the receiver, improving performance in interference limited environments.
6.2
RF Transmitter
6.2.1
IQ Modulator
The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot, which
results in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral
shaping.
6.2.2
Power Amplifier
The internal Power Amplifier (PA) has a maximum output power of +6dBm allowing BlueCore3-Multimedia
External to be used in Class 2 and Class 3 radios without an external RF PA. Support for transmit power control
allows a simple implementation for Class 1 with an external RF PA.
6.2.3
Auxiliary DAC
An 8-bit voltage Auxiliary DAC is provided for power control of an external PA for Class 1 operation.
6.3
RF Synthesiser
The radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled
Oscillator (VCO) screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is
guaranteed to lock in sufficient time across the guaranteed temperature range to meet the Bluetooth v1.2
specification.
6.4
Clock Input and Generation
The reference clock for the system is generated from a TCXO or crystal input between 8 and 40MHz. All internal
reference clocks are generated using a phase locked loop, which is locked to the external reference frequency.
BC352239A-ds-001Pc
© Cambridge Silicon Radio Limited 2004
Production Information
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_äìÉ`çêÉ»PJjìäíáãÉÇá~ Product
Data Data
SheetSheet
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä
Product
The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be
integrated on to the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input
allows the radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband
Code Division Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a
digital Frequency Shift Keying (FSK) discriminator means that no discriminator tank is needed and its excellent
performance in the presence of noise allows BlueCore3-Multimedia External to exceed the Bluetooth
requirements for co-channel and adjacent channel rejection.
Description of Functional Blocks
6.5
Baseband and Logic
6.5.1
Memory Management Unit
6.5.2
Burst Mode Controller
During radio transmission the Burst Mode Controller (BMC) constructs a packet from header information
previously loaded into memory-mapped registers by the software and payload data/voice taken from the
appropriate ring buffer in the RAM. During radio reception, the BMC stores the packet header in memory-mapped
registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention
required by the processor during transmission and reception.
6.5.3
Physical Layer Hardware Engine DSP
Dedicated logic is used to perform the following:
!
Forward error correction
!
Header error control
!
Cyclic redundancy check
!
Encryption
!
Data whitening
!
Access code correlation
!
Audio transcoding
The following voice data translations and operations are performed by the firmware:
!
A-law/µ-law/linear voice data (from host)
!
A-law/µ-law/Continuously Variable Slope Delta (CVSD) (over the air)
!
Voice interpolation for lost packets
!
Rate mismatches
The hardware supports all optional and mandatory features of Bluetooth v1.2, including AFH and eSCO.
6.5.4
RAM
32Kbytes of on-chip RAM is provided to support the RISC MCU and is shared between the ring buffers used to
hold voice/data for each active connection and the general purpose memory required by the Bluetooth stack.
6.5.5
Kalimba DSP RAM
Further on-chip RAM is provided to support the Kalimba DSP as follows:
!
8K x 24-bit for data memory 1 (DM1)
!
8K x 24-bit for data memory 2 (DM2)
!
4K x 32-bit for program memory (PM)
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The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data
which is in transit between the host, the air or Kalimba DSP. The dynamic allocation of memory ensures efficient
use of the available Random Access Memory (RAM) and is performed by a hardware MMU to minimise the
overheads on the processor during data/voice transfers.
Description of Functional Blocks
6.5.6
External Memory Driver
The External Memory Driver interface can be used to connect to the external Flash memory and also to the
optional external RAM for memory-intensive applications.
6.5.7
USB
6.5.8
Synchronous Serial Interface
This is a synchronous serial port interface (SPI) for interfacing with other digital devices. The SPI port can be
used for system debugging. It can also be used for programming the Flash memory.
6.5.9
UART
This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other
serial devices.
6.6
Microcontroller
The microcontroller (MCU), interrupt controller and event timer run the Bluetooth software stack and control the
radio and host interfaces. A 16-bit reduced instruction set computer (RISC) microcontroller is used for low power
consumption and efficient use of memory.
6.6.1
Programmable I/O
BlueCore3-Multimedia External has a total of 16 (12 digital and 4 analogue) programmable I/O terminals. These
are controlled by firmware running on the device.
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This is a full speed Universal Serial Bus (USB) interface for communicating with other compatible digital devices.
BlueCore3-Multimedia External acts as a USB peripheral, responding to requests from a Master host controller
such as a PC.
Description of Functional Blocks
6.7
Kalimba DSP
The Kalimba DSP is an open platform Kalimba DSP allowing signal processing functions to be performed on
over-air data or CODEC data in order to enhance audio applications. Figure 6.1 shows how the Kalimba DSP
interfaces to other functional blocks within BlueCore3-Multimedia External.
MCU Register Interface (including Debug)
Memory
Management Unit
Of BlueCore3
Subsystem
DSP Program Control
DSP’s MCU and FLASH Window Control
Registers
DSP MMU Port
Programmable Clock < 32MHz
Data Memory
Interface
Address
Generators
Instruction Decode
Program
Flow
DEBUG
Clock Select
PIO
ALU
Internal Control Registers
PIO In/Out
IRQ to BlueCore3 Subsystem
MMU Interface
Interrupt Controller
Timer
DSP RAMs
IRQ from BlueCore3 Subsystem
1µs Timer Clock
MCU Window
Flash Window
DM2
(8K x 24-bit)
DSP Data Memory 2 Interface (DM2)
DM1
(8K x 24-bit)
DSP Data Memory 1 Interface (DM1)
PM
(4K x 32-bit)
DSP Program Memory Interface (PM)
Figure 6.1: Kalimba DSP Interface to Internal Functions
The key features of the DSP include:
!
32MIPS performance, 24-bit fixed point DSP Core
!
Single cycle MAC of 24 x 24-bit multiply and 56-bit accumulate
!
32-bit instruction word
!
Separate program memory and dual data memory, allowing an ALU operation and up to two memory
accesses in a single cycle
!
Zero overhead looping and branching
!
Zero overhead circular buffer indexing
!
Single cycle barrel shifter with up to 56-bit input and 24-bit output
!
Multiple cycle divide (performed in the background)
!
Bit reversed addressing
!
Orthogonal instruction set
!
Low overhead interrupt
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Kalimba DSP Core
Description of Functional Blocks
6.8
Audio Interface
PCM
MMU Voice Port
Voice Port
Digital Audio
PCM Interface
Digital Audio Interface
Memory
Management Unit
MCU Register Interface
Registers
Stereo
Audio
CODEC
Driver
Left DAC
Right DAC
Left ADC
Right ADC
Figure 6.2: Audio Interface
The interface for the digital audio bus shares the same pins as the PCM CODEC Interface described in
Section 8.8.9. This means that each of the audio busses are mutually exclusive in their usage. The pin out for the
PCM interface with alternative pin descriptions can be seen in the device diagram shown in Figure 5.1 and Table
6.1 lists these alternative functions.
PCM Interface
SPDIF Interface
I2S Interface
PCM_OUT
SPDIF_OUT
SD_OUT
PCM_IN
SPDIF_IN
SD_IN
PCM_SYNC
WS
PCM_CLK
SCK
Table 6.1: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface
6.8.1
Audio Input and Output
The audio input circuitry consists of a dual audio input that can be configured to be either single ended or fully
differential and programmed for either microphone or line input. It has a programmable gain stage for
optimisation of different microphones.
The audio output circuitry consists of a dual differential class A-B output stage.
6.8.2
Digital Audio Interface
The digital audio interface supports various digital audio bus standard, which include I2S, and the interfaces
contained within the IEC 60958 specification such as SPDIF and AES3(1).
Note:
(1)
Subject to firmware support; contact CSR for current status.
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The audio interface circuit consists of a stereo audio CODEC, dual audio inputs and outputs, and a PCM, I2S or
SPDIF configurable interface. Figure 6.2 outlines the functional blocks of the interface. The CODEC supports
stereo playback and recording of audio signals at multiple sample rates with a resolution of 16-bit. The ADC and
the DAC of the CODEC each contain two independent channels. Any ADC or DAC channel can be run at its own
independent sample rate.
CSR Bluetooth Software Stacks
7
CSR Bluetooth Software Stacks
BlueCore3-Multimedia External is supplied with stack firmware which is compliant with the Bluetooth v1.2
specification and runs on the internal RISC microcontroller.
BlueCore HCI Stack
External FLASH
7.1
HCI
LM
LC
32KB RAM
Baseband
MCU
USB
Host
Host I/O
Radio
UART
PCM / SPDIF / I2S
Digital Audio
2
Microphone or Speaker
Analogue Audio
Figure 7.1: BlueCore HCI Stack
In the implementation shown in Figure 7.1 the internal processor runs the Bluetooth stack up to the Host
Controller Interface (HCI). The Host processor must provide all upper layers, including the application.
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The BlueCore3-Multimedia External software architecture allows Bluetooth processing and the application
program to be shared in different ways between the internal RISC microcontroller and an external host processor
(if any). The upper layers of the Bluetooth stack (above HCI) can be run either on-chip or on the host processor.
CSR Bluetooth Software Stacks
7.1.1
Key Features of the HCI Stack - Standard Bluetooth Functionality
New Bluetooth v1.2 Mandatory Functionality:
Adaptive Frequency Hopping (AFH), including classifier
!
Faster connection
!
LMP improvements
!
Parameter ranges
Optional v1.2 functionality supported:
!
Extended SCO (eSCO), eV3 +CRC, eV4, eV5
!
Scatter mode
!
SCO handle
!
Synchronisation
The firmware has been written against the Bluetooth Core Specification v1.2.
!
Bluetooth components:
!
Baseband (including LC)
!
LM
!
HCI
!
Standard USB v1.1 and UART HCI Transport Layers
!
All standard radio packet types
!
Full Bluetooth data rate, up to 723.2kbps asymmetric(1)
!
Operation with up to 7 active slaves(1)
!
Operation as slave to one master while master of several slaves (Scatternet “2.0”)
!
Page and Inquiry scanning while slave and master (Scatternet “2.5”)
!
Maximum number of simultaneous active ACL connections: 7(2)
!
Maximum number of simultaneous active SCO connections: 3(2)
!
Operation with up to 3 SCO links, routed to one or more slaves
!
All standard SCO voice coding, plus “transparent SCO”
!
Standard operating modes: page, inquiry, page-scan and inquiry-scan
!
All standard pairing, authentication, link key and encryption operations
!
Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including “Forced Hold”
!
Dynamic control of peers’ transmit power via LMP
!
Master/Slave switch
!
Broadcast
!
Channel quality driven data rate
!
All standard Bluetooth Test Modes
!
Standard firmware upgrade via USB (DFU)
The firmware’s supported Bluetooth features are detailed in the standard Protocol Implementation Conformance
Statement (PICS) documents, available from http://www.csr.com.
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!
CSR Bluetooth Software Stacks
Notes:
(1)
Maximum allowed by Bluetooth v1.2 specification.
(2)
BlueCore3-Multimedia External supports all combinations of active ACL and SCO channels for both
Master and Slave operation, as specified by the Bluetooth v1.2 specification.
Key Features of the HCI Stack - Extra Functionality
The firmware extends the standard Bluetooth functionality with the following features:
!
Supports BlueCore Serial Protocol (BCSP) – a proprietary, reliable alternative to the standard Bluetooth
UART Host Transport
!
Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set
(called BCCMD – “BlueCore Command”), provides:
!
Access to the chip’s general-purpose PIO port
!
The negotiated effective encryption key length on established Bluetooth links
!
Access to the firmware’s random number generator
!
Controls to set the default and maximum transmit powers – these can help minimise
interference between overlapping, fixed-location piconets
!
Dynamic UART configuration
!
Radio transmitter enable/disable – a simple command connects to a dedicated hardware
switch that determines whether the radio can transmit
!
The firmware can read the voltage on a pair of the chip’s external pins. This is normally used to build a
battery monitor, using either VM or host code
!
A block of BCCMD commands provides access to the chip’s “persistent store” configuration database
(PS). The database sets the device’s Bluetooth address, Class of Device, radio (transmit class)
configuration, SCO routing, LM, USB and DFU constants, etc.
!
A UART “break” condition can be used in three ways:
1.
Presenting a UART break condition to the chip can force the chip to perform a hardware reboot
2.
Presenting a break condition at boot time can hold the chip in a low power state, preventing normal
initialisation while the condition exists
3.
With BCSP, the firmware can be configured to send a break to the host before sending data – normally
used to wake the host from a deep sleep state
!
The DFU standard has been extended with public/private key authentication, allowing manufacturers to
control the firmware that can be loaded onto their Bluetooth modules
!
A modified version of the DFU protocol allows firmware upgrade via the chip’s UART
!
A block of “radio test” or BIST commands allows direct control of the chip’s radio. This aids the
development of modules’ radio designs, and can be used to support Bluetooth qualification.
!
Virtual Machine (VM). The firmware provides the VM environment in which to run application-specific
code. Although the VM is mainly used with BlueLab and “RFCOMM builds” (alternative firmware builds
providing L2CAP, SDP and RFCOMM), the VM can be used with this build to perform simple tasks such
as flashing LED’s via the chip’s PIO port.
!
Hardware low power modes: shallow sleep and deep sleep. The chip drops into modes that significantly
reduce power consumption when the software goes idle.
!
SCO channels are normally routed via HCI (over BCSP). However, up to three SCO channels can be
routed over the chip’s single PCM port (at the same time as routing any remaining SCO channels over
HCI).
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7.1.2
CSR Bluetooth Software Stacks
Stand-Alone BlueCore3-Multimedia External and Kalimba DSP
Applications
Internal RISC Processor
Kalimba DSP
VM Application Software
DSP Application
RFCOMM
SDP
HCI
LM
LC
32KB RAM
DSP Control
Baseband
MCU
DM1
8K x
24-bit
DM2
8K x
24-bit
PM
4K x
32-bit
USB
Host
Host I/O
UART
PCM / SPDIF / I2S
Radio
Digital Audio
2
Microphone or Speaker
Analogue Audio
Figure 7.2: Kalimba DSP Stack
In Figure 7.2, this version of the stack firmware requires no host processor (but can use a host processor for
debugging etc. as shown). The software layers for the application software runs on the internal RISC processor in
a protected user software execution environment known as a Virtual Machine (VM) and the DSP application code
runs from the DSP program memory RAM.
The user may write custom application code to run on the BlueCore VM using BlueLab™ software development
kit (SDK) supplied with the BlueLab Multimedia and Casira development kits, available separately from CSR.
This code will then execute alongside the main BlueCore firmware. The user is able to make calls to the
BlueCore firmware for various operations.
The execution environment is structured so the user application does not adversely affect the main software
routines, thus ensuring that the Bluetooth stack software component does not need re-qualification when the
application is changed.
Using the VM and the BlueLab SDK the user is able to develop applications such as a cordless headset or other
profiles without the requirement of a host controller. BlueLab is supplied with example code including a full
implementation of the headset profile.
Note:
Sample applications to control PIO lines can also be written with BlueLab SDK and the VM for the HCI stack.
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External FLASH
7.2
CSR Bluetooth Software Stacks
7.3
Host-Side Software
BlueCore3-Multimedia External can be ordered with companion host-side software:
BlueCore3-PC includes software for a full Windows®98/ME, Windows 2000 or Windows XP Bluetooth
host-side stack together with IC hardware described in this document.
!
BlueCore3-Mobile includes software for a full host-side stack designed for modern ARM based mobile
handsets together with IC hardware described in this document.
7.4
Device Firmware Upgrade
BlueCore3-Multimedia External is supplied with boot loader software, which implements a Device Firmware
Upgrade (DFU) capability. This allows new firmware to be uploaded to the Flash memory through
BlueCore3-Multimedia External UART or USB ports.
7.5
BCHS Software
BlueCore Embedded Host Software is designed to enable CSR customers to implement Bluetooth functionality
into embedded products quickly, cheaply and with low risk.
BCHS is developed to work with CSR's family of BlueCore IC's. BCHS is intended for embedded products that
have a host processor for running BCHS and the Bluetooth application e.g. a mobile phone or a PDA. BCHS
together with the BlueCore IC with embedded Bluetooth core stack (L2CAP, RFCOMM and SDP) is a complete
Bluetooth system solution from RF to profiles.
BCHS includes most of the Bluetooth intelligence and gives the user a simple API. This makes it possible to
develop a Bluetooth product without in-depth Bluetooth knowledge.
The BlueCore Embedded Host Software contains 3 elements:
!
Example Drivers (BCSP and proxies)
!
Bluetooth Profile Managers
!
Example Applications
The profiles are qualified which makes the qualification of the final product very easy. BCHS is delivered with
source code (ANSI C). With BCHS also come example applications in ANSI C, which makes the process of
writing the application easier.
7.6
Additional Software for Other Embedded Applications
When the upper layers of the Bluetooth protocol stack are run as firmware on BlueCore3-Multimedia External, a
UART software driver is supplied that presents the L2CAP, RFCOMM and Service Discovery (SDP) APIs to
higher Bluetooth stack layers running on the host. The code is provided as ‘C’ source or object code.
7.7
CSR Development Systems
CSR’s BlueLab Multimedia and Casira development kits are available to allow the evaluation of the
BlueCore3-Multimedia External hardware and software, and as toolkits for developing on-chip and host software.
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!
Device Terminal Descriptions
8
8.1
Device Terminal Descriptions
RF Ports
8.1.1 TX_A and TX_B
TX_A and TX_B form a complementary balanced pair. On transmit, their outputs are combined using a balun into
the single-ended output required for the antenna. Similarly, on receive, their input signals are combined internally.
Both terminals present similar complex impedances that require matching networks between them and the balun.
Starting from the substrate (chip side), the outputs can each be modelled as an ideal current source in parallel
with a lossy resistance and a capacitor. The bond wire can be represented as series inductance.
BlueCore3-Multimedia External
PA
L2
1.5nH
_
PA
RF
Switch
+
R2
10 Ω
0.9pF
L3
1.5nH
RF
Switch
R3
10 Ω
+
LNA
0.9pF
_
Figure 8.1: Circuit TX/RX_A and TX/RX_B
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The BlueCore3-Multimedia External RF_IN terminal can be configured as either a single ended or differential
input. The operational mode is determined by the setting the PS Key PSKEY_TXRX_PIO_CONTROL (0x20).
Device Terminal Descriptions
8.1.2 Transmit Port Impedances for 7 x 7 VFBGA Package (2.4-2.5GHz vs.
Temperature)
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Figure 8.2: TX_A Output at Power Setting 35
Figure 8.3: TX_A Output at Power Setting 50
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Figure 8.4: TX_A Output at Power Setting 63
Figure 8.5: TX_B Output at Power Setting 35
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Figure 8.6: TX_B Output at Power Setting 50
Figure 8.7: TX_B Output at Power Setting 63
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8.1.3
Receive Port Impedances for 7 x 7 VFBGA Package (2.4-2.5GHz vs.
Temperature)
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Figure 8.8: RX_A Balanced Receive Input Impedance
Figure 8.9: RX_B Balanced Receive Input Impedance
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Device Terminal Descriptions
8.1.4
Transmit S Parameters
Port 1:
TX_A
Port 2:
TX_B
(1)
Power Level: 50
Normalised impedance: 50Ω
Frequency
(MHz)
S11
S21
S12
S22
Real
Imaginary
Real
Imaginary
Real
Imaginary
Real
Imaginary
2402
-7.99E-02
-6.71E-01
2.06E-03
6.19E-02
1.03E-02
6.30E-02
-2.44E-02
-6.89E-01
2408
-8.97E-02
-6.82E-01
-5.02E-03
5.85E-02
7.25E-04
6.25E-02
-2.80E-02
-6.85E-01
2414
-9.33E-02
-6.82E-01
-5.33E-03
5.83E-02
5.53E-04
6.24E-02
-3.13E-02
-6.86E-01
2420
-9.76E-02
-6.83E-01
-5.32E-03
5.83E-02
2.06E-04
6.22E-02
-3.48E-02
-6.86E-01
2426
-1.01E-01
-6.83E-01
-5.89E-03
5.81E-02
-1.03E-04
6.21E-02
-3.86E-02
-6.87E-01
2432
-1.05E-01
-6.83E-01
-6.23E-03
5.80E-02
-4.01E-04
6.22E-02
-4.24E-02
-6.87E-01
2438
-1.09E-01
-6.84E-01
-6.66E-03
5.80E-02
-8.28E-04
6.19E-02
-4.63E-02
-6.88E-01
2444
-1.13E-01
-6.85E-01
-6.90E-03
5.79E-02
-1.38E-03
6.19E-02
-5.02E-02
-6.89E-01
2450
-1.18E-01
-6.85E-01
-7.34E-03
5.80E-02
-1.76E-03
6.19E-02
-5.44E-02
-6.89E-01
2456
-1.21E-01
-6.85E-01
-7.83E-03
5.80E-02
-2.25E-03
6.19E-02
-5.80E-02
-6.89E-01
2462
-1.26E-01
-6.85E-01
-8.27E-03
5.81E-02
-2.74E-03
6.20E-02
-6.20E-02
-6.90E-01
2468
-1.29E-01
-6.86E-01
-8.75E-03
5.81E-02
-3.22E-03
6.21E-02
-6.67E-02
-6.90E-01
2474
-1.33E-01
-6.86E-01
-9.32E-03
5.81E-02
-3.80E-03
6.22E-02
-7.00E-02
-6.90E-01
2480
-1.37E-01
-6.86E-01
-9.80E-03
5.82E-02
-4.33E-03
6.25E-02
-7.44E-02
-6.92E-01
Table 8.1: Transmit S Parameters
Notes:
(1)
Value assigned to PSKEY_LC_DEFAULT_TX_POWER.
S-Parameter data files available upon request.
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Temperature: +20°C
Device Terminal Descriptions
8.1.5
Balanced Receive S Parameters
Port 1:
RX_A
Port 2:
RX_B
Rx in balanced mode
Normalised impedance: 50Ω
Frequency
(MHz)
S11
S21
S12
S22
Real
Imaginary
Real
Imaginary
Real
Imaginary
Real
Imaginary
2402
-5.37E-02
-7.53E-01
1.57E-02
3.95E-02
2.11E-02
1.75E-02
2.08E-02
-7.76E-01
2408
-5.75E-02
-7.54E-01
1.57E-02
3.94E-02
2.04E-02
1.77E-02
1.74E-02
-7.78E-01
2414
-6.11E-02
-7.54E-01
1.55E-02
3.94E-02
1.97E-02
1.80E-02
1.36E-02
-7.78E-01
2420
-6.55E-02
-7.55E-01
1.56E-02
3.94E-02
1.89E-02
1.84E-02
9.98E-03
-7.78E-01
2426
-6.87E-02
-7.55E-01
1.53E-02
3.95E-02
1.83E-02
1.88E-02
5.80E-03
-7.79E-01
2432
-7.33E-02
-7.55E-01
1.52E-02
3.96E-02
1.77E-02
1.92E-02
1.74E-03
-7.80E-01
2438
-7.62E-02
-7.56E-01
1.50E-02
3.97E-02
1.70E-02
1.95E-02
-2.01E-03
-7.80E-01
2444
-8.01E-02
-7.56E-01
1.49E-02
3.96E-02
1.65E-02
1.99E-02
-5.52E-03
-7.80E-01
2450
-8.45E-02
-7.57E-01
1.47E-02
3.97E-02
1.60E-02
2.01E-02
-1.00E-02
-7.81E-01
2456
-8.77E-02
-7.57E-01
1.44E-02
3.97E-02
1.54E-02
2.04E-02
-1.37E-02
-7.81E-01
2462
-9.16E-02
-7.57E-01
1.42E-02
3.99E-02
1.49E-02
2.08E-02
-1.79E-02
-7.82E-01
2468
-9.48E-02
-7.58E-01
1.41E-02
4.00E-02
1.42E-02
2.11E-02
-2.29E-02
-7.82E-01
2474
-9.88E-02
-7.59E-01
1.39E-02
4.02E-02
1.37E-02
2.17E-02
-2.62E-02
-7.83E-01
2480
-1.02E-01
-7.59E-01
1.38E-02
4.02E-02
1.32E-02
2.22E-02
-3.04E-02
-7.85E-01
Table 8.2: Balanced Receiver S Parameters
Note:
S-Parameter data files available upon request
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Temperature: +20°C
Device Terminal Descriptions
8.1.6
Single-Ended Input (RF_IN)
This is the single ended RF input from the antenna. The input presents a complex impedance that requires a
matching network between the terminal and the antenna. Starting from the substrate (chip) side, the input can be
modelled as a lossy capacitor with the bond wire to the ball grid represented as a series inductance.
BlueCore3-Multimedia External
L1
1.5nH
RF_IN
R1
6.8Ω
C1
0.68pF
Figure 8.10: Circuit RF_IN
Note:
Both terminals must be externally DC biased to VDD_RADIO.
8.1.7
Transmit RF Power Control for Class 1 Applications (TX_PWR)
An 8-bit voltage DAC (AUX_DAC) is used to control the amplification level of the external PA for Class 1
operation. The DAC output is derived from the on chip band gap and is virtually independent of temperature and
supply voltage. The output voltage is given by:
⎛⎛
⎞
CNTRL _ WORD ⎞
VDAC = MIN⎜⎜ ⎜ 3.3v ×
⎟, (VDD _ PIO − 0.3v )⎟⎟
255
⎠
⎝⎝
⎠
Equation 8.1: Output Voltage with Load Current ≤ 10mA
for a load current ≤10mA (sourced from the device).
or
⎛⎛
⎞
CNTRL _ WORD ⎞
VDAC = MIN⎜⎜ ⎜ 3.3v ×
⎟, VDD _ PIO ⎟⎟
255
⎠
⎝⎝
⎠
Equation 8.2: Output Voltage with No Load Current
for no load current.
BlueCore3-Multimedia External enables the external PA only when transmitting. Before transmitting, the chip
normally ramps up the power to the internal PA, then it ramps it down again afterwards. However, if a suitable
external PA is used, it may be possible to ramp the power externally by driving the TX_PWR pin on the PA from
AUX_DAC.
TX Power
tcarrier
Modulation
Figure 8.11: Internal Power Ramping
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The terminal is DC blocked. The DC level must not exceed (VSS_RADIO -0.3V to VDD_RADIO + 0.3V).
Device Terminal Descriptions
The persistent store key (PS Key) PSKEY_TX_GAINRAMP (0x1d), is used to control the delay (in units of µs)
between the end of the transmit power ramp and the start of modulation. In this period the carrier is transmitted,
which gives the transmit circuitry time to fully settle to the correct frequency.
8.1.8
Control of External RF Components
A PS Key TXRX_PIO_CONTROL (0x209) is used to control external RF components such as a switch, an
external PA or an external LNA. PIO[0], PIO[1] and the AUX_DAC can be used for this purpose, as indicated in
Table 8.3.
TXRX_PIO_CONTROL Value
AUX_DAC Use
0
PIO[0], PIO[1], AUX_DAC not used to control RF. Power ramping is
internal.
1
PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC not used.
Power ramping is internal.
2
PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC used to set
gain of external PA. Power ramping is external.
3
PIO[0] is low during RX, PIO[1] is low during TX. AUX_DAC used to set
gain of external PA. Power ramping is external.
4
PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC used to set
gain of external PA. Power ramping is internal.
Table 8.3: TXRX_PIO_CONTROL Values
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Bits[15:8] define a delay, tcarrier, (in units of µs) between the end of the transmit power ramp and the start of
modulation. In this period the carrier is transmitted, which aids interoperability with some other vendor equipment
which is not strictly Bluetooth compliant.
Device Terminal Descriptions
8.2
External Reference Clock Input (XTAL_IN)
The BlueCore3-Multimedia External RF local oscillator and internal digital clocks are derived from the reference
clock at the BlueCore3-Multimedia External XTAL_IN input. This reference may be either an external clock or
from a crystal connected between XTAL_IN and XTAL_OUT. The crystal mode is described in Section 8.3.
External Mode
BlueCore3-Multimedia External can be configured to accept an external reference clock (from another device,
such as TCXO) at XTAL_IN by connecting XTAL_OUT to ground. The external clock can either be a digital level
square wave or sinusoidal and this may be directly coupled to XTAL_IN without the need for additional
components. If the peaks of the reference clock are below VSS_ANA or above VDD_ANA, it must be driven
through a DC blocking capacitor (~33pF) connected to XTAL_IN. A digital level reference clock gives superior
noise immunity as the high slew rate clock edges have lower voltage to phase conversion.
The external clock signal should meet the specifications in Table 8.4.
Minimum
Typical
Maximum
Frequency
7.5MHz
16MHz
40MHz
Duty cycle
20:80
50:50
80:20
-
-
15ps rms
400mV pk-pk
-
VDD_ANA(2)(3)
(1)
Edge Jitter (At Zero Crossing)
Signal Level
Table 8.4: External Clock Specifications
Notes:
(1)
The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies.
(2)
VDD_ANA is 1.8V nominal.
(3)
If the external clock driven through a DC blocking capacitor then maximum allowable amplitude is
reduced from VDD_ANA to 800mV pk-pk.
8.2.2
XTAL_IN Impedance in External Mode
The impedance of the XTAL_IN will not change significantly between operating modes, typically 10fF. When
transitioning from deep sleep to an active state a spike of up to 1pC may be measured. For this reason it is
recommended that a buffered clock input be used.
8.2.3
Clock Timing Accuracy
As Figure 8. indicates, the 250ppm timing accuracy on the external clock is required 7ms after the assertion of
the system clock request line. This is to guarantee that the firmware can maintain timing accuracy in accordance
with the Bluetooth v1.2 specification. Radio activity may occur after 11ms, therefore at this point, the timing
accuracy of the external clock source must be within 20ppm.
Figure 8.11: TCXO Clock Accuracy
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8.2.1
Device Terminal Descriptions
8.2.4
Clock Start-Up Delay
This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still
keeping the current consumption of BlueCore3-Multimedia External as low as possible.
BlueCore3-Multimedia External will consume about 2mA of current for the duration of
PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.
Actual Allowable Clock Presence Delay on XTAL_IN vs. PSKey Setting
30.0
25.0
D elay (m s)
20.0
15.0
10.0
5.0
0.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
PSKEY_CLOCK_STARTUP_DELAY
Figure 8.12: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting
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BlueCore3-Multimedia External hardware incorporates an automatic 5ms delay after the assertion of the system
clock request signal before running firmware. This is suitable for most applications using an external clock
source. However, there may be scenarios where the clock cannot be guaranteed to either exist or be stable after
this period. Under these conditions, BlueCore3-Multimedia External firmware provides a software function which
will extend the system clock request signal by a period stored in PSKEY_CLOCK_STARTUP_DELAY. This value
is set in milliseconds from 5-31ms.
Device Terminal Descriptions
8.2.5
Input Frequencies and PS Key Settings
BlueCore3-Multimedia External should be configured to operate with the chosen reference frequency. This is
accomplished by setting the PS Key PSKEY_ANA_FREQ (0x1fe) for all frequencies with an integer multiple of
250KHz. The input frequency default setting in BlueCore3-Multimedia External is 26MHz.
Reference Crystal Frequency (MHz)
PSKEY_ANA_FREQ (0x1fe) (Units of 1kHz)
7.68
7680
14.40
14400
15.36
15360
16.20
16200
16.80
16800
19.20
19200
19.44
19440
19.68
19680
19.80
19800
38.40
38400
n x 250kHz
-
+26.00 Default
26000
Table 8.5: PS Key Values for CDMA/3G phone TCXO Frequencies
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The following CDMA/3G TCXO frequencies are also catered for: 7.68, 14.4, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68,
19.8 and 38.4MHz. This is accomplished by also changing PSKEY PLLX_FREQ_REF (0xabc).
Device Terminal Descriptions
8.3
Crystal Oscillator (XTAL_IN, XTAL_OUT)
The BlueCore3-Multimedia External RF local oscillator and internal digital clocks are derived from the reference
clock at the BlueCore3-Multimedia External XTAL_IN input. This reference may be either an external clock or
from a crystal connected between XTAL_IN and XTAL_OUT. The external reference clock mode is described in
Section 8.2.
XTAL Mode
gm
-
Cint
C trim
XTAL_OUT
Ctrim
XTAL_IN
BlueCore3-Multimedia External
BlueCore3-Multimedia External contains a crystal driver circuit. This operates with an external crystal and
capacitors to form a Pierce oscillator.
Ct2
Ct1
Figure 8.13: Crystal Driver Circuit
Figure 8. shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant
frequency. It forms a resonant circuit with its load capacitors.
Cm
Lm
Rm
Co
Figure 8.14: Crystal Equivalent Circuit
The resonant frequency may be trimmed with the crystal load capacitance. BlueCore3-Multimedia External
contains variable internal capacitors to provide a fine trim.
The BlueCore3-Multimedia External driver circuit is a transconductance amplifier. A voltage at XTAL_IN
generates a current at XTAL_OUT. The value of transconductance is variable and may be set for optimum
performance.
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8.3.1
Device Terminal Descriptions
8.3.2
Load Capacitance
Cl = Cint +
C trim
C ⋅C
+ t1 t 2
2
C t1 + C t 2
Equation 8.3: Load Capacitance
Where:
Ctrim = 3.4pF nominal (Mid range setting)
Cint = 1.5pF
Note:
Cint does not include the crystal internal self capacitance, it is the driver self capacitance.
8.3.3
Frequency Trim
BlueCore3-Multimedia External enables frequency adjustments to be made. This feature is typically used to
remove initial tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the
crystal load capacitance with on chip trim capacitors, Ctrim. The value of Ctrim is set by a 6-bit word in the
Persistent Store Key PSKEY_ANA_FTRIM (0x1f6). Its value is calculated thus:
Ctrim = 110 fF × PSKEY_ANA_FTRIM
Equation 8.4: Trim Capacitance
There are two Ctrim capacitors, which are both connected to ground. When viewed from the crystal terminals, they
appear in series so each least significant bit (LSB) increment of frequency trim presents a load across the crystal
of 55fF.
The frequency trim is described by Equation 8.5:
∆(Fx )
= pullability × 55 × 10 −3 (ppm / LSB )
Fx
Equation 8.5: Frequency Trim
Where Fx is the crystal frequency and pullability is a crystal parameter with units of ppm/pF. Total trim range is 63
times the value above.
If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 8.6:
Cm
∂ (Fx )
= Fx ⋅
∂ (C)
4(Cl + C0 )2
Equation 8.6: Pullability
Where:
C0 = Crystal self capacitance (shunt capacitance)
Cm = Crystal motional capacitance (series branch capacitance in crystal model). See Figure 8..
Note:
It is a Bluetooth requirement that the frequency is always within ±20ppm. The trim range should be sufficient
to pull the crystal within ±5ppm of the exact frequency. This leaves a margin of ±15ppm for frequency drift
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For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is
defined for the crystal. This is the total capacitance across the crystal viewed from its terminals.
BlueCore3-Multimedia External provides some of this load with the capacitors Ctrim and Cint. The remainder
should be from the external capacitors labelled Ct1 and Ct2. Ct1 should be three times the value of Ct2 for best
noise performance. This maximises the signal swing, hence slew rate at XTAL_IN, to which all on chip clocks are
referred. Crystal load capacitance, Cl is calculated with the following equation:
Device Terminal Descriptions
with ageing and temperature. A crystal with an ageing and temperature drift specification of better than
±15ppm is required.
8.3.4
Transconductance Driver Model
gm >
3(Ct1 +Ctrim )(Ct 2 + Ctrim )
(2πFx ) Rm ((C0 + Cint )(Ct1 + Ct 2 + 2Ctrim ) + (Ct1 + Ctrim )(Ct 2 + Ctrim ))2
2
Equation 8.7: Transconductance Required for Oscillation
BlueCore3-Multimedia External guarantees a transconductance value of at least 2mA/V at maximum drive level.
Notes:
More drive strength is required for higher frequency crystals, higher loss crystals (larger Rm) or higher
capacitance loading.
Optimum drive level is attained when the level at XTAL_IN is approximately 1V pk−pk. The drive level is
determined by the crystal driver transconductance, by setting the Persistent Store KEY_XTAL_LVL (0x241).
8.3.5
Negative Resistance Model
An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element.
The driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of
the negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the
BlueCore3-Multimedia External crystal driver circuit is based on a transimpedance amplifier, an equivalent
negative resistance may be calculated for it with the following formula in Equation 8.8:
Rneg >
3(Ct1 +Ctrim )(Ct 2 + Ctrim )
gm (2πFx )2 (C0 + Cint )((Ct1 + Ct 2 + 2Ctrim ) + (Ct1 + Ctrim )(Ct 2 + Ctrim ))2
Equation 8.8: Equivalent Negative Resistance
This formula shows the negative resistance of the BlueCore3-Multimedia External driver as a function of its drive
strength.
The value of the driver negative resistance may be easily measured by placing an additional resistance in series
with the crystal. The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of
the oscillator.
Minimum
Frequency
Typical
Maximum
8MHz
16MHz
32MHz
Initial Tolerance
-
±25ppm
-
Pullability
-
±20ppm/pF
-
Table 8.6: Crystal Oscillator Specification
8.3.6
Crystal PS Key Settings
See Table 8.5.
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The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to
one terminal generates a voltage at the other. The transconductance amplifier in BlueCore3-Multimedia External
uses the voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the circuit will
oscillate if the transconductance, transimpedance product is greater than unity. For sufficient oscillation
amplitude, the product should be greater than 3. The transconductance required for oscillation is defined by the
following relationship:
Device Terminal Descriptions
8.3.7
Crystal Oscillator Characteristics
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
Max Xtal Rm Value (ESR), (Ohm)
100.0
10.0
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
Load Capacitance (pF)
8 MHz
20 MHz
32 MHz
12 MHz
24 MHz
16 MHz
28 MHz
Figure 8.15: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
Note:
Graph shows results for BlueCore3-Multimedia External crystal driver at maximum drive level.
Conditions:
Ctrim = 3.4pF centre value
Crystal Co = 2pF
Transconductance setting = 2mA/V
Loop gain = 3
Ct1/Ct2 = 3
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1000.0
Device Terminal Descriptions
BlueCore3-Multimedia External XTAL Driver Characteristics
0.007
0.006
Transconductance (S)
0.004
0.003
0.002
0.001
0.000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PSKEY_XTAL_LVL
Gm Typical
Gm Minimum
Gm Maximum
Figure 8.16: Crystal Driver Transconductance vs. Driver Level Register Setting
Note:
Drive level is set by Persistent Store Key PSKEY_XTAL_LVL (0x241).
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0.005
Device Terminal Descriptions
Negative Resistance for 16 MHz Xtal
1000
100
10
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
Drive Level Setting
Typical
Minimum
Maximum
Figure 8.17: Crystal Driver Negative Resistance as a Function of Drive Level Setting
Crystal parameters:
!
Crystal frequency 16MHz (Please refer to your software build release note for frequencies supported);
!
Crystal C0 = 0.75pF
Circuit parameters:
!
Ctrim = 8pF, maximum value
!
Ct1,Ct2 = 5pF (3.9pF plus 1.1 pF stray)
!
(Crystal total load capacitance 8.5pF)
Note:
This is for a specific crystal and load capacitance.
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Max -ve Resistance (Ω)
10000
Device Terminal Descriptions
8.4
Off-Chip Program Memory
The external memory port provides a facility to interface up to 8Mbits of 16-bit external memory. This off-chip
storage is used to store BlueCore3-Multimedia External settings and program code. Flash is the storage
mechanism typically used by BlueCore3-Multimedia External modules, however external masked-ROM may also
be used if the host takes over responsibility for storing configuration data.
Parameter
Value
Data width
16-bit
Minimum total capacity
4Mbit (256kWord)
Maximum access time
50ns @85°C 10pF load
Table 8.7: Flash Device Hardware Requirements
In addition to these hardware requirements, particular care should be taken to ensure that the sector organisation
of the extended memory has the correct format. A sector is defined as an individually erasable area of external
Flash.
It is important to make sure that external memory devices meet certain minimum specifications. In addition
particular care should be taken to ensure that the sector organisation of the extended memory has the correct
format.
Note:
The document “Selection of Flash Memory for Use with BlueCore”, (bcore-an-001Pd), provides guidance on
the selection of suitable flash devices for all BlueCore devices and should be read in conjuction with this
section.
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The external memory port consists of 16 bi-directional data lines, D[15:0]; 19 output address lines, A[18:0] and
three active low output control signals (WEB, CEB, REB). WEB is asserted when data is written to external
memory. REB is asserted when data is read from external memory and the chip select line. CSB is asserted
when any data transfer (read or write) is required. All of the external memory port connections are implemented
using CMOS technology and use standard 0V and VDD_MEM (1.8-3.6V) signalling levels.
Device Terminal Descriptions
8.4.1
Minimum Flash Specification
The flash device used with BlueCore3-Multimedia External must meet the following criteria:
Either standard or extended form of the JEDEC (AMD/Fujitsu/SST) or Intel command set.
!
Access time must be ≤50ns @85°C 10pF load.
!
Write strobe of 100ns.
!
Accessible in word mode, i.e., via a 16-bit data bus.
!
Support changing different bits within each word from 1 to 0 in at least two separate programming
operations.
!
Programming and erase times must have fixed upper limits.
!
Must be bottom boot or uniform sector.
!
Must have independently erasable sectors with at least the following boundaries (see Memory Map for
more information).
Word Address
Size (kWords)
0x00000 - 0x01FFF
8
0x02000 - 0x02FFF
4
0x03000 - 0x03FFF
4
0x04000 - 0x07FFF
16
0x08000 - 0x0FFFF
32
0x10000 - 0x17FFF
32
Don’t care
0x18000 - ...
Table 8.8: Flash Sector Boundaries
Important Note:
Satisfaction of these criteria is not sufficient for a particular device to be used; it must also support the
Common Flash Interface described in Section 8.4.2 or be supported in the BlueCore3-Multimedia External
firmware and host-side tools.
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!
Device Terminal Descriptions
8.4.2
Common Flash Interface
Many modern flash devices support the Common Flash Interface (CFI) that enables device information to be
interrogated in a standard manner. HCIStack1.1v13.2 and later versions of the BlueCore firmware can query this
interface to adapt automatically to work with a wide variety of additional flash devices, without requiring explicit
support for each device type.
!
The device must support the CFI, as defined by JEDEC standard JESD68.
!
The device must return one of the following codes for either the Primary or Alternative Algorithm
Command Set (offset 0x13b or 0x17 of the Query Structure Output respectively):
Code
Description
0x0001
Intel/Sharp Extended Command Set
0x0002
AMD/Fujitsu Standard Command Set
0x0003
Intel Standard Command Set
0x0701
AMD/Fujitsu Extended Command Set
Table 8.9: Common Flash Interface Algorithm Command Set Codes
!
The device must return one of the following patterns of Erase Block Region Information (beginning at
offset 0x2d of the Query Structure Output):
Erase Block Region
Number of Erase Blocks
Block Size
1
128, 256, 512 or 1024
4kbytes
Table 8.10: Erase Block Region Information for Uniform 2kword Sectors
Erase Block Region
Number of Erase Blocks
Block Size
1
256, 512, 1024 or 2048
2kbytes
Table 8.11: Erase Block Region Information for Uniform 1kword Sectors
Erase Block Region
Number of Erase Blocks
Block Size
1
8
8kbytes
2
7, 15, 31 or 63
64kbytes
Table 8.12: Erase Block Region Information for 8 x 4kword, n x 32kword Sectors
Erase Block Region
Number of Erase Blocks
Block Size
1
1
16kbytes
2
2
8kbytes
3
1
32kbytes
4
7, 15, 31 or 63
64kbytes
Table 8.13: Erase Block Region Information for 1 x 8kword, 2 x 4kword, 1 x 16kword, n x 32kword Sectors
If any of these criteria is not met, then the device will not work unless the device is supported by the
BlueCore3-Multimedia External firmware.
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For a flash device to be compatible, it must satisfy both the minimum requirements detailed in Section 8.4.1,
Minimum Requirements, and the following additional requirements:
Device Terminal Descriptions
8.4.3
Memory Timing
Memory Write Cycle
Typical
Maximum(1)
Unit
Write cycle time
300
-
-
ns
Data set-up time
150
-
-
ns
tdat:hd
Data hold time
150
-
-
ns
taddr:su
Address set-up time
150
-
-
ns
twe:low
WEB low
100
-
-
ns
Parameter
twc
tdat:su
Table 8.14: Memory Write Cycle
Note:
(1)
Valid for temperatures between -40°C and +105°C.
twc
A[18:0]
Address Valid
CSB
tdat:hd
twe:low
t addr:su
WEB
REB
t dat:su
D[15:0]
Data Valid
Figure 8.18: Memory Write Cycle
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Minimum(1)
Symbol
Device Terminal Descriptions
Memory Read Cycle
Typical
Maximum(1)
Unit
114
125
-
ns
Address access time
-
-
110
ns
tre
Read enable access time
-
-
110
ns
tdat:hd
Data hold time from
address line
0
-
-
ns
Parameter
trc
Read cycle time
taa
Table 8.15: Memory Read Cycle
Note:
(1)
Valid for temperatures between -40°C and +105°C.
trc
taa
A[18:0]
CSB
REB
tre
WEB
tdat:hd
D[15:0]
Data Valid
Data Valid
Figure 8.19: Memory Read Cycle
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Minimum(1)
Symbol
Device Terminal Descriptions
8.5
UART Interface
BlueCore3-Multimedia External Universal Asynchronous Receiver Transmitter (UART) interface provides a
(1)
simple mechanism for communicating with other serial devices using the RS232 protocol .
BlueCore3-Multimedia External
UART_RX
UART_RTS
UART_CTS
Figure 8.20: Universal Asynchronous Receiver
Four signals are used to implement the UART function, as shown in Figure 8.. When
BlueCore3-Multimedia External is connected to another digital device, UART_RX and UART_TX transfer data
between the two devices. The remaining two signals, UART_CTS and UART_RTS, can be used to implement
RS232 hardware flow control where both are active low indicators. All UART connections are implemented using
CMOS technology and have signalling levels of 0V and VDD_PADS.
UART configuration parameters, such as Baud rate and packet format, are set using
BlueCore3-Multimedia External software.
Notes:
In order to communicate with the UART at its maximum data rate using a standard PC, an accelerated serial
port adapter card is required for the PC.
(1)
Uses RS232 protocol but voltage levels are 0V to VDD_USB, (requires external RS232 transceiver
chip).
Parameter
Baud Rate
Possible Values
Minimum
Maximum
1200 Baud (≤2%Error)
9600 Baud (≤1%Error)
1.5MBaud (≤1%Error)
Flow Control
RTS/CTS or None
Parity
None, Odd or Even
Number of Stop Bits
1 or 2
Bits per channel
8
Table 8.16: Possible UART Settings
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UART_TX
Device Terminal Descriptions
The UART interface is capable of resetting BlueCore3-Multimedia External upon reception of a break signal. A
Break is identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 8.. If tBRK is
longer than the value, defined by the PS Key PSKEY_HOST_IO_UART_RESET_TIMEOUT, (0x1a4), a reset will
occur. This feature allows a host to initialise the system to a known state. Also, BlueCore3-Multimedia External
can emit a Break character that may be used to wake the Host.
BRK
UART RX
Figure 8.21: Break Signal
Note:
The DFU boot loader must be loaded into the Flash device before the UART or USB interfaces can be used.
This initial flash programming can be done via the SPI.
Table 8. shows a list of commonly used Baud rates and their associated values for the Persistent Store Key
PSKEY_UART_BAUD_RATE (0x204). There is no requirement to use these standard values. Any Baud rate
within the supported range can be set in the Persistent Store Key according to the formula in Equation 8.9.
Baud Rate =
PSKEY_UART _BAUD_RATE
0.004096
Equation 8.9: Baud Rate
Persistent Store Value
Baud Rate
Error
Hex
Dec
1200
0x0005
5
1.73%
2400
0x000a
10
1.73%
4800
0x0014
20
1.73%
9600
0x0027
39
-0.82%
19200
0x004f
79
0.45%
38400
0x009d
157
-0.18%
57600
0x00ec
236
0.03%
76800
0x013b
315
0.14%
115200
0x01d8
472
0.03%
230400
0x03b0
944
0.03%
460800
0x075f
1887
-0.02%
921600
0x0ebf
3775
0.00%
1382400
0x161e
5662
-0.01%
Table 8.17: Standard Baud Rates
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t
Device Terminal Descriptions
8.5.1
UART Bypass
RESET
RXD
RTS
TXD
PIO4
UART_RTS
PIO5
UART_CTS
PIO6
UART_RX
PIO7
Host Processor
TX
RTS
CTS
RX
Another Device
UART
BlueCore3-Multimedia
External
Test Interface
Figure 8.22: UART Bypass Architecture
8.5.2
UART Configuration While RESET is Active
The UART interface for BlueCore3-Multimedia External while the chip is being held in reset is tri-state. This will
allow the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any
devices connected to this bus must tri-state when BlueCore3-Multimedia External reset is de-asserted and the
firmware begins to run.
8.5.3
UART Bypass Mode
Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on
BlueCore3-Multimedia External can be used. The default state of BlueCore3-Multimedia External after reset is
de-asserted, this is for the host UART bus to be connected to the BlueCore3-Multimedia External UART, thereby
allowing communication to BlueCore3-Multimedia External via the UART.
In order to apply the UART bypass mode, a BCCMD command will be issued to BlueCore3-Multimedia External
upon this, it will switch the bypass to PIO[7:4] as shown in Figure 8.. Once the bypass mode has been invoked,
BlueCore3-Multimedia External will enter the deep sleep state indefinitely.
In order to re-establish communication with BlueCore3-Multimedia External, the chip must be reset so that the
default configuration takes affect.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode
is invoked. Therefore it is not possible to have active Bluetooth links while operating the bypass mode.
8.5.4
Current Consumption in UART Bypass Mode
The current consumption for a device in UART Bypass Mode is equal to the values quoted for a device in
standby mode.
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CTS
UART_TX
Device Terminal Descriptions
8.6
USB Interface
As USB is a Master/Slave oriented system (in common with other USB peripherals),
BlueCore3-Multimedia External only supports USB Slave operation.
8.6.1
USB Data Connections
The USB data lines emerge as pins USB_DP and USB_DN. These terminals are connected to the internal USB
I/O buffers of the BlueCore3-Multimedia External and therefore have a low output impedance. To match the
connection to the characteristic impedance of the USB cable, resistors must be placed in series with USB_DP /
USB_DN and the cable.
8.6.2
USB Pull-Up Resistor
BlueCore3-Multimedia External features an internal USB pull-up resistor. This pulls the USB_DP pin weakly high
when BlueCore3-Multimedia External is ready to enumerate. It signals to the PC that it is a full speed (12Mbit/s)
USB device.
The USB internal pull-up is implemented as a current source, and is compliant with Section 7.1.5 of the USB
specification v1.2. The internal pull-up pulls USB_DP high to at least 2.8V when loaded with a 15kΩ ±5%
pull-down resistor (in the hub/host) when VDD_PADS=3.1V. This presents a Thevenin resistance to the host of at
least 900Ω. Alternatively, an external 1.5kΩ pull-up resistor can be placed between a PIO line and D+ on the
USB cable. The firmware must be alerted to which mode is used by setting PS Key PSKEY_USB_PIO_PULLUP
appropriately. The default setting uses the internal pull-up resistor.
8.6.3
Power Supply
The USB specification dictates that the minimum output high voltage for USB data lines is 2.8V. To safely meet
the USB specification, the voltage on the VDD_USB supply terminals must be an absolute minimum of 3.1V.
CSR recommends 3.3V for optimal USB signal quality.
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BlueCore3-Multimedia External devices contain a full speed (12Mbits/s) USB interface that is capable of driving a
USB cable directly. No external USB transceiver is required. The device operates as a USB peripheral,
responding to requests from a master host controller such as a PC. Both the OHCI and the UHCI standards are
supported. The set of USB endpoints implemented can behave as specified in the USB section of the Bluetooth
specification v1.2 or alternatively can appear as a set of endpoints appropriate to USB audio devices such as
speakers.
Device Terminal Descriptions
8.6.4
Self-Powered Mode
Self-powered USB designs (powered from a battery or PSU) must ensure that a PIO line is allocated for USB
pull-up purposes. A 1.5K 5% pull-up resistor between USB_DP and the selected PIO line should be fitted to the
design. Failure to fit this resistor may result in the design failing to be USB compliant in self-powered mode. The
internal pull-up in BlueCore is only suitable for bus-powered USB devices i.e. dongles.
BlueCore3-Multimedia External
PIO
1.5KΩ 5%
Rs
USB_DP
D+
Rs
USB_DN
DR vb1
USB_ON
VBUS
R vb2
GND
Figure 8.23: USB Connections for Self-Powered Mode
The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting
PSKEY_USB_PIO_VBUS to the corresponding pin number.
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In self-powered mode, the circuit is powered from its own power supply and not from the VBUS (5V) line of the
USB cable. It draws only a small leakage current (below 0.5mA) from VBUS on the USB cable. This is the easier
mode for which to design for, as the design is not limited by the power that can be drawn from the USB hub or
root port. However, it requires that VBUS be connected to BlueCore3-Multimedia External via a resistor network
(Rvb1 and Rvb2), so BlueCore3-Multimedia External can detect when VBUS is powered up.
BlueCore3-Multimedia External will not pull USB_DP high when VBUS is off.
Device Terminal Descriptions
8.6.5
Bus-Powered Mode
In bus-powered mode the application circuit draws its current from the 5V VBUS supply on the USB cable.
BlueCore3-Multimedia External negotiates with the PC during the USB enumeration stage about how much
current it is allowed to consume.
For Class 1 Bluetooth applications, the USB power descriptor should be altered to reflect the amount of power
required. This is accomplished by setting the PS Key PSKEY_USB_MAX_POWER (0x2c6). This is higher than
for a Class 2 application due to the extra current drawn by the Transmit RF PA.
When selecting a regulator, be aware that VBUS may go as low as 4.4V. The inrush current (when charging
reservoir and supply decoupling capacitors) is limited by the USB specification (see USB specification v1.1,
Section 7.2.4.1). Some applications may require soft start circuitry to limit inrush current if more than 10µF is
present between VBUS and GND.
The 5V VBUS line emerging from a PC is often electrically noisy. As well as regulation down to 3.3V and 1.8V,
applications should include careful filtering of the 5V line to attenuate noise that is above the voltage regulator
bandwidth. Excessive noise on the 1.8V supply to the analogue supply pins of BlueCore3-Multimedia External
will result in reduced receive sensitivity and a distorted RF transmit signal.
BlueCore3-Multimedia External
Rs
D+
USB_DP
Rs
USB_DN
DR vb1
VBUS
USB_ON
GND
Voltage
Regulator
Figure 8.24: USB Connections for Bus-Powered Mode
Note:
USB_ON is shared with BlueCore3-Multimedia External PIO terminals.
Identifier
Rs
Value
27Ω nominal
Function
Impedance matching to USB cable
Rvb1
22kΩ 5%
VBUS ON sense divider
Rvb2
47kΩ 5%
VBUS ON sense divider
Table 8.18: USB Interface Component Values
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For Class 2 Bluetooth applications, CSR recommends that the regulator used to derive 3.3V from VBUS is rated
at 100mA average current and should be able to handle peaks of 120mA without foldback or limiting. In buspowered mode, BlueCore3-Multimedia External requests 100mA during enumeration.
Device Terminal Descriptions
8.6.6
Suspend Current
All USB devices must permit the USB controller to place them in a USB Suspend mode. While in USB Suspend,
bus-powered devices must not draw more than 0.5mA from USB VBUS (self-powered devices may draw more
than 0.5mA from their own supply). This current draw requirement prevents operation of the radio by buspowered devices during USB Suspend.
8.6.7
Detach and Wake_Up Signalling
BlueCore3-Multimedia External can provide out-of-band signalling to a host controller by using the control lines
called ‘USB_DETACH’ and ‘USB_WAKE_UP’. These are outside the USB specification (no wires exist for them
inside the USB cable), but can be useful when embedding BlueCore3-Multimedia External into a circuit where no
external USB is visible to the user. Both control lines are shared with PIO pins and can be assigned to any PIO
pin by setting the PS Keys PSKEY_USB_PIO_DETACH and PSKEY_USB_PIO_WAKEUP to the selected PIO
number.
USB_DETACH is an input which, when asserted high, causes BlueCore3-Multimedia External to put USB_DN
and USB_DP in a high impedance state and turned off the pull-up resistor on DP. This detaches the device from
the bus and is logically equivalent to unplugging the device. When USB_DETACH is taken low,
BlueCore3-Multimedia External will connect back to USB and await enumeration by the USB host.
USB_WAKE_UP is an active high output (used only when USB_DETACH is active) to wake up the host and
allow USB communication to recommence. It replaces the function of the software USB WAKE_UP message
(which runs over the USB cable), and cannot be sent while BlueCore3-Multimedia External is effectively
disconnected from the bus.
10ms max
10ms max
USB_DETACH
10ms max
No max
USB_WAKE_UP
Port_Impedance
USB_DP
USB_DN
USB_PULL_UP
Disconnected
Figure 8.25: USB_DETACH and USB_WAKE_UP Signal
8.6.8
USB Driver
A USB Bluetooth device driver is required to provide a software interface between
BlueCore3-Multimedia External and Bluetooth software running on the host computer. Suitable drivers are
available from http://www.csrsupport.com.
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The voltage regulator circuit itself should draw only a small quiescent current (typically less than 100µA) to
ensure adherence to the suspend current requirement of the USB specification. This is not normally a problem
with modern regulators. Ensure that external LEDs and/or amplifiers can be turned off by
BlueCore3-Multimedia External. The entire circuit must be able to enter the suspend mode. (For more details on
USB Suspend, see separate CSR documentation).
Device Terminal Descriptions
8.6.9
USB 1.1 Compliance
BlueCore3-Multimedia External is qualified to the USB specification v1.1, details of which are available from
http://www.usb.org. The specification contains valuable information on aspects such as PCB track impedance,
supply inrush current and product labelling.
Terminals USB_DP and USB_DN adhere to the USB specification 2.0 (Chapter 7) electrical requirements.
8.6.10 USB 2.0 Compatibility
BlueCore3-Multimedia External is compatible with USB v2.0 host controllers; under these circumstances the two
ends agree the mutually acceptable rate of 12Mbits/s according to the USB v2.0 specification.
8.7
Serial Peripheral Interface
BlueCore3-Multimedia External uses 16-bit data and 16-bit address serial peripheral interface, where
transactions may occur when the internal processor is running or is stopped. This section details the
considerations required when interfacing to BlueCore3-Multimedia External via the four dedicated serial
peripheral interface terminals. Data may be written or read one word at a time or the auto increment feature may
be used to access blocks.
8.7.1
Instruction Cycle
The BlueCore3-Multimedia External is the slave and receives commands on SPI_MOSI and outputs data on
SPI_MISO. The instruction cycle for a SPI transaction is shown in Table 8..
1
Reset the SPI interface
Hold SPI_CSB high for two SPI_CLK cycles
2
Write the command word
Take SPI_CSB low and clock in the 8 bit command
3
Write the address
Clock in the 16-bit address word
4
Write or read data words
Clock in or out 16-bit data word(s)
5
Termination
Take SPI_CSB high
Table 8.19: Instruction Cycle for an SPI Transaction
With the exception of reset, SPI_CSB must be held low during the transaction. Data on SPI_MOSI is clocked into
the BlueCore3-Multimedia External on the rising edge of the clock line SPI_CLK. When reading,
BlueCore3-Multimedia External will reply to the master on SPI_MISO with the data changing on the falling edge
of the SPI_CLK. The master provides the clock on SPI_CLK. The transaction is teminated by taking SPI_CSB
high.
Sending a command word and the address of a register for every time it is to be read or written is a significant
overhead, especially when large amounts of data are to be transferred. To overcome this
BlueCore3-Multimedia External offers increased data transfer efficiency via an auto increment operation. To
invoke auto increment, SPI_CSB is kept low, which auto increments the address, while providing an extra 16
clock cycles for each extra word to be written or read.
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Although BlueCore3-Multimedia External meets the USB specification, CSR cannot guarantee that an application
circuit designed around the chip is USB compliant. The choice of application circuit, component choice and PCB
layout all affect USB signal quality and electrical characteristics. The information in this document is intended as
a guide and should be read in association with the USB specification, with particular attention being given to
Chapter 7. Independent USB qualification must be sought before an application is deemed USB compliant and
can bear the USB logo. Such qualification can be obtained from a USB plugfest or from an independent USB test
house.
Device Terminal Descriptions
8.7.2
Writing to BlueCore3-Multimedia External
To write to BlueCore3-Multimedia External, the 8-bit write command (00000010) is sent first (C[7:0]) followed by
a 16-bit address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the location set by
the address (A). Thereafter for each subsequent 16-bits clocked in, the address (A) is incremented and the data
written to consecutive locations until the transaction terminates when SPI_CSB is taken high.
Write_Command
Address(A)
Data(A)
Data(A+1)
etc
SPI_CSB
SPI_CLK
C7
SPI_MOSI
SPI_MISO
C6
C1
C0
A15
A14
A1
A0
Processor
State
D15
D14
D1
D0
D15
D14
D1
D0
D15
D14
D1
D0
Don't Care
Processor
State
MISO Not Defined During Write
Figure 8.26: Write Operation
8.7.3
Reading from BlueCore 3-Multimedia External
Reading from BlueCore3-Multimedia External is similar to writing to it. An 8-bit read command (00000011) is sent
first (C[7:0]), followed by the address of the location to be read (A[15:0]). BlueCore3-Multimedia External then
outputs on SPI_MISO a check word during T[15:0] followed by the 16-bit contents of the addressed location
during bits D[15:0].
The check word is composed of {command, address [15:8]}. The check word may be used to confirm a read
operation to a memory location. This overcomes the problems encountered with typical serial peripheral interface
slaves, whereby it is impossible to determine whether the data returned by a read operation is valid data or the
result of the slave device not responding.
If SPI_CSB is kept low, data from consecutive locations is read out on SPI_MISO for each subsequent 16 clocks,
until the transaction terminates when SPI_CSB is taken high.
Reset
End of Cycle
Read_Command
Address(A)
Check_Word
Data(A)
Data(A+1)
etc
SPI_CSB
SPI_CLK
C7
SPI_MOSI
SPI_MISO
Processor
State
C6
C1
C0 A15 A14
A1
A0
MISO Not Defined During Address
Don't Care
T15 T14
T1
T0
D15 D14
D1
D0 D15 D14
D1
D0
D15 D14
D1
D0
Processor
State
Figure 8.27: Read Operation
8.7.4
Multi Slave Operation
BlueCore3-Multimedia External should not be connected in a multi slave arrangement by simple parallel
connection of slave MISO lines. When BlueCore3-Multimedia External is deselected (SPI_CSB = 1), the
SPI_MISO line does not float, instead, BlueCore3-Multimedia External outputs 0 if the processor is running or 1 if
it is stopped.
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End of Cycle
Reset
Device Terminal Descriptions
8.8
Stereo Audio Interface
The main features of the interface are:
Stereo and mono analogue input for voice band and audio band
!
Stereo and mono analogue output for voice band and audio band
!
Support for stereo digital audio bus standards such as I2S
!
Support for IEC-60958 standard stereo digital audio bus standards i.e. S/PDIF and AES3/EBU
!
Support for PCM interfaces including PCM master CODECs that require an external system clock
AUDIO_IN_P_LEFT
Input
Amplifier
Σ∆−ADC
AUDIO_IN_N_LEFT
LP Filter
AUDIO_OUT_P_LEFT
Output
Amplifier
AUDIO_OUT_N_LEFT
DAC
Digital
Circuitry
AUDIO_IN_P_RIGHT
Input
Amplifier
Σ∆−ADC
AUDIO_IN_N_RIGHT
LP Filter
AUDIO_OUT_P_RIGHT
AUDIO_OUT_N_RIGHT
Output
Amplifier
DAC
Figure 8.28: Stereo CODEC Audio Input and Output Stages
The stereo audio CODEC uses a fully differential architecture in the analogue signal path, which results in low
noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from
a single power-supply of 1.8V and uses a minimum of external components.
Important Notes:
To avoid any confusion with respect to stereo operation this data sheet explicitly states which is the left and
right channel for audio input and output. With respect to software and any registers, channel 0 or channel A
represents the left channel and channel 1 or channel B represents the right channel for both input and
output.
For mono operation this data sheet uses the left channel for standard mono operation for audio input and
output and with respect to software and any registers, channel 0 or channel A represents the standard mono
channel for audio input and output. In mono operation the second channel which is the right channel,
channel 1 or channel B could be used as a second mono channel if required and this channel will be known
as the auxilliary mono channel for audio input and output.
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!
Device Terminal Descriptions
8.8.1
Stereo CODEC Setup
The configuration and control of the ADC is through VM functions which are described in appropriate BlueLab
Multimedia documentation. This section covers an overview of the parameters that can be set up using the VM
functions.
8.8.2
ADC
The ADC consists of two second order Sigma Delta converters allowing two separate channels that are identical
in functionality, as shown in Figure 8..
8.8.3
ADC Sample Rate Selection and Warping
Each ADC supports the following sample rates:
!
8kHz
!
11.025kHz
!
16kHz
!
22.05kHz
!
24kHz
!
32kHz
!
44.1kHz
One of the main concerns for stereo wireless music applications is the ability to keep sample rates for the
CODECs at both ends of the wireless link in synchronisation. A VM function adjusts the sample rate using a
‘warping’ function to tune the sample rate to the required value. The ADC warp function allows the sample rate to
17
be changed by ±3%, in steps of 1/2 , or 7.6 ppm. The warp function preserves the signal quality – the distortion
introduced when warping the sample rate is negligible.
8.8.4
ADC Gain
The ADC contains two gain stages for each channel, an analogue and a digital gain stage.
The digital gain stage has a programmable selection value in the range of 0 to 15 with the associated ADC gain
settings summarised in Table 8.20.
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The Kalimba DSP can communicate its requirements of the CODEC to the MCU and hence the VM by exchange
of messages. The messages used between the Kalimba DSP and the embedded MCU are based on interrupts:
one interrupt between the MCU and Kalimba DSP and one interrupt between the Kalimba DSP and the MCU.
Message content is transmitted using shared memory. There are VM and DSP library functions to send and
receive messages; for further details refer to BlueLab Multimedia documentation.
Device Terminal Descriptions
Gain Selection Value
ADC Digital Gain Setting (dB)
0
1
3.5
2
6
3
9.5
4
12
5
15.5
6
18
7
21.5
8
-24
9
-20.5
10
-18
11
-14.5
12
-12
13
-8.5
14
-6
15
-2.5
Table 8.20: ADC Digital Gain Rate Selection
The ADC analogue amplifier is a two stage amplifier. The first stage of the analogue amplifier is responsible for
selecting the correct gain for either microphone input or line input and therefore has two gain settings, one for the
microphone and one for the line input, see Section 8.8.24 and Section 8.8.25 for details on the microphone and
line inputs respectively. In simple terms the first stage amplifier has a selectable 20dB gain stage for the
microphone and this creates the dual programmable gain required for the microphone or the line input. The
equivalent block diagram for the two stage is shown in Figure 8.10.
2
Differential
20dB Gain
Selection.
Note: Input
Impedance
Function of Mode
Selection
Microphone
Line
3dB x 7 Steps
2
Ref
(0.66V)
A
Differential
First Stage
2
Differential
Second Stage
Figure 8.10: First Stage of ADC Analogue Amplifier Block Diagram
The second stage of the analogue amplifier shown in Figure 8.10 has a programmable gain with seven individual
3dB steps. In simple terms, by combining the 20dB gain selection of the microphone input with the seven
individual 3dB gain steps, the overall range of the analogue amplifier is approximately -4dB to 40dB. The overall
gain control of the ADC is controlled by the a VM function and this setting is a combined function of the digital
and analogue amplifier settings, so that the fullscale range of the input to the ADC is kept to approximately
400mV rms
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0
Device Terminal Descriptions
8.8.5
DAC
The DAC consists of two second order Sigma Delta converters allowing two separate channels that are identical
in functionality as shown in Figure 8..
DAC Sample Rate Selection and Warping
Each DAC supports the following samples rates:
!
48kHz
!
44.1kHz
!
32kHz
!
24kHz
!
22.050kHz
!
16kHz
!
11.025kHz
!
8kHz
Like the ADC, one of the main concerns for the DAC used in stereo wireless music applications is, the ability to
keep sample rates for the CODECs at both ends of the wireless link in synchronisation. A VM function adjusts the
sample rate using a ‘warping’ function to tune the sample rate to the required value. The DAC warp function
allows the sample rate to be changed by ±3%, in steps of 1/217, or 7.6 ppm. The warp function preserves the
signal quality – the distortion introduced when warping the sample rate is negligible.
8.8.7
DAC Gain
The DAC contains two gain stages for each channel, a digital and an analogue gain stage.
The digital gain stage has a programmable selection value in the range of 0 to 15 with associated DAC gain
settings summarised by Table 8.3.
Gain Selection Value
DAC Digital Gain Setting (dB)
0
0
1
3.5
2
6
3
9.5
4
12
5
15.5
6
18
7
21.5
8
-24
9
-20.5
10
-18
11
-14.5
12
-12
13
-8.5
14
-6
15
-2.5
Table 8.3: DAC Digital Gain Rate Selection
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8.8.6
Device Terminal Descriptions
The DAC analogue amplifier unlike the ADC is a single stage amplifier with the same structure as the second
stage of the ADC analogue amplifier as shown in Figure 8.10. The structure of the DAC analogue amplifier is
similar to the second stage of the ADC analogue amplifier, consisting of programmable gain with seven individual
3dB steps.
Analogue Gain Setting
Output Voltage
+3dB
1.40V
0dB
1.00V
-3dB
0.72V
-6dB
0.50V
-9dB
0.36V
-12dB
0.25V
-15dB
0.18V
-18dB
0.13V
Table 8.4: DAC Analogue Gain Settings
8.8.8
Mono Operation
Mono operation is single channel operation of the stereo CODEC. The left channel represents the single mono
channel for audio in and audio out. In mono operation the right channel is auxilliary mono channel that may be
used in dual mono channel operation. See Section 8.8 for an important note on stereo and mono definitions.
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The overall gain control of the DAC is controlled by the a VM function and this setting is a combined function of
the digital and analogue amplifier settings, therefore for a 1V rms nominal digital output signal from the digital
gain stage of the DAC, the following approximate output values of the analogue amplifier of the DAC can be
expected:
Device Terminal Descriptions
8.8.9
PCM CODEC Interface
Hardware on BlueCore3-Multimedia External allows the data to be sent to and received from a SCO connection.
Up to three SCO connections can be supported by the PCM interface at any one time.
BlueCore3-Multimedia External can operate as the PCM interface Master generating an output clock of 128, 256
or 512kHz. When configured as PCM interface slave it can operate with an input clock up to 2048kHz.
BlueCore3-Multimedia External is compatible with a variety of clock formats, including Long Frame Sync, Short
Frame Sync and GCI timing environments.
It supports 13 or 16-bit linear, 8-bit µ-law or A-law companded sample formats at 8ksamples/s and can receive
and transmit on any selection of three of the first four slots following PCM_SYNC. The PCM configuration options
are enabled by setting the PS Key PS KEY_PCM_CONFIG32 (0x1b3).
BlueCore3-Multimedia External interfaces directly to PCM audio devices including the following:
!
Qualcomm MSM 3000 series and MSM 5000 series CDMA baseband devices
!
OKI MSM7705 four channel A-law and µ-law CODEC
!
Motorola MC145481 8-bit A-law and µ-law CODEC
!
Motorola MC145483 13-bit linear CODEC
!
STW 5093 and 5094 14-bit linear CODECs
!
BlueCore3-Multimedia External is also compatible with the Motorola SSI™ interface
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Pulse Code Modulation (PCM) is a standard method used to digitise audio (particularly voice) for transmission
over digital communication channels. Through its PCM interface, BlueCore3-Multimedia External has hardware
support for continual transmission and reception of PCM data, thus reducing processor overhead for wireless
headset applications. BlueCore3-Multimedia External offers a bi directional digital audio interface that routes
directly into the baseband layer of the on chip firmware. It does not pass through the HCI protocol layer.
Device Terminal Descriptions
8.8.10 PCM Interface Master/Slave
When configured as the Master of the PCM interface, BlueCore3-Multimedia External generates PCM_CLK and
PCM_SYNC.
BlueCore3-Multimedia External
PCM_IN
PCM_CLK
PCM_SYNC
128/256/512kHz
8kHz
Figure 8.11: BlueCore3-Multimedia External as PCM Interface Master
When configured as the Slave of the PCM interface, BlueCore3-Multimedia External accepts PCM_CLK rates up
to 2048kHz.
BlueCore3-Multimedia External
PCM_OUT
PCM_IN
PCM_CLK
PCM_SYNC
Upto 2048kHz
8kHz
Figure 8.12: BlueCore3-Multimedia External as PCM Interface Slave
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PCM_OUT
Device Terminal Descriptions
8.8.11 Long Frame Sync
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
Undefined
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
8
Undefined
Figure 8.13: Long Frame Sync (Shown with 8-bit Companded Sample)
BlueCore3-Multimedia External samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on
the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB
position or on the rising edge.
8.8.12 Short Frame Sync
In Short Frame Sync the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always
one clock cycle long.
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
Undefined
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Undefined
Figure 8.14: Short Frame Sync (Shown with 16-bit Sample)
As with Long Frame Sync, BlueCore3-Multimedia External samples PCM_IN on the falling edge of PCM_CLK
and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling
edge of PCM_CLK in the LSB position or on the rising edge.
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Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or
samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When
BlueCore3-Multimedia External is configured as PCM Master, generating PCM_SYNC and PCM_CLK, then
PCM_SYNC is 8-bits long. When BlueCore3-Multimedia External is configured as PCM Slave, PCM_SYNC may
be from two consecutive falling edges of PCM_CLK to half the PCM_SYNC rate, i.e. 62.5µs long.
Device Terminal Descriptions
8.8.13 Multi Slot Operation
More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO
connections can be carried over any of the first four slots.
LONG_PCM_SYNC
SHORT_PCM_SYNC
PCM_CLK
PCM_OUT
1
2
3
4
5
6
7 8
1
2
3
4
5
6
7
PCM_IN
Do Not Care 1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
8
8 Do Not Care
Figure 8.15: Multi Slot Operation with Two Slots and 8-bit Companded Samples
8.8.14 GCI Interface
BlueCore3-Multimedia External is compatible with the General Circuit Interface, a standard synchronous 2B+D
ISDN timing interface. The two 64Kbps B channels can be accessed when this mode is configured.
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
Do Not
C a re
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
B1 Channel
Do Not
C a re
B2 Channel
Figure 8.16: GCI Interface
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With
BlueCore3-Multimedia External in Slave mode, the frequency of PCM_CLK can be up to 4.096MHz.
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Or
Device Terminal Descriptions
8.8.15 Slots and Sample Formats
BlueCore3-Multimedia External can receive and transmit on any selection of the first four slots following each
sync pulse. Slot durations can be either 8 or 16 clock cycles. Duration’s of 8 clock cycles may only be used with
8-bit sample formats. Durations of 16 clocks may be used with 8, 13 or 16-bit sample formats.
Sign
Extension
PCM_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
8-Bit
Sample
A 16-bit slot with 8-bit companded sample and sign extension selected.
8-Bit
Sample
PCM_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Zeros
Padding
A 16-bit slot with 8-bit companded sample and zeros padding selected.
Sign
Extension
PCM_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
15
16
13-Bit
Sample
A 16-bit slot with 13-bit linear sample and sign extension selected.
13-Bit
Sample
PCM_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Audio
Gain
A 16-bit slot with 13-bit linear sample and audio gain selected.
Figure 8.17: 16-Bit Slot Length and Sample Formats
8.8.16 Additional Features
BlueCore3-Multimedia External has a mute facility that forces PCM_OUT to be 0. In Master mode, PCM_SYNC
may also be forced to 0 while keeping PCM_CLK running which some CODECS use to control power down.
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BlueCore3-Multimedia External supports 13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats. The
sample rate is 8ksamples/s. The bit order may be little or big endian. When 16-bit slots are used, the 3 or 8
unused bits in each slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio
attenuation compatible with some Motorola CODECs.
Device Terminal Descriptions
8.8.17 PCM Timing Information
Symbol
PCM_CLK frequency
-
Min
4MHz DDS generation.
Selection of frequency is
programmable, see
Table 8.7
-
48MHz DDS generation.
Selection of frequency is
programmable, see
Table 8.8 and
Section 8.8.19
2.9
PCM_SYNC frequency
tmclkh
(1)
Typ
Max
128
256
-
kHz
-
kHz
512
-
8
PCM_CLK high
4MHz DDS generation
980
-
tmclkl
PCM_CLK low
4MHz DDS generation
730
-
-
PCM_CLK jitter
48MHz DDS generation
tdmclksynch
Delay time from PCM_CLK high to PCM_SYNC
high
-
tdmclkpout
Delay time from PCM_CLK high to valid PCM_OUT
tdmclklsyncl
(1)
Unit
kHz
-
ns
ns
21
ns pk-pk
-
20
ns
-
-
20
ns
Delay time from PCM_CLK low to PCM_SYNC low
(Long Frame Sync only)
-
-
20
ns
tdmclkhsyncl
Delay time from PCM_CLK high to PCM_SYNC low
-
-
20
ns
tdmclklpoutz
Delay time from PCM_CLK low to PCM_OUT high
impedance
-
-
20
ns
tdmclkhpoutz
Delay time from PCM_CLK high to PCM_OUT high
impedance
-
-
20
ns
tsupinclkl
Set-up time for PCM_IN valid to PCM_CLK low
30
-
-
ns
thpinclkl
Hold time for PCM_CLK low to PCM_IN invalid
10
-
-
ns
Table 8.5: PCM Master Timing
Note:
(1)
Assumes normal system clock operation. Figures will vary during low power modes, when system clock
speeds are reduced.
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fmclk
Parameter
Device Terminal Descriptions
t
t
dmclklsyncl
t
dmclksynch
dmclkhsyncl
PCM_SYNC
t
mlk
t
mclkh
mclkl
PCM_CLK
t
t
t ,t
dmclkpout
r
t
t
supinclkl
t
f
MSB (LSB)
PCM_OUT
dmclkhpoutz
LSB (MSB)
hpinclkl
MSB (LSB)
PCM_IN
dmclklpoutz
LSB (MSB)
Figure 8.18: PCM Master Timing Long Frame Sync
t dmclksynch
t dmclkhsyncl
PCM_SYNC
fmlk
t mclkh
t mclkl
PCM_CLK
t dmclklpoutz
t dmclkpout
PCM_OUT
MSB (LSB)
t supinclkl
PCM_IN
tr ,t f
t dmclkhpoutz
LSB (MSB)
t hpinclkl
MSB (LSB)
LSB (MSB)
Figure 8.19: PCM Master Timing Short Frame Sync
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f
Device Terminal Descriptions
8.8.18 PCM Slave Timing
Parameter
Min
Typ
Max
Unit
fsclk
PCM clock frequency (Slave mode: input)
64
-
2048
kHz
fsclk
PCM clock frequency (GCI mode)
128
-
4096
kHz
tsclkl
PCM_CLK low time
200
-
-
ns
tsclkh
PCM_CLK high time
200
-
-
ns
thsclksynch
Hold time from PCM_CLK low to PCM_SYNC high
30
-
-
ns
tsusclksynch
Set-up time for PCM_SYNC high to PCM_CLK low
30
-
-
ns
tdpout
Delay time from PCM_SYNC or PCM_CLK whichever is
later, to valid PCM_OUT data (Long Frame Sync only)
-
-
20
ns
tdsclkhpout
Delay time from CLK high to PCM_OUT valid data
-
-
20
ns
tdpoutz
Delay time from PCM_SYNC or PCM_CLK low, whichever
is later, to PCM_OUT data line high impedance
-
-
20
ns
tsupinsclkl
Set-up time for PCM_IN valid to CLK low
30
-
-
ns
thpinsclkl
Hold time for PCM_CLK low to PCM_IN invalid
30
-
-
ns
Table 8.6: PCM Slave Timing
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Symbol
Device Terminal Descriptions
f
t
sclk
t
sclkh
tsclkl
PCM_CLK
t
hsclksynch
susclksynch
PCM_SYNC
t
t
t
dpout
dsclkhpout
MSB (LSB)
PCM_OUT
t
supinsclkl
t
r
t
f
dpoutz
dpoutz
LSB (MSB)
hpinsclkl
MSB (LSB)
PCM_IN
t ,t
LSB (MSB)
Figure 8.20: PCM Slave Timing Long Frame Sync
fsclk
t sclkh
t tsclkl
PCM_CLK
t susclksynch
t hsclksynch
PCM_SYNC
t dsclkhpout
PCM_OUT
MSB (LSB)
t supinsclkl
PCM_IN
tr ,t f
t dpoutz
t dpoutz
LSB (MSB)
t hpinsclkl
MSB (LSB)
LSB (MSB)
Figure 8.21: PCM Slave Timing Short Frame Sync
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t
Device Terminal Descriptions
8.8.19 PCM_CLK and PCM_SYNC Generation
The Equation 8.10 describes PCM_CLK frequency when being generated using the internal 48MHz clock:
f =
CNT _ RATE
× 24MHz
CNT _ LIMIT
Equation 8.10: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock
The frequency of PCM_SYNC relative to PCM_CLK can be set using following equation:
f=
PCM _ CLK
SYNC _ LIMIT × 8
Equation 8.11: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an
example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set
PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
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BlueCore3-Multimedia External has two methods of generating PCM_CLK and PCM_SYNC in master mode. The
first is generating these signals by Direct Digital Synthesis (DDS) from BlueCore3-Multimedia External internal
4MHz clock (which is used in BlueCore2-External). Using this mode limits PCM_CLK to 128, 256 or 512kHz and
PCM_SYNC to 8kHz. The second is generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz
clock which allows a greater range of frequencies to be generated with low jitter but consumes more power. This
second method is selected by setting bit ‘48M_PCM_CLK_GEN_EN’ in PSKEY_PCM_CONFIG32. When in this
mode and with long frame sync, the length of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined
by ‘LONG_LENGTH_SYNC_EN’ in PSKEY_PCM_CONFIG32.
Device Terminal Descriptions
8.8.20 PCM Configuration
Name
Bit Position
Description
-
0
Set to 0.
SLAVE_MODE_EN
1
0 selects Master mode with internal generation of
PCM_CLK and PCM_SYNC. 1 selects Slave mode
requiring externally generated PCM_CLK and
PCM_SYNC.
SHORT_SYNC_EN
2
0 selects long frame sync (rising edge indicates start of
frame), 1 selects short frame sync (falling edge indicates
start of frame).
-
3
Set to 0.
SIGN_EXTEND_EN
4
0 selects padding of 8 or 13-bit voice sample into a 16bit slot by inserting extra LSBs, 1 selects sign extension.
When padding is selected with 13-bit voice sample, the
3 padding bits are the audio gain setting; with 8-bit
samples, the 8 padding bits are zeroes.
LSB_FIRST_EN
5
0 transmits and receives voice samples MSB first, 1
uses LSB first.
TX_TRISTATE_EN
6
0 drives PCM_OUT continuously, 1 tri-states PCM_OUT
immediately after the falling edge of PCM_CLK in the
last bit of an active slot, assuming the next slot is not
active.
TX_TRISTATE_RISING_EDGE_EN
7
0 tristates PCM_OUT immediately after the falling edge
of PCM_CLK in the last bit of an active slot, assuming
the next slot is also not active. 1 tristates PCM_OUT
after the rising edge of PCM_CLK.
SYNC_SUPPRESS_EN
8
0 enables PCM_SYNC output when master, 1
suppresses PCM_SYNC whilst keeping PCM_CLK
running. Some CODECS utilise this to enter a low power
state.
GCI_MODE_EN
9
1 enables GCI mode.
MUTE_EN
10
1 forces PCM_OUT to 0.
48M_PCM_CLK_GEN_EN
11
0 sets PCM_CLK and PCM_SYNC generation via DDS
from internal 4 MHz clock, as for BlueCore2-External. 1
sets PCM_CLK and PCM_SYNC generation via DDS
from internal 48 MHz clock.
LONG_LENGTH_SYNC_EN
12
0 sets PCM_SYNC length to 8 PCM_CLK cycles and 1
sets length to 16 PCM_CLK cycles. Only applies for long
frame sync and with 48M_PCM_CLK_GEN_EN set to 1.
-
[20:16]
Set to 0b00000.
MASTER_CLK_RATE
[22:21]
Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz
PCM_CLK frequency when master and
48M_PCM_CLK_GEN_EN (bit 11) is low.
ACTIVE_SLOT
[26:23]
Default is ‘0001’. Ignored by firmware.
SAMPLE_FORMAT
[28:27]
Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit
sample with 16 cycle slot duration or 8 (0b11) bit sample
with 8 cycle slot duration.
Table 8.7: PSKEY_PCM_CONFIG32 Description
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The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 and
PSKEY_PCM_LOW_JITTER_CONFIG. The following tables detail these PS Keys. PSKEY_PCM_CONFIG32.
The default for this key is 0x00800000 i.e. first slot following sync is active, 13-bit linear voice format, long frame
sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no tristating of
PCM_OUT. PSKEY_PCM_LOW_JITTER_CONFIG is described in Table 8.8.
Device Terminal Descriptions
Name
Bit Position
Description
CNT_LIMIT
[12:0]
Sets PCM_CLK counter limit.
CNT_RATE
[23:16]
Sets PCM_CLK count rate.
SYNC_LIMIT
[31:24]
Sets PCM_SYNC division relative to PCM_CLK.
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Table 8.8: PSKEY_PCM_LOW_JITTER_CONFIG Description
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Device Terminal Descriptions
8.8.21 Digital Audio Bus
The digital audio interface supports the industry standard formats for I2S, left-justified (LJ) or right-justified(RJ)(1).
The interface shares the same pins as the PCM interface as shown in Table 6.1 and the timing diagram is shown
in Figure 8.22.
Left Channel
Right Channel
SCK
SD_IN/OUT
MSB
LSB
MSB
LSB
Left-Justified Mode
WS
Left Channel
Right Channel
SCK
SD_IN/OUT
MSB
LSB
MSB
LSB
Right-Justified Mode
WS
Left Channel
Right Channel
SCK
SD_IN/OUT
MSB
LSB
MSB
LSB
I2S Mode
Figure 8.22: Digital Audio Interface Modes
The internal representation of audio samples within BlueCore3-Multimedia External is 16-bit and data on
SD_OUT is limited to 16-bit per channel. On SD_IN, if more than 16-bit per channel is present will round
th
considering the 17 bit.
SCK typically operates 64 x WS frequency and cannot be less than 36 x WS.
Note:
(1)
Subject to firmware support; contact CSR for current status.
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WS
Device Terminal Descriptions
Parameter
Minimum
Typical
Maximum
Unit
-
SCK Frequency
6.2
MHz
WS Frequency
96
kHz
tch
SCK high time
ns
tcl
SCK low time
ns
topd
SCK to SD_OUT delay
ns
tssu
WS to SCK high set-up time
ns
tsh
WS to SCK high hold time
ns
tisu
SD_IN to SCK high set-up time
ns
tih
SD_IN to SCK high hold time
ns
Table 8.9: Digital Audio Interface Slave Timing
WS(Input)
tssu
t ch
t sh
t cl
SCK(Input)
topd
SD_OUT
t isu
t ih
SD_IN
Figure 8.23: Digital Audio Interface Slave Timing
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Symbol
Device Terminal Descriptions
Symbol
Parameter
-
Minimum
Typical
Unit
SCK Frequency
6.2
MHz
-
WS Frequency
96
kHz
topd
SCK to SD_OUT delay
ns
tspd
SCK to WS delay
ns
tisu
SD_IN to SCK high set-up time
ns
tih
SD_IN to SCK high hold time
ns
Table 8.10: Digital Audio Interface Master Timing
WS(Output)
t spd
SCK(Output)
t opd
SD_OUT
t isu
t ih
SD_IN
Figure 8.24: Digital Audio Interface Master Timing
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Maximum
Device Terminal Descriptions
8.8.22 IEC 60958 Interface
The IEC 60958 interface is a digital audio interface that uses bi-phase coding to minimise the DC content of the
transmitted signal and allows the receiver to decode the clock information from the transmitted signal. The
IEC 60958 specification is based on the two industry standards AES/EBU and the Sony and Philips interface
specification SPDIF. The interface is compatible with IEC 60958-1, IEC 60958-3 and IEC 60958-4(1).
(1)
Subject to firmware support; contact CSR for current status.
The SPDIF interface signals are SPDIF_IN and SPDIF_OUT and are shared on the PCM interface pins as shown
in Figure 5.1. The input and output stages of the SPDIF pins can interface either 75Ω coaxial cable with an RCA
connector or there is an option to use an optical link that uses Toslink optical components. Typical output and
input stage interfaces for the coaxial solution interface is shown in Figure 8.25 and Figure 8.26 and the equivalent
optical solution is shown in Figure 8.27 and Figure 8.28.
74HCU04
10nF
SPDIF_OUT
RCA
Connector
100Ω
SPDIF Output
74HCU04
74HCU04
75Ω
74HCU04
Figure 8.25: Example Circuit for SPDIF Interface with Coaxial Output
Note:
The 100Ω and 75Ω resistors are dependent on the supply voltage and therefore subject to change
10KΩ
RCA
Connector
10nF
100Ω
SPDIF_IN
SPDIF Input
75Ω
74HCU04
74HCU04
Figure 8.26: Example Circuit for SPDIF Interface with Coaxial Input
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Note:
Device Terminal Descriptions
SPDIF_OUT
4
+5V
3
4.7Ω
TOTX173
8.2KΩ
100nF
1
Figure 8.27: Example Circuit for SPDIF Interface with Optical Output
Level Translator
SPDIF_IN
1
+5V
3
100nF
2
TORX173
47 µH
4
5
6
Figure 8.28: Example Circuit for SPDIF Interface with Optical Input
8.8.23 Audio Input Stage
The input stage of BlueCore3-Multimedia External consists of a low noise input amplifier, which receives its
analogue input signal from pins AUDIO_IN_P_LEFT and AUDIO_IN_N_LEFT to a second-order Σ-∆ ADC that
outputs a 4MBit/sec single-bit stream into the digital circuitry. The input can be configured to be either single
ended or fully differential. It can be programmed for either microphone or line input and has a 3-bit digital gain
setting of the input-amplifier in 3dB steps to optimize it for the use of different microphones.
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2
Device Terminal Descriptions
8.8.24 Microphone Input
The audio-input is intended for use from 1µA@94dB SPL to about 10µA@94dB SPL. With biasing-resistors R1
and R2 equal to 1kΩ, this requires microphones with sensitivity between about –40dBV and –60dBV. The
microphone for each channel should be biased as shown in Figure 8.29.
BlueCore3-Multimedia External
R2
C1
AUDIO_IN_P_LEFT
C3
R1
C4
+
C2
AUDIO_IN_N_LEFT
Input
Amplifier
MIC1
Figure 8.29: Microphone Biasing (Left Channel Shown)
The input impedance at AUDIO_IN_N_LEFT, AUDIO_IN_P_LEFT, AUDIO_IN_N_RIGHT and
AUDIO_IN_P_RIGHT is typically 20kΩ. C1 and C2 should be 47nF. R1 sets the microphone load impedance and
is normally in a range of 1 to 2 kΩ. R2, C3 and C4 improve the supply rejection by decoupling supply noise from
the microphone. Values should be selected as required in the specification. R2 may be connected to a
convenient supply, in which case the bias network is permanently enabled, or to the AUX_DAC output (which is
ground referenced and so provides good rejection of the supply), which maybe configured to provide bias only
when the microphone is required.
8.8.25 Line Input
If the input gain is set to less than 21dB BlueCore3-Multimedia External automatically selects line input mode. In
this mode the input impedance at AUDIO_IN_N_LEFT, AUDIO_IN_P_LEFT, AUDIO_IN_N_RIGHT and
AUDIO_IN_P_RIGHT are increased to 130kΩ typically. In line-input mode, the full-scale input signal is about
400mV rms. Figure 8.30 and Figure 8.31 show two circuits for line input operation and show connections for
either differential or single ended inputs.
C1
AUDIO_IN_P_LEFT
C2
AUDIO_IN_N_LEFT
Figure 8.30: Differential Input (Left Channel Shown)
C1
AUDIO_IN_P_LEFT
C2
AUDIO_IN_N_LEFT
Figure 8.31: Single Ended Input (Left Channel Shown)
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Microphone Bias
Device Terminal Descriptions
8.8.26 Output Stage
The output digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling frequency
to an 8 MBits/sec bit stream, which is fed into the analogue output circuitry.
AUDIO_OUT_P_LEFT
AUDIO_OUT_N_LEFT
Figure 8.32: Speaker Output (Left Channel Shown)
The gain of the output stage is controlled by a 3-bit programmable resistive divider, which sets the gain in steps
of approximately 3dB.
The single bit stream from the digital circuitry is low pass filtered by a second order bi-quad filter with a pole at
20kHz. The signal is then amplified in the fully differential output stage, which has a gain bandwidth of typically
1MHz. It uses its high open loop gain in the closed loop application circuit to achieve low distortion while
operating with low standing current.
8.9
I/O Parallel Ports
Fifteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[11:8] and PIO[3:0] are powered
from VDD_PIO. PIO[7:4] are powered from VDD_PADS. AIO [3:0] are powered from VDD_MEM.
PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines
are configured as inputs with weak pull-downs at reset.
PIO[0] and PIO[1] are normally dedicated to RXEN and TXEN respectively, but they are available for general
use.
Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or
PIO [2] can be configured as a request line for an external clock source. This is useful when the clock to
BlueCore3-Multimedia External is provided from a system application specific integrated circuit (ASIC).
BlueCore3-Multimedia External has four general purpose analogue interface pins, AIO[0], AIO[1], AIO[2] and
AIO[3]. These are used to access internal circuitry and control signals. One pin is allocated to decoupling for the
on-chip band gap reference voltage, the other three may be configured to provide additional functionality.
Auxiliary functions available via these pins include an 8-bit ADC and an 8-bit DAC. Typically the ADC is used for
battery voltage measurement. Signals selectable at these pins include the band gap reference voltage and a
variety of clock signals; 48, 24, 16, 8MHz and the XTAL clock frequency. When used with analogue signals the
voltage range is constrained by the analogue supply voltage (1.8V). When configured to drive out digital level
signals (clocks) generated from within the analogue part of the device, the output voltage level is determined by
VDD_MEM (1.8V).
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The output circuit comprises a digital to analogue converter with gain setting and output amplifier. Its class-AB
output-stage is capable of driving a signal on both channels of up to 2V pk-pk- differential into a load of 32Ω and
500pF with a typical THD+N of -74dBc. The output is available as a differential signal between
AUDIO_OUT_N_LEFT and AUDIO_OUT_P_LEFT for the left channel as shown in Figure 8.32; and between
AUDIO_OUT_N_RIGHT and AUDIO_OUT_P_RIGHT for the right channel. The output is capable of driving a
speaker directly if its impedance is at least 16Ω if only one channel is connected or an external regulator is used.
Device Terminal Descriptions
8.9.1
PIO Defaults for BTv1.2 HCI Level Bluetooth Stack
I/O Terminal
PIO[0]
Pull high on boot up to select USB transport rather than BCSP
Control output for external LNA after boot up completion
Pull high on boot up to select 16MHz reference clock frequency rather than 26MHz
Control output for external PA (Class 1 operation) after boot up completion
PIO[2]
Clock request output
PIO[3]
Clock request “OR” gate input
PIO[4]
UART Bypass (UART_TX)
PIO[5]
UART Bypass (UART_RTS)
PIO[6]
PIO[7]
UART Bypass (UART_CTS)
E2PROM (SCL)
UART Bypass (UART_RX)
E2PROM (SDA)
PIO[8]
E2PROM (write protect)
AIO[0]
32kHz sleep clock input
AIO[2]
Vref output. Must be decoupled
Table 8.11: PIO Defaults
Important Note:
CSR cannot guarantee that these terminal functions remain the same. Please refer to the software release
note for the implementation of these PIO lines, since they are firmware build specific.
8.10
I2C Interface
PIO[8:6] can be used to form a Master I2C interface. The interface is formed using software to drive these lines.
Therefore it is suited only to relatively slow functions such as driving a dot matrix liquid crystal display (LCD),
keyboard scanner or EEPROM.
Notes:
PIO lines need to be pulled-up through 2.2kΩ resistors.
PIO[7:6] dual functions, UART bypass and EEPROM support, therefore devices using an EEPROM cannot
support UART bypass mode.
For connection to EEPROMs, refer to CSR documentation on I2C EEPROMS for use with BlueCore. This
provides information on the type of devices which are currently supported.
+1.8V
10nF
2.2KΩ 2.2KΩ 2.2KΩ
U2
8
PIO[8]
PIO[6]
PIO[7]
7
6
5
VCC
A0
WP
A1
SCL
A2
SDA
GND
1
2
3
4
Serial EEPROM
(AT24C16A)
Figure 8.33: Example EEPROM Connection
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PIO[1]
Description
Device Terminal Descriptions
8.11
TCXO Enable OR Function
An OR function exists for clock enable signals from a host controller and BlueCore3-Multimedia External where
either device can turn on the clock without having to wake up the other device. PIO[3] can be used as the Host
clock enables input and PIO[2] can be used as the OR output with the TCXO enable signal from
BlueCore3-Multimedia External.
GSM System
TCXO
CLK IN
Enable
CLK REQ OUT
BlueCore System
CLK REQ IN/
PIO[3]
XTAL IN
CLK REQ OUT/
PIO[2]
Figure 8.34: Example TXCO Enable OR Function
On reset and up to the time the PIO has been configured, PIO[2] will be tri-stated. Therefore, the developer must
ensure that the circuitry connected to this pin is pulled via a 470kΩ resistor to the appropriate power rail. This
ensures that the TCXO is oscillating at start up.
8.12
RESET and RESETB
BlueCore3-Multimedia External may be reset from several sources: RESET or RESETB pins, power on reset, a
UART break character or via a software configured watchdog timer.
The RESET pin is an active high reset and is internally filtered using the internal low frequency clock oscillator. A
reset will be performed between 1.5 and 4.0ms following RESET being active. It is recommended that RESET be
applied for a period greater than 5ms. The RESETB pin is the active low version of RESET and is ‘ORed’ on chip
with the active high RESET with either causing the reset function.
The power on reset occurs when the VDD_CORE supply falls below typically 1.5V and is released when
VDD_CORE rises above typically 1.6V.
At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tristated. The PIOs have weak
pull-downs.
Following a reset, BlueCore3-Multimedia External assumes the maximum XTAL_IN frequency, which ensures
that the internal clocks run at a safe (low) frequency until BlueCore-Multimedia is configured for the actual
XTAL_IN frequency. If no clock is present at XTAL_IN, the oscillator in BlueCore3-Multimedia External free runs,
again at a safe frequency.
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VDD
Device Terminal Descriptions
8.12.1 Pin States on Reset
Table 8.12 shows the pin states of BlueCore3-Multimedia External on reset.
State: BlueCore3-Multimedia External
PIO[11:0]
Input with weak pull-down
PCM_OUT
Tri-stated with weak pull-down
PCM_IN
Input with weak pull-down
PCM_SYNC
Input with weak pull-down
PCM_CLK
Input with weak pull-down
UART_TX
Output tri-stated with weak pull-up
UART_RX
Input with weak pull-down
UART_RTS
Output tri-stated with weak pull-up
UART_CTS
Input with weak pull-down
USB_DP
Input with weak pull-down
USB_DN
Input with weak pull-down
SPI_CSB
Input with weak pull-up
SPI_CLK
Input with weak pull-down
SPI_MOSI
Input with weak pull-down
SPI_MISO
Output tri-stated with weak pull-down
AIO[3:0]
Output, driving low
RESET
Input with weak pull-down
RESETB
Input with weak pull-up
TEST_EN
Input with strong pull-down
AUX_DAC
High impedance
TX_A
High impedance
TX_B
High impedance
RX_IN
High impedance
XTAL_IN
High impedance, 250k to XTAL_OUT
XTAL_OUT
High impedance, 250k to XTAL_IN
_äìÉ`çêÉ»PJjìäíáãÉÇá~=bñíÉêå~ä Product Data Sheet
Pin Name
Table 8.12: Pin States of BlueCore3-Multimedia External on Reset
8.12.2 Status after Reset
The chip status after a reset is as follows:
!
Warm Reset: Baud rate and RAM data remain available
!
Cold Reset(1): Baud rate and RAM data not available
Note:
(1)
Cold Reset consititutes one of the following:
!
Power cycle
!
System reset (firmware fault code)
!
Reset signal, see Section 8.12
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Device Terminal Descriptions
8.13
Power Supply
8.13.1 Voltage Regulator
The regulator is switched into a low power mode when the device is sent into deep sleep mode. When the on
chip regulator is not required VDD_ANA is a 1.8V input and VREG_IN must be either open circuit or tied to
VDD_ANA.
8.13.2 Sequencing
It is recommended that VDD_CORE, VDD_RADIO, VDD_LO and VDD_ANA be powered at the same time. The
order of powering supplies for VDD_CORE, VDD_PIO, VDD_PADS and VDD_USB is not important. However if
VDD_CORE is not present, all inputs have a weak pull-down irrespective of the reset state.
8.13.3 Sensitivity to Disturbances
It is recommended that if you are supplying BlueCore3-Multimedia External from an external voltage source that
VDD_LO, VDD_ANA and VDD_RADIO should have less than 10mV rms noise levels between 0 to 10MHz.
Single tone frequencies are also to be avoided. A simple RC filter is recommended for VDD_CORE as this
reduces transients put back onto the power supply rails.
The remaining supplies VDD_MEM, VDD_PIO, VDD_PADS and VDD_USB can be connected together with the
VREG_IN to the 3.3V supply and simply decoupled as shown in Figure 11.10.1.
The transient response of the regulator is also important. At the start of a packet, power consumption will jump to
high levels, see average current consumption section. The regulator should have a response time of 20µs or
less, it is essential that the power rail recovers quickly.
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An on-chip linear voltage regulator can be used to power the 1.8V dependent supplies. It is advised that a
smoothing circuit using a 2.2µF low ESR capacitor and 2.2Ω resistor be placed on the output VDD_ANA adjacent
to VREG_IN.
Typical Audio CODEC Performance
9
Typical Audio CODEC Performance
9.1
Output
-70
-72
-74
-76
-78
Harmonic / dB0
-80
Measurements below noise floor
-82
-84
-86
-88
-90
-92
-94
-96
-98
-20.0
-18.0
-16.0
-14.0
-12.0
-10.0
-8.0
-6.0
-4.0
-2.0
0.0
Digital Level Relative to Full Scale
227mV
321mV
457mV
639mV
Figure 10.9.1: Relative Level of 2nd Harmonic to Fundamental, PL = 600Ω
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Relative Level of 2nd Harmonic to Fundamental as a Function of Digital Level
2nd Harmonic @ 600Ω load
Typical Audio CODEC Performance
Relative Level of 3rd Harmonic to Fundamental as a Function of Digital Level
3rd Harmonic @ 600Ω Load
-70
-72
-76
-78
-80
Harmonic / dB0
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
-20.0
-18.0
-16.0
231mV
324mV
639mV
904mV
-14.0
-12.0
462mV
-10.0
-8.0
-6.0
-4.0
-2.0
0.0
Digital Level Relative to Full Scale
Figure 10.9.2: Relative Level of 3rd Harmonic to Fundamental, PL = 600Ω
Note:
Signal below full scale – 7dB are below measurement system’s noise floor.
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-74
Typical Audio CODEC Performance
Relative Level of 2nd Harmonic to Fundamental as a Function of Digital Level
2nd Harmonic @ 32Ω Load
-70
-72
-76
-78
Harmonic / dB0
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-20.0
-18.0
-16.0
-14.0
-12.0
-10.0
-8.0
-6.0
-4.0
-2.0
0.0
)
Digital Level Relative to Full Scale
227mV
320mV
455mV
636mV
Figure 10.9.3: Relative Level of 2nd Harmonic to Fundamental, PL = 32Ω
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-74
Typical Audio CODEC Performance
Relative Level of 3rd Harmonic to Fundamental as a Function of Digital Level
3rd Harmonic @ 32Ω Load
-70
-72
-76
-78
Harmonic / dB0
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-20.0
-18.0
-16.0
-14.0
-12.0
-10.0
-8.0
-6.0
-4.0
-2.0
0.0
Digital Level Relative to Full Scale
227mV
320mV
455mV
636mV
Figure 10.9.4: Relative Level of 3rd Harmonic to Fundamental, PL = 32Ω
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-74
Typical Audio CODEC Performance
Relative Level of 2nd Harmonic to Fundamental as a Function of Digital Level
2nd Harmonic @ 22Ω Load
-70
-72
-76
-78
Harmonic / dB0
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-20.0
-18.0
-16.0
-14.0
-12.0
-10.0
-8.0
-6.0
-4.0
-2.0
0.0
Digital Level Relative to Full Scale
227mV
321mV
457mV
639mV
Figure 10.9.5: Relative Level of 2nd Harmonic to Fundamental, PL = 22Ω
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-74
Typical Audio CODEC Performance
Relative Level of 3rd Harmonic to Fundamental as a Function of Digital Level
3rd Harmonic @ 22Ω Load
-70
-72
-76
-78
Harmonic / dB0
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-20.0
-18.0
-16.0
-14.0
-12.0
-10.0
-8.0
-6.0
-4.0
-2.0
0.0
Digital Level Relative to Full Scale
227mV
320mV
455mV
639mV
Figure 10.9.6: Relative Level of 3rd Harmonic to Fundamental, PL = 22Ω
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-74
Typical Audio CODEC Performance
Noise Floor, Sample Rate = 44.1kHz, Noise A-Weighted in 17kHz Band Width
0
-10
-30
Noise / dBV
-40
-50
-60
-70
-80
-90
-100
-110
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
800.0
900.0
1000.0
Full Scale rms Output, mV
600ohm
22ohm
Figure 10.9.7: Noise Floor
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-20
Typical Audio CODEC Performance
THD+N, Input Signal is Full Scale Sine Wave at 1kHz, Sample Rate = 44.1kHz
0.200
0.180
0.140
THD+N %
0.120
0.100
0.080
0.060
0.040
0.020
0.000
10.0
100.0
1000.0
10000.0
Full Scale rms Output, mV
600ohm
22ohm
Figure 10.9.8: THD+N
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0.160
Application Schematic
10 Application Schematic
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Figure 11.10.1: Application Circuit for Radio Characteristics Specification with 7 x 7 VFBGA Package
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Package Dimensions
11 Package Dimensions
11.1
7 x 7 VFBGA 120-Ball Package
Bottom View
D
D1
PIN A1
PIN 1
CORNER
Y
A
B
C
D
E
F
G
H
J
K
L
M
N
0.1
Z
12X e
E1
E
A
B
C
D
E
F
G
H
J
K
L
M
N
13 12 11 10 9 8 7 6 5 4 3 2 1
120X "b
13 12 11 10 9 8 7 6 5 4 3 2 1
"0.15M M
"0.05M M
DETAIL K
//
3
0.1
1
Z X Y
Z
Z
A3
A
A2
SEE DETAIL K
A1
0.08
Z
SEATING PLANE
DIM
A
A1
Package: 7 x 7 x 1mm
MIN
TYP
MAX
1
0.18
0.28
A2
0.21 REF
A3
0.45 REF
b
0.27
0.5mm Pitch
2
120 Ball VFBGA
NOTES
1
DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER PARALLEL TO
DATUM PLANE Z.
2
DATUM Z IS DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS
3
PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE
0.37
D
7 BSC
E
e
7 BSC
0.5 BSC
D1
6 BSC
E1
6 BSC
VFBGA 120 BALLS
7 x 7 x 1 mm
(JEDEC-MO-225)
UNIT
MM
Figure 12.11.1: BlueCore3-Multimedia External 120-Ball VFBGA Package Dimensions
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X
Top View
Solder Profiles
12 Solder Profiles
The soldering profile depends on various parameters necessitating a set up for each application. The data here is
given only for guidance on solder re-flow. There are four zones:
Preheat Zone - This zone raises the temperature at a controlled rate, typically 1-2.5°C/s.
2.
Equilibrium Zone - This zone brings the board to a uniform temperature and also activates the flux.
The duration in this zone (typically 2-3 minutes) will need to be adjusted to optimise the out gassing of
the flux.
3.
Reflow Zone - The peak temperature should be high enough to achieve good wetting but not so high as
to cause component discoloration or damage. Excessive soldering time can lead to intermetallic growth
which can result in a brittle joint.
4.
Cooling Zone - The cooling rate should be fast, to keep the solder grains small which will give a longer
lasting joint. Typical rates will be 2-5°C/s.
12.1
Solder Re-flow Profile for Devices with Lead-Free Solder Balls
Composition of the solder ball: Sn 95.5%, Ag 4.0%, Cu 0.5%
Lead Free Reflow Solder Profile 2
300
250
Temperature (°C)
200
150
100
50
0
0
50
100
150
200
250
300
350
400
450
500
Time (s)
Figure 13.12.1: Typical Lead-Free Re-flow Solder Profile
Key features of the profile:
!
Initial Ramp = 1-2.5°C/sec to 175°C±25°C equilibrium
!
Equilibrium time = 60 to 180 seconds
!
Ramp to Maximum temperature (250°C) = 3°C/sec max.
!
Time above liquidus temperature (217°C): 45-90 seconds
!
Device absolute maximum reflow temperature: 260°C
Devices will withstand the specified profile. Lead-free devices will withstand up to 5 reflows to a maximum
temperature of 260°C.
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1.
Ordering Information
13 Ordering Information
13.1
BlueCore3-Multimedia External
Order Number
Type
UART and USB
120-Ball VFBGA
(Pb free)
Size
Shipment Method
7 x 7 x 1mm
Tape and reel
BC352239A-IVQ-E4(1)
Minimum Order Quantity
2kpcs Taped and Reeled
Note:
(1)
Until BlueCore3-Multimedia External reaches Production status order number is BC352239AES-IVQ-E4.
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Package
Interface Version
Contact Information
14 Contact Information
CSR Japan
CSR Korea
Churchill House
CSR KK
Cambridge Business Park
9F Kojimachi KS Square 5-3-3,
Rm. 1111 Keumgang Venturetel,
#1108 Beesan-dong,
Cowley Road
Kojimachi,
Dong An-ku, Anyang-city,
Cambridge CB4 0WZ
Chiyoda-ku,
Kyunggi-do 431-050,
United Kingdom
Tokyo 102-0083
Korea
Tel: +44 (0) 1223 692 000
Japan
Tel: +82 31 389 0541
Fax: +44 (0) 1223 692 001
Tel: +81-3-5276-2911
Fax : +82 31 389 0545
e-mail: [email protected]
Fax: +81-3-5276-2915
e-mail: [email protected]
e-mail: [email protected]
CSR Denmark
CSR Taiwan
CSR U.S.
Novi Science Park
Rm6A,6F, No. 118,
1651 N. Collins Blvd.
Niels Jernes Vej 10
Hsing-Shan Rd.,
Suite 210
9220 Aalborg East
NeiHu, Taipei,
Richardson
Denmark
Taiwan, R.O.C.
TX75080
Tel: +45 72 200 380
Tel: +886 2 7721 5588
Tel: +1 (972) 238 2300
Fax: +45 96 354 599
Fax: +886 2 7721 5589
Fax: +1 (972) 231 1440
e-mail: [email protected]
e-mail: [email protected]
e-mail: [email protected]
To contact a CSR representative, go to http://www.csr.com/contacts.htm
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CSR plc
Document References
15 Document References
Reference, Date:
Specification of the Bluetooth System
v1.2, 05 November 2003
Universal Serial Bus Specification
v2.0, 27 April 2000
2
Selection of I C EEPROMS for Use with BlueCore
bcore-an-008Pb, 30 September 2003
Selection of Flash Memory for Use with BlueCore
bcore-an-001Pd, 30 March 2004
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Document:
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Acronyms and Definitions
Acronyms and Definitions
Group term for CSR’s range of Bluetooth chips
Bluetooth™
Set of technologies providing audio and data transfer over short-range radio connections
CSR
Cambridge Silicon Radio
ACL
Asynchronous Connection-Less. A Bluetooth data packet.
ADC
Analogue to Digital Converter
AGC
Automatic Gain Control
A-law
Audio encoding standard
API
Application Programming Interface
ASIC
Application Specific Integrated Circuit
BCSP
BlueCore™ Serial Protocol
BER
Bit Error Rate. Used to measure the quality of a link
BIST
Built-In Self-Test
BMC
Burst Mode Controller
CFI
Common Flash Interface
CMOS
Complementary Metal Oxide Semiconductor
CODEC
Coder Decoder
CQDDR
Channel Quality Driven Data Rate
CSB
Chip Select (Active Low)
CSR
Cambridge Silicon Radio
CTS
Clear to Send
CVSD
Continuous Variable Slope Delta Modulation
DAC
Digital to Analogue Converter
dBm
Decibels relative to 1mW
DC
Direct Current
DFU
Device Firmware Upgrade
DSP
Digital Signal Processor
ESR
Equivalent Series Resistance
FIR
Finite Impulse Response
FSK
Frequency Shift Keying
GSM
Global System for Mobile communications
HCI
Host Controller Interface
IQ Modulation
In-Phase and Quadrature Modulation
IF
Intermediate Frequency
IIR
Infinite Impulse Response
ISDN
Integrated Services Digital Network
ISM
Industrial, Scientific and Medical
ksps
KiloSamples Per Second
L2CAP
Logical Link Control and Adaptation Protocol (protocol layer)
LC
Link Controller
LCD
Liquid Crystal Display
LFBGA
Low profile Fine Ball Grid Array
LJ
Left-Justified
LNA
Low Noise Amplifier
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BlueCore™
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Acronyms and Definitions
LPF
Low Pass Filter
LSB
Least-Significant Bit
MCU
MicroController Unit
µ-law
Audio Encoding Standard
MIPS
Million Instructions Per Second
Memory Management Unit
MISO
Master In Serial Out
OHCI
Open Host Controller Interface
PA
Power Amplifier
PCM
Pulse Code Modulation. Refers to digital voice data
PIO
Parallel Input Output
PLL
Phase Lock Loop
ppm
parts per million
PS Key
Persistent Store Key
RAM
Random Access Memory
REB
Read enable (Active Low)
REF
Reference. Represents dimension for reference use only.
RF
Radio Frequency
RFCOMM
Protocol layer providing serial port emulation over L2CAP
RISC
Reduced Instruction Set Computer
RJ
Right-Justified
rms
root mean squared
RoHS
The Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive
(2002/95/EC)
RSSI
Receive Signal Strength Indication
RTS
Ready To Send
RX
Receive or Receiver
SCO
Synchronous Connection-Oriented. Voice oriented Bluetooth packet
SD
Secure Digital
SDK
Software Development Kit
SDP
Service Discovery Protocol
SIG
Special Interest Group
SPI
Serial Peripheral Interface
SSI
Signal Strength Indication
TBD
To Be Defined
TX
Transmit or Transmitter
UART
Universal Asynchronous Receiver Transmitter
USB
Universal Serial Bus or Upper Side Band (depending on context)
VCO
Voltage Controlled Oscillator
VFBGA
Very Fine Ball Grid Array
VM
Virtual Machine
W-CDMA
Wideband Code Division Multiple Access
WEB
Write Enable (Active Low)
www
world wide web
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MMU
Record of Changes
Record of Changes
Revision
19FEB04
a
11AUG04
b
Reason for Change:
Original publication of this document. (CSR reference: BC352239A-ds-001Pa)
Update to external memory section.
Update to power consumption table, to include 'Digital audio processing subsystem'
figure. Datasheet still at Advance Information status.
Added typical audio CODEC performance data. Updated application schematic.
Added the following sub-sections:
15NOV04
c
!
8.1.2: Transmit Port Impedances for 7 x 7 VFBGA Package (2.4-2.5GHz
vs. Temperature)
!
8.1.3: Receive Port Impedances for 7 x 7 VFBGA Package (2.4-2.5GHz vs.
Temperature)
!
8.1.4: Transmit S Parameters
!
8.1.5:Balanced Receive S Parameters
Data Book and Data Sheet now have Production Information status.
BlueCore™3-Multimedia External
Product Data Sheet
BC352239A-ds-001Pc
November 2004
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Date: