TI1 DS100BR210SQ Ultra low power 10.3 gbps 2-channel repeater with input equalization and output de-emphasis Datasheet

DS100BR210
Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input
Equalization and Output De-Emphasis
General Description
Features
The DS100BR210 is an extremely low power, high performance dual-channel repeater for serial links with data rates
up to 10.3 Gbps. The DS100BR210 is configured as two unidirectional channels.
The DS100BR210 inputs feature a powerful 4-stage continuous time linear equalizer (CTLE) to provide a boost of up to
+36 dB at 5 GHz and open an input eye that is completely
closed due to inter-symbol interference (ISI) induced by the
interconnect mediums such as an FR-4 backplane or
AWG-30 cables. The transmitter features a programmable
output de-emphasis driver with up to -12 dB and allows amplitude voltage levels to be selected from 700 mVp-p to 1200
mVp-p to suit multiple application scenarios.
When configured as a 10G-KR repeater, the DS100BR210
allows the KR host and the end point to optimize the full link
by adjusting transmit and receive equalizer coefficients using
back-channel communication techniques specified by the
802.3ap standard.
The programmable settings can be applied via pin contol,
SMBus (I2C) protocol or an external EEPROM. When operating in the EEPROM mode, the configuration information is
automatically loaded on power up – This eliminates the need
for an external microprocessor or software driver.
Part of National's PowerWise family of energy efficient devices, the DS100BR210 consumes just 65 mW/channel (typical), and allows the option to turn-off unused channels. This
ultra low power consumption eliminates the need for external
heat sinks and simplifies thermal management in active cable
applications.
■ Two channel repeater for up to 10.3 Gbps
■
■
■
■
■
■
■
■
— DS100BR210 : 2x unidirectional channels
— DS100BR111 : 1x bidirectional lane
10G-KR bi-directional interface compatibility
— Allows for back-channel communication and training
Low 65mW/channel (typical) power consumption, with
option to power down unused channels
Advanced signal conditioning features
— Receive equalization up to +36 dB
— Transmit de-emphasis up to -12 dB
— Transmit VOD control: 700 to 1200 mVp-p
— < 0.3 UI of residual DJ at 10 Gbps
Programmable via pin selection, EEPROM or SMBus
interface
Single supply operation selectable: 2.5V or 3.3v
Flow-thru pinout in 4mmx4mm 24-pin leadless LLP
package
>5kV HBM ESD rating
Industrial -40 to 85°C operating temperature range
Applications
■ High-speed active copper cable modules and FR-4
backplane in communication systems
■ 10GE, 10G-KR, FC, SAS, SATA 3/6 Gbps (with OOB
detection), InfiniBand, CPRI, RXAUI and many others.
Typical Application
30175390
© 2012 Texas Instruments Incorporated
301753 SNLS348C
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DS100BR210 Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input Equalization and Output
De-Emphasis
April 9, 2012
DS100BR210
Block Diagram - Detail View Of Channel (1 Of 2)
30175386
Pin Diagram
30175324
DS100BR210 Pin Diagram 24 lead
Note 1: The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through multiple (minimum of 4) vias to
ensure optimal electrical and thermal performance.
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2
DS100BR210
Ordering Information
NSID
Qty
Spec
Package
DS100BR210SQ
Tape & Reel Supplied As 1,000 Units
NOPB
SQA24A
DS100BR210SQE
Tape & Reel Supplied As 250 Units
NOPB
SQA24A
3
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DS100BR210
Pin Descriptions
Pin Name
Pin Number
I/O, Type
Pin Descriptions
Differential High Speed I/O's
INA+, INA- ,
INB+, INB-,
7, 8
11, 12
I, CML
Inverting and non-inverting CML differential inputs to the
equalizer. A on-chip 50Ω termination resistor connects INx+ to
VDD and INx- to VDD when enabled.
OUTA+, OUTA-,
OUTB+, OUTB-,
24, 23
20, 19
O,CML
Inverting and non-inverting 50Ω driver outputs with de-emphasis.
Compatible with AC coupled CML inputs.
3
I, LVCMOS
Float
System Management Bus (SMBus) enable pin
Control Pins
ENSMB
Tie HIGH = Register Access, SMBus Slave mode
FLOAT = SMBus Master read from External EEPROM
Tie LOW = External Pin Control Mode
ENSMB = 1 (SMBUS MODE)
SCL
5
I, LVCMOS
O, Open
Drain
ENSMB Master or Slave mode
SMBUS clock input pin is enabled. A clock input in Slave mode.
Can also be a clock output in Master mode.
SDA
4
I, LVCMOS,
O, Open
Drain
ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open
drain (pull-down only) output.
AD0-AD3
10, 9, 2, 1
I, LVCMOS,
Float
(4-Levels)
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are
the user set SMBus slave address inputs. There are 16
addresses supported by these pins.
Pins must be tied LOW or HIGH when used to define the device
SMBus address.
Note: Setting VOD_SEL = High in SMBus Mode will force the
Address = B0'h
READEN#
17
I, LVCMOS
When using an External EEPROM, a transition from high to low
starts the load from the external EEPROM
DONE#
18
IO, LVCMOS, EEPROM Download Status
Float
HIGH indicates Error / Still Loading
(4-Levels)
LOW indicates download complete. No Error.
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1
10, 9
1, 2
I, LVCMOS,
Float
(4-Levels)
DEMA, DEMB
4, 5
IO, LVCMOS, DEMA/B controls the level of de-emphasis. The DEMA/B pins
Float
are only active when ENSMB is de-asserted (LOW). The default
(4-Levels)
SMBus setting is -3.5 dB. Each of the 4 A/B channels have the
same level unless controlled by the SMBus control registers.
When ENSMB goes high the SMBus registers provide
independent control of each lane and the DEM pins are
converted to SMBUS SCL and SDA pins.
Table 4: De-emphasis and Output Voltage Settings
TX_DIS
6
I, LVCMOS
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EQA/B ,0/1 control the level of equalization of each channel. The
EQA/B pins are active only when ENSMB is de-asserted (LOW).
When ENSMB goes high the SMBus registers provide
independent control of each lane, and the EQB0/B1 pins are
converted to SMBUS AD2/AD3 inputs.
Table 3: Equalizer Settings
DS100BR210
High = OUTA/B Disabled
Low = OUTA/B Enabled
4
Pin Number
I/O, Type
Pin Descriptions
VOD_SEL
17
I, LVCMOS,
Float
(4-Levels)
EQ Mode and VOD select.
High = 10G-KR Mode (VOD = 1.1V/1.3V)
Float = (VOD = 1.0 V)
20K = (VOD = 1.2 V)
Low = (VOD = 700m V)
Note: Setting VOD_SEL = High in SMBus Mode will force the
SMBus Address = B0'h
VDD_SEL
16
I, Internal
Pull-up
Enables the 3.3V to 2.5V internal regulator
Low = 3.3 V Operation
Float = 2.5 V Operation
MODE
18
I, LVCMOS,
Float
(4-Levels)
Controls Device Mode of Operation
13
O, Open
Drain
When HIGH, indicates Loss of Signal (Default is LOS on INA).
Can be modified via SMBus registers.
14
I, LVCMOS,
Float
(4-Levels)
The SD_TH pin controls LOS threshold setting;
Assert (mV), Deassert (mV)
20K = 160 mV, 100 mV
Float = 180 mV, 110 mV (Default)
High = 190 mV, 130 mV
Low = 210 mV, 150 mV
Note: Using values less than the default level can extend the
time required to detect LOS and are not recommended.
21, 22
Power
Power supply pins
High = Continuous Talk (no output IDLE)
Float = 10G-KR Mode, Slow OOB
20KΩ = eSATA Mode, Fast OOB, Auto Low Power on 100 uS of
inactivity. SD stays active.
Low = SAS Mode, Fast OOB
Status Output
LOS
LOS Threshold Input
SD_TH
Power
VDD
2.5V mode connect to 2.5V
3.3V mode do not connect to any supply voltage. Should be used
to attach external decoupling to device, 100 - 200 nF recommended.
NOTE: See Applications section for additional information.
VIN
15
Power
VIN = 3.3V +/-10% (input to internal LDO regulator)
NOTE: Must FLOAT for 2.5V operation. See Applications
section for additional information.
GND
DAP
Power
Ground pad (DAP - die attach pad).
Notes:
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not
guaranteed. Unless the "Float" level is desired; 4-Level input pins require a minimum 1K resistor to GND, VDD (in 2.5V
mode), or VIN (in 3.3V mode). For Additional information. Tables Table 2: 4-Level Control Pin Settings, Table 6: 4-Level
Input Voltage
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
5
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DS100BR210
Pin Name
DS100BR210
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
Supply Voltage (VIN)
LVCMOS Input/Output Voltage
CML Input Voltage
CML Input Current
Junction Temperature
Storage Temperature
ESD Rating
HBM, STD - JESD22-A114F
Symbol
100 V
1250 V
θJC
3.2°C/W
33.0°C/W
θJA, No Airflow, 4 layer JEDEC
For soldering specifications:
See product folder at www.national.com
www.national.com/ms/MS/MS-SOLDERING.pdf
-0.5V to +2.75V
-0.5V to +4.0V
-0.5V to +4.0V
-0.5V to (VDD+0.5)
-30 to +30 mA
125°C
-40°C to +125°C
Supply Voltage (2.5V mode)
Supply Voltage (3.3V mode)
Ambient Temperature
SMBus (SDA, SCL)
> 5 kV
Parameter
MM, STD - JESD22-A115-A
CDM, STD - JESD22-C101-D
Package Thermal Resistance
Conditions
Min
Typ
Min
2.375
3.0
-40
Typ
2.5
3.3
25
Max
Max
2.625
3.6
+85
3.6
Units
V
V
°C
V
Units
Power Supply Current
IDD
Supply Current
TX_DIS = LOW, EQ = ON
VOD_SEL = Float ( 1000 mV)
50
63
Auto Low Power Mode
TX_DIS = LOW, MODE = 20K
VID CHA and CHB = 0.0V
VOD_SEL = Float (1000 mV)
12
15
TX_DIS = HIGH (BR210)
12
mA
15
LVCMOS DC Specifications
VIH
High Level Input
Voltage
VIL
Low Level Input Voltage
VOH
High Level Output
Voltage
IOH = -4.0 mA
(Note 5)
VOL
Low Level Output
Voltage
IOL = 4.0 mA
IIN
Input Leakage Current
SCL and SDA
Vinput = 0V or VDD
VDD_SEL = Float
IIN-P
Input Leakage Current
4-Level Input
(Note 3)
2.0
VDD
V
GND
0.7
V
2.0
V
0.4
V
-15
+15
uA
Vinput = 0V or VIN
VDD_SEL = Low
-15
+15
Vinput = 0V or VDD - 0.05V
VDD_SEL = Float
Vinput = 0V or VIN - 0.05V
VDD_SEL = Low
-160
+80
uA
LOS and ENABLE / DISABLE Timing
TLOS_OFF
Input IDLE to Active
(Note 13)
RX_LOS response time
0.035
uS
TLOS_ON
Input Active to IDLE
(Note 13)
RX_LOS response time
0.4
uS
TOFF
TX Disable assert Time (Note 13)
TX_DIS = HIGH to
Output OFF
0.005
uS
TON
TX Disable negateTime (Note 13)
TX_DIS = LOW to
Output ON
0.150
uS
TLP_EXIT
Auto Low Power Exit
ALP to Normal
Operation
150
nS
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(Note 13)
6
Parameter
Conditions
TLP_ENTER
Auto Low Power Enter
Normal Operation to
Auto Low Power
(Note 13)
Min
Typ
Max
Units
100
uS
CML RECEIVER INPUTS
VTX
Source Transmit
Launch Signal Level
Default power-up conditions
ENSMB = 0 or 1
RLRX-IN
RX return loss
SDD11 @ 4.1 GHz
190
800
1600
-12
SDD11 @ 11.1 GHz
-8
SCD11 @ 11.1 GHz
-10
mV
dB
HIGH SPEED TRANSMITTER OUTPUTS
VOD1
Output Voltage
Differential Swing
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = LOW (700 mV
setting)
DE = LOW
500
650
800
VOD2
Output Voltage
Differential Swing
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = FLOAT (1000
mV setting)
DE = LOW
800
1000
1100
VOD3
Output Voltage
Differential Swing
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = 20K (1200 mV
setting)
DE = LOW
950
1150
1350
VOD_DE1
De-Emphasis Levels
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = FLOAT (1000
mV setting)
DE = FLOAT
- 3.5
dB
VOD_DE2
De-Emphasis Levels
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = FLOAT (1000
mV setting)
DE = 20K
- 6.0
dB
VOD_DE3
De-Emphasis Levels
OUT+ and OUT- AC coupled
and terminated by 50Ω to
GND
VOD_SEL = FLOAT (1000
mV setting)
DE = HIGH
- 9.0
dB
VCM-AC
Output Common-Mode AC Common Mode Voltage
Voltage
DE = 0 dB, VOD <= 1000 mV
4.5
mV (RMS)
VCM-DC
Output DC CommonMode Voltage
VIDLE
TX IDLE Output
Voltage
DC Common Mode Voltage
7
0
1.1
mVp-p
1.9
V
30
mV
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DS100BR210
Symbol
DS100BR210
Symbol
Parameter
Conditions
Min
Typ
Max
RLTX-DIFF
TX return loss
SDD22 @ 4.1 GHz
-13
SDD22 @ 11.1 GHz
-9
SCC22 @ 2.5 GHz
-22
Units
dB
SCC22 @ 11.1 GHz
-10
delta ZM
Transmitter
Termination Mismatch
Measured at DC operating
point
(Note 6)
2.5
%
TR/F
Transmitter Rise and
Fall Time
Measurement points at 20% 80%
(Note 14)
38
ps
TPD
Propagation Delay
Measured at 50% crossing
EQ = 00
230
ps
TCCSK
Channel to Channel
Skew
T = 25°C, VDD = 2.5V
7
ps
TPPSK
Part to Part Skew
T = 25°C, VDD = 2.5V
20
ps
TTX-IDLE-SET-TO-
Max time to transition to VIN = 1Vpp, 10 Gbps
idle after differential
EQ = 00, DE = 0
signal
6.5
ns
TTX-IDLE-TO-DIFF- Max time to transition to VIN = 1Vpp, 10 Gbps
valid differential signal EQ = 00, DE = 0
DATA
after idle
3.2
ns
TENV_DISTORT
3.3
ns
IDLE
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Active OOB timing
distortion, input active
time vs. output active
time
8
Parameter
Conditions
Min
Typ
Max
Units
RJ
Random Jitter
DJ1
Deterministic Jitter
No Media
Source Amplitude = 700 mV,
PRBS15 pattern,
10.3125 Gbps
VOD = Default, EQ =
minimum, DE = 0 dB
0.3
ps (RMS)
0.09
UI
Equalization
DJE1
Residual Deterministic 8 meter 30AWG Cable on
Jitter
Input
10.3125 Gbps
Source = 700 mV, PRBS15
pattern
EQ = 0F'h; See Figure 15
0.27
UI
DJE2
Residual Deterministic
30" 4-mil FR4 on Inputs
Jitter
Source = 700 mV, PRBS15
10.3125 Gbps
pattern
EQ = 16'h; See Figure 12
0.17
UI
Residual Deterministic 10” 4 mil stripline FR4 on
Jitter
Outputs
10.3125 Gbps
Source = 700 mV, PRBS15
pattern
EQ = Min, VOD = 1200 mV,
DE = 010'b
See Figure 17
0.13
UI
De-emphasis
DJD1
Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur, including inoperability and degradation of device
reliability and/or performance. Functional operation of the device and/or nondegradation at the Absolute Maximum Ratings or other conditions beyond
those indicated in the Recommended Operating Conditions is not implied.
The Recommended Operating Conditions indicate conditions at which the
device is functional and the device should not be operated beyond such
conditions. Absolute Maximum Numbers are guaranteed for a junction
temperature range of -40°C to +125°C. Models are validated to Maximum
Operating Voltages only.
Note 4: Typical jitter reported is determined by jitter decomposition software
on the DSA8200 Oscilloscope.
Note 5: VOH only applies to the DONE# pin; LOS, SCL, and SDA are opendrain outputs that have no internal pull-up capability. DONE# is a full
LVCMOS output with pull-up and pull-down capability
Note 6: Force +/- 100 uA on output, measure delta V on the Output and
calculate impedance. Mismatch is the percentage difference of OUTn+ and
OUTn- impedance driving the same logic state.
Note 3: Input is held to a maximum of 50 mV below VDD or VIN to simulate
the use of a 1K resistor on the input.
9
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DS100BR210
Symbol
OUTPUT JITTER SPECIFICATIONS: (Note 4)
DS100BR210
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
3.6
V
SERIAL BUS INTERFACE DC SPECIFICATIONS: (Note 7)
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
(Note 8)
CI
Capacitance for SDA and SCL
(Note 8, Note 9, Note 12)
RTERM
External Termination Resistance Pullup VDD = 3.3V,
pull to VDD = 2.5V ± 5% OR 3.3V ± (Note 8, Note 9, Note 10)
10%
Pullup VDD = 2.5V,
(Note 8, Note 9, Note 10)
2.1
4
mA
2.375
3.6
V
-200
+200
µA
10
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
ENSMB = FLOAT (Master Mode)
(Note 7)
280
400
400
kHz
520
kHz
TBUF
Bus Free Time Between Stop and
Start Condition
1.3
µs
THD:STA
Hold time after (Repeated) Start
At IPULLUP, Max
Condition. After this period, the first
clock is generated.
0.6
µs
TSU:STA
Repeated Start Condition Setup
Time
0.6
µs
TSU:STO
Stop Condition Setup Time
0.6
µs
THD:DAT
Data Hold Time
0
ns
TSU:DAT
Data Setup Time
100
ns
TLOW
Clock Low Period
1.3
µs
THIGH
Clock High Period
(Note 11)
50
µs
tF
Clock/Data Fall Time
(Note 11)
300
ns
tR
Clock/Data Rise Time
(Note 11)
300
ns
tPOR
Time in which a device must be
operational after power-on reset
(Note 11, Note 12)
500
ms
0.6
Note 7: EEPROM interface requires 400 KHz capable EEPROM device.
Note 8: Recommended value.
Note 9: Recommended maximum capacitance load per bus segment is 400pF.
Note 10: Maximum termination voltage should be identical to the device supply voltage.
Note 11: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
Note 12: Guaranteed by Design and/or characterization. Parameter not tested in production.
Note 13: Parameter not tested in production.
Note 14: Default VOD used for testing. DE = -1.5 dB level used to compensate for fixture attenuation.
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10
DS100BR210
Timing Diagrams
30175302
FIGURE 1. CML Output Transition Times
30175303
FIGURE 2. Propagation Delay Timing Diagram
11
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DS100BR210
30175304
FIGURE 3. Idle Timing Diagram
30175301
FIGURE 4. SMBus Timing Parameters
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12
The DS100BR210 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the
details associated with high-speed design as well as providing a clean power supply. Refer to the information below and Revision
4 of the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity design issues.
The control pins have been enhanced to have 4 different levels and provide a wider range of control settings. Refer to
Table 2: 4-Level Control Pin Settings
Pin Setting
Description
0
Tie pin to GND through a 1 KΩ resistor
R
Tie pin to ground through 20 KΩ resistor
Float
Float the pin (no connection)
1
Tie pin to VDD through a 1 KΩ resistor
Note: 4-Level IO pins require a 1K resistance to GND or VDD/VIN. It is possible to tie mulitple 4-level IO pins together with a single
resistor to GND or VDD/VIN. When multiple IOs are connected in parallel, the resistance to GND or VDD/VIN should be adjusted
to compensate. For 2 pins the optimal resistance is 500 Ohms, 3 pins = 330 Ohms, and 4 pins = 250 Ohms.
Note: For 2.5V mode the control pin logic 1 level is VDD (pins 21 and 22), in 3.3V mode the control pin logic 1 level is defined by
VIN (pin 15).
Table 3: Equalizer Settings
Level
EQA1/
EQB1
EQA0/
EQB0
EQ — 8 bits [7:0]
dB Boost at 5 Ghz
Suggested Media
1
2
0
0
0000 0000 = 0x00
2.5
FR4 < 5 inch trace
0
R
0000 0001 = 0x01
6.5
FR4 5 inch trace
3
0
Float
0000 0010 = 0x02
9
FR4 10 inch trace
4
0
1
0000 0011 = 0x03
11.5
FR4 15 inch trace
5
R
0
0000 0111 = 0x07
14
FR4 20 inch trace
6
R
R
0001 0101 = 0x15
15
FR4 25 inch trace
7
R
Float
0000 1011 = 0x0B
17
FR4 25 inch trace
8
R
1
0000 1111 = 0x0F
19
7m 30AWG Cable
9
Float
0
0101 0101 = 0x55
20
FR4 30 inch trace
10
Float
R
0001 1111 = 0x1F
23
8m 30 AWG Cable
FR4 35 inch trace
11
Float
Float
0010 1111 = 0x2F
25
10m 30 AWG Cable
12
Float
1
0011 1111 = 0x3F
27
10m - 12m, Cable
13
1
0
1010 1010 = 0xAA
30
14
1
R
0111 1111 = 0x7F
31
15
1
Float
1011 1111 = 0xBF
33
16
1
1
1111 1111 = 0xFF
34
Note: Settings are approximate and will change based on PCB material, trace dimensions, and driver waveform characteristics.
13
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DS100BR210
Functional Description
DS100BR210
Table 4: De-emphasis and Output Voltage Settings
Level
VOD_SEL
DEMA/B
SMBus Register DEM Level
SMBus Register VOD
Level
VOD (mV)
DEM (dB)
1
0
0
000
000
700
0
2
0
Float
010
000
700
- 3.5
3
0
R
011
000
700
-6
4
0
1
101
000
700
-9
5
Float
0
000
011
1000
0
6
Float
Float
010
011
1000
- 3.5
7
Float
R
011
011
1000
-6
8
Float
1
101
011
1000
-9
9
R
0
000
101
1200
-0
10
R
Float
010
101
1200
- 3.5
11
R
R
011
101
1200
-6
12
R
1
101
101
1200
-9
13
1
0
000
100
1100
0
14
1
Float
001
110
1300
- 1.5
15
1
R
001
100
1100
- 1.5
16
1
1
010
110
1300
- 3.5
Note: When VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the DS100BR210 will support 10G-KR back-channel
communication using pin control.
Note: In SMBus Mode if VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the DS100BR210 AD0-AD3 pins are internally
forced to 0'h
Table 5: Signal Detect Threshold Level
SD_TH
SMBus REG bit
[3:2] and [1:0]
Assert Level (Typical)
De-assert Level (Typical)
0
10
210 mV
150 mV
20K to GND
01
160 mV
100 mV
Float (Default)
00
180 mV
110 mV
1
11
190 mV
130 mV
Note: VDD = 2.5V, 25°C, and 010101 pattern at 10 Gbps
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14
4-Level Input Configuration Guidelines
The 4-level input pins utilize a resistor divider to help set the
4 valid levels. There is an internal 30K pull-up and a 60K pulldown connected to the package pin. These resistors, together
with the external resistor connection combine to achieve the
desired voltage level. Using the 1K pull-up, 1K pull-down, no
connect, and 20K pull-down provide the optimal voltage levels
for each of the four input states.
Table 6: 4-Level Input Voltage
•
Level
Setting
3.3V Mode
2.5V Mode
0
01K to GND
0.1 V
0.08 V
R
20K to GND
0.33 * VIN
0.33 * VDD
F
FLOAT
0.67 * VIN
0.67 * VDD
1
1K to VDD/VIN
VIN - 0.05V
VIN - 0.04V
Power Supply Configuration Guidelines
The DS100BR210 can be configured for 2.5V operation or
3.3V operation. The lists below outline required connections
for each supply selection.
Typical 4-Level Input Thresholds
— Level 1 - 2 = 0.2 VIN or VDD
— Level 2 - 3 = 0.5 VIN or VDD
— Level 3 - 4 = 0.8 VIN or VDD
3.3V Mode of Operation
1. Tie VDD_SEL = 0 with 1K resistor to GND.
2. Feed 3.3V supply into VIN pin. Local 1.0 uF decoupling
at VIN is recommended.
3. See information on VDD bypass below.
4. SDA and SCL pins should connect pull-up resistor to VIN
5. Any 4-Level input which requires a connection to "Logic
1" should use a 1K resistor to VIN
In order to minimize the startup current associated with the
integrated 2.5V regulator the 1K pull-up / pull-down resistors
are recommended. If several 4 level inputs require the same
setting, it is possible to combine two or more 1K resistors into
a single lower value resistor. As an example; combining two
inputs with a single 500Ω resistor is a good way to save board
space.
2.5V Mode of Operation
1. VDD_SEL = Float
2. VIN = Float
3. Feed 2.5V supply into VDD pins.
4. See information on VDD bypass below.
5. SDA and SCL pins connect pull-up resistor to VDD for
2.5V uC SMBus IO
6. SDA and SCL pins connect pull-up resistor to 3.3V for
3.3V uC SMBus IO
7. Any 4-Level input which requires a connection to "Logic
1" should use a 1K resistor to VDD
Note: The DAP (bottom solder pad) is the GND connection.
10G-KR Configuration Guidelines
When configured in "KR Mode", using eith the VOD_SEL pin
setting or SMBus register control, the DS100BR210 is designed to operate transparently within a KR backplance channel environment. Installing a DS100 repeater within the KR
backplane channel splits the total channel attenuation into
two parts. Ideally the repeater can be placed near the middle
of the channel maximizing the signal to noise ratio across the
bidirectional interface.
In order to maximize the 10G-KR solution space, the 802.3ap
specification calls for an optimization of the transmit signal
conditioning coefficients based on feedback for the KR receiver. Setting the DS100BR210 active CTLE to compensate
for the channel loss from each of the KR transmitters will reduce the transmit and receive equalization settings required
on the KR physical layer devices. This central location keeps
a larger S/N raito at all points in the channel, extending the
available solution space and increasing the overall margin of
almost any channel.
Power Supply Bypass
Two approaches are recommended to ensure that the
DS100BR210 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.1 μF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the device. Smaller
body size capacitors can help facilitate proper component
placement.
PCB Layout Guidelines
The CML inputs and outputs have been optimized to work with
interconnects using a controlled differential impedance of 85
- 100Ω. It is preferable to route differential lines exclusively on
one layer of the board, particularly for the input traces. The
use of vias should be avoided if possible. If vias must be used,
they should be used sparingly and must be placed symmet-
15
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DS100BR210
rically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a
low inductance path for the return currents as well. Route the
differential signals away from other signals and noise sources
on the printed circuit board. See AN-1187 for additional information on LLP packages.
Different transmission line topologies can be used in various
combinations to achieve the optimal system performance.
Impedance discontinuities at vias can be minimized or eliminated by increasing the swell around each hole and providing
for a low inductance return current path. When the via structure is associated with thick backplane PCB, further optimization such as back drilling is often used to reduce the
detrimental high frequency effects of stubs on the signal path.
APPLICATIONS INFORMATION
DS100BR210
IDLE: If SCL and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
System Management Bus (SMBus) and Configuration
Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be pulled
high to enable SMBus mode and allow access to the configuration registers.
The DS100BR210 has AD[3:0] inputs in SMBus mode. These
pins are the user set SMBus slave address inputs. When
pulled low the AD[3:0] = 0000'b, the device default address
byte is B0'h. Based on the SMBus 2.0 specification, this configuration results in a 7-bit slave address of 1011000'b. The
LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1011
0000'b or B0'h. The device address byte can be set with the
use of the AD[3:0] inputs.
Shown in the form of an expression:
Slave Address [7:4] = The DS100BR210 hardware address
(1011'b) + Address pin AD[3]
Slave Address [3:1] = Address pins AD[2:0]
Slave Address [0] = 0'b for a WRITE or 1'b for a READ
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Slave Address Examples:
• AD[3:0] = 0001'b, the device slave address byte is B2'h
— Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h
— Slave Address [3:1] = 001'b
— Slave Address [0] = 0'b for a WRITE
• AD[3:0] = 0010'b, the device slave address byte is B4'h
— Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h
— Slave Address [3:1] = 010'b
— Slave Address [0] = 0'b for a WRITE
• AD[3:0] = 0100'b, the device slave address byte is B8'h
— Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h
— Slave Address [3:1] = 100'b
— Slave Address [0] = 0'b for a WRITE
• AD[3:0] = 1000'b, the device slave address byte is C0'h
— Slave Address [7:4] = 1011'b + 1'b = 1100'b or C'h
— Slave Address [3:1] = 000'b
— Slave Address [0] = 0'b for a WRITE
READING A REGISTER
To read a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the
READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Please see SMBus Register Map Table for more information.
TRANSFER OF DATA VIA THE SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High
indicates a message STOP condition.
30175305
FIGURE 5. Typical SMBus Write Operation
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16
The DS100BR210 device supports reading directly from an external EEPROM device by implementing SMBus Master mode. When
using the SMBus master mode, the DS100 will read directly from specific location in the external EEPROM. When designing a
system for using the external EEPROM, the user needs to follow these specific guidelines.
•
•
•
•
•
•
•
•
Set the DS100BR210 into SMBus Master Mode
— Float ENSMB (PIN 3)
The external EEPROM device must support 400 KHz operation
The external EEPROM device address byte must be 0xA0'h
Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h.
Based on the SMBus 2.0 specification, a device can have a 7-bit slave address of 1010 000'b. The LSB is set to 0'b (for a
WRITE). The bit mapping for SMBus is listed below:
— [7:5] = Reserved Bits from the SMBus specification
— [4:1] = Usable SMBus Address Bits
— [0] = Write Bit
The DS100BR210 device has AD[3:0] inputs in SMBus mode (pins 1, 2, 9, 10). These pins set SMBus slave address. When
the AD[3:0] = 0001'b, the device address byte is B2'h.
— [7:5] = Default to 3b'101
— [4:1] = Address of 4'b0001
— [0] = Write Bit, 1'b0
The device address can be set with the use of the AD[3:0] input up to 16 different addresses. Use the example below to set
each of the SMBus addresses.
— AD[3:0] = 0001'b, the device address byte is B2'h
— AD[3:0] = 0010'b, the device address byte is B4'h
— AD[3:0] = 0011'b, the device address byte is B6'h
— AD[3:0] = 0100'b, the device address byte is B8'h
The master implementation in the DS100BR210, supports multiple devices reading from 1 EEPROM. When tying multiple
devices to the SDA and SCL pins, use these guidelines:
— Use adjacent SMBus addresses for the 4 devices
— Use a pull-up resistor on SDA; value = 4.7KΩ
— Use a pull-up resistor on SCL: value = 4.7KΩ
— Daisy-chain READEN# (pin 17) and DONE# (pin18) from one device to the next device in the sequence
1. Tie READEN# of the 1st device in the chain (U1) to GND
2. Tie DONE# of U1 to READEN# of U2
3. Tie DONE# of U2 to READEN# of U3
4. Tie DONE# of U3 to READEN# of U4
5. Optional: Tie DONE# of U4 to a LED to show each of the devices have been loaded successfully
17
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DS100BR210
EEPROM Modes in the DS100BR210
DS100BR210
Master EEPROM Mode in the DS100BR210
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS100BR210 device. The first 3 bytes of the EEPROM
always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag
to enable/disable CRC checking. There is a MAP bit to flag the presence of an address map that specifies the configuration data
start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS100BR210 address
and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM.
There are 37 bytes of data size for each DS100BR210 device.
30175315
FIGURE 6. Typical EEPROM Data Set
The CRC-8 calculation is performed on the first 3 bytes of header information plus the 37 bytes of data for the DS100BR210 or 40
bytes in total. The result of this calculation is placed immediately after the DS100BR210 data in the EEPROM which ends with
"5454". The CRC-8 in the DS100BR210 uses a polynomial = x8 + x2 + x + 1
In SMBus master mode the DS100BR210 reads its initial configuration from an external EEPROM upon power-up. Some of the
pins of the DS100BR210 perform the same functions in SMBus master and SMBus slave mode. Once the DS100BR210 has
finished reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus slave mode and
can be further configured by an external controller over the SMBus. The connection to an external SMBus master is optional and
can be omitted for applications were additional security is desirable. There are two pins that provide unique functions in SMBus
master mode.
•
•
DONE#
READEN#
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18
30175316
FIGURE 7. Typical multi-device EEPROM connection diagram
19
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DS100BR210
When the DS100BR210 is powered up in SMBus master mode, it reads its configuration from the external EEPROM when the
READEN# pin goes low. When the DS100BR210 is finished reading its configuration from the external EEPROM, it drives the
DONE# pin low. In applications where there is more than one DS100BR210 on the same SMBus, bus contention can result if more
than one DS100BR210 tries to take control of the SMBus at the same time. The READEN# and DONE# pins prevent this bus
contention. The system should be designed so that the READEN# pin from one DS100BR210 in the system is driven low on powerup. This DS100BR210 will take command of the SMBus on power-up and will read its initial configuration from the external
EEPROM. When it is finished reading its configuration, it will drive the DONE# pin low. This pin should be connected to the
READEN# pin of another DS100BR210. When this DS100BR210 senses its READEN# pin driven low, it will take command of the
SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE# pin low. By connecting the
DONE# pin of each DS100BR210 to the READEN# pin of the next DS100BR210, each DS100BR210 can read its initial configuration from the EEPROM without causing bus contention.
DS100BR210
Table 7: Multi-Device EEPROM Register Map Overview
Addr Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
BIt 0
0
CRC EN
Address
Map
EEPROM > Reserved
256 Bytes
COUNT[3]
COUNT[2]
COUNT[1]
COUNT[0]
1
Reserved
Reserved
2
EE Burst[7] EE Burst[6] EE Burst[5] EE Burst[4] EE Burst[3]
Reserved
Reserved
Reserved
Reserved
Reserved
EE Burst[2]
EE Burst[1]
EE Burst[0]
Device 0 3
Info
4
CRC[7]
CRC[6]
CRC[5]
CRC[4]
EE AD0 [7]
EE AD0 [6]
EE AD0 [5]
EE AD0 [4]
CRC[3]
CRC[2]
CRC[1]
CRC[0]
EE AD0 [3]
EE AD0 [2]
EE AD0 [1]
Device 1 5
Info
6
CRC[7]
CRC[6]
CRC[5]
EE AD0 [0]
CRC[4]
CRC[3]
CRC[2]
CRC[1]
CRC[0]
EE AD1 [7]
EE AD1 [6]
Device 2 7
Info
8
CRC[7]
CRC[6]
EE AD1 [5]
EE AD1 [4]
EE AD1 [3]
EE AD1 [2]
EE AD1 [1]
EE AD1 [0]
CRC[5]
CRC[4]
CRC[3]
CRC[2]
CRC[1]
EE AD2 [7]
CRC[0]
EE AD2 [6]
EE AD2 [5]
EE AD2 [4]
EE AD2 [3]
EE AD2 [2]
EE AD2 [1]
Device 3 9
Info
10
EE AD2 [0]
CRC[7]
CRC[6]
CRC[5]
CRC[4]
CRC[3]
CRC[2]
CRC[1]
CRC[0]
Device 0 11
Addr 3
EE AD3 [7]
EE AD3 [6]
EE AD3 [5]
EE AD3 [4]
EE AD3 [3]
EE AD3 [2]
EE AD3 [1]
EE AD3 [0]
RES
RES
RES
RES
RES
RES
RES
RES
Device 0 12
Addr 4
RES
RES
PDWN Inp
PDWN OSC RES
eSATA CHA eSATA CHB Ovrd TX_DIS
Device 0 46
Addr 38
RES
RES
RES
RES
RES
RES
RES
RES
Device 0 47
Addr 39
DRES
RES
RES
RES
RES
RES
RES
RES
Device 1 48
Addr 3
RES
RES
RES
RES
RES
RES
RES
RES
Device 1 49
Addr 4
RES
RES
PDWN Inp
PDWN OSC RES
eSATA CHA eSATA CHB Ovrd TX_DIS
Device 1 83
Addr 38
RES
RES
RES
RES
RES
RES
RES
RES
Device 1 84
Addr 39
RES
RES
RES
RES
RES
RES
RES
RES
Device 2 85
Addr 3
RES
RES
RES
RES
RES
RES
RES
RES
Device 2 86
Addr 4
RES
RES
PDWN Inp
PDWN OSC RES
eSATA CHA eSATA CHB Ovrd TX_DIS
Device 2 120
Addr 38
RES
RES
RES
RES
RES
RES
RES
RES
Device 2 121
Addr 39
RES
RES
RES
RES
RES
RES
RES
RES
Device 3 122
Addr 3
RES
RES
RES
RES
RES
RES
RES
RES
Device 3 123
Addr 4
RES
RES
PDWN Inp
PDWN OSC RES
eSATA CHA eSATA CHB Ovrd TX_DIS
Device 3 157
Addr 38
RES
RES
RES
RES
RES
RES
RES
RES
Device 3 158
Addr 39
RES
RES
RES
RES
RES
RES
RES
RES
Header
•
•
•
•
Bit 4
Reserved
CRC EN = 1; Address Map = 1
EEPROM > 256 Bytes = 0
COUNT[3:0] = 0011'b
Note: Multiple DS100BR210 devices may point at the same address space if they have identical programming values.
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20
EEPROM
Address Byte
Bit 7
Bit 6
Bit 5
CRC EN
Address
Map
Present
Value
0
Description 1
RES
Value
0
0
Description
2
Bit 4
Bit 3
Bit 2
Bit 1
BIt 0
EEPROM > RES
256 Bytes
COUNT[3]
COUNT[2]
COUNT[1]
COUNT[0]
0
0
0
0
0
0
0
RES
RES
RES
RES
RES
RES
RES
0
0
0
0
0
0
0
Description
Max
Max
Max
Max
Max
Max
Max
Max
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Burst size[7] Burst size[6] Burst size[5] Burst size[4] Burst size[3] Burst size[2] Burst size[1] Burst size[0]
Value
0
0
0
0
0
0
0
0
Description 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register
0x01 [7]
0x01 [6]
0x01 [5]
0x01 [4]
0x01 [3]
0x01 [2]
0x01 [1]
0x01 [0]
Value
0
0
0
0
0
0
0
0
Description 4
Ovrd_LOS
LOS_Value PDWN Inp
PWDN Osc Reserved
eSATA
Enable A
eSATA
Enable B
Ovrd
TX_DIS
Register
0x02 [5]
0x02 [4]
0x02 [3]
0x02 [2]
0x02 [0]
0x04 [7]
0x04 [6]
0x04 [5]
Value
0
0
0
0
0
0
0
0
Description 5
TX_DIS
CHA
TX_DIS
CHB
Reserved
EQ Stage 4 EQ Stage 4
CHB
CHA
Reserved
Overide
IDLE_th
Reserved
Register
0x04 [4]
0x04 [3]
0x04 [2]
0x04 [1]
0x04 [0]
0x06 [4]
0x08 [6]
0x08 [5]
Value
0
0
0
0
0
1
0
0
Description 6
Ovrd_IDLE
Reserved
Ovrd_Out
Mode
Reserved
Reserved
Reserved
Reserved
Reserved
Register
0x08 [4]
0x08 [3]
0x08 [2]
0x08 [1]
0x08 [0]
0x0B [6]
0x0B [5]
0x0B [4]
Value
0
0
0
0
0
1
1
1
Description 7
Reserved
Reserved
Reserved
Reserved
Idle auto A
Idle sel A
Reserved
Reserved
Register
0x0B [3]
0x0B [2]
0x0B [1]
0x0B [0]
0x0E [5]
0x0E [4]
0x0E [3]
0x0E [2]
Value
0
0
0
0
0
0
0
0
Description 8
CHA EQ[7]
CHA EQ[6]
CHA EQ[5]
CHA EQ[4]
CHA EQ[3]
CHA EQ[2]
CHA EQ[1]
CHA EQ[0]
Register
0x0F [7]
0x0F [6]
0x0F [5]
0x0F [4]
0x0F [3]
0x0F [2]
0x0F [1]
0x0F [0]
Value
0
0
1
0
1
1
1
1
Description 9
A Sel scp
A Out Mode Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register
0x10 [7]
0x10 [6]
0x10 [5]
0x10 [4]
0x10 [3]
0x10 [2]
0x10 [1]
0x10 [0]
Value
1
1
1
0
1
1
0
1
Description 1
0
Register
DEMA[2]
DEMA[1]
DEMA[0]
CHA Slow
IDLE thA[1]
IDLE thA[0]
IDLE thD[1]
IDLE thD[0]
0x11 [2]
0x11 [1]
0x11 [0]
0x12 [7]
0x12 [3]
0x12 [2]
0x12 [1]
0x12 [0]
Value
0
1
0
0
0
0
0
0
Description 1
1
Register
Idle auto B
Idle sel B
Reserved
Reserved
CHB EQ[7]
CHB EQ[6]
CHB EQ[5]
CHB EQ[4]
0x15 [5]
0x15 [4]
0x15 [3]
0x15 [2]
0x16 [7]
0x16 [6]
0x16 [5]
0x16 [4]
Value
0
0
0
0
0
0
1
0
Description 1
2
Register
CHB EQ[3]
CHB EQ[2]
CHB EQ[1]
CHB EQ[0]
B Sel scp
B Out Mode
Reserved
Reserved
0x16 [3]
0x16 [2]
0x16 [1]
0x16 [0]
0x17 [7]
0x17 [6]
0x17 [5]
0x17 [4]
Value
1
1
1
1
1
1
1
0
Description 1
3
Register
Reserved
Reserved
Reserved
Reserved
CHB DEM[2] CHB DEM[1] CHB DEM[0] CHB Slow
0x17 [3]
0x17 [2]
0x17 [1]
0x17 [0]
0x18 [2]
0x18 [1]
0x18 [0]
0x19 [7]
Value
1
1
0
1
0
1
0
0
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DS100BR210
Table 8: Single EEPROM Header + Register Map with Default Value
DS100BR210
Description 1
4
Register
IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0] Reserved
0x19 [3]
0x19 [2]
0x19 [1]
0x19 [0]
Value
0
0
0
0
Description 1
5
Register
Reserved
Reserved
Reserved
Reserved
Value
0
0
1
Description 1
6
Register
Reserved
Reserved
Reserved
Value
1
0
Description 1
7
Register
Reserved
Reserved
Value
0
Description 1
8
Register
Reserved
Value
Description 1
9
Register
Value
1
1
1
1
1
0
1
0
Description 2
0
Register
A VOD[1]
A VOD[0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x25 [3]
0x25 [2]
Value
1
1
0
1
0
1
0
0
Description 2
1
Register
Reserved
Reserved
Reserved
Reserved
ovrd fst idle
en hi idle th A en hi idle th B en fst idle A
0x28 [6]
0x28 [5]
0x28 [4]
0x28 [3]
Value
0
0
0
0
0
0
0
Description 2
2
Register
en fst idle B Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x28 [2]
0x28 [1]
0x28 [0]
Value
1
0
0
0
0
0
0
0
Description 2
3
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0
1
0
1
1
1
1
1
Description 2
4
Register
Reserved
Reserved
Reserved
Reserved
B VOD[2]
B VOD[1]
B VOD[0]
Reserved
0x2D [4]
0x2D 3]
0x2D [2]
Value
0
1
0
1
0
1
1
0
Description 2
5
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
1
0
0
0
0
0
0
0
Description 2
6
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0
0
0
0
0
1
0
1
Description 2
7
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
1
1
1
1
0
1
0
1
Description 2
8
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
1
0
1
0
1
0
0
0
Description 2
9
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0
0
0
0
0
0
0
0
Description 3
0
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0
1
0
1
1
1
1
1
www.ti.com
Reserved
Reserved
Reserved
0
0
0
0
Reserved
Reserved
Reserved
Reserved
0
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
1
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x23 [4]
0x23 [3]
0x23 [2]
0
0
0
0
0
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A VOD[2]
0x25 [4]
0
22
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0
1
0
1
1
0
1
0
Description 3
2
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
1
0
0
0
0
0
0
0
Description 3
3
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0
0
0
0
0
1
0
1
Description 3
4
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
1
1
1
1
0
1
0
1
Description 3
5
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
1
0
1
0
1
0
0
0
Description 3
6
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0
0
0
0
0
0
0
0
Description 3
7
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0
0
0
0
0
0
0
0
Description 3
8
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0
1
0
1
0
1
0
0
Description 3
9
Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0
1
0
1
0
1
0
0
23
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DS100BR210
Description 3
1
Register
DS100BR210
Below is an example of a 2 kbits (256 x 8-bit) EEPROM Register Dump in hex format for a multi-device DS100BR210 application.
Table 9: Multi DS100BR210 EEPROM Data
EEPROM
Address
Address
(Hex)
EEPROM
Data
Comments
0
00
0x43
1
01
0x00
2
02
0x08
EEPROM Burst Size
3
03
0x00
CRC not used
4
04
0x0B
Device 0 Address Location
5
05
0x00
CRC not used
6
06
0x30
Device 1 Address Location
7
07
0x00
CRC not used
8
08
0x30
Device 2 Address Location
9
09
0x00
CRC not used
10
0A
0x0B
Device 3 Address Location
11
0B
0x00
Begin Device 0 and Device 3 - Address Offset 3
12
0C
0x00
13
0D
0x04
14
0E
0x07
15
0F
0x00
16
10
0x2F
17
11
0xED
18
12
0x40
19
13
0x02
Default EQ CHB
20
14
0xFE
Default EQ CHB
21
15
0xD4
22
16
0x00
23
17
0x2F
24
18
0xAD
25
19
0x40
26
1A
0x02
27
1B
0xFA
BR210 CHA VOD = 1000 mV
28
1C
0xD4
BR210 CHA VOD = 1000 mV
29
1D
0x01
30
1E
0x80
31
1F
0x5F
32
20
0x56
33
21
0x80
34
22
0x05
35
23
0xF5
36
24
0xA8
37
25
0x00
38
26
0x5F
39
27
0x5A
40
28
0x80
41
29
0x05
42
2A
0xF5
43
2B
0xA8
44
2C
0x00
45
2D
0x00
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CRC_EN = 0, Address Map = 1, Device Count = 3 (Devices 0, 1, 2, and 3)
Default EQ CHA
BR210 CHB VOD = 1000 mV
24
Address
(Hex)
EEPROM
Data
DS100BR210
EEPROM
Address
Comments
46
2E
0x54
47
2F
0x54
End Device 0 and Device 3 - Address Offset 39
48
30
0x00
Begin Device 1 and Device 2 - Address Offset 3
49
31
0x00
50
32
0x04
51
33
0x07
52
34
0x00
53
35
0x2F
54
36
0xED
55
37
0x40
56
38
0x02
Default EQ CHB
57
39
0xFE
Default EQ CHB
58
3A
0xD4
59
3B
0x00
60
3C
0x2F
61
3D
0xAD
62
3E
0x40
63
3F
0x02
64
40
0xFA
BR210 CHA VOD = 1000 mV
65
41
0xD4
BR210 CHA VOD = 1000 mV
66
42
0x01
67
43
0x80
68
44
0x5F
69
45
0x56
70
46
0x80
71
47
0x05
72
48
0xF5
73
49
0xA8
74
4A
0x00
75
4B
0x5F
76
4C
0x5A
77
4D
0x80
78
4E
0x05
79
4F
0xF5
80
50
0xA8
81
51
0x00
82
52
0x00
83
53
0x54
84
54
0x54
Default EQ CHA
BR210 CHB VOD = 1000 mV
End Device 1 and Device 2 - Address Offset 39
25
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DS100BR210
TABLE 1. Table 10: SMBus Register Map
Address
Register
Name
Bits
Field
Type
Default
0x00
Device ID
7
Reserved
R/W
0x00
6:3
I2C Address [3:0]
R
[6:3] SMBus strap observation
2
EEPROM reading
done
R
1: EEPROM Loading
0: EEPROM Done Loading
1
Reserved
RWSC
0
Reserved
RWSC
7:6
Idle Control
R/W
5:3
Reserved
R/W
Set bits to 0
2
LOS Select
R/W
LOS Monitor Selection
1: Use LOS from CH B
0: Use LOS from CH A
1:0
Reserved
R/W
Set bits to 00'b
7
Reserved
R/W
6
Reserved
5
LOS override
Yes
LOS pin override enable (1);
Use Normal Signal Detection (0)
4
LOS override
value
Yes
1: Normal Operation
0: Output LOS
3
PWDN Inputs
Yes
2
PWDN Oscillator
Yes
1: PWDN
0: Normal Operation
1
Reserved
0
Reserved
Yes
Set bit to 0
7:6
eSATA Mode
Enable
Yes
[7] Channel A (1)
[6] Channel B (1)
5
TX_DIS Override
Enable
1: Override Use Reg 0x04[4:3]
0: Normal Operation - uses pin
4
TX_DIS Value
Channel A
1: TX Disabled
0: TX Enabled
3
TX_DIS Value
Channel B
2
Reserved
Set bit to 0
1:0
EQ CONTROL
[1]: Channel B - EQ Stage 4 ON/OFF
[0]: Channel A - EQ Stage 4 ON/OFF
0x01
0x02
0x04
Control 1
Control 2
Control 3
EEPROM
Reg Bit
Description
set bit to 0
set bit to 0
set bit to 0
0x00
Yes
0x00
Control
[7]: Continuous talk ENABLE (Channel A)
[6]: Continuous talk ENABLE (Channel B)
Set bit to 0
Set bit to 0
R/W
0x00
0x05
CRC 1
7:0
CRC[7:0]
R/W
0x00
Slave Mode CRC Bits
0x06
CRC 2
7
Disable EEPROM R/W
CFG
0x10
Disable Master Mode EEPROM Configuration
6:5
Reserved
4
Reserved
3
CRC Slave Mode
Disable
[1]: CRC Disable (No CRC Check)
[0]: CRC Check ENABLE
Note: With CRC check DISABLED register
updates take immediate effect on high speed
data path. With CRC check ENABLED
register updates will NOT take effect until
correct CRC value is loaded
2:1
Reserved
Set bits to 0
0
CRC Enable
Slave CRC Trigger
www.ti.com
Set bits to 0
Yes
26
Set bit to 1
0x08
0x0C
Digital Reset 7
and Control 6
R/W
0x01
Set bit to 0
Reset Regs
Self clearing reset for registers.
Writing a [1] will return register settings to
default values.
5
Reset SMBus
Master
Self clearing reset for SMBus master state
machine
4:0
Reserved
Pin Override 7
CH A
Analog
Override 1
Reserved
Reserved
Set bits to '0001b
R/W
0x00
Set bit to 0
6
Override Idle
Threshold
Yes
[1]: Override by Channel - see Reg 0x13 and
0x19
[0]: SD_TH pin control
5
Reserved
Yes
Set bit to 0
4
Override IDLE
Yes
[1]: Force IDLE by Channel - see Reg 0x0E
and 0x15
[0]: Normal Operation
3
Reserved
Yes
2
Override Out
Mode
Set bit to 0
[1]: Enable Output Mode control for individual
outputs. See register locations 0x10[6] and
0x17[6].
[0]: Disable - Outputs are kept in the normal
mode of operation allowing VOD and DE adjustments.
1
Override DEM
0
Reserved
7
Reserved
6
Reserved
Set bit to 0
5
Reserved
Set bit to 0
4
Reserved
Set bit to 0
3:0
Reserved
Set bits to 0000'b.
Yes
Yes
R/W
0x00
Set bit to 0
Set bit to 0
0x0D
CH A
Reserved
7:0
Reserved
R/W
0x00
Set bits to 00'h.
0x0E
CH A
Idle Control
7:6
Reserved
R/W
0x00
5
Idle Auto
Yes
Auto IDLE value when override bit is set (reg
0x08 [4] = 1)
4
Idle Select
Yes
Force IDLE value when override bit is set (reg
0x08 [4] = 1)
3
Reserved
Yes
Set bit to 0.
Set bits to 00'b.
2:0
Reserved
0x0F
CH A
EQ Setting
7:0
BOOST [7:0]
R/W
0x2F
Yes
Set bits to 0.
EQ Boost Default to 24 dB
See EQ Table for Information
0x10
CH A
Control 1
7
Sel_scp
R/W
0xED
Yes
[1]: Short Circuit Protection ON
[0]: Short Circuit Protection OFF
6
Output Mode
Yes
[1]: Normal operation
[0]: 10G-KR operation
5:3
Reserved
Yes
Set bits to = 101'b
2:0
Reserved
Yes
Set bits to = 101'b
27
www.ti.com
DS100BR210
0x07
DS100BR210
0x11
0x12
0x13
CH A
Control 2
CH A
Idle
Threshold
CH B
Analog
Override 1
0x82
7:5
Reserved
R
Set bits to = 100'b
4
Reserved
R/W
3
Reserved
2:0
DEM [2:0]
7
Slow OOB
6:4
Reserved
3:2
IDLE thA[1:0]
Yes
Assert Thresholds
Use only if register 0x08 [6] = 1
00 = 180 mV (Default)
01 = 160 mV
10 = 210 mV
11= 190 mV
1:0
IDLE thD[1:0]
Yes
De-assert Thresholds
Use only if register 0x08 [6] = 1
00 = 110 mV (Default)
01 = 100 mV
10 = 150 mV
11= 130 mV
7
Reserved
6
Reserved
Set bit to 0
5
Reserved
Set bit to 0
4
Reserved
Set bit to 0
Set bit to 0
Set bit to 0
R/W
0x00
Yes
De-Emphasis (Default = -3.5 dB)
000'b = -0.0 dB
001'b = -1.5 dB
010'b = -3.5 dB
011'b = -6.0 dB
100'b = -8.0 dB
101'b = -9.0 dB
110'b = -10.5 dB
111'b = -12.0 dB
Yes
Slow OOB Enable (1); Disable (0)
Set bits to 000'b.
R/W
0x00
Set bit to 0
3:0
Reserved
0x14
CH B
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0000'b.
Set bits to 00'h.
0x15
CH B
Idle Control
7:6
Reserved
R/W
0x00
Set bits to 00'b
5
Idle Auto
Yes
Auto IDLE value when override bit is set (reg
0x08 [4] = 1)
4
Idle Select
Yes
Force IDLE value when override bit is set (reg
0x08 [4] = 1)
3:2
Reserved
Yes
Set bits to 00'b.
1:0
Reserved
Set bits to 00'b.
0x16
CH B
EQ Setting
7:0
BOOST [7:0]
R/W
0x2F
Yes
EQ Boost Default to 24 dB
See EQ Table for Information
0x17
CH B
Control 1
7
Sel_scp
R/W
0xED
Yes
1 = Short Circuit Protection ON
0 = Short Circuit Protection OFF
6
Output Mode
Yes
[1]: Normal operation
[0]: 10G-KR operation
5:3
Reserved
Yes
Set bits to = 101'b
2:0
Reserved
www.ti.com
Set bits to = 101'b
28
0x19
0x23
0x25
0x28
CH B
Control 2
CH B
Idle
Threshold
Reserved
CH A VOD
Control
Idle Control
0x82
7:5
Reserved
R
4
Reserved
R/W
3
Reserved
2:0
DEM [2:0]
7
Slow OOB
6:4
Reserved
3:2
IDLE thA[1:0]
Yes
Assert Thresholds
Use only if register 0x08 [6] = 1
00 = 180 mV (Default)
01 = 160 mV
10 = 210 mV
11= 190 mV
1:0
IDLE thD[1:0]
Yes
De-assert Thresholds
Use only if register 0x08 [6] = 1
00 = 110 mV (Default)
01 = 100 mV
10 = 150 mV
11= 130 mV
7:6
Reserved
4:2
Reserved
1:0
Reserved
7:5
Reserved
4:2
VOD_CHA[2:0]
1:0
Reserved
7
Reserved
6
Override Fast Idle
Yes
5:4
en_high_idle_th
[1:0]
Yes
Enable high SD thresholds
[5]: CH A
[4]: CH B
3:2
en_fast_idle[1:0]
Yes
Enable Fast IDLE
[3]: CH A
[2]: CH B
1:0
Reserved
Yes
Set bits to 00'b.
DS100BR210
0x18
Set bits to = 100'b
Set bit to 0
Set bit to 0
R/W
0x00
Yes
De-Emphasis (Default = -3.5 dB)
000'b = -0.0 dB
001'b = -1.5 dB
010'b = -3.5 dB
011'b = -6.0 dB
100'b = -8.0 dB
101'b = -9.0 dB
110'b = -10.5 dB
111'b = -12.0 dB
Yes
Slow OOB Enable (1); Disable (0)
Set bits to 000'b.
R/W
0x00
Set bits to 00'b.
Yes
Set bits to 000'b.
Set bits to 00'b.
R/W
0xAD
Set bits to 101'b.
Yes
VOD Controls for CH A
(Default = 011'b)
000'b = 700 mV
001'b = 800 mV
010'b = 900 mV
011'b = 1000 mV
100'b = 1100 mV
101'b = 1200 mV
110'b = 1300 mV
Set bits to 01'b.
R/W
0x00
29
www.ti.com
DS100BR210
0x2D
0x51
www.ti.com
CH B VOD
Control
Device
Information
7:5
Reserved
4:2
VOD_CHB[2:0]
1:0
Reserved
7:5
Version[2:0]
4:0
Device ID[4:0]
R/W
0xAD
Set bits to 101'b.
Yes
VOD Controls for CH B
(Default = 011'b)
000'b = 700 mV
001'b = 800 mV
010'b = 900 mV
011'b = 1000 mV
100'b = 1100 mV
101'b = 1200 mV
110'b = 1300 mV
Set bits to = 01'b
R
0x66
Read bits = 011'b
BR210 = 0 0110'b
30
DS100BR210
Typical DC Performance
Characteristics
The following data was collected at 25°C
100
SUPPLY CURRENT (mA)
90
80
3.3V Mode
70
60
50
40
2.5V Mode
30
20
10
0
700
800 900 1000 1100 1200 1300
OUTPUT VOLTAGE (mV)
30175393
FIGURE 8. Supply Current vs. Output Voltage Setting
SUPPLY CURRENT (mA)
60
VOD = 700 mV
Temp = 25°C
56
52
2.5V Mode
48
44
40
2.0
2.2
2.4
2.6
2.8
SUPPLY VOLTAGE (V)
3.0
30175394
FIGURE 9. Supply Current vs. Supply Voltage
1500
OUTPUT VOLTAGE (mV)
1400
1300
1200
1100
1000
900
800
700
600
500
0
1
2
3
4
5
VOD SETTING
6
7
30175395
FIGURE 10. Output Voltage vs. Output Voltage Setting
31
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DS100BR210
Typical AC Performance Characteristics
NO MEDIA:
Device
DS100BR210 @
10.3125 Gbps
Random Jitter (Rj)
280 fs
Deterministic Jitter
(Dj)
9.8 ps
Dj Component Breakdown
DDJ = 7.6 ps
13.7 ps
DCD = 2.1 ps
DDPWS = 5.4 ps
PJ = 0.25 ps
30175363
FIGURE 11. No Media; D3186 driving device directly
www.ti.com
32
Total Jitter (Tj @
1E-12)
DS100BR210
The following lab setups were used to collect typical performance data on FR4 and Cable media.
30175371
FIGURE 12. Equalization Test Setup for FR4
EQUALIZATION RESULTS:
30175342
FIGURE 13. Equalization Performance with 10" of 4 mil FR4 using EQ settting 0x01
30175357
FIGURE 14. Equalization Performance with 30" of 4 mil FR4 using EQ settting 0x16
33
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DS100BR210
30175372
FIGURE 15. Equalization Test Setup for Cables
CABLE TRANSMIT and RECEIVE RESULTS:
30175361
FIGURE 16. 8M 30AWG Cable Performance with 700mV Launch VOD and Rx EQ setting 0x0F
www.ti.com
34
DS100BR210
30175370
FIGURE 17. De-Emphasis Test Setup
DE-EMPHASIS RESULTS:
30175339
FIGURE 18. De-Emphasis Performance with 5" of 4 mil FR4 using DE settting 0x01
30175338
FIGURE 19. 5" of 4 mil FR4 Without De-Emphasis
35
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DS100BR210
30175341
FIGURE 20. De-Emphasis Performance with 10" of 4 mil FR4 using DE settting 0x02
30175340
FIGURE 21. 10" of 4 mil FR4 Without De-Emphasis
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36
DS100BR210
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS100BR210SQ (Tape and Reel 1000 units)
Order Number DS100BR210SQE (Tape and Reel 250 units)
NS Package Number SQA24A
(See AN-1187 for PCB Design and Assembly Recommendations)
37
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DS100BR210 Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input Equalization and Output
De-Emphasis
Notes
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
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