ON NCV7425DW5R2G Lin transceiver with voltage regulator and reset pin Datasheet

NCV7425
LIN Transceiver with
Voltage Regulator and
Reset Pin
General Description
The NCV7425 is a fully featured local interconnect network (LIN)
transceiver designed to interface between a LIN protocol controller
and the physical bus.
The NCV7425 LIN device is a member of the in−vehicle
networking (IVN) transceiver family of ON Semiconductor that
integrates a LIN v2.1 physical transceiver and a low−drop voltage
regulator. It is designed to work in harsh automotive environment and
is submitted to the TS16949 qualification flow.
The LIN bus is designed to communicate low rate data from control
devices such as door locks, mirrors, car seats, and sunroofs at the
lowest possible cost. The bus is designed to eliminate as much wiring
as possible and is implemented using a single wire in each node. Each
node has a slave MCU−state machine that recognizes and translates
the instructions specific to that function. The main attraction of the
LIN bus is that all the functions are not time critical and usually relate
to passenger comfort.
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MARKING
DIAGRAM
16
SOIC−16 LEAD
WIDE BODY
EXPOSED PAD
CASE 751AG
16
NCV7425−x
AWLYYWWG
1
x
A
WL
YY
WW
G
1
= 0 or 5
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 19 of this data sheet.
Features
• LIN−Bus Transceiver
LIN compliant to specification revision 2.1
(backward compatible to versions 2.0 and 1.3) and
J2602
♦ Bus Voltage ±45 V
♦ Transmission Rate up to 20 kBaud
♦ Integrated Slope Control for Improved EMI
Compatibility
Package
♦ SOIC−16 Wide Body Green Package with Exposed
Pad
Protection
♦ Thermal Shutdown
♦ Indefinite Short−Circuit Protection on Pins LIN and
WAKE Towards Supply and Ground
♦ Load Dump Protection (45 V)
♦ Bus Pins Protected Against Transients in an
Automotive Environment
♦ ESD Protection Level for LIN, INH, WAKE and
VBB up to ±10 kV
Voltage Regulator
♦ Two Device Versions: Output Voltage 3.3 V or 5 V
For Loads up to 150 mA
♦
•
•
•
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 1
Under−Voltage Detector with a Reset Output to the
Supplied Microcontroller
♦ INH Output for Auxiliary Purposes (switching of an
external pull−up or resistive divider towards battery,
control of an external voltage regulator etc.)
Modes
♦ Normal Mode: LIN Communication in Either Low
(up to 10 kBaud) or Normal Slope
♦ Sleep Mode: VCC is Switched “off” and No
Communication on LIN Bus
♦ Stand−by Mode: VCC is Switched “on” but There is
No Communication on LIN Bus
♦ Wake−up Bringing the Component From Sleep
Mode Into Standby Mode is Possible Either by LIN
Command or Digital Input Signal on WAKE Pin
Wake−up from LIN Bus can also be Detected and
Flagged When the Chip is Already in Standby Mode
These are Pb−Free Devices
♦
•
•
Typical Applications
• Automotive
• Industrial Networks
1
Publication Order Number:
NCV7425/D
NCV7425
Table 1. KEY TECHNICAL CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
5
12
28
V
3.3 V VERSION
VBB
Nominal battery operating voltage
VBB
Load dump protection (Note 1)
45
V
IBB_SLP
Supply current in sleep mode
20
mA
VCC_OUT
(Note 2)
Regulated VCC output in normal mode, VCC load 0−100 mA
3.234
3.3
3.366
V
Regulated VCC output in normal mode, 100 mA < VCC load < 150 mA
3.201
3.3
3.399
IOUT_LIM
VCC regulator current limitation
150
225
300
mA
0
VBB
V
−45
45
0
VBB
V
VWAKE
Operating DC voltage on WAKE pin
Maximum rating voltage on WAKE pin
VINH
Operating DC voltage on INH pin
TJ_tsd
Junction thermal shutdown temperature
165
195
°C
Operating junction temperature
−40
+150
°C
28
V
TJ
5 V VERSION
VBB
Nominal battery operating voltage
6
12
VBB
Load dump protection (Note 1)
45
V
IBB_SLP
Supply current in sleep mode
20
mA
5
5.10
V
VCC_OUT
(Note 2)
Regulated VCC output in normal mode, VCC load 0−100 mA
4.90
Regulated VCC output in normal mode, 100 mA < VCC load < 150 mA
4.85
5
5.15
V
IOUT_LIM
VCC regulator current limitation
150
225
300
mA
0
VBB
V
−45
45
0
VBB
V
Junction thermal shutdown temperature
165
195
°C
Operating junction temperature
−40
+150
°C
VWAKE
Operating DC voltage on WAKE pin
Maximum rating voltage on WAKE pin
VINH
TJ_TSD
TJ
Operating DC voltage on INH pin
1. The applied transients shall be in accordance with ISO 7637 part 1, test pulse 5. The device complies with functional class C;. The LIN
communication itself complies with functional class B. On regulator class A can be reached depending on the application and external
components
2. VCC voltage must be properly stabilized by external capacitors: capacitor of min. 80 nF with ESR < 10 mW in parallel with a capacitor of min.
8 mF, ESR < 1 W.
Table 2. THERMAL CHARACTERISTICS
Conditions
Value
Unit
Rth(vj−a)_1
Symbol
Thermal resistance junction−to−ambient on JEDEC 1S0P PCB
Free Air
138
K/W
Rth(vj−a)_2
Thermal resistance junction−to−ambient on JEDEC 1S0P + 300 mm2 PCB
Free Air
94
K/W
Rth(vj−a)_3
Thermal resistance junction−to−ambient on JEDEC 2S2P PCB
Free Air
70
K/W
Free Air
49
K/W
Rth(vj−a)_4
Parameter
Thermal resistance junction−to−ambient on JEDEC 2S2P + 300
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2
mm2
PCB
NCV7425
V CC
V BB
INH
NCV7425
Band−
gap
V−reg
VBB
WAKE
VCC
VBB
POR
VCC
STB
Thermal
shutdown
EN
Control Logic
Osc
VCC
VBB
TxD
VCC
RxD
Receiver
LIN
VCC
RSTN
Timeout
Slope
Control
GND
OTP _ZAP
TEST
PD20090609 .1
Figure 1. Block Diagram
TYPICAL APPLICATION
Application Information
VCC voltage must be properly stabilized by external
capacitors: capacitor of min. 80 nF (ESR < 10 mW) in
parallel with a capacitor of min. 8 mF (ESR < 1 W).
The 10 mF capacitor on the battery is optional and serves
as reservoir capacitor to deal with battery supply
micro−cuts.
The EMC immunity of the Master−mode device can be
further enhanced by adding a capacitor between the LIN
output and ground. The optimum value of this capacitor is
determined by the length and capacitance of the LIN bus, the
number and capacitance of Slave devices, the pull−up
resistance of all devices (Master and Slave), and the required
time constant of the system, respectively.
Master Node
10uF
100nF
V BB
VCC
WAKE
OTP_ZAP
GND
100nF
10uF
VCC
V BB
VCC
TxD
LIN
EN
LIN
controller
STB
TEST
VCC
TxD
Micro
220 pF
EN
100nF
RxD
INH
WAKE
RSTN
WAKE
10nF
GND
NCV 7425
1kW
1 nF
LIN
10uF
VBAT
RxD
INH
LIN
Slave Node
100nF
GND
GND
Micro
controller
STB
RSTN
WAKE
10nF
10uF
VBAT
OTP_ZAP
GND
TEST
GND
PD20090609.2
KL30
LIN−BUS
KL31
Figure 2. Application Diagram
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NCV7425
1
16
LIN
2
15
RxD
GND
3
14
TxD
GND
4
13
RSTN
WAKE
5
12
STB
INH
6
11
EN
OTP_SUP
7
10
TEST
n.c.
8
9
n.c.
NCV7425
VBB
VCC
Figure 3. Pin Assignment
Table 3. PIN FUNCTION DESCRIPTION
Pin Number
Pin Name
Description
1
VBB
Battery supply input
2
LIN
LIN bus output/input
3
GND
Ground
4
GND
Ground
5
WAKE
6
INH
7
OTP_SUP
8
n.c.
not connected
9
n.c.
not connected
10
TEST
High voltage digital input pin to switch the part from sleep− to standby mode
Inhibit output
Supply for programming of trimming bits at factory testing, needs to be grounded in the application
Digital input for factory testing, needs to be grounded in the application
11
EN
Enable input for mode control
12
STB
Standby mode control input
13
RSTN
14
TxD
Transmit data input, low in dominant state
15
RxD
Receive data output; low in dominant state; push−pull output
16
VCC
Voltage regulator output
Reset output; open−drain output with an on−chip pull−up resistor
FUNCTIONAL DESCRIPTION
Overall Functional Description
with EMC performance due to reduced slew rate of the LIN
output.
The junction temperature is monitored via a thermal
shutdown circuit that switches the LIN transmitter and
voltage regulator off when temperature exceeds the TSD
trigger level.
NCV7425 has four operating states (normal mode, low
slope mode, stand−by mode, and sleep mode) that are
determined by the input signals EN, WAKE, STB, and TxD.
LIN is a serial communication protocol that efficiently
supports the control of mechatronic nodes in distributed
automotive applications. The domain is class−A multiplex
buses with a single master node and a set of slave nodes.
NCV7425 is designed as a master or slave node for the
LIN communication interface with an integrated 3.3 V or
5 V voltage regulator having a current capability up to
150 mA for supplying any external components
(microcontroller, CAN node, etc.).
NCV7425 contains the LIN transmitter, LIN receiver,
voltage regulator, power−on−reset (POR) circuits and
thermal shutdown (TSD). The LIN transmitter is optimized
for the maximum specified transmission speed of 20 kBaud
Operating States
NCV7425 provides four operating states, two modes for
normal operation with communication, one stand−by
without communication and one low power mode with very
low current consumption − see Figure 4 and Table 4.
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NCV7425
Table 4. MODE SELECTION
LIN
Transceiver
30 kW on LIN
RSTN
High if STB = High
during state transition;
Floating otherwise
Normal Slope
ON
High
Low = Dominant State
High = Recessive State
High if STB = High
during state transition;
Floating otherwise
Low Slope
ON
High
ON
Low after LIN
wake−up, high
otherwise (Note 6)
Floating
OFF
OFF
Controlled by VCC
under−voltage
monitor
OFF
Clamped to VCC
(Note 6)
Floating
OFF
OFF
Low
Mode
VCC
RxD
INH
Normal −
Slope (Note 3)
ON
Low = Dominant State
High = Recessive State
Normal − Low
Slope (Note 4)
ON
Stand−by
(Note 5)
Sleep
3. The normal slope mode is entered when pin EN goes HIGH while TxD is in HIGH state during EN transition.
4. The low slope mode is entered when pin EN goes HIGH while TxD is in LOW state during EN transition. LIN transmitter gets on only after
TxD returns to high after the state transition.
5. The stand−by mode is entered automatically after power−up.
6. In Stand−by and Sleep mode, the High state is achieved by internal pull−up resistor to VCC.
Standby mode
EN changes 1−>0 while STB=1
VCC under−voltage
VCC under−voltage
EN changes 1−>0 while STB=1
EN changes 0−>1 while TxD=1
Normal mode
(low slope )
− VCC: on
−LIN TRX: on
−INH: High/floating
−LIN term.: 30kW
−RxD pin: LIN data
−RSTN pin: High
Normal mode
(normal slope )
− VCC: on
−LIN TRX: on
−INH: High/floating
−LIN term.: 30kW
−RxD pin: LIN data
−RSTN pin: High
EN changes 1−>0 while STB=0
EN changes 0−>1 while TxD=0
VBB power−up
− VCC: on
−LIN TRX: off
−INH: floating
−LIN term.: current source
−RxD pin: High/Low
−RSTN pin: VCC_UV
Sleep mode
EN changes 1−>0 while STB=0
− VCC: off
−LIN TRX: off
−INH: floating
−LIN term.: current source
−RxD pin: at VCC
−RSTN pin: Low
PD20090610 .01
Figure 4. State Diagram
Normal Slope Mode
The mode selection is done by EN=HIGH when TxD pin is
HIGH. If STB pin is high during the standby−to−normal
slope mode transition, INH pin is pulled high. Otherwise, it
stays floating.
In normal slope mode the transceiver can transmit and
receive data via LIN bus with speed up to 20 kBaud. The
transmit data stream of the LIN protocol is present on the
TxD pin and converted by the transmitter into a LIN bus
signal with controlled slew rate to minimize EMC emission.
The receiver consists of the comparator that has a threshold
with hysteresis in respect to the supply voltage and an input
filter to remove bus noise. The LIN output is pulled HIGH
via an internal 30 kW pull−up resistor. For master
applications it is needed to put an external 1 kW resistor with
a serial diode between LIN and VBB (or INH) − see Figure 2.
Low Slope Mode
In low slope mode the slew rate of the signal on the LIN
bus is reduced (rising and falling edges of the LIN bus signal
are longer). This further reduces the EMC emission. As a
consequence the maximum speed on the LIN bus is reduced
up to 10 kBaud. This mode is suited for applications where
the communication speed is not critical. The mode selection
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NCV7425
Sleep Mode
is done by EN=HIGH when TxD pin is LOW. In order not
to transmit immediately a dominant state on the bus (because
TxD = LOW), the LIN transmitter is enabled only after TxD
returns to HIGH. If STB pin is high during the
standby−to−low slope mode transition, INH pin is pulled
high. Otherwise, it stays floating.
The Sleep Mode provides extremely low current
consumption. This mode is entered when both EN and STB
pins are LOW coming from normal mode. The internal
termination resistor of 30 kW between LIN and VBB is
disconnected and also the VCC regulator is switched off to
minimize current consumption.
Stand−by Mode
Wake−up
The stand−by mode is always entered after power−up of
the NCV7425. It can also be entered from normal mode
when the EN pin is low and the stand−by pin is high. From
sleep mode it can be entered after a local wake−up or LIN
wakeup. In stand−by mode the VCC voltage regulator for
supplying external components (e.g. a microcontroller)
stays active. Also the LIN receiver stays active to be able to
detect a remote wake−up via bus. The LIN transmitter is
disabled and the slave internal termination resistor of 30 kW
between LIN and VBB is disconnected in order to minimize
current consumption. Only a pull−up current source
between VBB and LIN is active.
Wake
NCV7425 has two possibilities to wake−up from sleep or
stand−by mode (see Figure 4):
Local wake−up: enables the transition from sleep mode to
stand−by mode
Remote wake−up via LIN: enables the transition from
sleep− to stand−by mode and can be also detected when
already in standby mode.
A local wake−up is only detected in sleep mode if a
transition from LOW to HIGH or from HIGH to LOW is
seen on the wake pin.
Detection of Local Wake−Up
Wake
VBB
Detection of Local Wake−Up
VBB
50% VBB typ.
Sleep Mode
t
Stand−by Mode
50% VBB typ.
Sleep Mode
Figure 5. Local Wake−Up Signal
A remote wake−up is only detected if a combination of (1)
a falling edge at the LIN pin (transition from recessive to
dominant) is followed by (2) a dominant level maintained
Stand−by Mode
t
PC20060427.3
for a time period > tWAKE and (3) again a rising edge at pin
LIN (transition from dominant to recessive) happens.
LIN
Detection of Remote Wake−Up
VBB
LIN recessive level
tWAKE
60% VBB
40% VBB
LIN dominant level
Sleep Mode
Stand−by Mode
t
PC20060427.2
Figure 6. Remote Wake−Up Behavior
VCC Under−voltage Detection and RSTN Pin
The wake−up source is distinguished by pin RxD in the
stand−by mode:
RxD remains HIGH after power−up or local wake−up.
RxD is kept LOW until normal mode is entered after a
remote wake−up (LIN)
In standby, normal and low−slope modes, the VCC
regulator is monitored. Whenever the regulator output falls
below VCC_UV_THR level (typically 90% of the nominal
voltage) for longer than VCC_UV_deb (typically 5 ms), an
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NCV7425
In the sleep mode, RSTN pin is kept Low regardless the
VCC level − it means that RSTN becomes Low immediately
at sleep mode entry even if the VCC capacitor is still charged.
In all situations where RSTN pin is kept Low, the digital
inputs to NCV7425 are discarded by the internal control
logic and have no effect on its behavior.
The RSTN pin function is illustrated in Figure 7.
under−voltage is detected. Output pin RSTN is pulled to
Low level to indicate the under−voltage condition to the
external load (a microcontroller). At the same time, the
device enters automatically the standby mode. As soon as
the regulator output returns above the under−voltage level,
the RSTN Low level is extended by typically 6ms and only
then released to High level in order to ensure
microcontroller initialization under correct supply
conditions.
Figure 7. RSTN Pin Behavior
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NCV7425
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND. Positive currents flow into the IC.
Table 5. ABSOLUTE MAXIMUM RATINGS − 3.3 V and 5 V VERSIONS
Symbol
Parameter
Min.
Max.
Unit
−0.3
+45
V
0
+6
V
VBB
Battery voltage on pin VBB (Note 7)
VCC
DC voltage on pin VCC
IVCC
Current delivered by the VCC regulator
150
VLIN
LIN bus voltage (Note 8)
−45
+45
V
VINH
DC voltage on inhibit pin
−0.3
VBB + 0.3
V
VWAKE
Voltage on WAKE pin
−45
45
V
VDig_IO
DC voltage on pins TxD, RxD, EN, STB, RSTN
−0.3
VCC + 0.3
V
Maximum junction temperature
−40
+165
°C
Electrostatic discharge voltage (INH, WAKE and VBB) system
Human Body Model (HBM) (Note 9)
−10
+10
kV
Electrostatic discharge voltage (LIN pin, no external capacitor) HBM (Note 9)
−10
+10
Electrostatic discharge voltage (LIN pin, 220 pF) System HBM (Note 9)
−15
+15
Electrostatic discharge voltage (pins LIN, INH, WAKE and VBB) HBM (Note 10)
−8
+8
Electrostatic discharge voltage (other pins) HBM (Note 10)
−4
+4
−250
+250
TJ
Vesd
Electrostatic discharge voltage; charge device model (Note 11)
mA
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
7. The applied transients shall be in accordance with ISO 7637 part 1, test pulses 1, 2, 3a, 3b, and 5. The device complies with functional class
C; class A can be reached depending on the application and external components.
8. The applied transients shall be in accordance with ISO 7637 part 1, test pulses 1, 2, 3a, and 3b. The device complies with functional class
C; class A can be reached depending on the application and external components.
9. Equivalent to discharging a 150 pF capacitor through a 330 W resistor conform to IEC Standard 61000−4−2. The specified values are verified
by external test house.
10. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor conform to MIL STD 883 method 3015.7.
11. Conform to EOS/ESD−DS5.3 (socket mode).
Table 6. DC CHARACTERISTICS − 3.3 V VERSION
VBB = 5 V to 28 V; TJ = −40°C to +150°C; unless otherwise specified.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC CHARACTERISTICS SUPPLY − PINS VBB AND VCC
IBB_ON
Supply current
Normal mode; LIN
recessive
1.6
mA
IBB_STB
Supply current
Stand−by mode, VBB = 5 −
18 V, TJ < 105°C
60
mA
IBB_SLP
Supply current
Sleep mode, VBB = 5 −
18 V, TJ < 105°C
20
mA
V
DC CHARACTERISTICS − VOLTAGE REGULATOR
VCC_OUT
Regulator output voltage
VCC load 0 − 100 mA
3.234
3.30
3.366
100 mA < VCC load <
150 mA
3.201
3.30
3.399
12. Measured at output voltage VCC_OUT = (VCC_OUT @ VBB = 5 V) − 2%.
13. The voltage drop in Normal mode between LIN and VBB pin is the sum of the diode drop and the drop at serial pull up resistor. The drop
at the switch is negligible. See Figure 2.
14. Guaranteed by design. Not tested
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NCV7425
Table 6. DC CHARACTERISTICS − 3.3 V VERSION
VBB = 5 V to 28 V; TJ = −40°C to +150°C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Over−current limitation
150
225
300
mA
Under−voltage detection threshold
2.80
2.97
3.13
V
DC CHARACTERISTICS − VOLTAGE REGULATOR
IOUT_LIM
VCC_UV_THR
DVCC_OUT
Vdo
Line Regulation
VBB 5 − 28 V, Iout = 5 mA
TJ = 25°C
0.41
Load Regulation
Iout 1−100 mA,
VBB = 14 V, TJ = 25°C
25
Dropout Voltage (VBB − VCC_OUT)
(Note 12) Figure 12
Iout = 10 mA, TJ = 25°C
22
Iout = 50 mA, TJ = 25°C
108
Iout = 100 mA, TJ = 25°C
216
mV
mV
DC CHARACTERISTICS − LIN TRANSMITTER
VLIN_dom_LoSup
LIN dominant output voltage
TxD = low; VBB = 7.3 V
1.2
V
VLIN_dom_HiSup
LIN dominant output voltage
TxD = low; VBB = 18 V
2.0
V
1
V
Vser_diode
LIN Voltage drop at serial diode
(Note 13)
ILIN_lim
Short circuit current limitation
Rslave
Internal pull−up resistance
CLIN
TxD = high; ILIN = 10 mA
0.3
VLIN = VBB(max)
40
20
Capacitance on pin LIN (Note 14)
ILIN_off_dom
LIN output current bus in dominant state
Driver off; VBB = 12 V
ILIN_off_rec
LIN output current bus in recessive state
Driver off; VBB < 18 V,
VBB < VLIN < 18 V
ILIN_no_GND
Communication not affected
VBB = GND = 12 V;
0 < VLIN < 18 V
ILIN_no_VBB
LIN bus remains operational
VBB = GND = 0 V;
0 < VLIN < 18 V
200
mA
33
47
kW
25
35
pF
−1
mA
−1
1
mA
1
mA
5
mA
0.4
VBB
DC CHARACTERISTICS − LIN RECEIVER
VBUS_dom
bus voltage for dominant state
VBUS_rec
bus voltage for recessive state
Vrec_dom
Receiver threshold
LIN bus recessive →
dominant
0.4
0.6
VBB
Vrec_rec
Receiver threshold
LIN bus dominant →
recessive
0.4
0.6
VBB
Vrec_cnt
Receiver centre voltage
(VBUS_dom + VBUS_rec) / 2
0.475
0.525
VBB
Vrec_hys
Receiver hysteresis
0.05
0.175
VBB
0.35
0.65
VBB
1
mA
54
ms
0.8
V
0.6
VBB
DC CHARACTERISTICS − DIGITAL I/O PINS
PIN WAKE
VWAKE_TH
Ileak
TWAKE(min)
Threshold voltage
Input leakage current
Debounce time
VWAKE = 0 V; VBB = 18 V
−1
Sleep mode; rising and
falling edge
8
−0.5
PINS TxD AND STB
Vil
Low level input voltage
12. Measured at output voltage VCC_OUT = (VCC_OUT @ VBB = 5 V) − 2%.
13. The voltage drop in Normal mode between LIN and VBB pin is the sum of the diode drop and the drop at serial pull up resistor. The drop
at the switch is negligible. See Figure 2.
14. Guaranteed by design. Not tested
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NCV7425
Table 6. DC CHARACTERISTICS − 3.3 V VERSION
VBB = 5 V to 28 V; TJ = −40°C to +150°C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DC CHARACTERISTICS − DIGITAL I/O PINS
PINS TxD AND STB
Vih
High level input voltage
2.0
Rpu
Pull−up resistance to VCC
50
V
200
kW
0.75
V
1
mA
0.8
V
PIN INH
Delta_VH
Ileak
High level voltage drop
IINH = 15 mA
Leakage current
Sleep mode; VINH = 0 V
0.35
−1
PIN EN
Vil
Low level input voltage
Vih
High level input voltage
2.0
Rpd
Pull−down resistance to ground
50
V
200
kW
0.65
V
PIN RxD
Vol
Low level output voltage
Isink = 2 mA
Voh
High level output voltage
(In Normal mode)
Normal mode,
Isource = −2 mA
Rpu
Pull−up resistance to VCC
(In Standby and Sleep mode)
Standby mode,
Sleep mode
VCC −
0.65
V
10
kW
PIN RSTN
Vol
Low level output voltage
Rpu
Pull−up resistance to VCC
Isink = 2 mA
0.65
V
200
kW
4.5
V
3.8
V
2
V/ms
165
195
°C
9
18
°C
50
DC CHARACTERISTICS
POWER−ON RESET
PORH_VBB
VBB POR high level detection threshold
PORL_VBB
VBB POR low level detection threshold
POR_VBB_sl
Maximum slope on VBB to guarantee
POR
1.7
THERMAL SHUTDOWN
TJ_tsd
Junction temperature
TJ_hyst
Thermal shutdown hysteresis
For shutdown
12. Measured at output voltage VCC_OUT = (VCC_OUT @ VBB = 5 V) − 2%.
13. The voltage drop in Normal mode between LIN and VBB pin is the sum of the diode drop and the drop at serial pull up resistor. The drop
at the switch is negligible. See Figure 2.
14. Guaranteed by design. Not tested
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NCV7425
Table 7. DC CHARACTERISTICS − 5 V VERSION
VBB = 6 V to 28 V; TJ = −40°C to +150°C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DC CHARACTERISTICS SUPPLY − PINS VBB AND VCC
IBB_ON
Supply current
Normal mode; LIN recessive
1.6
mA
IBB_STB
Supply current
Stand−by mode, VBB = 6 − 18 V,
TJ < 105°C
60
mA
IBB_SLP
Supply current
Sleep mode, VBB = 6 − 18V,
TJ < 105°C
20
mA
DC CHARACTERISTICS − VOLTAGE REGULATOR
VCC_OUT
IOUT_LIM
VCC_UV_THR
DVCC_OUT
Vdo
Regulator output voltage
VCC load 0 − 100 mA
4.9
5
5.1
V
100 mA < VCC load < 150 mA
4.85
5
5.15
V
Over−current limitation
150
225
300
mA
Under−voltage detection
threshold
4.25
4.5
4.75
V
Line Regulation
VBB 6 − 28 V, Iout = 5 mA
TJ = 25°C
0.41
mV
Load Regulation
Iout 1 − 100 mA, VBB = 14 V,
TJ = 25°C
22
mV
Iout = 10 mA, TJ = 25°C
22
mV
Iout = 50 mA, TJ = 25°C
108
mV
Iout = 100 mA, TJ = 25°C
216
mV
Dropout Voltage (VBB −
VCC_OUT) (Note 15)
(Figure 20)
DC CHARACTERISTICS LIN TRANSMITTER
VLIN_dom_LoSup
LIN dominant output voltage
TxD = low; VBB = 7.3 V
1.2
V
VLIN_dom_HiSup
LIN dominant output voltage
TxD = low; VBB = 18 V
2.0
V
Vser_diode
LIN Voltage drop at serial diode
(Note 16)
ILIN_lim
Short circuit current limitation
Rslave
Internal pull−up resistance
CLIN
TxD = high; ILIN = 10 mA
0.3
1
V
VLIN = VBB(max)
40
200
mA
33
47
kW
25
35
pF
20
Capacitance on pin LIN (Note 17)
ILIN_off_dom
LIN output current bus in
dominant state
Driver off; VBB = 12 V
ILIN_off_rec
LIN output current bus in
recessive state
Driver off; VBB < 18 V,
VBB < VLIN < 18 V
ILIN_no_GND
Communication not affected
VBB = GND = 12 V;
0 < VLIN < 18 V
ILIN_no_VBB
LIN bus remains operational
VBB = GND = 0 V;
0 < VLIN < 18 V
−1
−1
mA
1
mA
1
mA
5
mA
0.4
VBB
DC CHARACTERISTICS LIN RECEIVER
VBUS_dom
bus voltage for dominant state
VBUS_rec
bus voltage for recessive state
Vrec_dom
Receiver threshold
LIN bus recessive → dominant
Vrec_rec
Receiver threshold
LIN bus dominant → recessive
Vrec_cnt
Receiver center voltage
(VBUS_dom + VBUS_rec) / 2
Vrec_hys
Receiver hysteresis
0.05
0.6
0.4
VBB
0.6
VBB
0.4
0.6
VBB
0.475
0.525
VBB
0.175
VBB
15. Measured at output voltage VCC_OUT = (VCC_OUT @ VBB = 6 V) − 2%.
16. The voltage drop in Normal mode between LIN and VBB pin is the sum of the diode drop and the drop at serial pull up resistor. The drop
at the switch is negligible. See Figure 2.
17. Guaranteed by design. Not tested
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NCV7425
Table 7. DC CHARACTERISTICS − 5 V VERSION
VBB = 6 V to 28 V; TJ = −40°C to +150°C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.65
VBB
1
mA
54
ms
0.8
V
200
kW
0.75
V
1
mA
0.8
V
DC CHARACTERISTICS − DIGITAL I/O PINS
PIN WAKE
VWAKE_TH
Ileak
TWAKE_MIN
Threshold voltage
Input leakage current
Debounce time
0.35
VWAKE = 0 V; VBB = 18 V
−1
Sleep mode; rising and falling
edge
8
−0.5
PINS TxD AND STB
Vil
Low level input voltage
Vih
High level input voltage
2.0
Rpu
Pull−up resistance to VCC
50
V
PIN INH
Delta_VH
I_leak
High level voltage drop
Leakage current
IINH = 15 mA
Sleep mode; VINH = 0 V
0.35
−1
PIN EN
Vil
Low level input voltage
Vih
High level input voltage
2.0
Rpd
Pull−down resistance to ground
50
V
200
kW
0.65
V
PIN RxD
Vol
Low level output voltage
Isink = 2 mA
Voh
High level output voltage
(In Normal mode)
Normal mode, Isource = −2 mA
Rpu
Pull−up resistance to VCC
(In Standby and Sleep mode)
VCC −
0.65
Standby mode, Sleep mode
V
10
kW
PIN RSTN
Vol
Low level output voltage
Rpu
Pull−up resistance to VCC
Isink = 2 mA
0.65
V
200
kW
4.5
V
3.8
V
2
V/ms
165
195
°C
9
18
°C
50
DC CHARACTERISTICS
POWER−ON RESET
PORH_VBB
VBB POR high level detection
threshold
PORL_VBB
VBB POR low level detection
threshold
POR_VBB_sl
Maximum slope on VBB to
guarantee POR
1.7
THERMAL SHUTDOWN
TJ_tsd
Junction temperature
TJ_hyst
Thermal shutdown hysteresis
For shutdown
15. Measured at output voltage VCC_OUT = (VCC_OUT @ VBB = 6 V) − 2%.
16. The voltage drop in Normal mode between LIN and VBB pin is the sum of the diode drop and the drop at serial pull up resistor. The drop
at the switch is negligible. See Figure 2.
17. Guaranteed by design. Not tested
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NCV7425
Table 8. AC CHARACTERISTICS − 3.3 V AND 5 V VERSIONS
VBB = 7 V to 18 V; TJ = −40°C to +150°C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
AC CHARACTERISTICS LIN TRANSMITTER
D1
Duty Cycle 1 = tBUS_rec(min) /
(2 x TBit) see Figure 24
normal slope mode
THrec(max) = 0.744 x VBB
THdom(max) = 0.581 x VBB
TBit = 50 ms
VBB = 7 V to 18 V
0.396
0.5
D2
Duty Cycle 2 = tBUS_rec(max) /
(2 x TBit) see Figure 24
normal slope mode
THrec(min) = 0.422 x VBB
THdom(min) = 0.284 x VBB
TBit = 50 ms
VBB = 7.6 V to 18 V
0.5
0.581
D3
Duty Cycle 3 = tBUS_rec(min) /
(2 x Tbit) see Figure 24
normal slope mode
THrec(max) = 0.778 x VBB
THdom(max) = 0.616 x VBB
TBit = 96 ms
VBB = 7 V to 18 V
0.417
0.5
D4
Duty Cycle 4 = tBUS_rec(max) /
(2 x Tbit) see Figure 24
normal slope mode
THrec(min) = 0.389 x VBB
THdom(min) = 0.251 x VBB
TBit = 96 ms
VBB = 7.6 V to 18 V
0.5
0.590
Tfall_norm
LIN falling edge
Normal slope mode; VBB = 12 V;
L1, L2 (Note 18)
22.5
ms
Trise_norm
LIN rising edge
Normal slope mode; VBB = 12 V;
L1, L2 (Note 18)
22.5
ms
Tsym_norm
LIN slope symmetry
Normal slope mode; VBB = 12 V;
L1, L2 (Note 18)
4
ms
Tfall_norm
LIN falling edge
Normal slope mode; VBB = 12 V;
L3 (Note 18)
27
ms
Trise_norm
LIN rising edge
Normal slope mode; VBB = 12 V;
L3 (Note 18)
27
ms
Tsym_norm
LIN slope symmetry
Normal slope mode; VBB = 12 V;
L3 (Note 18)
5
ms
Tfall_low
LIN falling edge
Low slope mode (Note 19);
VBB = 12 V; L3 (Note 18)
62
ms
Trise_low
LIN rising edge
Low slope mode (Note 19);
VBB = 12 V; L3 (Note 18)
62
ms
TWAKE
Dominant time−out for
wake−up via LIN bus
30
150
ms
Tdom
TxD dominant time−out
6
20
ms
VCC_UV_deb
VCC under−voltage detection
debounce time
1.5
5
10
ms
RSTN_ext
Extension time of RSTN Low
pulse beyond VCC
under−voltage
3
6
10
ms
TxD = low
−4
−5
AC CHARACTERISTICS LIN RECEIVER
Trec_prop_down
Propagation delay of receiver
falling edge
0.1
6
ms
Trec_prop_up
Propagation delay of receiver
rising edge
0.1
6
ms
Trec_sym
Propagation delay symmetry
−2
2
ms
Trec_prop_down − Trec_prop_up
18. The AC parameters are specified for following RC loads on the LIN bus: L1 = 1 kW / 1 nF; L2 = 660 W / 6.8 nF; L3 = 500 W / 10 nF.
19. Low slope mode is not compliant to the LIN 1.3 or LIN 2.0/2.1 standard.
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NCV7425
REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS
(3.3 V Version)
Load Transient Responses
Figure 8. Load Transient Response
(ICC 100 mA to 100 mA)
Figure 9. Load Transient Response
(ICC 1 mA to 100 mA)
Line Transient Responses
Figure 10. Line Transient Response
(VBB 5 V to 28 V)
Figure 11. Line Transient Response
(VBB 5 V to 28 V)
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NCV7425
REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS
(3.3 V Version)
Static Characteristics
Figure 12. Dropout Voltage vs.
Temperature
Figure 13. Output Voltage vs. Output
Current
Figure 14. Ground Current vs. Output
Current
Figure 15. Output Voltage vs.
Temperature
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NCV7425
REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS
(5 V Version)
Load Transient Responses
Figure 16. Load Transient Response
(ICC 100 mA to 100 mA)
Figure 17. Load Transient Response
(ICC 1 mA to 100 mA)
Line Transient Responses
Figure 18. Line Transient Response
(VBB 6 V to 28 V)
Figure 19. Line Transient Response
(VBB 6 V to 28 V)
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NCV7425
REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS
(5 V Version)
Static Characteristics
Figure 20. Dropout Voltage vs.
Temperature
Figure 21. Output Voltage vs. Output
Current
Figure 22. Ground Current vs. Output
Current
Figure 23. Output Voltage vs.
Temperature
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NCV7425
TxD
tBIT
tBIT
50%
t
tBUS_dom(max)
LIN
tBUS_rec(min)
THrec (max)
THdom (max)
Thresholds of
receiving node 1
THrec (min)
THdom (min)
Thresholds of
receiving node 2
t
tBUS_dom(min)
tBUS_rec(max)
PC20060428.2
Figure 24. LIN Transmitter Duty Cycle
LIN
100%
60%
60%
40%
40%
0%
Tfall
t
Trise
PC20060428.1
Figure 25. LIN Transmitter Rising and Falling Times
LIN
VBB
60% VBB
40% VBB
t
RxD
trec_prop_down
trec_prop_up
50%
Figure 26. LIN Receiver Timing
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18
t
PC20060428.3
NCV7425
ORDERING INFORMATION
Device
NCV7425DW0G
NCV7425DW0R2G
NCV7425DW5G
NCV7425DW5R2G
Description
Temperature Range
Package
LIN Transceiver + 3.3 V
Regulator + Reset Pin
LIN Transceiver + 5 V
Regulator + Reset Pin
Shipping†
46 Units / Tube
−40°C to 125°C
SOIC−16, WB, EP
(Pb−Free)
1500 / Tape & Reel
46 Units / Tube
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCV7425
PACKAGE DIMENSIONS
SOIC−16 LEAD WIDE BODY, EXPOSED PAD
PDW SUFFIX
CASE 751AG
ISSUE A
−U−
A
M
P
0.25 (0.010)
M
W
M
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
6. 751R-01 OBSOLETE, NEW STANDARD 751R-02.
9
B
1
R x 45_
8
−W−
G
PIN 1 I.D.
14 PL
DETAIL E
TOP SIDE
C
F
−T−
0.10 (0.004) T
K
D 16 PL
0.25 (0.010)
T U
M
SEATING
PLANE
W
S
J
S
DETAIL E
H
EXPOSED PAD
1
SOLDERING FOOTPRINT*
8
0.350
L
16
DIM
A
B
C
D
F
G
H
J
K
L
M
P
R
0.050
BACK SIDE
CL
0.200
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.136
0.144
0.010
0.012
0.000
0.004
0.186
0.194
0_
7_
0.395
0.415
0.010
0.029
Exposed
Pad
0.175
9
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
3.45
3.66
0.25
0.32
0.00
0.10
4.72
4.93
0_
7_
10.05
10.55
0.25
0.75
0.188
CL
0.376
0.074
0.150
0.024
DIMENSIONS: INCHES
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Phone: 81−3−5817−1050
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ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
Sales Representative
NCV7425/D