HI-1567, HI-1568 March 2001 PIN CONFIGURATIONS DESCRIPTION The HI-1567 and HI-1568 are low power CMOS dual transceivers designed to meet the requirements of MIL-STD-1553 /1760 specifications. The transmitter section of each channel takes complimentary CMOS / TTL digital input data and converts it to bi-phase Manchester encoded 1553 signals suitable for driving the bus isolation transformer. Separate transmitter inhibit control signals are provided for each transmitter. The receiver section of the each channel converts the 1553 bus bi-phase data to complimentary CMOS / TTL data suitable for inputting to a Manchester decoder. Each receiver has a separate enable input which can be used to force the output of the receiver to a logic 0 (HI-1567) or logic 1 (HI-1568). 20 TXA BUSA 2 19 TXA BUSA 3 18 TXINHA RXENA 4 17 RXA GNDA 5 16 RXA VDDB 6 15 TXB BUSB 7 14 TXB BUSB 8 13 TXINHB RXENB 9 12 RXB GNDB 10 11 RXB To minimize the package size for this function, the transmitter outputs are internally connected to the receiver inputs, so that only two pins are required for connection to each coupling transformer. For designs requiring independent access to transmitter and receiver 1553 signals, please contact your Holt Sales representative. 20 Pin Ceramic DIP package FEATURES ! Compliant to MIL-STD-1553A & B, MIL-STD-1760 ! CMOS technology for low standby power ! Smallest footprint available in 20 pin plastic ESOIC (thermally enhanced SOIC) package ! Less than 1.0W maximum power dissipation ! Available in DIP, Flatpack and small outline VDDA 1 VDDA 1 20 TXA BUSA 2 19 TXA BUSA 3 18 TXINHA RXENA 4 17 RXA GNDA 5 16 RXA VDDB 6 15 TXB BUSB 7 14 TXB BUSB 8 13 TXINHB RXENB 9 12 RXB GNDB 10 11 RXB 20 Pin Plastic ESOIC - WB package (ESOIC) package options ! Military processing options ! Industry standard pin configurations (DS1567 Rev. B) HOLT INTEGRATED CIRCUITS 1 03/01 HI-1567, HI-1568 PIN DESCRIPTIONS PIN SYMBOL FUNCTION DESCRIPTION 1 VDDA power supply +5 volt power for channel A 2 BUSA analog output MIL-STD-1533 bus driver A, positive signal 3 BUSA analog output MIL-STD-1553 bus driver A, negative signal 4 RXENA digital input 5 GNDA power supply Ground for channel A 6 VDDB power supply +5 volt power for channel B 7 BUSB analog output MIL-STD-1533 bus driver B, positive signal 8 BUSB analog output MIL-STD-1553 bus driver B, negative signal Receiver A enable. If low, forces RXA and RXA low (HI-1567) or High (HI-1568) Receiver B enable. If low, forces RXB and RXB low (HI-1567) or High (HI-1568) 9 RXENB digital input 10 GNDB power supply Ground for channel B 11 RXB digital output Receiver B output, inverted 12 RXB digital output Receiver B outpot, non-invertedl 13 TXINHB digital input Transmit inhibit, channel B. If high BUSB, BUSB disabled 14 TXB digital input Transmitter B digital data input, non-inverted 15 TXB digital input Transmitter B digital data input, inverted 16 RXA digital output Receiver A output, inverted 17 RXA digital output Receiver A output, non-inverted 18 TXINHA digital input Transmit inhibit, channel A. If high BUSA, BUSA disabled 19 TXA digital input Transmitter A digital data input, non-inverted 15 TXA digital input Transmitter A digital data input, inverted FUNCTIONAL DESCRIPTION The HI-1567 family of data bus transceivers contain differential voltage source drivers and differential receivers. They are intended for applications using a MIL-STD-1553 A/B data bus. The device produces a trapezoidal output waveform during transmission. The transmitter is automatically inhibited and placed in the high impedance state when both TXA/B and TXA/B are either at a logic “1” or logic “0” simultaneously. A logic “1:” applied to the TXINHA/B input will force the transmitter to the high impedance state, regardless of the state of TXA/B and TXA/B TRANSMITTER RECEIVER Data input to the transmitter section of these devices is from the complimentary CMOS /TTL inputs TXA/B and TXA/B. This produces a nominal 30V peak to peak signal across a 140 ohm load. The transmitter is connected to the bus via a 1:2.5 transformer whose secondary is connected to two 52 ohm isolation resisters which feed the terminated 70 ohm bus. This will produce a nominal voltage on the bus of 7.5 volts peak to peak. The receiver is transformer coupled to the bus by a 1:1 transformer. Its differential input stage drives a filter and threshold comparator. CMOS/TTL data is outputted at the RXA/B and RXA/B pins. The receiver outputs can both be forced to a logic "0" (HI-1567) or logic “1” (HI-1568) by setting RXENA or RXENB low. HOLT INTEGRATED CIRCUITS 2 HI-1567, HI-1568 Data Bus Each Channel TRANSMITTER Isolation Transformer Coupler Network BUSA/B TXA/B Transmit Logic Direct or Transformer Slope Control TXA/B BUSA/B TXINHA/B RECEIVER RXA/B Receive Logic Input Filter RXA/B Comparator RXENA/B Figure 1. Block Diagram TXA/B TXA/B BUSA/B - BUSA/B Vin (Line to Line) RXA/B RXA/B HOLT INTEGRATED CIRCUITS 3 HI-1567, HI-1568 RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS Supply voltage (VDD) Logic input voltage range -0.3 V to +7 V -0.3 V dc to +5.5 V Receiver differential voltage 10 Vp-p Driver peak output current +1.0 A Power dissipation at 25°C ceramic DIL, derate 0.5 W 7mW/°C Supply Voltage VDD....................................... 5V... ±5% Temperature Range Solder Temperature 275°C for 10 sec Storage Temperature -65°C to +150°C Industrial Screening.........-40°C to +85°C Hi-Temp Screening........-55°C to +125°C Military Screening..........-55°C to +125°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. VDD = 5.0V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS 4.75 5 5.25 V 22 mA Operating Voltage VDD Total Supply Current ICC1 Not Transmitting ICC2 Transmit one channel @ 50% duty cycle 320 340 mA ICC3 Transmit one channel @ 100% duty cycle 570 615 mA Power Dissipation PD1 Not Transmitting 0.4 W PD2 Transmit one channel @ 100% duty cycle 0.95 W 0.8 V 20 µA Min. Input Voltage (HI) VIH Digital inputs Max. Input Voltage (LO) VIL Digital inputs Min. Input Current (HI) IIH VIH = 4.9V, Digital inputs Max. Input Current (LO) IIL VIL = 0.1V, Digital inputs -20 µA Min. Output Voltage (HI) VOH IOUT = -0.4mA, Digital outputs 2.7 V Max. Output Voltage (LO) VIH IOUT = 4.0mA, Digital outputs RECEIVER 1.4 1.4 V 0.4 V (Measured at Point “VIN” in Figure 2) Input resistance Rin Differential Input capacitance Cin Differential Common mode rejection ratio CMRR Input Level Vin Input common mode voltage VICM Threshold Voltage VTH TRANSMITTER 2.0 20 kohm 5 40 Differential 1 MHz Sine Wave pF dB 8 Vp-p -5.0 5.0 V-pk 0.56 1.2 Vp-p (Measured at Point “A” in Figure 2) Output Voltage Output Noise Output Dynamic Offset Voltage Vout VON Vdyn 35 ohm load 7.0 9.0 Vp-p 140 ohm load 28.0 36.0 Vp-p 10.0 mVp-p Differential, inhibited Across 35 ohm load -90 90 mV Across 140 ohm load -360 360 mV 10 Output resistance Rout Differential, not transmitting Output Capacitance Cout 1 MHz sine wave HOLT INTEGRATED CIRCUITS 4 kohm 15 pF HI-1567, HI-1568 VCC = 5.0V, VSS = 0V, TA =Operating Temperature Range (unless otherwise specified). PARAMETER RECEIVER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 450 ns 40 ns 150 ns (Measured at Point “VIN” in Figure 2) Receiver Delay tDR Receiver Enable Delay tREN From input zero crossing to RXA/B or RXA/B From RXENA/B rising or falling edge to RXA/B or RXA/B TRANSMITTER (Measured at Point “A” in Figure 2) Driver Delay tDT TXA/B, TXA/B to BUSA/B, BUSA/B Rise time tr 35 ohm load 100 300 ns Fall Time tf 35 ohm load 100 300 ns tDI-H Inhibited output 100 ns tDI-L Active output 150 ns Inhibit Delay TRANSMITTER 1:2.5 BUSA/B TXA/B 55 Ω 35 Ω TXA/B BUSA/B A 55 Ω TXINHA/B 55 Ω 2.5:1 RECEIVER RXA/B VIN 35 Ω RXA/B 55 Ω RXENA/B Figure 2. Test circuit HOLT INTEGRATED CIRCUITS 5 HI-1567, HI-1568 ORDERING INFORMATION HI-1567PSI 0 20 PIN PLASTIC ESOIC - WB -40°C TO +85°C I NO SOLDER HI-1567PST 0 20 PIN PLASTIC ESOIC - WB -55°C TO +125°C T NO SOLDER HI-1567CD 0 20 PIN CERAMIC SIDE BRAZED DIP -40°C TO +85°C I NO GOLD HI-1567CDT 0 20 PIN CERAMIC SIDE BRAZED DIP -55°C TO +125°C T NO GOLD HI-1567CDM 0 20 PIN CERAMIC SIDE BRAZED DIP -55°C TO +125°C M YES SOLDER HI-1567CDM-03 0 20 PIN CERAMIC SIDE BRAZED DIP -55°C TO +125°C M YES SOLDER HI-1568PSI 1 20 PIN PLASTIC ESOIC - WB -40°C TO +85°C I NO SOLDER HI-1568PST 1 20 PIN PLASTIC ESOIC - WB -55°C TO +125°C T NO SOLDER HI-1568CDI 1 20 PIN CERAMIC SIDE BRAZED DIP -40°C TO +85°C I NO GOLD HI-1568CDT 1 20 PIN CERAMIC SIDE BRAZED DIP -55°C TO +125°C T NO GOLD HI-1568CDM 1 20 PIN CERAMIC SIDE BRAZED DIP -55°C TO +125°C M YES SOLDER HI-1568CDM-03 1 20 PIN CERAMIC SIDE BRAZED DIP -55°C TO +125°C M YES SOLDER Legend: ESOIC - Thermally Enhanced Small Outline Package (SOIC w/built-in heat sink) WB - Wide Body HOLT INTEGRATED CIRCUITS 6 PACKAGE DIMENSIONS inches (millimeters) 20-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB (Wide Body, Thermally Enhanced) .0105 ± .0015 (.2667 ± .0381) .5035 ± .0075 (12.789 ± .191) .4065 ± .0125 (10.325 ± .318) Top View Package Type: 24HEW Heat sink stud on bottom of package. .300 TYP. (7.620) Bottom View .215 TYP. (5.461) .296 ± .003 (7.518 ± .076) .025 Min.. (.635) SEE DETAIL A .018 TYP. (.457) .025 Min.. (.635) .090 ± .010 (2.286 ± .254) 0° to 8° .050 TYP (1.27) .0075 ± .0035 (.191 ± .889) .033 ± .017 (.838 ± .432) DETAIL A 20-PIN CERAMIC SIDE-BRAZED DIP PACKAGE TYPE: 20C 1.000 ± .010 (25.400 ± .254) .310 ± .010 (7.874 ± .254) .050 TYP. (1.270 TYP.) .200 MAX. (5.080 MAX.) .125 MIN. (3.175 MIN.) .300 ± .010 (7.620 ± .254) .085 ± .009 (2.159 ± .229) .017 ± .002 (.432 ± .051) .100 ± .005 (2.540 ± .127) HOLT INTEGRATED CIRCUITS 7 .010 + .002/− .001 (.254 ± .051/−.025)