Maxim MAX6916EO33 Spi-compatible rtc with microprocessor supervisor, alarm, and nv ram controller Datasheet

19-3694; Rev 0; 10/05
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Features
The MAX6916 provides all the features of a real-time
clock (RTC) plus a microprocessor supervisory circuit,
NV RAM controller, and backup-battery monitor function. In addition, 96 x 8 bits of static RAM are available
for scratchpad storage. The MAX6916 communicates
with a microprocessor through an SPI™-bus-compatible serial interface.
♦ Real-Time Clock Counts
Seconds, Minutes, Hours, Date, Month, Day of
Week, and Year with Leap-Year Compensation
Through 2099
The real-time clock/calendar provides seconds, minutes, hours, day, date, month, and year information.
The end of the month date is automatically adjusted for
months with fewer than 31 days, including corrections
for leap years through 2099. The clock operates in
either 24hr or 12hr format with an AM/PM indicator. A
time/date-programmable alarm function is provided
with an open-drain, active-low alarm output.
♦ SPI Interface Supports Modes 1 and 3 (0, 1 and 1, 1)
The microprocessor supervisory circuit features an
open-drain, active-low reset available in three different
reset thresholds. A manual reset input and a watchdog
function are included as well.
The NV RAM controller provides power for external SRAM
from a backup battery plus chip-enable gating. The backup battery also provides data retention of the on-board 96
x 8 bits of RAM. An open-drain, active-low, battery-on signal alerts the system when operating from a battery.
The battery-test circuitry periodically tests the backup
battery for a low-battery condition. An optional external
resistor network selects different battery thresholds. A
freshness seal prevents battery drain until the first VCC
power-up.
The MAX6916 has a crystal-fail-detect circuit and a
data-valid bit. The MAX6916 is available in a 20-pin
QSOP package and is guaranteed to operate over the
-40°C to +85°C extended temperature range.
Applications
♦ 4MHz SPI-Bus-Compatible Interface at 5V, 2MHz
at 3V, and 3.3V
♦ 96 x 8 Bits of RAM for Scratchpad Data Storage
♦ Uses Standard 32.768kHz, 6pF Load, Watch
Crystal
♦ Single-Byte or Multiple-Byte (Burst Mode) Data
Transfer for Read or Write of Clock Registers or
RAM
♦ Battery Monitor and Low-Battery Warning Output
Internal Default for Lithium Backup-Battery
Testing
Pins Available for Other Backup-Battery
Testing Configurations
♦ Dual Power-Supply Pins for Primary and Backup
Power
♦ Battery-On Output
♦ NV RAM Controller
Chip-Enable Gating (Control of CE with Reset
and Power Valid)
VOUT for SRAM Power
♦ µP Supervisor with Watchdog Input
♦ Programmable Time/Date Alarm Output
♦ Data Valid Bit (Loss of All Voltage Alerts User of
Corrupt Data)
Point-of-Sale Equipment
♦ Crystal-Fail Detect
Programmable Logic Controllers
♦ Small 20-Pin, QSOP Surface-Mount Package
Intelligent Instruments
Fax Machines
Ordering Information
Digital Thermostats
Industrial Controls
Pin Configuration and Selector Guide appear at end of data
sheet.
SPI is a trademark of Motorola, Inc.
TEMP RANGE
PINPACKAGE
PKG
CODE
MAX6916EO30+
-40°C to +85°C
20 QSOP
E20-2
MAX6916EO33+
-40°C to +85°C
20 QSOP
E20-2
MAX6916EO50+
-40°C to +85°C
20 QSOP
E20-2
PART
+Denotes lead-free package.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX6916
General Description
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
ABSOLUTE MAXIMUM RATINGS
VBATT, VCC to GND ...............................................-0.3V to +6.0V
All Other Pins to GND.................................-0.3V to (VCC + 0.3V)
All Other Pins to GND..............................-0.3V to (VBATT + 0.3V)
Input Currents
VCC ............................................................................200mA
VBATT ...........................................................................20mA
GND ..............................................................................20mA
All Other Pins ..............................................................±20mA
Output Currents
VOUT Continuous .........................................................200mA
All Other Outputs ...........................................................20mA
Continuous Power Dissipation (TA = +70°C)
20-Pin QSOP (derate 9.1mW/°C over +70°C).............727mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2)
PARAMETER
Operating Voltage Range
(Note 3)
Operating Voltage Range BATT
(Note 4)
SYMBOL
VCC
VBATT
MIN
TYP
MAX
MAX6916EO30
CONDITIONS
2.7
3.0
3.3
MAX6916EO33
3.0
3.3
3.6
MAX6916EO50
4.5
5.0
5.5
MAX6916EO30
2.0
5.5
MAX6916EO33
2.0
5.5
MAX6916EO50
2.0
5.5
VBATT = 2V, VCC = 0
XTAL FAIL
disabled
Timekeeping Current VBATT
(Note 5)
IBATT
XTAL FAIL
enabled
XTAL FAIL
disabled
Active Supply Current VCC
(Note 6)
ICCA
XTAL FAIL
enabled
XTAL FAIL
disabled
Standby Current VCC
(Note 5)
ICCS
XTAL FAIL
enabled
2
V
V
1
VBATT = 3V, VCC = 0
1.4
VBATT = 3.6V, VCC = 0
1.9
VBATT = 5.5V, VCC = 0
3.8
VBATT = 2V, VCC = 0
1.23
VBATT = 3V, VCC = 0
1.61
VBATT = 3.6V, VCC = 0
2.3
VBATT = 5.5V, VCC = 0
4.08
VCC = 3.3V, VBATT = 0
0.35
VCC = 3.6V, VBATT = 0
0.4
VCC = 5.5V, VBATT = 0
1.1
VCC = 3.3V, VBATT = 0
0.36
VCC = 3.6V, VBATT = 0
0.42
VCC = 5.5V, VBATT = 0
1.2
VCC = 3.3V, VBATT = 0
20
VCC = 3.6V, VBATT = 0
25
VCC = 5.5V, VBATT = 0
76
VCC = 3.3V, VBATT = 0
27
VCC = 3.6V, VBATT = 0
30
VCC = 5.5V, VBATT = 0
81
_______________________________________________________________________________________
UNITS
µA
mA
µA
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VOUT
VOUT in VCC Mode
(Note 4)
VOUT
VOUT in Battery-Backup Mode
(Notes 4, 7)
VOUT
VCC = 2.7V, VBATT = 0, IOUT = 35mA
VCC 0.2
VCC = 3.0V, VBATT = 0, IOUT = 35mA
VCC 0.2
VCC = 4.5V, VBATT = 0, IOUT = 70mA
VCC 0.2
VBATT = 2V, VCC = 0, IOUT = 400µA
VBATT 0.02
VBATT = 3V, VCC = 0, IOUT = 800µA
VBATT 0.03
VBATT = 4.5V, VCC = 0, IOUT = 1.5mA
VBATT 0.05
V
V
VBATT-to-VCC Switchover
Threshold
VTRU
Power-up (VCC < VRST) switch from VBATT
to VCC (Note 7)
VBATT
+ 0.1
V
VCC-to-VBATT Switchover
Threshold
VTRD
Power-down (VCC < VRST) switch from VCC
to VBATT (Note 7)
VBATT
- 0.1
V
CE_IN AND CE_OUT (Figures 7, 11, 12, 13)
CE_IN Leakage Current
IIL, IIH
Disabled, VCC < VRST,
V CE_IN = VCC or GND
-1
+1
µA
CE_IN-to-CE_OUT Resistance
VCC = VCC(MIN), VIH = 0.9VCC, CE_OUT =
GND, VIL = 0.1VCC, CE_OUT = VCC
46
140
Ω
CE_IN-to-CE_OUT Propagation
Delay
tCED
50Ω source impedance driver,
CLOAD = 10pF, VCC = VCC(MIN),
VIH = 0.9VCC, VIL = 0.1VCC
(Note 8); measured from 50% point on
CE_IN to the 50% point of CE_OUT
10
20
ns
RESET Active to CE_OUT High
Delay
tRCE
MR high to low
2
10
50
µs
CE_OUT Active-Low Delay after
VCC > VRST
tRP
140
200
280
ms
CE_OUT Output High Voltage
VOH
IOH = -100µA, VBATT = 2V, VCC = 0,
RESET = low
0.8 x
VBATT
V
MR INPUT (Figure 7)
VIL
MR Input Voltage
0.8
VIH
MR Pullup Resistance
2.0
Internal pullup resistor
MR Minimum Pulse Width
50
kΩ
1
MR Glitch Immunity
tGW
MR to RESET Delay
tRD
VCC = VCC(MIN), VBATT = 0
V
µs
450
35
ns
600
ns
_______________________________________________________________________________________
3
MAX6916
DC ELECTRICAL CHARACTERISTICS (continued)
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
s
WDI INPUT (Figure 9)
VCC > VRST from rising edge of RESET
1.00
1.6
2.25
tWDL
Long watchdog timeout period
1.00
1.6
2.25
s
tWDS
Short watchdog timeout period
140
200
280
ms
WDI Initial Timeout Period
Watchdog Timeout Period
Minimum WDI Input Pulse Width
WDI Input Threshold
tWDI
ns
VWDI = VCC or GND
ICCSW
0.8
V
+100
nA
450
µA
2.0
VIH
WDI Input Leakage Current
VCC Standby Current with WDI
Max Frequency
100
VIL
-100
Watchdog frequency = 1MHz,
VCC = VCC(MAX) (Note 5)
BATTERY TEST AND TRIP (Figures 14, 15, and 16)
VBATT Trip Point
VBTP
Internal mode
2.45
2.6
2.7
V
TRIP Input Threshold
VTRIP
VCC = VCC(MAX), VBATT = 2V,
external mode
1.14
1.24
1.31
V
TRIP Input Comparator
Hysteresis
VTRIP_HYST
10
TRIP Input Current
ITRIP_LKG
Battery Test Load
RLOAD_INT Internal
TEST Output High Voltage
VTEST_HIG
H
TEST Output Low Voltage
External mode
-100
0.5
0.91
mV
+100
nA
1.3
MΩ
VOUT 0.3V
ITEST = -5mA
V
VTEST_LOW ITEST = 5mA
0.3
V
BATT_LO, ALM OUTPUT
VOL
VBATT = 2V, VCC = 0, IOL = 5mA
0.5
Output Low Voltage
VOL
VCC = 2.7V, VBATT = 0, IOL = 10mA
0.5
VOL
VCC = 4.5V, VBATT = 0, IOL = 20mA
Off-Leakage
ILKG
V
0.5
-100
+100
nA
BATT_ON OUTPUT
Output Low Voltage
Off-Leakage
VOL
VBATT = 2V, VCC = 0, IOL = 5mA
0.5
VOL
VBATT = 2.7V, VCC = 0, IOL = 10mA
0.5
VOL
VBATT = 4.5V, VCC = 0, IOL = 20mA
0.5
ILKG
-100
+100
V
nA
RESET
RESET Threshold Voltage
VRST Hysteresis
VCC Falling-Reset Delay
4
VRST
MAX6916EO30
2.5
2.63
2.7
MAX6916EO33
2.8
2.93
3.0
MAX6916EO50
4.1
4.38
4.5
VHYST
tRPD
30
VCC falling from VRST(MAX)
to VRST(MIN) measured from
the beginning of VCC falling
to RESET low
mV
MAX6916EO30
27
75
MAX6916EO33
37
90
MAX6916EO50
50
120
_______________________________________________________________________________________
V
µs
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
140
200
280
ms
0.2
V
+100
nA
Main Reset Active-Timeout Period
tRP
RESET Output-Low Voltage
VOL
Off-Leakage
ILKG
-100
Input High Voltage
VIH
2
Input Low Voltage
VIL
RESET asserted, IOL = 1.6mA, VBATT = 2V,
VCC = 0
SPI DIGITAL INPUTS DIN, SCLK, CS
Input Hysteresis
V
0.8
0.05 x
VCC
VHYS
Input Leakage Current
VIN = 0 to VCC
Input Capacitance
(Note 8)
-100
V
V
+100
nA
10
pF
SPI DIGITAL OUTPUT DOUT
Output High Voltage
VOH
IOH = -1.6mA
Output Low Voltage
VOL
IOL = 1.6mA
0.4
V
(Note 8)
10
pF
+100
nA
Output Capacitance
Output Off-State Leakage Current
0.9 x VCC
IOZ
V
-100
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPI BUS TIMING (Figure 2 (Note 9))
Maximum-Input Rise Time
tRIN
DIN, SCLK, CS
2
µs
Maximum-Input Fall Time
tFIN
2
µs
10
ns
10
ns
Output Rise Time
tROUT
DIN, SCLK, CS
DOUT, CLOAD = 100pF
Output Fall Time
tFOUT
DOUT, CLOAD = 100pF
MAX6916EO30, MAX6916EO33
500
MAX6916EO50
238
MAX6916EO30, MAX6916EO33
200
MAX6916EO50
100
MAX6916EO30, MAX6916EO33
200
MAX6916EO50
100
SLCK Period
tCP
SCLK High Time
tCH
SCLK Low Time
tCL
SCLK Fall to DOUT Valid
tDO
DIN-to-SCLK Setup Time
tDS
100
ns
DIN-to-SCLK Hold Time
tDH
0
ns
SCLK Rise to CS Rise Hold Time
tCSH
0
ns
CS High Pulse Width
tCSW
200
ns
CS High-to-DOUT High
Impedance
tCSZ
CS to SCLK Setup Time
tCSS
CLOAD = 100pF
ns
ns
ns
100
100
100
ns
ns
ns
BATTERY TEST TIMING (Figure 15)
Battery Test to BATT_LO Active
tBL
(Note 8)
1
s
_______________________________________________________________________________________
5
MAX6916
DC ELECTRICAL CHARACTERISTICS (continued)
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Battery Test Cycle—Normal
tBTCN
(Note 8)
Battery Test Pulse Width
tBTPW
(Note 8)
MIN
TYP
MAX
24
UNITS
hr
1
s
Note 1: VRST is the reset threshold for VCC. See the Ordering Information.
Note 2: All parameters are 100% tested at TA = +85°C. Limits over temperature are guaranteed by design and are not production
tested.
Note 3: The SPI serial interface is operational for VCC > VRST.
Note 4: See the Detailed Description (VOUT function).
Note 5: ICCS is specified with CS = VCC, SCLK = DIN = WDI = CE_IN = GND, DOUT, VOUT, CE_OUT, and MR floating. IBATT is
specified with WDI = CE_IN = SCLK = DIN = GND, CS = VCC, DOUT, VOUT, CE_OUT, and MR floating.
Note 6: ICCA is specified with SCLK = 4MHz for VCC = +5.5V and SCLK = 2MHz for VCC = +3.3V and +3.6V. DOUT = OPEN, CS =
GND, DIN = VCC, CE_IN = VCC, VOUT and CE_OUT open, WDI = VCC or GND.
Note 7: For OUT switchover to BATT, VCC must fall below VRST and VBATT. For OUT switchover to VCC, VCC must be above VRST or
above VBATT.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: All values are referred to VIH(MIN) and VIL(MAX) levels.
Typical Operating Characteristics
(VCC = 3.3V, VBATT = 3V, TA = +25°C, unless otherwise noted.)
VCC-TO-OUT VOLTAGE vs. TEMPERATURE
VCC = 3V
VBATT = 0V
IOUT = 35mA
25.0
22.5
VCC = 3.3V
VBATT = 0V
IOUT = 35mA
20.0
17.5
MAX6916 toc02
9
8
VCC = 0V
VBATT = 3V
IOUT = 800µA
7
6
5
4
3
2
VCC = 0V
VBATT = 2V
IOUT = 400µA
1
15.0
0
-40
-15
10
35
60
85
-40
-15
TEMPERATURE (°C)
TIMEKEEPING CURRENT vs. TEMPERATURE
SCLK = GND, DOUT = OPEN
CS = VCC, DIN = GND
CE_IN = GND
XTAL FAIL ENABLED
1.6
1.5
60
85
TIMEKEEPING CURRENT vs. TEMPERATURE
SCLK = GND, DOUT = OPEN
CS = VCC, DIN = GND
CE_IN = GND
XTAL FAIL DISABLED
1.7
1.6
1.5
IBATT (µA)
1.4
1.3
1.2
1.4
1.3
1.2
1.1
1.1
1.0
1.0
0.9
0.9
0.8
0.8
-40
-15
10
35
TEMPERATURE (°C)
6
35
1.8
MAX6916 toc03a
1.8
1.7
10
TEMPERATURE (°C)
MAX6916 toc03b
VCC-TO-OUT VOLTAGE (mV)
27.5
BATT-TO-OUT VOLTAGE vs. TEMPERATURE
10
BATT-TO-OUT VOLTAGE (mV)
MAX6916 toc01
30.0
IBATT (µA)
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
60
85
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
RESET COMPARATOR DELAY
vs. VCC FALLING
RESET DELAY (µs)
220
210
200
100
10
190
50
MAX6916 toc06
230
MAX6916 toc05
1000
MAX6916 toc04
RESET TIMEOUT PERIOD (ms)
240
RESET COMPARATOR DELAY
vs. TEMPERATURE
VCC FALLING AT 10V/ms
45
RESET COMPARATOR DELAY (µs)
RESET TIMEOUT PERIOD
vs. TEMPERATURE
40
35
30
25
20
15
10
180
-15
10
35
60
1
10
100
1000
-40
-15
10
35
60
85
TEMPERATURE (°C)
VCC FALLING (V/ms)
TEMPERATURE (°C)
RESET THRESHOLD vs. TEMPERATURE
(MAX6916EO33)
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
MAXIMUM TRANSIENT DURATION
vs. RESET COMPARATOR OVERDRIVE
2.925
RESET GOES LOW BELOW
THIS THRESHOLD
2.900
2.875
230
220
210
200
190
100
180
-40
-15
10
35
60
60
50
40
30
20
-40
-15
10
35
60
100 150 200 250 300 350 400 450 500
85
CHIP-ENABLED PROPAGATION DELAY
vs. CE_OUT LOAD CAPACITANCE
(MAX6916EO33)
CHIP-ENABLED PROPAGATION DELAY
vs. CE_OUT LOAD CAPACITANCE
(MAX6916EO33)
ACTIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
3
VCC = 3.3V
2
VCC = 5V
4
VCC = 3.3V
3
VCC = 5V
2
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
1
0
MAX6919 toc12
0.300
VCC = 3V
5
SCLK - 2MHz, DOUT = OPEN
CS = GND, DIN = CE_IN = VCC
XTAL FAIL ENABLED
0.375
0.350
0.325
6
0
0
0.400
MAX6916 toc111
FALLING EDGE OF CE_IN TO
FALLING EDGE OF CE_OUT
7
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
ICCA (mA)
VCC = 3V
8
CHIP-ENABLED PROPAGATION DELAY (ns)
MAX6916 toc10
5
0
RESET ASSERTS ABOVE THIS LINE
70
OVERDRIVE (mV)
6
1
80
TEMPERATURE (°C)
RISING EDGE OF CE_IN TO
RISING EDGE OF CE_OUT
4
90
TEMPERATURE (°C)
8
7
85
MAX6916 toc09
MAX6916 toc08
WD TIME BIT SET TO 1
MAXIMUM TRANSIENT DURATION (µs)
2.950
240
WATCHDOG TIMEOUT PERIOD (ms)
MAX6916 toc07
RESET GOES HIGH ABOVE
THIS THRESHOLD
2.975
RESET THRESHOLD (V)
0.1
85
3.000
CHIP-ENABLED PROPAGATION DELAY (ns)
5
1
-40
0.275
0.250
0.225
0.200
TA = +85°C
TA = -40°C
TA = +25°C
0.175
0.150
0.125
0.100
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
MAX6916
Typical Operating Characteristics (continued)
(VCC = 3.3V, VBATT = 3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = 3.3V, VBATT = 3V, TA = +25°C, unless otherwise noted.)
SCLK = GND, DOUT = OPEN
CS = VCC, DIN = GND
CE_IN = GND
XTAL FAIL ENABLED
2.75
2.50
0.325
2.25
0.300
0.275
IBATT (mA)
TA = +85°C
0.250
0.225
0.200
0.175
0.150
0.125
0.100
TA = -40°C
TA = +25°C
TA = +85°C
TA = +25°C
1.50
2.50
4.3
4.7
5.1
5.5
2.5
3.0
3.5 4.0
VBATT (V)
0.05
MAX6916 toc16
VCC = +3.3V
0.04
VCC = +5V
0.03
0.02
5.0
2.0
5.5
2.5
3.0
3.5 4.0
VBATT (V)
0.025
0.020
VBATT TO VOUT DROP (V)
VCC TO VOUT DROP (V)
VCC = +2.7V
4.5
VBATT TO VOUT DROP vs. OUTPUT CURRENT
(BATTERY BACKUP MODE)
VCC TO VOUT DROP vs. OUTPUT CURRENT
(NORMAL MODE)
0.06
TA = -40°C
0.50
2.0
SUPPLY VOLTAGE (V)
0.07
TA = +25°C
MAX6916 toc17
3.9
1.50
0.75
0.50
3.5
TA = +85°C
1.75
1.00
TA = -40°C
0.75
3.1
2.00
1.25
1.25
1.00
2.7
SCLK = GND, DOUT = OPEN
CS = VCC, DIN = GND
CE_IN = GND
XTAL FAIL DISABLED
2.75
2.25
2.00
1.75
3.00
IBATT (mA)
SCLK - 2MHz, DOUT = OPEN
CS = GND, DIN = CE_IN = VCC
XTAL FAIL DISABLED
MAX6916 toc14
3.00
MAX6919 toc13
0.400
0.375
0.350
TIMEKEEPING CURRENT
vs. SUPPLY VOLTAGE
TIMEKEEPING CURRENT
vs. SUPPLY VOLTAGE
VBATT = +2V
0.015
0.010
VBATT = +5V
VBATT = +3.3V
0.005
0.01
0
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
8
MAX6919 toc15
ACTIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
ICCA (mA)
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
0
0.4
0.8
1.2
1.6
2.0
2.4
OUTPUT CURRENT (mA)
_______________________________________________________________________________________
4.5
5.0
5.5
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
PIN
NAME
FUNCTION
1
VOUT
Supply Output for External SRAM or Other ICs Requiring Use of Backup Battery Power. When VCC rises
above the reset threshold or above VBATT, VOUT is connected to VCC. When VCC falls below VRESET and
VBATT, VBATT is connected to VOUT. Connect a 0.1µF low-leakage bypass capacitor from VOUT to GND.
Leave open if not used.
2
TEST
External Battery Test. Active high for 1s during each battery test. Intended to drive an external MOSFET
or bipolar transistor for an external battery-test configuration. External test must be selected in the control
register to use TEST; otherwise, it remains low. Leave open if not used.
3
TRIP
External Trip Set. If a different battery-low threshold is desired other than the internal POR default of
VBTP, then connect RSET+ between VBATT and TRIP and RSET- between TRIP and the drain or collector of
an external transistor whose base or gate is connected to TEST; see Figure 14 (see the Battery Test
section). External test must be selected in the control register to use TRIP. Leave open if not used.
4
BATT_ON
5
CE_IN
Open-Drain, Battery-On Indicator. BATT_ON is active low when the MAX6916 is powered from VBATT.
Chip-Enable Input. The input to the chip-enable gating circuitry. Connect CE_IN to GND if unused.
MR
Manual-Reset Input. A logic-low on MR asserts RESET. RESET remains asserted as long as MR is low
and for tRP after MR returns high. The active-low MR input has an internal pullup resistor. MR can be
driven from a TTL- or CMOS-logic line or shorted to ground with a switch. Internal debouncing circuitry
ensures noise immunity. Leave MR open if unused.
7
WDI
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the
internal watchdog timer runs out and RESET is asserted. The internal watchdog timer clears while RESET
is asserted or when WDI sees a rising or falling edge. The watchdog function can be disabled from the
control register. The timeout period is configurable in the control register for 200ms or 1.6s.
8
GND
Ground
6
9
X1
32.768kHZ Crystal-Oscillator Input
10
X2
32.768kHZ Crystal-Oscillator Output
_______________________________________________________________________________________
9
MAX6916
Pin Description
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6916
Pin Description (continued)
PIN
NAME
11
DIN
SPI Serial Bus Data Input
12
CS
SPI Serial Bus Chip-Select Input. Drive CS low to initiate a data transfer.
13
DOUT
SPI Serial Bus Data Output
14
SCLK
SPI Serial Bus Clock Input
15
ALM
Open-Drain, Active-Low Alarm Output. ALM goes low when RTC time matches alarm thresholds set in
the alarm threshold registers. ALM stays low until cleared by reading or writing to the alarm configuration
register or to any of the alarm threshold registers.
16
CE_OUT
Chip-Enable Output. CE_OUT goes low only when CE_IN is low and RESET is not asserted. If CE_IN is
low when RESET is asserted, CE_OUT remains low for tRCE or until CE_IN goes high, whichever occurs
first. CE_OUT is pulled to VOUT.
17
BATT_LO
Open-Drain, Battery-Low Indicator. BATT_LO is active low when the VBATT input is tested below VBTP if
the internal trip is selected in the control register (POR default). If external trip is selected in the control
register, then BATT_LO is active low when TRIP is less than VTRIP.
18
RESET
19
VCC
20
VBATT
FUNCTION
Open-Drain, Active-Low Reset Output. RESET pulses low for tRP when triggered, and stays low
whenever VCC is below the reset threshold or when MR is logic-low. RESET remains low for tRP after
either VCC rises above the reset threshold or MR goes from low to high.
Main Supply Input. Connect a 0.1µF bypass capacitor from VCC to GND.
Backup-Battery Input. When VCC falls below the reset threshold and VBATT, VOUT switches from VCC to
VBATT. When VCC rises above VBATT or the reset threshold, VOUT reconnects to VCC. VBATT may exceed
VCC. Connect VBATT to GND if no backup-battery supply is used. Connect a 0.1µF low-leakage bypass
capacitor from VBATT to GND.
Detailed Description
Functional Description
The MAX6916 contains eight 8-bit timekeeping registers,
seven 8-bit alarm threshold registers, one status register,
one control register, one alarm-configuration register, and
96 x 8 bits of SRAM. In addition to single-byte reads and
writes to registers and RAM, there is a burst timekeeping
register read/write command, a burst RAM read/write
command, and a battery-test command that allows software-commanded testing of the backup battery at any
time. An SPI-bus-compatible interface allows serial communication with a microprocessor. When VCC is less than
the reset threshold, the serial interface is disabled to prevent erroneous data from being written to the MAX6916.
A microprocessor supervisory section and an NVRAM
controller are provided for ease of implementation with
microprocessor-based systems. A crystal-fail-detect circuit and a data-valid bit can be used to guarantee RAM
data integrity and valid timekeeping data. Time and calendar data are stored in a binary-coded decimal (BCD)
format. Figure 1 shows the functional diagram of the
MAX6916.
10
Real-Time Clock
The RTC provides seconds, minutes, hours, day, date,
month, and year information. The end of the months is
automatically adjusted for months with fewer than 31
days, including corrections for leap years through 2099.
Crystal Oscillator
The MAX6916 uses an external, standard 6pF load
watch crystal. No other external components are
required for this timekeeping oscillator. Power-up oscillator start time is dependent mainly upon applied VCC
and ambient temperature. The MAX6916, because of
its low timekeeping current, exhibits a typical startup
time of 1s to 2s.
SPI-Compatible Interface
Interface the MAX6916 to a microcontroller using a
4-wire, serial peripheral interface (SPI). The SPI is a
synchronous bus for address and data transfer and is
used when interfacing with Motorola and other microcontrollers with an SPI port. Four connections are
required for the interface: DOUT (serial data out), DIN
(serial data in), SCLK (serial clock), and CS (chip
select). The MAX6916 acts as a slave device and the
______________________________________________________________________________________
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6916
WATCHDOG
TIMER
WDI
RESET
MAX6916
RESET
LOGIC
DEBOUNCE
CIRCUIT
MR
CRYSTALFAIL
DETECT
X1
XTAL FAIL
DIVIDERS
OSCILLATOR
32.768kHz
X2
CE
CONTROL
CE_IN
CE_OUT
SECONDS
MINUTES
TEST
HOURS
TRIP
GND
DATE
POWER
CONTROL
AND
MONITOR
VBATT
VOUT
VCC
BATT_LO
MONTH
CONTROL
LOGIC
BATT_ON
DAY
YEAR
CONTROL
CENTURY
SCLK
INPUTSHIFT
REGISTERS
CS
DIN
DOUT
ALARM
CONFIG
ADDRESS
REGISTER
BATT
TEST
STATUS
96 x 8
RAM
ALARM
CONTROL
LOGIC
ALM
DATA
VALID
LOGIC
CONFIG
ALARM
THRESHOLDS
CLOCK
BURST
RAM
BURST
Figure 1. Functional Diagram
______________________________________________________________________________________
11
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
tCSH
CS
tCSS
tCH
tCSW
tCP
SCLK
tCL
tDH
tDS
DIN
D7
D6
D5
D0
tCSZ
DOUT
D7
D0
tDO
Figure 2. SPI Bus Timing Diagram
microcontroller acts as the master in an SPI application.
CS is asserted low by the microcontroller to initiate a
transfer and deasserted high to terminate a transfer.
DIN transfers input data to the MAX6916 from the
microcontroller, and DOUT transfers output data from
the MAX6916 to the microcontroller. SCLK is used to
synchronize data movement between the microcontroller and the MAX6916. SCLK, which is generated by
the microcontroller, is active only during address and
data transfer to any device on the SPI bus. The inactive
clock polarity is usually programmable on the microcontroller side of the SPI interface. For the MAX6916,
input data (DIN) is latched on the positive edge and
output data (DOUT) is shifted out on the negative edge.
There is one clock for each bit transferred. Address
and data bits are transferred in groups of eight. Figure
2 shows an SPI bus timing diagram.
The SPI protocol allows for one of four combinations of
serial clock phase and polarity from the microcontroller,
through a 2-bit selection in its SPI control register. The
clock polarity is specified by the CPOL control bit,
which selects active-high or active-low clock, and has
no significant effect on the transfer format. The clockphase control bit, CPHA, selects one of two different
transfer formats. The clock phase and polarity must be
identical for the master and the slave. For the
MAX6916, set the control bits to CPHA = 1 and CPOL =
1. This setting configures the system for data to be
launched on the negative edge of SCLK and sampled
on the positive edge. With CPHA equal to 1, CS can
remain low between successive data byte transfers,
allowing burst-mode data transfers to occur.
12
Address and data bytes are shifted, most significant bit
(MSB) first, into the serial data input DIN of the
MAX6916 and out of the serial data output DOUT. Data
is shifted out at the negative edge of SCLK and shifted
in or sampled at the positive edge of SCLK. Any transfer requires the address of the byte to be followed by 1
or more bytes of data. Data is transferred out of DOUT
for a read operation and into DIN for a write operation.
When not transferring data out, DOUT is put into a highimpedance state (Figure 2).
To maximize battery life and prevent erroneous data
from being entered into the MAX6916, the serial bus
interface is disabled when VCC is below VRST or when
RESET is active.
In order to initiate SPI communications with the
MAX6916, CS needs to be driven low, after which an
address/command byte must be input. The
address/command byte specifies the register to or from
which information is to be transferred, as well as the
nature of the transfer (read or write). After the
address/command byte, 1 or more data bytes can be
written or read. For a single-byte transfer, 1 byte is written or read and then CS is driven high by the microcontroller (Figures 3 and 5). For a multiple-byte transfer,
however, multiple bytes can be read or written to the
MAX6916 after the address/command byte has been
written (Figures 4 and 6). In the case of burst operation,
each read or write cycle causes the RTC register or
RAM address to automatically increment. Incrementing
continues (maximum value is 96 for RAM and 8 for register bank) until SPI transmission is terminated. To terminate the SPI transmission, drive CS high.
______________________________________________________________________________________
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
determines if a read (logic 1) or write (logic 0) takes
place. Data transfers can occur 1 byte at a time or in
multiple-byte burst mode. Bits 6–0 specify the designated register or RAM location to be read or written to.
Figures 3, 4, 5, and 6 show the different transfer operations that can take place with the MAX6916.
SINGLE WRITE
CS
SCLK
0
DIN
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
ADDRESS/COMMAND BYTE
D3
D2
D1
D0
DATA BYTE
DOUT
DOUT IS HIGH IMPEDANCE; THERE IS NO ACTIVITY ON DOUT DURING WRITES
Figure 3. SPI Interface Single Write
BURST WRITE
CS
SCLK
0
DIN
A6
A5
A4
A3
A2
A1
A0
D7
ADDRESS/COMMAND BYTE
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE N
DATA BYTE 1
DOUT
DOUT IS HIGH IMPEDANCE; THERE IS NO ACTIVITY ON DOUT DURING WRITES
Figure 4. SPI Interface Multiple/Burst Write
SINGLE READ
CS
SCLK
DIN
1
A6
A5
A4
A3
A2
A1
A0
ADDRESS/COMMAND BYTE
DOUT
DOUT IS HIGH IMPEDANCE
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
Figure 5. SPI Interface Single Read
______________________________________________________________________________________
13
MAX6916
Address/Command Byte
Each data transfer into or out of the MAX6916 is initiated by an address/command byte. The address/command byte specifies which registers are to be
accessed, and if the access is a read or write. The
address command byte is input MSB (bit 7) first. Bit 7
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
BURST READ
CS
SCLK
DIN
1
A6
A5
A4
A3
A2
A1
A0
ADDRESS/COMMAND BYTE
DOUT
DOUT IS HIGH IMPEDANCE
D7
D6
D5
D4
D3
DATA BYTE 1
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE N
Figure 6. SPI Interface Multiple/Burst Read
Chip Select (CS)
CS serves two functions. First, CS turns on the control
logic that allows access to the shift register for
address/command and data transfer. Second, CS provides a method of terminating either single-byte or multiple-byte data transfers. All data transfers are initiated
by driving CS low. If CS is high, then DOUT is high
impedance.
Serial Clock (SCLK)
A clock cycle on SCLK consists of a rising edge followed by a falling edge. For data input, data must be
valid at DIN before the rising edge of the clock. For
data outputs, bits are valid on DOUT after the falling
edge of the clock.
Reading from the Timekeeping Registers
The timekeeping registers (seconds, minutes, hours,
date, month, day, and year) and the control register
can be read either with a single read (Figure 5) or a
burst read (Figure 6). Since the RTC runs continuously
and a read takes a finite amount of time, there is the
possibility that the clock counters could change during
a read operation, thereby reporting inaccurate timekeeping data. In the MAX6916, each clock counter’s
data is buffered by a latch. Clock counter data is
latched by the SPI bus read command (on the falling
edge of SCLK after the address/command byte has
been sent by the master to read a timekeeping register). Collision-detection circuitry ensures that this does
not happen coincident with a seconds counter update
to ensure accurate time data is being read. This avoids
time-data changes during a read operation. The clock
counters continue to count and keep accurate time during the read operation.
14
If single reads are used to read each of the timekeeping registers individually, then it is necessary to do
some error checking on the receiving end. An error can
occur when the seconds counter increments before all
the other registers are read out. For example, suppose
a carry of 13:59:59 to 14:00:00 occurs during singleread operations of the timekeeping registers. Then the
net data could become 14:59:59, which is erroneous
real-time data. To prevent this with single-read operations, read the seconds register first (initial seconds)
and store this value for future comparison. When the
remaining timekeeping registers have been read out,
read the seconds register again (final seconds). If the
initial seconds value is 59, check that the final-seconds
value is still 59; if not, repeat the entire single-read
process for the timekeeping registers. A comparison of
the initial-seconds value with the final-seconds value
can indicate if there was a bus-delay problem in reading the timekeeping data (difference should always be
1s or less). Using a 2MHz bus speed, and sequential
single reads, it would take under 75µs to read all seven
of the timekeeping registers plus a second read of the
seconds register.
The most accurate way to read the timekeeping registers is to perform a burst read. With burst reads, the
main timekeeping registers (seconds, minutes, hours,
date, month, day, year) and the control register are
read sequentially, in the order listed with the seconds
register first. They must be all read out as a group of
eight registers, with 8 bytes each, for proper execution
of the burst-read function. All seven timekeeping registers are latched upon the receipt of the burst-read command. Worst-case error that can occur between the
actual time and the read time is 1s.
______________________________________________________________________________________
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
If single-write operations (Figure 3) are used to write to
each of the timekeeping registers, then error checking is
needed. If the seconds register is the one to be updated, update it first and then read it back and store its
value as the initial seconds. Update the remaining timekeeping registers and then read the seconds register
again (final seconds). If initial seconds was 59, ensure it
is still 59. If initial seconds was not 59, ensure that final
seconds is within 1s of initial seconds. If the seconds
register is not to be written to, then read the seconds
register first and save it as initial seconds. Write to the
required timekeeping registers and then read the seconds register again (final seconds). If initial seconds
was 59, ensure it is still 59. If initial seconds was not 59,
ensure that final seconds is within 1s of initial seconds.
Although both single writes and burst writes are possible, the most accurate way to write to the timekeeping
counters is to do a burst write (Figure 4). In the burst
write, the main timekeeping registers (seconds, minutes, hours, date, month, day, year) and the control
register are written sequentially. They must be all written to as a group of eight registers, with 8 bytes each,
for proper execution of the burst-write function. All
seven timekeeping registers and the control register
are simultaneously loaded into the clock counters at the
rising edge of CS, at the end of the SPI bus write operation. The worst-case error that can occur between the
actual time and the write time update is 1s.
To avoid rollover issues when writing time data to the
MAX6916, the remaining time and date registers must
be written within 1s of updating the seconds register
when using single writes. For burst writes, all eight registers must be written within this period (1s).
The weekday data in the day register increments at
midnight. Values that correspond to the day of week
are user defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday, and so on). If
invalid values are written to the timekeeping registers,
operation becomes undefined.
Registers
Tables 1 and 2 show the register map, as well as the
register descriptions for the MAX6916.
Control Register
The control register contains bits for configuring the
MAX6916 for custom applications. Bit D0 (BATT ON
BLINK) and D1 (BATT LO BLINK) are used to enable a
1Hz blink rate on BATT_ON and BATT_LO when they
are active; see the Battery Test section for details. D2
(WD TIME) and D3 (WD EN) are used to enable the
watchdog function and select its timeout. For details,
see the Watchdog Input section. D5 (INT/EXT TEST)
sets whether the internal resistor ratio or an external
resistor ratio is to be used to check for the low-battery
condition; see the Battery Test section for details. D6
(XTAL EN) enables the crystal-fail-detect circuitry when
set. See the Crystal-Fail Detect section for details. D7
(WP) is the write-protect bit. Before any write operation
to the registers (except the control register) or RAM, bit
7 must be zero. When set to one, the write-protect bit
prevents write operations to any register (except the
control register) or RAM locations.
Timekeeping and Alarm Thresholds Registers
Time and date data is stored in the timekeeping and
alarm threshold registers in BCD format as shown in Table
1. The weekday data in the day register is user defined (a
common format is 1 = Sunday, 2 = Monday, etc.).
AM-PM/12–24 Mode
For both timekeeping and alarm threshold registers
(Table 1), D7 of the hours register is defined as the
12hr or 24hr mode-select bit. When set to one, the 12hr
mode is selected. In the 12hr mode, D5 is the AM/PM
bit with logic one being PM. In the 24hr mode, D5 is the
second 10hr bit (20hr to 23hr).
______________________________________________________________________________________
15
MAX6916
Writing to the Timekeeping Registers
The time and date can be set by writing to the timekeeping registers (seconds, minutes, hours, date,
month, day, year, and century). To avoid changing the
current time by an incomplete write operation, the current time value is buffered from being written directly to
the clock counters. The new data sent replaces the current contents of this input buffer. This time update data
is loaded into the clock counters at the rising edge of
CS, which indicates the end of the SPI bus write operation. Collision-detection circuitry ensures that this does
not happen coincident with a seconds-counter update
to guarantee that accurate time data is being written.
This avoids time data changes during a write operation.
An incomplete write operation aborts the time-update
procedures and the contents of the input buffer are discarded. The clock counter is reset immediately after a
write to the seconds register or a burst write to the timekeeping registers. This process ensures that 1s clock
tick is synchronous to timekeeping writes.
Table 1. Register Map
REGISTER ADDRESS
A7
CLOCK
BURST
R
SEC
REGISTER FUNCTION
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
W
R
0–59
W
MIN
R
R
W
DATE
MONTH
R
0
0
0
0
1
0
0
0
0
0
0
1
0
1
W
DAY
YEAR
R
W
R
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
W
CONTROL
R
W
CENTURY
R
0
0
0
1
0
0
1
0
0
0
1
0
1
0
W
ALARM
CONFIGURATION
R
R
0
0
0
1
1
0
D5
D4
D3
D2
10 SEC
0
D0
1 SEC
0
0
0
0
0
0
0
10 MIN
0
0
0
1 MIN
0
0
0
12/24
0
POR STATE
0
0
0
01–28/29
01–30/31
POR STATE
0
0
10 DATE
0
0
POR STATE
0
0
10 HR
00–23
AM/
PM
10 HR
1 HR
0
0
0
0
0
0
0
01–12
0
0
0
10 M
0
0
0
0
01–07
POR STATE
0
0
0
0
0
0
0
0
0
0
00–99
POR STATE
0
0
1
1 MONTH
0
0
0
1
WEEKDAY
0
0
1
0
0
1 YEAR
10 YEAR
0
1
1
1
0
WP
XTAL
EN
INT/
EXT
TEST
0
WD
EN
POR STATE
0
1
0
0
1
00–99
POR STATE
0
0
0
1
1
ONE
SEC
YEAR
DAY
0
0
0
XTAL
FAIL
0
0
0
1 DATE
POR STATE
POR STATE
0
BATT BATT
WD
LO
ON
TIME BLINK BLINK
0
0
0
0
1
DATE
HR
MIN
SEC
0
0
0
0
0
BATT
LO
ALM
OUT
0
0
0
0
0
0
0
0
0
0
0
1000 YEAR
0
100 YEAR
POR STATE DEFINES THE POWER-ON RESET STATE OF THE REGISTER
16
D1
0
W
W
D6
0
POR STATE
STATUS
D7
01–12
W
R
POR STATE
0–59
W
HR
VALUE
MONTH
FUNCTION
DATA
VALID
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
______________________________________________________________________________________
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6916
Table 1. Register Map (continued)
REGISTER ADDRESS
FUNCTION
BATT TEST
REGISTER FUNCTION
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
VALUE
D7
D6
D5
D4
D3
D2
D1
D0
ALARM
THRESHOLDS:
R
SEC
0–59
W
R
MIN
R
HR
W
R
DATE
W
R
MONTH
W
R
DAY
W
R
YEAR
R
1
1
1 SEC
1
1
0
1
10 MIN
1
1
1
1
12/24
0
POR STATE
1
0
1
1
1
1
01–28/29
01–30/31
POR STATE
0
0
0
0
10 DATE
1
1
1
POR STATE
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
0
1
1
1
1
1
0
0
1 MIN
AM/
PM
1
1
1
1
1 DATE
1
1
1
10 HR
1 HR
01–12
0
0
0
10 M
POR STATE
0
0
0
1
1
01–07
POR STATE
0
0
0
0
0
0
0
0
0
0
0
0
00–99
POR STATE
1
1
1
1
1
1
0
1
POR STATE
0
0
0
0
1
1
1
1
RAM DATA 0
00h–FFh
X
X
X
1
1
1
1
0
RAM DATA 95
00h–FFh
X
X
X
1
1
1
1
1
W
1
10 HR
00–23
01–12
W
TEST
CONFIGURATION
(FACTORY
RESERVED)
10 SEC
1
0–59
W
0
1
POR STATE
1 MONTH
1
1
1
1
WEEKDAY
1
1
1
1
1
0
0
0
0
X
X
X
X
X
X
X
X
X
X
10 YEAR
1
1 YEAR
RAM REGISTERS:
RAM 0
R
W
RAM 95
R
W
RAM BURST
R
W
POR STATE DEFINES THE POWER-ON RESET STATE OF THE REGISTER
______________________________________________________________________________________
17
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Clock-Burst Mode
Addressing the clock-burst register specifies burstmode operation. In this mode, the first eight clock/calendar registers (seven timekeeping and the control
register) can be consecutively read or written to by
using the address/command byte 00h for a write or 80h
for a read (Table 1). If the write-protect bit is set to one
when a write-clock/calendar-burst mode is specified,
no data transfer occurs to any of the seven timekeeping
registers or the control register. When writing to the
clock/calendar registers in the burst mode, the first
eight registers must be written to for the data to be
transferred; see Table 2.
RAM
The static RAM consists of 96 x 8 bits addressed consecutively in the RAM address/command space.
Address/commands (1Fh to 7Eh) are used for RAM
writes and address/commands (9Fh to FEh) are used
for RAM reads (Table 2).
RAM-Burst Mode
Sending the RAM burst address/command (7Fh for
write, FFh for read) specifies burst-mode operation. In
this mode, the 96 RAM locations can be consecutively
read or written to starting with bit 7 of address/command 1Fh for writes, and 9Fh for reads. A burst read
outputs all 96 bytes of RAM. When writing to RAM in
burst mode, it is not necessary to write all 96 bytes for
the data to transfer; each complete byte written is
transferred to the RAM. When reading from RAM, data
is output until all 96 bytes have been read, or until the
CS is driven high.
Status Register
The status register contains individual bits for monitoring the status of several functions of the MAX6916. Bits
D0–D3 are unused and always read zero (Table 1). D4
(ALM OUT) reflects the state of the alarm function; see
the Alarm Function section for details. D5 (BATT LO)
indicates the state of the battery connected to VBATT;
see the Battery Test section for more information. D6
(DATA VALID) alerts the user if all power was lost. See
the Data Valid Bit section for details. D7 (XTAL FAIL) is
the output of the crystal-fail detect circuit. See the
Crystal-Fail Detect section for details.
Power Control
VBATT provides power as a battery backup. VCC provides the primary power in dual-supply systems where
VBATT is connected as a backup source to maintain
timekeeping in the absence of primary power. When
VCC rises above the reset threshold, VRST, VCC powers
the MAX6916. When VCC falls below the reset threshold, VRST, and is less than VTRD, VBATT powers the
18
MAX6916. If VCC falls below the reset threshold, VRST,
and is more than VTRU, VCC still powers the MAX6916.
The VCC slew rate in power-down is limited to 10V/ms
(max) for proper data retention.
VOUT Function
VOUT is an output supply voltage for battery-backed-up
devices such as SRAM. When V CC rises above the
reset threshold or is greater than VBATT, VOUT connects
to VCC (Figure 16). When V CC falls below V RST and
V BATT , V OUT connects to V BATT . There is a typical
±100mV hysteresis associated with the switching
between VCC and VBATT on the VOUT output. Connect
a 0.1µF capacitor from VOUT to GND.
Power-On Reset (POR)
The MAX6916 contains an integral POR circuit that
ensures all registers are reset to a known state on powerup. Once either VCC or VBATT rises above 1.6V (typ), the
POR circuit releases the registers for normal operation.
When VCC or VBATT drops to less than 0.9V (typ), the
MAX6916 resets all register contents to the POR defaults.
Oscillator Start Time
The MAX6916 oscillator typically takes 1s to 2s to begin
oscillating. To ensure the oscillator is operating correctly, the system software should validate proper timekeeping. This validation is accomplished by reading
the seconds register. Any reading with more than 0s,
from the POR value of 0s, is a validation of proper startup.
Alarm-Generation Function
The alarm function is configured using the alarm-configuration register and the alarm-threshold registers
(Tables 1 and 2). Writing a one to D7 (ONE SEC) in the
alarm-configuration register sets the alarm function to
occur once every second, regardless of any other setting in the alarm-configuration register or in any of the
alarm-threshold registers. When the alarm is triggered,
D4 (ALM OUT) in the status register is set to one and
the open-drain alarm output ALM goes low. The alarm
is cleared by reading or writing to the alarm-configuration register or by reading or writing to any of the alarmthreshold registers. This process resets the ALM output
to a high and the ALM OUT bit to zero.
When D7 (ONE SEC) is set to zero in the alarm-configuration register, then the alarm function is set by the
remaining bits in the alarm-configuration register and
the contents of the respective alarm-threshold register.
For example, writing 01h (0000 0001) to the alarm-configuration register causes the alarm to trigger every
time the seconds-timekeeping register matches the
seconds alarm-threshold register (i.e., once every
minute on a specific second). Writing 02h (0000 0010)
to the alarm-configuration register causes the alarm to
______________________________________________________________________________________
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6916
Table 2. Hex Register Address and Description
WRITE ADDRESS/COMMAND
(HEX)
READ ADDRESS/COMMAND
(HEX)
DESCRIPTION
POR SETTING
(HEX)
00
80
Clock burst
N/A
01
81
Seconds
00
02
82
Minutes
00
03
83
Hour
00
04
84
Date
01
05
85
Month
01
06
86
Day
01
07
87
Year
70
08
88
Control
48
09
89
Century
19
0A
8A
Alarm configuration
00
0C
8C
Status
00
0D
N/A
Battery test
N/A
0E
8E
Seconds alarm threshold
7F
0F
8F
Minutes alarm threshold
7F
10
90
Hours alarm threshold
BF
11
91
Date alarm threshold
3F
12
92
Month alarm threshold
1F
13
93
Day alarm threshold
07
14
94
Year alarm threshold
FF
15
95
Test configuration
00
1F
9F
RAM 0
Indeterminate
20
A0
RAM 1
Indeterminate
21
A1
RAM 2
Indeterminate
22
A2
RAM 3
Indeterminate
23
A3
RAM 4
Indeterminate
•
•
•
•
•
•
•
•
•
•
•
•
7A
FA
RAM 91
Indeterminate
7B
FB
RAM 92
Indeterminate
7C
FC
RAM 93
Indeterminate
7D
FD
RAM 94
Indeterminate
7E
FE
RAM 95
Indeterminate
7F
FF
RAM BURST
N/A
trigger on a minutes match (i.e., once every hour).
Writing a 4Fh (0100 1111) to the alarm configuration
register causes the alarm to be triggered on a specific
second, of a specific minute, of a specific hour, of a
specific date, of a specific year.
When setting the alarm-threshold registers, ensure that
______________________________________________________________________________________
19
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
both the hour-timekeeping register and the hour-alarmthreshold register are using the same hour format
(either 12hr or 24hr format).
The alarm function as well as the ALM output are operational in both VCC and battery-backup mode.
MR
CE OUT
tRCE
tRP
Crystal-Fail Detect
The crystal-fail detect circuit looks for a loss of oscillation
from the 32.768kHz oscillator for 30 cycles (typ) or more.
Both the control register and the status register are used
in the crystal-failure detection scheme (Table 1).
The crystal-fail detect circuit sets the XTAL FAIL bit in
the status register to one for a crystal failure and to zero
for normal operation. Once the status register is read,
the XTAL FAIL bit is reset to zero, if it was previously
one. If the crystal-fail-detect circuit continues to sense
a failed crystal, then the XTAL FAIL bit is set again.
On initial power-up, the crystal-fail detect circuit is
enabled. Since it takes a while for the low-power,
32.768kHz oscillator to start, the XTAL FAIL bit in the
status register can be set to one, indicating a crystal
failure. The XTAL FAIL bit should be polled a number of
times to see if it is set to zero for successive polls. If the
polling is far enough apart, a few polled results could
guarantee that a maximum of 10s had elapsed since
power-on, at which time the oscillator would be considered truly failed if the XTAL FAIL bit remains one.
On subsequent power-ups, when XTAL EN is set to
one, if XTAL FAIL is set to one, time data should be
considered suspect.
The crystal-fail-detection circuit functions in both VCC
and VBATT modes when the XTAL EN bit is set in the
control register.
Manual Reset Input
A logic-low on MR asserts RESET. RESET remains
asserted while MR is low, and for tRP after it returns
high (Figure 7). MR has an internal pullup resistor, so it
can be left open if it is not used. Internal debounce circuitry requires a minimum low time on the MR input of
1µs with 35ns maximum glitch immunity.
Reset Output
A microprocessor’s (µP’s) reset input starts the µP in a
known state. The MAX6916’s µP supervisory circuit
asserts a reset to prevent code-execution errors during
power-up, power-down, and brownout conditions. The
RESET output is guaranteed to be active for 0V < VCC
< VRST, provided VBATT is greater than VBATT (min). If
VCC drops below and then exceeds the reset threshold,
an internal timer keeps RESET active for the reset
timeout period tRP; after this interval, RESET becomes
20
tRP
RESET
CE IN
Figure 7. Manual Reset Timing Diagram
inactive high. This condition occurs at either power-up
or after a VCC brownout.
The RESET output is also activated when the watchdog
interrupt function is enabled but no transition is detected on the WDI input. In this case, RESET is active for
the period tRP before becoming inactive again. When
RESET is active, all inputs—WDI, MR, CE_IN, DIN, CS,
and SCLK—are disabled. DOUT is also disabled.
The MAX6916EO30 is optimized to monitor 3.0V ±10%
power supplies. Except when MR is asserted, RESET is
not active until VCC falls below 2.7V (3.0V - 10%), but is
guaranteed to occur before the power supply falls
below 2.5V (3.0V - 15%).
The MAX6916EO33 is optimized to monitor 3.3V ±10%
power supplies. Except when MR is asserted, RESET is
not active until VCC falls below 3.0V (3.0V is just above
3.3V - 10%), but is guaranteed to occur before the
power supply falls below 2.8V (3.3V - 15%).
The MAX6916EO50 is optimized to monitor 5.0V ±10%
power supplies. Except when MR is asserted, RESET is
not active until VCC falls below 4.5V (5.0V - 10%), but is
guaranteed to occur before the power supply falls
below 4.2V (4.2V is just below 5.0V - 15%).
Negative-Going VCC Transients
The MAX6916 is relatively immune to short-duration
negative transients (glitches) while issuing resets to the
µP during power-up, power-down, and brownout conditions. Therefore, resetting the µP when V CC experiences only small glitches is usually not recommended.
Typically, a VCC transient that goes 150mV below the
reset threshold and lasts for 50µs or less does not
cause a reset pulse to be issued. A 0.1µF capacitor
mounted close to the VCC pin provides additional transient immunity.
______________________________________________________________________________________
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6916
BUFFER
VCC
VRST
VCC
VCC
VCC
tRP
µP
MAX6916
RESET
4.7kΩ
RESET
tRP
tWD
tWD
RESET
WDI
GND
WD EN AND WD TIME ARE SET
TO ZERO AND THE WATCHDOG
FUNCTION IS DISABLED.
GND
Figure 8. Interfacing to µP with Bidirectional Reset I/O
Interfacing to Microprocessors with
Bidirectional Reset Pins
Microprocessors with bidirectional reset pins, such as
the Motorola 68HC11 series, can contend with the
MAX6916 RESET output. If, for example, the RESET
output is driven high and the µP wants to pull it low,
indeterminate logic levels can result. To correct this,
connect a 4.7kΩ resistor between the RESET output
and the µP reset I/O as shown in Figure 8. Buffer the
RESET output to other system components.
Battery-On Output
The battery-on output, BATT_ON, is an open-drain output that indicates when the MAX6916 is powered from
the backup-battery input, VBATT. When VCC falls below
the reset threshold, V RST , and below V BATT , V OUT
switches from VCC to VBATT and BATT_ON becomes
low. When VCC rises above the reset threshold, VRST,
VOUT reconnects to VCC and BATT_ON becomes high
(open-drain output with pullup resistor). If desired, the
BATT_ON output can be register selected, through the
BATT ON BLINK bit in the control register, to toggle on
and off (0.5s on, 0.5s off) when active. The POR default
is logic zero for no blink.
Watchdog Input
The watchdog circuit monitors the µP’s activity. If the
µP does not toggle the watchdog input (WDI) within the
register-selectable watchdog-timeout period, RESET is
asserted for tRP. At the same time, the WD EN and WD
TIME bits in the control register (Table 1) are reset to
zero and can only be set again by writing the appropriate command to the control register. Thus, once a
RESET is asserted due to a watchdog timeout, the
watchdog function is disabled (Figure 9).
Figure 9. Watchdog Timing Diagram
WDI can detect pulses as short as tWDI. Data bit D2
in the control register controls the selection of the watchdog-timeout period. The power-up default is 1.6s
(D2 = 0). A reset condition returns the timeout to 1.6s
(D2 = 0). If D2 is set to one, then the watchdog-timeout
period is changed to 200ms. Data bit D3 in the control
register is the watchdog-enable function. A logic zero disables the watchdog function, while a logic one enables it.
The POR state of WD EN is logic one, or the watchdog
function is enabled. Disable the watchdog function by
writing a zero to the WD EN bit in the control register,
within the 1.6s POR default timeout after power-up.
WDI does not include a pulldown or pullup feature. For
this reason, WDI should not be left floating. When the
WD EN bit in the control register is set to zero, WDI
should be connected to VCC or GND. WDI is disabled
and does not draw cross-conduction current when VCC
falls below VRST.
Watchdog Software Considerations
There is a way to help the watchdog-timer monitor software execution more closely, which involves setting and
resetting the watchdog input at different points in the
program rather than “pulsing” the watchdog input. This
technique avoids a “stuck” loop, in which the watchdog
timer would continue to be reset within the loop, keeping
the watchdog from timing out. Figure 10 shows an
example of a flow diagram where the I/O driving the
watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or
loop, then set high again when the program returns to
the beginning. If the program should “hang” in any subroutine, the problem would quickly be corrected since
the I/O is continually set low and the watchdog timer is
allowed to time out, causing a reset to be issued.
______________________________________________________________________________________
21
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
START
MAX6916
VOUT
SET WDI
HIGH
CHIP-ENABLE
OUTPUT
CONTROL
PROGRAM
CODE
RESET
GENERATOR
SUBROUTINE OF
PROGRAM LOOP
SET WDI LOW
CE_IN
CE_OUT
RETURN
Figure 10. Watchdog Flow Diagram
Figure 11. Chip-Enable Gating
Chip-Enable Gating
Internal gating of chip-enable (CE) signals prevents
erroneous data from corrupting external SRAM in the
event of an undervoltage condition. The MAX6916 uses
a transmission gate from CE_IN to CE_OUT (Figure 11).
During normal operation (RESET inactive), the transmission gate is enabled and passes all CE transitions.
When reset is asserted, this path becomes disabled,
preventing erroneous data from corrupting the external
SRAM. The short CE propagation delay from CE_IN to
CE_OUT enables the MAX6916 to be used with most
microprocessors. If CE_IN is low when reset asserts,
CE_OUT remains low for tRCE to permit completion of
the current write cycle.
The propagation delay through the CE transmission
gate depends on VCC, the source impedance of the
driver connected to CE_IN, and the loading on
CE_OUT (see the Chip-Enable Propagation Delay vs.
CE_OUT Load Capacitance graph in the Typical
Operating Characteristics). For minimum propagation
delay, the capacitive load at CE_OUT should be minimized, and a low-output-impedance driver should be
used on CE_IN (Figure 12).
VCC
Chip-Enable Input
The CE transmission gate is disabled and CE_IN is
high impedance (disabled mode) while RESET is
active. During a power-down sequence when V CC
passes the reset threshold, the CE transmission gate
disables and CE_IN immediately becomes high impedance if the voltage at CE_IN is high. If CE_IN is low
when RESET becomes active, the CE transmission gate
disables at the moment CE_IN goes high or tRCE after
RESET is active, whichever occurs first (see the ChipEnable Timing section). This condition permits the current write cycle to complete during power-down. The
CE transmission gate remains disabled and CE_IN
remains high impedance (regardless of CE_IN activity)
for most of the reset-timeout period (tRST) any time a
RESET is generated. When the CE transmission gate is
enabled, the impedance of CE_IN appears as a 46Ω
(typ) load in series with the load at CE_OUT.
22
VCC
BATT
3.6V
25Ω EQUIVALENT
SOURCE IMPEDANCE
MAX6916
50Ω
50Ω CABLE
CE_IN
CE_OUT
CL
10pF
50Ω
GND
CL INCLUDES LOAD CAPACITANCE AND SCOPE PROBE CAPACITANCE
Figure 12. Propagation Delay Test Circuit
______________________________________________________________________________________
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6916
VRST
VRST
2.0V
VCC
tRPD
tRP
RESET
tRP
VCC
CE_OUT
VBATT
tRCE
tCED
CE_IN
Figure 13. Chip-Enable Timing Diagram
Chip-Enable Output
When the CE transmission gate is enabled, the impedance seen at CE_OUT is equivalent to a 46Ω (typ)
resistor in series with the source driving CE_IN. In the
disabled mode, the transmission gate is off and an
active pullup connects CE_OUT to VOUT (see Figures
11 and 13). This pullup turns off when the transmission
gate is enabled.
Test Configuration Register
This is a read-only register.
Data Valid Bit
DATA VALID has a POR setting of zero, indicating that
the data in the MAX6916 RTC is not guaranteed to be
valid (Table 1). A read of the status register sets the
DATA VALID bit to one, indicating valid data in the
MAX6916 RTC. In a system that uses a backup power
supply, the DATA VALID bit should be set to one by the
system software on first system power-up by reading the
status register. After that, any time the system recovers
from a reset condition caused by VCC < VRST, the DATA
VALID bit can be read to see if the data stored during
operation from the backup power supply is still valid (i.e.,
the backup power supply did not drop out). A one indicates valid data, and a zero indicates corrupted data.
Any time the internal supply to the MAX6916 (either
VBATT or VCC depending upon the operating conditions)
drops below 1.5V to 1.6V (typ), the DATA VALID bit is set
to zero even if it has recently been set by a read of the
status register.
Battery Test
Battery-Test Normal Operation
In normal operation, the battery-test circuitry uses the
control register POR settings of INT/EXT TEST, which is
set to logic-low as default (Table 1). In this mode, all battery-test load resistors and threshold settings are internal.
When VCC rises above VRST, the MAX6916 automatically
performs one power-on battery monitor test. Additionally,
a battery check is performed every time that a reset is
issued, either from a manual reset or from a watchdog
timeout. After that, periodic battery voltage monitoring at
the factory-programmed time interval of 24hr begins while
VCC is applied.
______________________________________________________________________________________
23
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
VBATT
VCC
BATT_LO
BATT_LO
CONTROL
LOGIC
1.24V
RSET+_EXT
RSET+_INT
480kΩ
RLOAD_EXT
(OPTIONAL)
INT/EXT
TEST
TRIP
INT/EXT
TEST = 0
RSET-_EXT
VOUT
TEST
QEXT
RSET-_INT
430kΩ
BATT
TEST
(±5mA)
MAX6916
Figure 14. MAX6916 Battery Load and Test Circuit
After each 24hr period (t BTCN ) has elapsed, the
MAX6916 connects VBATT to an internal 0.91MΩ (typ)
test resistor (R SET+_INT + R SET-_INT) for 1s (t BTPW)
(Figure 14). During this 1s, if VBATT falls below the factory-programmed battery trip point V BTP, the opendrain, battery-low output, BATT_LO, is asserted active
low and the BATT LO bit in the status register is set to
one. The BATT LO output can be register selected to
toggle at a 1Hz rate (0.5s on, 0.5s off) when active.
Once BATT LO is active, the 24hr tests stop until a
fresh battery is inserted and BATT LO is cleared by
writing any data to the battery test register at address
0x0D (Figure 15). Writing to this register performs a
battery test and provided that the fresh battery is not
low, deactivates the BATT LO output and resets BATT
LO in the status register. Normal 24hr testing resumes.
If a different load or BATT LO thresholds are desired for
testing the backup battery, then external program resistors can be used in conjunction with the TRIP and TEST
inputs (see the Battery-Test Control Register and Other
Test Options section).
Battery replacement following BATT_LO activation
should be done with VCC nominal and not in battery-
24
backup mode so that SRAM data is not lost.
Alternatively, if SRAM data need not be saved, the battery can be replaced with the VCC supply removed. If a
battery is replaced in battery-backup mode, sufficient
time must be allowed for the voltage on the VOUT output to decay to zero. This timing ensures that the freshness-seal mode of operation has been reset and is
active when VCC is powered up again. If insufficient
time is allowed, then VCC must exceed VBATT during
the subsequent power-up to ensure that the MAX6916
has left battery-backup mode (Figure 16).
The MAX6916 does not constantly monitor an attached
battery because such monitoring would drastically
reduce the life of the battery. As a result, the MAX6916
only tests the battery for 1s every 24hr. If a good battery (one that has not been previously flagged with
BATT_LO) is removed between battery tests, the
MAX6916 does not immediately sense the removal and
does not activate BATT_LO until the next-scheduled
battery test. For this reason, a software-commanded
battery test should be performed after a battery
replacement by writing any data to the battery-test register at address 0Dh.
______________________________________________________________________________________
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6916
VRST
VCC
VBATT
VBTP (BATTERY TEST POINT)
tBTCN
tBTPW
BATTERYTEST ACTIVE
tBL
ONCE THE BATTERY IS DETECTED AS LOW,
THE PERIODIC BATTERY TESTING CEASES.
A BATTERY CHECK CAN BE INITIATED BY
WRITING TO THE REGISTER 0x0D.
BATT_LO
Figure 15. Battery Test Timing Diagram
VBATT
VRST
VRST
VRST
VRST
VCC
VBATT
0V
BATTERY
DETACH
BATTERY
ATTACH
BATTERY
DETACH
BATTERY
ATTACH
VBATT
FLOATING
VBATT
FLOATING
EXIT FRESHNESS
SEAL MODE
VOUT
0V
VBATT CONNECTED TO VOUT
VCC CONNECTED
TO VOUT
VBATT CONNECTED
TO VOUT
FRESHNESS
SEAL RESET
VCC CONNECTED
TO VOUT
VBATT CONNECTED
TO VOUT
Figure 16. Battery Switchover Diagram
Battery monitoring is only a useful technique when testing can be done regularly over the entire life of a lithium
battery. Because the MAX6916 only performs battery
monitoring when VCC is nominal, systems that are powered down for excessively long periods can completely
drain their lithium cells without receiving any advanced
warning. To prevent such an occurrence, systems
using the MAX6916 battery-monitoring feature should
be powered up periodically (at least every few months)
in order to perform battery testing. Furthermore, anytime BATT_LO is activated on the first battery test after
a power-up, data integrity should be checked through
a checksum or other technique. Timekeeping data
would also be suspect and should be checked for
accuracy against an accurate known reference.
Freshness-Seal Mode
When the battery is first attached to the MAX6916 without VCC power applied, the device does not immediately provide battery-backup power to VOUT (Figure 16).
Only after VCC exceeds VRST and later falls below both
VRST and VBATT does the MAX6916 leave freshnessseal mode and provide battery-backup power. This
mode allows a battery to be attached during manufacturing but not used until after the system has been activated for the first time. As a result, no battery energy is
drained during storage and shipping.
______________________________________________________________________________________
25
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
One final battery-test feature of the MAX6916 is the
software write address/command of 0Dh that forces a
1s battery test to be performed every time it is sent.
Rf
MAX6916
Applications Information
Crystal Selection
Cg
12pF
Cd
12pF
X1
X2
EXTERNAL
CRYSTAL
Figure 17. Oscillator Functional Schematic
Battery-Test Control Register
and Other Test Options
There are two warning formats for the BATT_LO and
BATT_ON outputs. By setting D0 (BATT ON BLINK)
and/or D1 (BATT LO BLINK) in the control register to
one, the respective warning output toggles on every
0.5s and off every 0.5s when set to active low by the
internal MAX6916 logic. This setting allows a more
noticeable warning indicator in systems where an LED
is connected as a status or warning light for the end
user. The POR default settings of zero leave these outputs set to logic-low when they are active.
D5 (INT/EXT TEST) selects whether the battery test circuit is configured as internal or external (Table 1). If D5
is set to zero (default value), then the internal resistordivider is used between VBATT and GND to select the
battery-low trip point (Figure 14). The internal resistors,
RSET+_INT and RSET-_INT, are used to divide VBATT in
half, as well as to provide the battery-test-load resistance of 0.91MΩ (typ).
If D5 (INT/EXT TEST) is set to one, then the two external
resistors, RSET+_EXT and RSET-_EXT, are used to divide
VBATT down to the ratio for a trip point set at TRIP of
1.24V (VTRIP) (typ). RSET+_EXT plus RSET-_EXT in series
provide the load resistance used during the 1s every24hr-battery test. If additional load resistance is
desired, then an external load resistor, RLOAD_EXT, can
be placed between VBATT and the collector or drain of
the transistor driven by TEST. The equivalent load resistance used to test the battery is then RLOAD_EXT in parallel with the series combination of RSET+_EXT plus
R SET-_EXT . In this mode, the internal resistors are
removed from TRIP and are not used as a load during
the battery-test pulse. TEST pulses high to perform the
battery test and remains low between tests.
Connect a 32.768kHz watch crystal directly to the
MAX6916 through pins 9 and 10 (X1, X2) (Figure 17).
Use a crystal with a specified load capacitance (CL) of
6pF. Refer to Applications Note 616: Considerations for
Maxim Real-Time Clock Crystal Selection from the
Maxim website (www.maxim-ic.com) for more information regarding crystal parameters and crystal selection,
as well as a list of crystal manufacturers.
When designing the PC board, keep the crystal as close
to the X1 and X2 pins of the MAX6916 as possible. Keep
the trace lengths short and small to reduce capacitive
loading and prevent unwanted noise pickup. Place a
guard ring around the crystal and connect the ring to
ground to help isolate the crystal from unwanted noise
pickup. Keep all signals out from beneath the crystal and
the X1 and X2 pins to prevent noise coupling. Finally, an
additional local ground plane on an adjacent PC board
layer can be added under the crystal to shield it from
unwanted pickup from traces on other layers of the board.
This plane should be isolated from the regular PC board
ground, connected to the GND pin of the MAX6916, and
needs to be no larger than the perimeter of the guard ring.
Ensure that this ground plane does not contribute to significant capacitance between the signal line and ground
on the connections that run from X1 and X2 to the crystal.
See Figure 18.
GROUND PLANE
VIA CONNECTION
*
GUARD RING
*
*
MAX6916
Rd
*
X1
*
**
*
X2
*
SM WATCH CRYSTAL
*
**
*
GROUND PLANE
VIA CONNECTION
**
*LAYER 1 TRACE
**LAYER 2 LOCAL GROUND PLANE
CONNECT ONLY TO PIN 8
GROUND PLANE VIA CONNECTION
Figure 18. Crystal Layout
26
*
*
______________________________________________________________________________________
GROUND
PLANE VIA
CONNECTION
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Pin Configuration
TOP VIEW
+
VOUT 1
Selector Guide
20 VBATT
TEST 2
19 VCC
TRIP 3
18 RESET
PART
SUPPLY VOLTAGE (V)
MAX6916EO30
3.0
MAX6916EO33
3.3
CE_IN 5
MAX6916EO50
5.0
MR 6
15 ALM
WDI 7
14 SCLK
GND 8
13 DOUT
BATT_ON 4
Chip Information
PROCESS: CMOS
17 BATT_LO
MAX6916
16 CE_OUT
X1 9
12 CS
X2 10
11 DIN
QSOP
Typical Application Circuit
3.3V
3.3V
3.3V
3.3V
LED
INTO
ALM
BATT_LO
SS
CS
N.C.
BATT_ON
X1
CRYSTAL
X2
3.3V
VCC
0.1µF
DOUT
MISO
DIN
MOSI
SCLK
SCK
RESET
RST
CE_IN
P1.0
µC
GND
WDI
MAX6916
TRIP
N.C.
N
TEST
VBATT
3.0V
N.C.
0.1µF
I/O
VOUT
0.1µF
CMOS SRAM
USER RESET
MR
CE_OUT
CE
GND
GND
______________________________________________________________________________________
27
MAX6916
For frequency stability over temperature, refer to the
Applications Note 617: Real-Time-Clock Selection and
Optimization from the Maxim website (www.maxim-ic.com.)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.