Cypress CY7C1440AV25-200BZI 36-mbit (1m x 36/2m x 18/512k x 72) pipelined sync sram Datasheet

CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined Sync SRAM
Functional Description[1]
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• 2.5V core power supply
• 2.5V/1.8V I/O powersupply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single-cycle Chip Deselect
• CY7C1440AV25, CY7C1442AV25 available in
JEDEC-standard lead-free 100-pin TQFP package,
lead-free and non-lead-free 165-ball FBGA package.
CY7C1446AV25 available in lead-free and non-lead- free
209-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 SRAM
integrates 1M x 36/2M x 18/512K x 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The
CY7C1440AV25/CY7C1442AV25/CY7C1446AV25
operates from a +2.5V core power supply while all outputs
may operate with a +2.5V/1.8V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
2.6
3.2
3.4
ns
Maximum Operating Current
435
385
335
mA
Maximum CMOS Standby Current
120
120
120
mA
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05350 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 21, 2006
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Logic Block Diagram – CY7C1440AV25 (1M x 36)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
ADSC
ADSP
BWD
DQD ,DQPD
BYTE
WRITE REGISTER
DQD ,DQPD
BYTE
WRITE DRIVER
BWC
DQC ,DQPC
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE DRIVER
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
DQA ,DQPA
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Logic Block Diagram – CY7C1442AV25 (2M x 18)
A0, A1, A
ADDRESS
REGISTER
2 A[1:0]
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BWB
DQB,DQPB
WRITE DRIVER
DQB,DQPB
WRITE REGISTER
MEMORY
ARRAY
BWA
DQA,DQPA
WRITE DRIVER
DQA,DQPA
WRITE REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
E
BWE
GW
CE1
CE2
CE3
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document #: 38-05350 Rev. *E
Page 2 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Logic Block Diagram – CY7C1446AV25 (512K x 72)
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
Q1
BINARY
COUNTER
CLR
Q0
ADV
CLK
ADSC
ADSP
BWH
DQH, DQPH
WRITE DRIVER
DQH, DQPH
WRITE DRIVER
BWG
DQF, DQPF
WRITE DRIVER
DQG, DQPG
WRITE DRIVER
BWF
DQF, DQPF
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
BWE
DQE, DQPE
WRITE DRIVER
DQ
E, DQP
BYTE
“a”E
WRITE DRIVER
BWD
DQD, DQPD
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
BWC
DQC, DQPC
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BWB
BWA
BWE
ENABLE
REGISTER
OUTPUT
BUFFERS
E
DQA, DQPA
WRITE DRIVER
DQA, DQPA
WRITE DRIVER
GW
CE1
CE2
CE3
OE
ZZ
DQB, DQPB
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
OUTPUT
REGISTERS
PIPELINED
ENABLE
INPUT
REGISTERS
DQs
DQPA
DQPB
DQPC
DQPD
DQPE
DQPF
DQPG
DQPH
SLEEP
CONTROL
Document #: 38-05350 Rev. *E
Page 3 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Pin Configurations
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1442AV25
(2M x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05350 Rev. *E
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
CY7C1440AV25
(1M x 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP Pinout
Page 4 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Pin Configurations (continued)
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1440AV25 (1M x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
2
A
3
4
5
6
7
8
9
10
11
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
NC/576M
VDDQ
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VDD
OE
VSS
VDD
A
NC
DQC
GW
VSS
VSS
ADSP
DQPC
DQC
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQB
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
TCK
A
A
A
A
8
9
10
11
A
A0
CY7C1442AV25 (2M x 18)
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
3
4
5
6
NC
CE3
A
CE1
CE2
BWB
NC/144M
NC
BWA
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VDDQ
R
7
CLK
BWE
GW
ADSC
OE
ADV
ADSP
A
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VDDQ
NC/1G
NC
NC/576M
A
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
DQB
DQB
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05350 Rev. *E
Page 5 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Pin Configurations (continued)
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1442AV25 (512K x 72)
1
2
3
7
8
9
10
11
A
DQG
DQG
ADV
CE3
A
DQB
DQB
B
DQG
DQG
BWSC
BWSG NC/288M BW
DQB
C
DQG
DQB
DQG
BWSH
BWSD NC/144M CE1
BWSA DQB
DQB
D
DQG
DQG
VSS
NC
NC/1G
OE
NC
VSS
E
DQB
DQB
DQPG
DQPC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPF
DQPB
F
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
G
DQF
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
H
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
J
DQF
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
K
NC
NC
CLK
NC
VSS
VSS
VSS
L
NC
NC
NC
NC
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
M
DQH
DQH
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQA
DQA
N
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
P
DQH
DQH
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQA
DQA
R
DQPD
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPA
T
DQD
DQD
NC
NC
MODE
NC
NC
VSS
DQE
DQE
U
DQD
DQD
V
DQD
DQD
W
DQD
DQD
A
DQPH VDDQ
VSS
4
CE2
5
6
ADSP ADSC
A
BWSB
NC/576M BWSE
GW
BWSF
DQPE
A
A
A
A
A
A
DQE
DQE
A
A
A
A1
A
A
A
DQE
DQE
TMS
TDI
A
A0
A
TCK
DQE
DQE
NC/72M
TDO
Pin Definitions
I/O
Description
A0, A1, A
Name
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]are sampled
active. A1: A0 are fed to the two-bit counter.
BWA, BWB, BWC,
BWD, BWE, BWF,
BWG, BWH
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX
and BWE).
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
InputClock
CE1
InputSynchronous
Document #: 38-05350 Rev. *E
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is
HIGH. CE1 is sampled only when a new external address is loaded.
Page 6 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Pin Definitions (continued)
Name
I/O
Description
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.Not available for AJ package
version.Not connected for BGA. Where referenced, CE3 is assumed active throughout
this document for BGA. CE3 is sampled only when a new external address is loaded.
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
InputAsynchronous
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPs
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state
condition.
VDD
Power Supply
Power supply inputs to the core of the device.
VSS
VSSQ
VDDQ
MODE
Ground
I/O Ground
Ground for the core of the device.
Ground for the I/O circuitry.
I/O Power Supply Power supply for the I/O circuitry.
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode Pin has an internal pull-up.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous
JTAG feature is not being utilized, this pin should be disconnected. This pin is not
available on TQFP packages.
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not being utilized, this pin can be disconnected or connected to VDD. This pin
is not available on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not being utilized, this pin can be disconnected or connected to VDD. This pin
is not available on TQFP packages.
TCK
JTAGClock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
NC
-
No Connects. Not internally connected to the die
NC/72M,NC/144M,
NC/288M,
NC/576,NC/1G
-
No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M and 1G are
address expansion pins are not internally connected to the die.
Document #: 38-05350 Rev. *E
Page 7 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Functional Overview
memory array. The Write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.6 ns
(250-MHz device).
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BWX
signals.
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 supports
secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence is
suited for processors that utilize a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the
Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
Document #: 38-05350 Rev. *E
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 provides
Byte Write capability that is described in the Write Cycle
Descriptions table. Asserting the Byte Write Enable input
(BWE) with the selected Byte Write (BWX) input, will selectively write to only the desired bytes. Bytes not selected during
a Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Because CY7C1440AV25/CY7C1442AV25/CY7C1446AV25
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE,
and BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV input is ignored
during this cycle. If a global Write is conducted, the data
presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Because CY7C1440AV25/CY7C1442AV25/CY7C1446AV25
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 provides
a two-bit wraparound counter, fed by A1: A0, that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel
Pentium applications. The linear burst sequence is designed
to support processors that follow a linear burst sequence. The
burst sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Page 8 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Interleaved Burst Address Table
(MODE = Floating or VDD)
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00
01
10
Second
Address
A1: A0
01
10
11
Third
Address
A1: A0
10
11
00
Fourth
Address
A1: A0
11
00
01
First
Address
A1: A0
11
Second
Address
A1: A0
00
Third
Address
A1: A0
01
Fourth
Address
A1: A0
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Document #: 38-05350 Rev. *E
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
100
2tCYC
2tCYC
2tCYC
0
Unit
mA
ns
ns
ns
ns
Page 9 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Truth Table [2, 3, 4, 5, 6, 7]
Add. Used
CE1
CE2
ADSP
ADSC
ADV
None
H
X
CE3
X
ZZ
Deselect Cycle, Power Down
Operation
L
X
L
X
WRITE OE CLK
X
X
L-H Tri-State
DQ
Deselect Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L-H Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L-H Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L-H Tri-State
L-H Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
X
X
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H Tri-State
WRITE Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H Tri-State
Next
X
X
X
L
H
H
L
H
L
L-H
READ Cycle, Continue Burst
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H Tri-State
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H Tri-State
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H Tri-State
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H Tri-State
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Q
Q
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only two chip selects CE1 and CE2.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05350 Rev. *E
Page 10 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Truth Table for Read/Write[4,8,9]
GW
BWE
BWD
BWC
BWB
BWA
Read
Function (CY7C1440AV25)
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – ( DQA and DQPA )
H
L
H
H
H
L
Write Byte B – ( DQB and DQPB )
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – ( DQC and DQPC )
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – ( DQD and DQPD )
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Truth Table for Read/Write[4,8,9]
Function (CY7C1442AV25)
Read
GW
H
BWE
H
BWB
X
BWA
X
Read
H
L
H
H
Write Byte A – ( DQA and DQPA )
H
L
H
L
Write Byte B – ( DQB and DQPB )
H
L
L
H
Write Bytes B, A
H
L
L
L
Write All Bytes
H
L
L
L
Truth Table for Read/Write[4,8,9]
Read
Function (CY7C1446AV25)
GW
H
BWE
H
BWx
X
Read
H
L
All BW = H
Write Byte x – (DQx and DQPx)
H
L
L
Write All Bytes
H
L
All BW = L
Notes:
8. BWx represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled
at the same time for any given write.
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05350 Rev. *E
Page 11 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Data-In (TDI)
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with IEEE Standard 1149.1.The TAP
operates using JEDEC-standard 2.5V/1.8V I/O logic level.
The
CY7C1440AV25/CY7C1442AV25/CY7C1446AV25
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
1
TEST-LOGIC
RESET
2 1 0
TDI
Selection
Circuitry
31 30 29 . . . 2 1 0
0
0
RUN-TEST/
IDLE
Instruction Register
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
CAPTURE-DR
x . . . . . 2 1 0
Boundary Scan Register
CAPTURE-IR
0
SHIFT-DR
0
SHIFT-IR
1
0
TCK
1
EXIT1-DR
1
EXIT1-IR
0
1
TMS
TAP CONTROLLER
0
PAUSE-DR
0
PAUSE-IR
1
0
Performing a TAP Reset
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
TDO
Identification Register
0
1
0
0
1
Selection
Circuitry
0
UPDATE-IR
1
0
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test MODE SELECT (TMS)
Instruction Register
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Test Access Port (TAP)
Test Clock (TCK)
Document #: 38-05350 Rev. *E
Page 12 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
IDCODE
EXTEST
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
EXTEST OUTPUT BUS TRI-STATE
BYPASS
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209-FBGA package).
Document #: 38-05350 Rev. *E
Page 13 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
Test Clock
(TCK)
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
20
ns
tTL
TCK Clock LOW time
20
ns
50
ns
20
MHz
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
ns
0
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
Notes:
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document #: 38-05350 Rev. *E
Page 14 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
2.5V TAP AC Test Conditions
1.8V TAP AC Test Conditions
Input pulse levels .............................................. VSS to 2.5V
Input pulse levels .....................................0.2V to VDDQ – 0.2
Input rise and fall time .................................................... 1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ........................................1.25V
Input timing reference levels .......................................... 0.9V
Output reference levels ................................................1.25V
Output reference levels ................................................. 0.9V
Test load termination supply voltage............................ 1.25V
Test load termination supply voltage ............................. 0.9V
2.5V TAP AC Output Load Equivalent
1.8V TAP AC Output Load Equivalent
0.9V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[12]
Parameter
Description
Test Conditions
VOH1
Output HIGH Voltage
IOH = –1.0 mA
VOH2
Output HIGH Voltage
IOH = –100 µA
Min.
Max.
Unit
VDDQ = 2.5V
2.0
V
VDDQ = 2.5V
2.1
V
VDDQ = 1.8V
1.6
V
VOL1
Output LOW Voltage
IOL = 1.0 mA
VDDQ = 2.5V
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
VDDQ = 2.5V
0.2
V
VIH
Input HIGH Voltage
VDDQ = 2.5V
VIL
Input LOW Voltage
VDDQ = 1.8V
IX
Input Load Current
VDDQ = 1.8V
GND < VIN < VDDQ
0.2
V
1.7
VDD + 0.3
V
VDDQ = 1.8V
1.26
VDD + 0.3
V
VDDQ = 2.5V
–0.3
0.7
V
–0.3
0.36
V
–5
5
µA
Note:
12. All voltages referenced to VSS (GND).
Document #: 38-05350 Rev. *E
Page 15 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Identification Register Definitions
CY7C1440AV25 CY7C1442AV25 CY7C1446AV25
(1M x36)
(2M x18)
(512K x72)
Instruction Field
Revision Number (31:29)
Description
000
000
000
01011
01011
01011
Architecture/Memory Type(23:18)
000000
000000
000000
Defines memory type and architecture
Bus Width/Density(17:12)
100111
010111
110111
Defines width and density
00000110100
00000110100
00000110100
1
1
1
Device Depth (28:24)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Describes the version number.
Reserved for Internal Use
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary Scan Order (165-ball FBGA package)
89
89
–
Boundary Scan Order (209-ball FBGA package)
–
–
138
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05350 Rev. *E
Page 16 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
165-ball FBGA Boundary Scan Order [13,14]
CY7C1440AV25 (1M x 36), CY7C1442AV25 (2M x 18)
Bit #
Ball ID
Bit #
Ball ID
1
26
E11
N6
2
27
D11
N7
3
N10
28
G10
4
P11
29
F10
5
P8
30
E10
6
R8
31
D10
7
R9
32
C11
8
P9
33
A11
9
P10
34
B11
10
R10
35
A10
11
R11
36
B10
12
H11
37
A9
13
N11
38
B9
14
M11
39
C10
15
L11
40
A8
16
K11
41
B8
17
J11
42
A7
18
M10
43
B7
19
L10
44
B6
20
K10
45
A6
21
J10
46
B5
22
H9
47
A5
23
H10
48
A4
24
G11
49
B4
25
F11
50
B3
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
K2
L2
M2
Bit #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
Notes:
13. Balls which are NC (No Connect) are Pre-Set LOW.
14. Bit# 89 is Pre-Set HIGH.
Document #: 38-05350 Rev. *E
Page 17 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
209-ball FBGA Boundary Scan Order [13,15]
CY7C1446AV25 (512K x 72)
Bit #
Ball ID
1
W6
2
V6
3
U6
4
W7
5
V7
6
U7
7
T7
8
V8
9
U8
10
T8
11
V9
12
U9
13
P6
14
W11
15
W10
16
V11
17
V10
18
U11
19
U10
20
T11
21
T10
22
R11
23
R10
24
P11
25
P10
26
N11
27
N10
28
M11
29
M10
30
L11
31
L10
32
K11
33
M6
34
L6
35
J6
Bit #
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Ball ID
F6
K8
K9
K10
J11
J10
H11
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
B11
B10
A11
A10
C9
B9
A9
D7
C8
B8
A8
D8
C7
B7
A7
D6
G6
Bit #
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Ball ID
H6
C6
B6
A6
A5
B5
C5
D5
D4
C4
A4
B4
C3
B3
A3
A2
A1
B2
B1
C2
C1
D2
D1
E1
E2
F2
F1
G1
G2
H2
H1
J2
J1
K1
N6
Bit #
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Ball ID
K3
K4
K6
K2
L2
L1
M2
M1
N2
N1
P2
P1
R2
R1
T2
T1
U2
U1
V2
V1
W2
W1
T6
U3
V3
T4
T5
U4
V4
5W
5V
5U
Internal
Note:
15. Bit# 138 is Pre-Set HIGH.
Document #: 38-05350 Rev. *E
Page 18 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.3V to +3.6V
Supply Voltage on VDDQ Relative to GND ...... –0.3V to +VDD
Range
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Commercial
Industrial
Ambient
Temperature
VDD
VDDQ
0°C to +70°C
2.5V + 5%
1.7V to VDD
–40°C to +85°C
Electrical Characteristics Over the Operating Range [16, 17]
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
for 2.5V I/O, IOL = 1.0 mA
VIH
Input HIGH Voltage[16]
VIL
Input LOW Voltage[16]
IX
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
Min.
Unit
2.375
2.625
V
2.375
2.625
V
for 1.8V I/O
1.7
1.9
for 2.5V I/O, IOH = –1.0 mA
2.0
for 1.8V I/O, IOH = –100 µA
1.6
for 2.5V I/O
for 1.8V I/O, IOL= 100 µA
V
V
V
0.4
V
0.2
V
1.7
VDD + 0.3V
V
for 1.8V I/O
1.26
VDD + 0.3V
V
for 2.5V I/O
–0.3
0.7
V
for 1.8V I/O
–0.3
0.36
V
–5
5
µA
for 2.5V I/O
µA
–30
Input Current of MODE Input = VSS
Input = VDD
Input Current of ZZ
Max.
5
Input = VSS
µA
µA
–5
30
µA
5
µA
4-ns cycle, 250 MHz
435
mA
5-ns cycle, 200 MHz
385
mA
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
6-ns cycle, 167 MHz
335
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
All speeds
185
mA
ISB2
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
All speeds
120
mA
ISB3
VDD = Max, Device Deselected, or All speeds
Automatic CE
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX = 1/tCYC
VDD = Max, Device Deselected,
Automatic CE
All speeds
Power-down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
160
mA
135
mA
ISB4
–5
Notes:
16. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
17. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05350 Rev. *E
Page 19 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Capacitance[18]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
VDD/VDDQ = 2.5V
100 TQFP
Max.
165 FBGA
Max.
209 FBGA
Max
Unit
6.5
7
5
pF
3
7
5
pF
5.5
6
7
pF
100 TQFP
Package
165 FBGA
Package
209 FBGA
Package
Unit
25.21
20.8
25.31
°C/W
2.28
3.2
4.48
°C/W
Thermal Resistance[18]
Parameter
ΘJA
ΘJC
Description
Test Conditions
Thermal Resistance
(Junction to Ambient)
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
Thermal Resistance
(Junction to Case)
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
Z0 = 50Ω
10%
(a)
INCLUDING
JIG AND
SCOPE
1.8V I/O Test Load
R = 1538Ω
(b)
(c)
0.2
5 pF
R = 14 KΩ
VT = 0.9V
(a)
ALL INPUT PULSES
VDDQ - 0.2
OUTPUT
RL = 50Ω
Z0 = 50Ω
≤ 1 ns
≤ 1 ns
R = 14 KΩ
1.8V
OUTPUT
90%
10%
90%
GND
5 pF
VT = 1.25V
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
(c)
Note:
18. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05350 Rev. *E
Page 20 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Switching Characteristics Over the Operating Range[23, 24]
–250
Parameter
tPOWER
Description
Min.
[19]
VDD(Typical) to the first Access
Max.
–200
Min.
Max.
–167
Min.
Max.
Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
5.0
6.0
ns
tCH
Clock HIGH
1.5
2.0
2.4
ns
tCL
Clock LOW
1.5
2.0
2.4
ns
Output Times
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
[20, 21, 22]
2.6
1.0
3.2
1.5
1.5
ns
Clock to Low-Z
tCHZ
Clock to High-Z[20, 21, 22]
2.6
3.0
3.4
ns
tOEV
OE LOW to Output Valid
2.6
3.0
3.4
ns
tOELZ
tOEHZ
OE LOW to Output
OE HIGH to Output
High-Z[20, 21, 22]
1.3
ns
tCLZ
Low-Z[20, 21, 22]
1.0
3.4
0
1.5
0
2.6
ns
0
3.0
ns
3.4
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.2
1.4
1.5
ns
tADS
ADSC, ADSP Set-up Before CLK Rise
1.2
1.4
1.5
ns
tADVS
ADV Set-up Before CLK Rise
1.2
1.4
1.5
ns
tWES
GW, BWE, BWX Set-up Before CLK Rise
1.2
1.4
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.2
1.4
1.5
ns
tCES
Chip Enable Set-Up Before CLK Rise
1.2
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.3
0.4
0.5
ns
tADVH
ADV Hold After CLK Rise
0.3
0.4
0.5
ns
Hold Times
tWEH
GW, BWE, BWX Hold After CLK Rise
0.3
0.4
0.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.3
0.4
0.5
ns
Notes:
19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD( minimum) initially before a read or write operation
can be initiated.
20. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
23. Timing reference level is 1.25V when VDDQ = 2.5V and 0.9V when VDDQ = 1.8V .
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05350 Rev. *E
Page 21 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Switching Waveforms
Read Cycle Timing[25]
t CYC
CLK
t
CH
t
ADS
t
CL
t
ADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
tCES
Deselect
cycle
tCEH
CE
tADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
Q(A1)
High-Z
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05350 Rev. *E
Page 22 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Switching Waveforms (continued)
Write Cycle Timing[25, 26]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
26. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document #: 38-05350 Rev. *E
Page 23 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Switching Waveforms (continued)
Read/Write Cycle Timing[25, 27, 28]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BWX
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes:
27. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
28. GW is HIGH.
Document #: 38-05350 Rev. *E
Page 24 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Switching Waveforms (continued)
ZZ Mode Timing[29, 30]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
29. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
30. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05350 Rev. *E
Page 25 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
167
Ordering Code
CY7C1440AV25-167AXC
Package
Diagram
Operating
Range
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1442AV25-167AXC
CY7C1440AV25-167BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1442AV25-167BZC
CY7C1440AV25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-167BZXC
CY7C1446AV25-167BGC
CY7C1446AV25-167BGXC
CY7C1440AV25-167AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
CY7C1442AV25-167AXI
CY7C1440AV25-167BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1442AV25-167BZI
CY7C1440AV25-167BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-167BZXI
CY7C1446AV25-167BGI
CY7C1446AV25-167BGXI
200
CY7C1440AV25-200AXC
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1442AV25-200AXC
CY7C1440AV25-200BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1442AV25-200BZC
CY7C1440AV25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-200BZXC
CY7C1446AV25-200BGC
CY7C1446AV25-200BGXC
CY7C1440AV25-200AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
CY7C1442AV25-200AXI
CY7C1440AV25-200BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1442AV25-200BZI
CY7C1440AV25-200BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-200BZXI
CY7C1446AV25-200BGI
CY7C1446AV25-200BGXI
Document #: 38-05350 Rev. *E
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
Page 26 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
250
Ordering Code
CY7C1440AV25-250AXC
Package
Diagram
Operating
Range
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1442AV25-250AXC
CY7C1440AV25-250BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1442AV25-250BZC
CY7C1440AV25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-250BZXC
CY7C1446AV25-250BGC
CY7C1446AV25-250BGXC
CY7C1440AV25-250AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
CY7C1442AV25-250AXI
CY7C1440AV25-250BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1442AV25-250BZI
CY7C1440AV25-250BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-250BZXI
CY7C1446AV25-250BGI
CY7C1446AV25-250BGXI
Document #: 38-05350 Rev. *E
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
Page 27 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Package Diagrams
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
Document #: 38-05350 Rev. *E
A
Page 28 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Package Diagrams (continued)
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45±0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
F
F
G
G
H
J
14.00
E
17.00±0.10
E
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
1.00
5.00
0.35
0.15 C
+0.05
-0.10
0.53±0.05
0.25 C
10.00
1.40 MAX.
0.36
15.00±0.10
51-85165-*A
SEATING PLANE
C
Document #: 38-05350 Rev. *E
B
0.15(4X)
Page 29 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Package Diagrams (continued)
209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)
51-85167-**
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05350 Rev. *E
Page 30 of 32
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Document History Page
Document Title:CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined Sync SRAM
Document Number: 38-05350
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
124417
03/04/03
CJM
New Data Sheet
*A
254909
See ECN
SYT
Part number changed from previous revision. New and old part number differ by
the letter “A”
Modified Functional Block diagrams
Modified switching waveforms
Added Boundary scan information
Added IDD, IX and ISB values in the DC Electrical Characteristics
Added tPOWER specifications in Switching Characteristics table
Removed 119 PBGA Package
Changed 165 FBGA Package from BB165C (15 x 17 x 1.20 mm) to BB165
(15 x 17 x 1.40 mm)
Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A
(14 x 22 x 1.76 mm)
*B
303533
See ECN
SYT
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA on
Page # 6
Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical
Characteristics table
Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All Packages
on the Thermal Resistance Table
Changed IDD from 450, 400 & 350 mA to 435,385 & 335 mA for 250, 200 and 167
Mhz respectively
Changed ISB1 from 190, 180 and 170 mA to 185 mA for 250, 200 and 167 Mhz
respectively
Changed ISB2 from 80 mA to 100 mA for all frequencies
Changed ISB3 from 180, 170 & 160 mA to 160 mA for 250, 200 and 167 Mhz
respectively
Changed ISB4 from 100 mA to 110 mA for all frequencies
Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP
Package
Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 Mhz speed bin
Added lead-free information for 100-pin TQFP, 165 FBGA and 209 FBGA
Packages
*C
331778
See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA and 209 FBGA
Package as per JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA
Package
Added Industrial Temperature Grade
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively
Updated the Ordering Information by Shading and Unshading MPNs as per availability
*D
417509
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed IX current value in MODE from –5 & 30 µA to –30 & 5 µA respectively
and also Changed IX current value in ZZ from –30 & 5 µA to –5 & 30 µA respectively
on page# 20
Modified test condition from VIH < VDD to VIH < VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information Table
Document #: 38-05350 Rev. *E
Page 31 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Document Title:CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined Sync SRAM
Document Number: 38-05350
REV.
ECN NO.
Issue
Date
Orig. of
Change
*E
473229
See ECN
VKN
Document #: 38-05350 Rev. *E
Description of Change
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table
Updated the Ordering Information table.
Page 32 of 32
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