INTEGRATED CIRCUITS ABT22V10A5, A7 5V high-speed universal PLD device with live insertion capability Product specification IC13 Data Handbook 1996 Dec 16 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 DESCRIPTION PIN CONFIGURATIONS The ABT22V10A is a versatile PAL device fabricated on Philips BiCMOS process known as QUBiC. A Package The QUBiC process produces very high speed, 5 volt devices (5.0ns) which have excellent noise immunity. The ground bounce of an output held low while the 9 remaining outputs are switching is less than 1.0V (typical). The ABT22V10A outputs are designed to support Live Insertion/Extraction into powered-up systems. The output is specially designed so that during VCC ramp, the output remains 3-Stated until VCC ≈ 2.1V. At that time, the outputs become fully functional, depending upon device inputs. (See DC Electrical Characteristics, Symbol IPU/PD, Page 4). I1 4 3 CLK/ I0 VCC VCC F9 F8 2 1 28 27 26 I3 5 25 F7 I4 6 24 F6 I5 7 23 F5 GND The ABT family of devices have virtually no ground bounce— less than 1.0 volts VOLP, measured on an unswitched output (9 remaining outputs switching, each with a 50pF load tied to ground). I2 22 GND 8 I6 9 21 F4 I7 10 20 F3 I8 11 The ABT family of devices has been designed with high drive outputs (48mA sink and 16mA source currents), which allow for direct connection to a backplane bus. This feature eliminates the need for additional, standalone bus drivers, which are traditionally required to boost the drive of a standard 16/–4mA PLDs. 19 F2 12 13 14 15 16 17 18 I9 I10 GND GND I11 F0 F1 A = Plastic Leaded Chip Carrier SP00367 PIN LABEL DESCRIPTIONS Philips has developed a new means of testing the integrity of fuses, both blown and intact fuses, which insures that all the fuses have been correctly programmed and that each and every fuse—whether “blown” or “intact”—is at the appropriate and optimal fuse resistance. This dual verify scheme represents a significant improvement over single reference voltage comparison schemes that have been used for bipolar devices since the late 1980’s. SYMBOL The ABT22V10A uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. FUNCTION I1 – I11 Dedicated Input F0 – F9 Macro Cell Input/Output CLK/I0 Clock Input/Dedicated Input VCC Supply Voltage GND Ground This device has a programmable AND array, which drives a fixed OR array. The OR sum-of-products feeds an “Output Macro Cell” (OMC) that can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. FEATURES • Fastest 5V 22V10 • Low ground bounce (<1.0V typical) • Live insertion/extraction permitted • High output drive capability: 48mA/–16mA • Varied product term distribution with up to 16 product terms per output for complex functions • Metastable hardened flip-flops • Programmable output polarity • Design support provided for third party CAD development and programming hardware • Improved fuse verification circuitry increases reliability ORDERING INFORMATION DESCRIPTION 28-Pin Plastic Leaded Chip Carrier ORDER CODE ABT22V10A5A (5ns device) ABT22V10A7A (7.5ns device) DRAWING NUMBER SOT261-3 PAL is a registered trademark of Advanced Micro Devices, Inc. 1996 Dec 16 2 853–1795 17606 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 ABSOLUTE MAXIMUM RATINGS1 RATINGS SYMBOL PARAMETER UNIT Supply voltage2 VCC voltage2 MIN MAX –0.5 +7.0 VDC –1.2 VCC + 0.5 VDC VIN Input VOUT Output voltage –0.5 VCC + 0.5 VDC IIN Input currents –30 +30 mA IOUT Output currents +100 mA Tstg Storage temperature range +150 °C –65 NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. Except in programming mode. OPERATING RANGES RATINGS SYMBOL PARAMETER VCC Supply voltage Tamb Operating free-air temperature UNIT MIN MAX +4.75 +5.25 VDC 0 +75 °C THERMAL RATINGS TEMPERATURE Maximum junction 150°C Maximum ambient 75°C Allowable thermal rise ambient to junction 75°C VOLTAGE WAVEFORM TEST LOAD CIRCUIT VCC +5V S1 +3.0V 90% C1 C2 R1 F0 I0 10% 0V R2 tR DUT tF 1.5ns INPUTS 1.5ns Fn In CK MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses 1996 Dec 16 CL NOTE: C1 and C2 are to bypass VCC to GND. SP00368 3 OE GND SP00369 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 DC ELECTRICAL CHARACTERISTICS Over operating ranges. SYMBOL LIMITS TEST CONDITIONS1 PARAMETER UNIT MIN MAX Input voltage VIL Low VCC = MIN VIH High VCC = MAX VI Clamp 0.8 2.0 VCC = MIN, IIN = –18mA V V –1.2 V Output voltage VOH High-level output voltage VOL Low-level output voltage VCC = MIN VI = VIH or VIL VCC = MIN VI = VIH or VIL IOH = –32mA 2.0 V IOH = –16mA 2.4 V IOL = 48mA 0.5 V Input current IIL Low VCC = MAX, VIN = 0.4V –10 µA IIH High VCC = MAX, VIN = 2.7V 10 µA II Max input current VCC = MAX, VIN = 5.5V 20 µA VCC <2.1V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = X 50 µA Output current IPU/PD Power-up/down 3-State output current4 VCC = MAX IOZH IOZL Output leakage2 VIN = VIL or VIH, VOUT = 2.7V 20 µA Output leakage2 VIN = VIL or VIH, VOUT =0.4V –20 µA –220 mA 200 mA TYP MAX UNIT 1.0 1.2 V ISC Short circuit3 VOUT = 0.5V ICC VCC supply current VCC = MAX, Outputs enabled, VI = VCC or GND; IO = 0 Ground Bounce VOLP Minimum dynamic VOH 5 VCC = MAX, 25°C CL = 50pF (including jig capacitance) –30 NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IOZX or IIX (where X = H or L). 3. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is valid for any VCC between 0V and 1.2 V with a transition time up to 10 mS. From VCC = 1.2 to VCC = 5.0V ±0.25V a transition time of 100 µS is permitted. X = Don’t care. 5. Guaranteed by design, but not tested. Measured holding one output (the output under test) Low and simultaneously switching all remianing output from a High to a Low state. Switch S1 is closed; 50pF load. 1996 Dec 16 4 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 AC ELECTRICAL CHARACTERISTICS1 4.75V ≤ VCC ≤ 5.25V; 0C ≤ Tamb ≤ +75C LIMITS SYMBOL PARAMETER TEST CONDITIONS ABT22V10A5 ABT22V10A7 UNIT MIN TYP MAX MIN TYP MAX Active-LOW 2.0 4.5 5.0 2.0 6.0 7.5 ns Active-HIGH 2.0 4.5 5.0 2.0 6.0 7.5 ns tPD Input or feedback to non-registered output2 tS Setup time from input or SP to Clock 2.0 1.3 3.5 3.0 ns tSIO Setup time from feedback to Clock 2.25 1.5 3.5 3.0 ns tH Hold time tSKEWR Skew between registered outputs 4, 7 tCO Clock to output 0 0 ns 1.0 2.0 feedback3 3.5 4.0 2.0 4.0 2.0 1.0 ns 4.5 5.5 ns 3.0 5.0 ns 10.0 ns tCF Clock to tAR Asynchronous Reset to registered output tARW Asynchronous Reset width 6.0 7.5 ns tARR Asynchronous Reset recovery time 4.0 5.5 ns tSPR Synchronous Preset recovery time 4.5 5.0 ns tWL Width of Clock LOW 2.0 3.0 ns tWH Width of Clock HIGH 2.0 3.0 ns Maximum frequency; External feedback 1/(tS + tCO)4 167 208 111 133 MHz Maximum frequency; Internal feedback 1/(tS + tCF)4 167 303 125 166 MHz fMAX 10.0 tEA Input to Output Enable5 8.0 8.0 ns tER Disable5 7.5 7.5 ns Input to Output Capacitance6 CIN COUT Input Capacitance (Pin 2) VIN = 2.0V Input Capacitance (Others) VIN = 2.0V Output Capacitance VOUT = 2.0V VCC = 5.0V Tamb = 25°C f = 1MHz 8 8 pF 4 4 pF 8 8 pF NOTES: 1. Test Conditions: R1 = 300Ω, R2 =390Ω 2. tPD is tested with switch S1 closed and CL = 50pF (including jig capacitance). VIH = 3V, VIL = 0V, VT = 1.5V. 3. Calculated from measured fMAX internal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 7. Skew is measured with all outputs switching in the same direction. 1996 Dec 16 5 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 PRODUCT FEATURES Power-Up Reset All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the ABT22V10A will depend on the programmed output polarity. The VCC rise must be monotonic and the reset delay time is 1–10µs maximum. Low Ground Bounce The Philips Semiconductors BiCMOS QUBiC process produces exceptional noise immunity. The typical ground bounce, with 9 outputs simultaneously switching and the 10th output held low, is less than 1.0V. VOLP is tested by holding one output (the output uncer test) in the Low state and then simultaneously switching all remaining outputs from a High to a Low state (each output is loaded with 50pF). The maximum peak voltage on the output under test is guaranteed to be less than 1.2 Volts. Security Fuse After programming and verification, ABT22V10A designs can be secured by programming the security fuse link. Once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is programmed. Live Insertion/Extraction Capability There are some inherent problems associated with inserting or extracting an unpowered module from a powered-up, active system. The ABT22V10A outputs have been designed such that any chance of bus contention, glitching or clamping is eliminated. Quality and Testability The ABT22V10A offers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In addition, this verifies programmability and functionality of the device to provide the highest programming and post-programming functional yields. Detailed information on this feature is provided in an application note AN051: Philips PLDs Support Live Insertion Applications. Improved Fuse Verification Circuitry Increases Reliability Technology The BiCMOS ABT22V10A is fabricated with the Philips Semiconductors process known as QUBiC. QUBiC combines an advanced, state-of-the-art 1.0µm (drawn feature size) CMOS process with an ultra fast bipolar process to achieve superior speed and drive capabilities. QUBiC incorporates three layers of Al/Cu interconnects for reduced chip size, and our proven Ti-W fuse technology ensures highest programming yields. Philips has developed a new means of testing the integrity of fuses, both blown and intact fuses, which insures that all the fuses have been correctly programmed and that each and every fuse – whether “blown” or “intact” – is at the appropriate and optimal fuse resistance. This dual verify scheme represents a significant improvement over single reference voltage comparisons schemes that have been used for bipolar devices since the late 1980s. Detailed information on this feature is provided in an application note entitled Dual Verify Technique Increases Reliability of PLDs. Programming The ABT22V10A is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL CUPL and PALASM 90 design software packages also support the ABT22V10A architecture. Programmable 3-stage Outputs Each output has a 3-Stage output buffer with 3-State control. A product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional I/O pin, and may be configured as a dedicated input if the buffer is always disabled. All packages allow Boolean and state equation entry formats, SNAP, ABEL and CUPL also accept, as input, schematic capture format. Programmable Output Polarity Output Register Preload The polarity of each macro cell output can be Active-HIGH or Active-LOW, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. The register on the ABT22V10A can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. The procedure for preloading follows: 1. Raise VCC to 5.0V ± 0.25V. Selection is controlled by programmable bit S0 in the Output Macro Cell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be Active-HIGH (S0 = 1). 2. Set pin 2 or 3 to VHH to disable outputs and enable preload. 3. Apply the desired value (VILP/VIHP) to all registered output pins. Leave combinatorial output pins floating. 4. Clock Pin 1 from VILP to VIHP. 5. Remove VILP/VIHP from all registered output pins. 6. Lower pin 2 or 3 to VILP. 7. Enable the output registers according to the programmed pattern. 8. Verify VOL/VOH at all registered output pins. Note that the output pin signal will depend on the output polarity. Preset/Reset For initialization, the ABT22V10A has additional Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the Asynchronous Reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW, independent of the clock. Note that Preset and Reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMD Corp. 1996 Dec 16 6 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 In this formula, FC is the frequency of the clock, F1 is the average input event frequency, and t is the time after the clock pulse that the output is sampled (t > TCO). T0 and τ are device parameters provided by the semiconductor manufacturer (refer to Table 1 for the ABT22V10A5 metastability specifications). T0 and τ are derived from tests and can be most nearly be defined as follows: τ is a function of the rate at which a latch in a metastable state resolves that condition. T0 is a function of the measurement of the propensity of a latch to enter a metastable state. T0 is also a normalization constant which is a very strong function of the normal propagation dely of the device. Metastable Characteristics Philips provides complete data on the ABT22V10A5’s metastable characteristics. While the ABT22V10A5 does not employ Philips patented metastable immune flip-flop, its metastabel characteristics are still quite favorable relative to competitive devices. For information on metastable immune PLDs, refer to the datasheets for the ABT22V10-7 for 5V applications or the LVT22V10-7 for 3.3V designs. Design Example Suppose a designer wants to use the ABT22V10A5 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), in a 5V system that has a clock frequency of 50MHz, at an ambient temperature of 25°C. The next device in the sytem samples the output fo the ABT22V10A5 5.5ns after the clock edge to ensure that any metastable conditions that occur have time to resolve to the correct state. The MTBF for this situatio can be calcuclated by using the equation below: In this situation, the F1 will be twice that data frequency, or 20MHz, because input events consist of both low and high transitions. Thus in this case FC is 50MHz, F1 is 20MHz, τ is 85.6ps, t is 5.5ns, and T0 is 4.55 seconds. Using the above formula, the actual MTBF for this situation is 1.76 × 1012 seconds, or 55,889 years for the ABT22V10A5. MTBF = e(t/τ)/T0FCF1 Table 1. Typical Values for τ and T0 at various VCC’s and Temperatures 0°C +25°C VCC τ T0 τ 5.25V 72.00ps 7.20E+01 5.00V 72.80ps 2.06E+02 4.75V 68.70ps 9.97E+03 1996 Dec 16 +75°C T0 τ T0 96.70ps 4.59E–01 105.00ps 1.43E–01 85.60ps 4.55E+00 100.00ps 8.37E–01 81.70ps 4.85E+01 99.80ps 1.29E+00 7 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 LOGIC DIAGRAM CLK/I0 1, 28 2 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 VCC 43 AR 0 1 DAR 9 SP Q Q 1 1 0 0 0 1 0 1 27 F9 1 1 0 0 0 1 0 1 26 F8 1 1 0 0 0 1 0 1 25 F7 1 1 0 0 0 1 0 1 24 F6 1 1 0 0 0 1 0 1 23 F5 1 1 0 0 0 1 0 1 21 F4 1 1 0 0 0 1 0 1 20 F3 1 1 0 0 0 1 0 1 19 F2 1 1 0 0 0 1 0 1 18 F1 1 1 0 0 0 1 0 1 17 F0 16 I11 0 1 10 DAR 20 I1 SP Q Q 0 1 3 21 DAR SP 33 I2 Q Q 0 1 4 34 DAR SP Q Q 48 I3 0 1 5 49 DAR SP Q Q 65 I4 0 1 6 66 DAR SP Q Q 82 I5 0 1 7 83 DAR SP Q Q 97 I6 0 1 9 98 DAR SP 110 Q Q 0 1 I7 10 111 DAR 121 I8 SP Q Q 0 1 11 122 DAR 130 SP I9 12 SP 131 I10 13 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 Q Q 0 1 43 GND 14, 15, 8, 22 NOTE: Programmable connection. 1996 Dec 16 SP00390 8 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 FUNCTIONAL DIAGRAM CLK/I0 I1 – I11 1 11 PROGRAMMABLE AND ARRAY (44 × 132) 8 RESET OUTPUT MACRO CELL 10 OUTPUT MACRO CELL 12 OUTPUT MACRO CELL 14 16 OUTPUT MACRO CELL 16 OUTPUT MACRO CELL OUTPUT MACRO CELL 14 OUTPUT MACRO CELL 12 OUTPUT MACRO CELL 10 OUTPUT MACRO CELL 8 OUTPUT MACRO CELL PRESET F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 SP00060 Figure 1. Functional Diagram registered output or combinatorial I/O, Active-HIGH or Active-LOW (see Figure 2). The configuration choice is made according to the user’s design specification and corresponding programming of the configuration bits S0 –S1. Multiplexer controls are connected to ground (0) through a programmable fuse link, selecting the “0” path through the multiplexer. Programming the fuse disconnects the control line from GND and it floats to VCC (1), selecting the “1” path. FUNCTIONAL DESCRIPTION The ABT22V10A allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Product terms with all fuses opened assume the logical HIGH state; product terms connected to both True and Complement of any single input assume the logical LOW state. The ABT22V10A has 12 inputs and 10 I/O Macro Cells (Figure 1). The Macro Cell allows one of four potential output configurations, 1996 Dec 16 9 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 OUTPUT MACRO CELL 1 0 1 1 Q 0 0 Q 0 1 AR D CLK SP F S1 S0 OUTPUT CONFIGURATION 0 0 Registered/Active-LOW 0 1 Registered/Active-HIGH 1 0 Combinatorial/Active-LOW 1 1 Combinatorial/Active-HIGH 0 = Unprogrammed fuse 1 = Programmed fuse S1 S0 0 1 SP00375 Figure 2. Output Macro Cell Logic Diagram S0 = 0 S1 = 0 AR D Q CLK S0 = 0 S1 = 1 F F Q SP a. Registered/Active-LOW S0 = 1 S1 = 0 AR D Q CLK c. Combinatorial/Active-LOW S0 = 1 S1 = 1 F F Q SP b. Registered/Active-HIGH d. Combinatorial/Active-HIGH SP00376 Figure 3. Output Macro Cell Configurations Registered Output Configuration Variable Input/Output Pin Ratio Each Macro Cell of the ABT22V10A includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration (S1 = 0), the array feedback is from Q of the flip-flop. The ABT22V10A has twelve dedicated input lines, and each Macro Cell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Combinatorial I/O Configuration Any Macro Cell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin. 1996 Dec 16 10 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 SWITCHING WAVEFORMS VT = 1.5V. Input pulse amplitude 0V to 3.0V. Input rise and fall times 1.5ns max. INPUT OR FEEDBACK INPUT OR FEEDBACK VT VT tPD COMBINATORIAL OUTPUT tS tH CLOCK VT VT tCO REGISTERED OUTPUT Combinatorial Output VT Registered Output CLK tS + tCF CLOCK tS LOGIC VT REGISTER tCF Clock to Feedback (fMAX Internal) (See Path at Right) Clock to Feedback INPUT VT tWH tER CLOCK VT tEA VOH – 0.5V OUTPUT VT VOL + 0.5V tWL Clock Width Input to Output Disable/Enable tARW INPUT ASSERTING ASYNCHRONOUS RESET INPUT ASSERTING SYNCHRONOUS PRESET VT tAR REGISTERED OUTPUT VT tS CLOCK VT tARR CLOCK tH tSPR VT VT tCO REGISTERED OUTPUT VT Asynchronous Reset VT Synchronous Preset SP00377 1996 Dec 16 11 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 “AND” ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B P, D I, B P, D I, B P, D P, D STATE CODE STATE CODE STATE CODE INACTIVE1 O TRUE H COMPLEMENT L STATE DON’T CARE CODE — SP00008 NOTE: 1. This is the initial state. PRELOAD SET-UP LIMITS SYMBOL PARAMETER UNIT MIN REC MAX 9.5 9.5 10 V VHH Super-level input voltage VILH Low-level input voltage 0 0 0.8 V VIHP High-level input voltage 2.4 5.0 5.5 V tD Delay time 100 200 1000 ns tI/O I/O valid after Pin 2 or 3 drops from VHH to VILP 100 ns VHH PINS 2, 3 VILP tD tD REGISTERED OUTPUTS DATA IN tI/O DATA OUT tD tD VIHP VOH VOL VILP VIHP CLOCK tD Output Register Preload Waveform 1996 Dec 16 12 VILP SP00373 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. LIMITS SYMBOL PARAMETER UNIT MIN tPR Power-up Reset Time tS Input or Feedback Setup Time tWL Clock Width LOW MAX µs 1 See AC Electrical Characteristics VCC 4V POWER tPR REGISTERED ACTIVE-LOW OUTPUT tS CLOCK tWL Power-Up Reset Waveform SP00066 OTHER PHILIPS 22V10 DEVICES Philips offers a complete family of 22V10 devices, addressing a wide variety of design applications. This Features Matrix summarizes the basic features of each specific device. PHILIPS 22V10 FEATURES MATRIX PL22V10-10/-15 Operating supply voltage +4.75 to +5.25V LVT22V10-7 +3.0 to +3.6V 1 ABT22V10-7 ABT22V10A5 ABT22V10A7 +4.75 to +5.25V +4.75 to +5.25V +4.75 to +5.25V Live Insertion No Yes No Yes Yes Dual Verify No Yes No Yes Yes Metastability No Hardened Immune No No Source Drive Capability 4mA (VOH = 2.4V) 16mA (VOH = 2.0V) 16mA (VOH = 2.4V) 16mA (VOH = 2.4V) 16mA (VOH = 2.4V) Sink Drive Capability 16mA (VOL = 0.5V) 32mA (VOL = 0.5V) 48mA (VOL = 0.5V) 48mA (VOL = 0.5V) 48mA (VOL = 0.5V) Low Ground Bounce No Yes Yes Yes Yes Plastic Dual In-Line (N) 24-Pin 24-Pin 24-Pin not available not available Plastic Leaded Chip Carrier (A) 24-Pin 28-Pin 28-Pin 28-Pin 28-Pin Plastic Small Outline Large (D) 24-Pin 24-Pin not available not available not available Package Availability: NOTE: 1. 5 volt compatible I/O. Inputs are capable of handling 7V and the outputs can also be pulled up to 7 volts. 1996 Dec 16 13 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 ABT22V10A5 TIMING CHARACTERIZATION Normalized tCO vs Temperature (VCC = 5.0V, output capacitance = 50pF, 5 outputs switching) Normalized tPD vs Temperature (VCC = 5.0V, output capacitance = 50pF, 5 outputs switching) 1.10 1.00 1.00 Normalized t PD Normalized t CO 1.10 0.90 0.90 RISE RISE FALL FALL 0.80 0.80 0 25 50 0 75 25 Temperature (°C) 75 Temperature (°C) Normalized tCO vs VCC (temp = 25°C, output capacitance = 50pF, 5 outputs switching) Normalized tPD vs VCC (temp = 25°C, output capacitance = 50pF, 5 outputs switching) 1.10 1.10 1.05 1.05 Normalized t PD Normalized t CO 50 1.00 0.95 1.00 0.95 RISE RISE FALL FALL 0.90 4.5 0.90 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 4.5 5.5 Supply Voltage (V) 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 Supply Voltage (V) The timing characterization represents the average values of a representative sample for each parameter. The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design. Philips guarantees the MAX AC CHARACTERIZATION specifications. SP00370 1996 Dec 16 14 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 ABT22V10A5 TIMING CHARACTERIZATION Delta tPD vs Number of Outputs Switching (VCC = 5.0V, temp = 25°C, output capacitance = 50pF) 0.20 0.0 0.0 –0.20 –0.20 –0.40 –0.40 (ns) 0.20 –0.60 –0.60 Delta t PD Delta t CO (ns) Delta tCO vs Number of Outputs Switching (VCC = 5.0V, temp = 25°C, output capacitance = 50pF) –0.80 –1.00 –0.80 –1.00 –1.20 –1.20 –1.40 –1.40 RISE –1.60 RISE –1.60 FALL FALL –1.80 –1.80 1 2 3 4 5 6 7 8 9 10 1 2 3 Number of Outputs Switching Delta tCO vs Output Capacitance (VCC = 5.0V, temp = 25°C, 5 Outputs Switching) 5 6 7 8 9 10 Delta tPD vs Output Capacitance (VCC = 5.0V, temp = 25°C, 5 Outputs Switching) 4.50 3.50 3.50 2.50 (ns) 4.50 2.50 1.50 Delta t PD Delta t CO (ns) 4 Number of Outputs Switching 1.50 0.50 0.50 –0.50 –0.50 RISE RISE FALL FALL –1.50 –1.50 10 50 100 200 400 10 Output Capacitance 50 100 200 Output Capacitance The timing characterization represents the average values of a representative sample for each parameter. The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design. Philips guarantees the MAX AC CHARACTERIZATION specifications. 1996 Dec 16 400 15 SP00371 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 PLCC28: plastic leaded chip carrer; 28 leads; pedestal 1996 Dec 16 16 SOT261-3 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 NOTES 1996 Dec 16 17 Philips Semiconductors Product specification 5V high-speed universal PLD device with live insertion capability ABT22V10A5, A7 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1996 Dec 16 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. 18