ON NB2309AI1HDTG 3.3 v zero delay clock buffer Datasheet

NB2309A
3.3 V Zero Delay
Clock Buffer
The NB2309A is a versatile, 3.3 V zero delay buffer designed to
distribute high−speed clocks. It accepts one reference input and drives
out nine low−skew clocks. It is available in a 16 pin package.
The −1H version of the NB2309A operates at up to 133 MHz, and
has higher drive than the −1 devices. All parts have on−chip PLL’s that
lock to an input clock on the REF pin. The PLL feedback is on−chip
and is obtained from the CLKOUT pad.
The NB2309A has two banks of four outputs each, which can be
controlled by the Select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
three−stated. The select inputs also allow the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2309A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle−to−cycle jitter. The input
and output propagation delay is guaranteed to be less than 350 ps, and
the output to output skew is guaranteed to be less than 250 ps.
The NB2309A is available in two different configurations, as shown
in the ordering information table. The NB2309A1 is the base part. The
NB2309Ax1H* is the high drive version of the −1 and its rise and fall
times are much faster than −1 part.
Features
• 15 MHz to 133 MHz Operating Range, Compatible with CPU and
•
•
•
•
•
•
•
•
•
•
PCI Bus Frequencies
Zero Input − Output Propagation Delay
Multiple Low−Skew Outputs
Output−Output Skew Less than 250 ps
Device−Device Skew Less than 700 ps
One Input Drives 9 Outputs, Grouped as 4 + 4 + 1
Less than 200 ps Cycle−to−Cycle Jitter is Compatible with PentiumR
Based Systems
Test Mode to Bypass PLL
Available in 16 Pin, 150 mil SOIC and 4.4 mm TSSOP
3.3 V Operation, Advanced 0.35 CMOS Technology
These are Pb−Free Devices**
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MARKING
DIAGRAMS*
16
16
XXXXXXXXG
AWLYWW
1
SOIC−16
D SUFFIX
CASE 751B
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
XXXX
A
WL, L
Y
W, WW
G or G
1
XXXX
XXXX
ALYWG
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*x = C for Commercial; I for Industrial.
**For additional information on our Pb−Free strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 4
1
Publication Order Number:
NB2309A/D
NB2309A
PLL
CLKOUT
MUX
REF
CLKA1
CLKA2
CLKA3
CLKA4
S2
SELECT INPUT
DECODING
CLKB1
S1
CLKB2
CLKB3
CLKB4
Figure 1. Block Diagram
Table 1. SELECT INPUT DECODING
S2
S1
Clock A1 − A4
Clock B1 − B4
CLKOUT
(Note 1)
Output Source
PLL
ShutDown
0
0
Three−state
Three−state
Driven
PLL
N
0
1
Driven
Three−state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and the output.
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2
NB2309A
REF
1
16
CLKOUT
CLKA1
2
15
CLKA4
CLKA2
3
14
CLKA3
VDD
4
13
VDD
GND
5
12
GND
CLKB1
6
11
CLKB4
CLKB2
7
10
CLKB3
S2
8
9
S1
NB2309A
Figure 2. Pin Configuration
Table 2. PIN DESCRIPTION
Pin #
Pin Name
Description
1
REF (Note 2)
2
CLKA1 (Note 3)
Buffered clock output, Bank A.
3
CLKA2 (Note 3)
Buffered clock output, Bank A.
Input reference frequency, 5 V tolerant input.
4
VDD
3.3 V supply.
5
GND
Ground.
6
CLKB1 (Note 3)
Buffered clock output, Bank B.
7
CLKB2 (Note 3)
Buffered clock output, Bank B.
8
S2 (Note 4)
Select input, bit 2.
9
S1 (Note 4)
Select input, bit 1.
10
CLKB3 (Note 3)
Buffered clock output, Bank B.
11
CLKB4 (Note 3)
Buffered clock output, Bank B.
12
GND
Ground.
13
VDD
3.3 V supply.
14
CLKA3 (Note 3)
Buffered clock output, Bank A.
15
CLKA4 (Note 3)
Buffered clock output, Bank A.
16
CLKOUT (Note 3)
Buffered output, internal feedback on this pin.
2. Weak pulldown.
3. Weak pulldown on all outputs.
4. Weak pullup on these inputs.
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3
NB2309A
Table 3. MAXIMUM RATINGS
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
−0.5
+7.0
V
DC Input Voltage (Except REF)
−0.5
VDD + 0.5
V
DC Input Voltage (REF)
−0.5
7
V
Storage Temperature
−65
+150
°C
Maximum Soldering Temperature (10 sec)
260
°C
Junction Temperature
150
°C
>2000
V
Static Discharge Voltage (per MIL−STD−883, Method 3015)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Table 4. OPERATING CONDITIONS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES
Parameter
Description
Min
Max
Unit
3.0
3.6
V
0
−40
70
85
°C
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, below 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
10
pF
CIN
Input Capacitance
7
pF
Commercial
Industrial
Table 5. ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage (Note 5)
VIH
Input HIGH Voltage (Note 5)
IIL
Input LOW Current
VIN = 0 V
50.0
A
IIH
Input HIGH Current
VIN = VDD
100.0
A
VOL
Output LOW Voltage
IOL = 8 mA (−1)
IOL = 12 mA (−1H)
0.4
V
VOH
Output HIGH Voltage
IOH = −8 mA (−1)
IOH = −12 mA (−1H)
IDD
Supply Current (Commercial Temp)
Unloaded outputs at 66.67 MHz,
Select inputs at VDD
34
mA
IDD
Supply Current (Industrial Temp)
Unloaded outputs at
50
34
19
mA
2.0
100 MHz
66.67 MHz
33 MHz
Select inputs at VDD or GND, at Room
Temp
5. REF input has a threshold voltage of VDD/2.
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4
V
2.4
V
NB2309A
Table 6. SWITCHING CHARACTERISTICS (Commercial and Industrial) (Note 6)
Parameter
Description
1/t1
Output Frequency
1/t1
Duty Cycle = (t2 / t1) * 100
t3
Output Rise Time
t4
Test Conditions
Min
Typ
Max
Unit
100
133.33
MHz
60
55
%
30 pF load
10 pF load
15
15
(−1, −1H)
(−1H)
Measured at 1.4 V, FOUT = 66.67 MHz
< 50 MHz
40
45
(−1, −1H)
(−1H)
Measured between 0.8 V and 2.0 V
2.5
1.5
ns
Output Fall Time
Measured between 2.0 V and 0.8 V
1.5
ns
t5
Output−to−Output Skew
All outputs equally loaded
250
ps
t6
Delay, REF Rising Edge to CLKOUT
Rising Edge
Measured at VDD/2
0
±350
ps
t7
Device−to−Device Skew
Measured at VDD/2 on the CLKOUT pins of
the device
0
700
ps
t8
Output Slew Rate
Measured between 0.8 V and 2.0 V using
Test Circuit #2
tJ
Cycle−to−Cycle Jitter
Measured at 66.67 MHz, loaded outputs
200
ps
tLOCK
PLL Lock Time
Stable power supply, valid clock presented
on REF pin
1.0
ms
trin
REF Input Rise Time
Measured between 0.8 V to 2.0 V
1.0
ns
tfin
REF Input Rise Fall Time
Measured between 2.0 V to 0.8 V
1.0
ns
6. All parameters specified with loaded outputs and apply to both PLL−Mode and PLL−Bypass Mode.
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5
50
50
1
V/ns
NB2309A
Zero Delay and Skew Control
For applications requiring zero input−output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero−input−output
delay.
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
SWITCHING WAVEFORMS
t1
t2
1.4 V
1.4 V
0.8 V
0.8 V
OUTPUT
t3
Figure 3. Duty Cycle Timing
t4
V DD
2
INPUT
1.4 V
OUTPUT
0V
Figure 4. All Outputs Rise/Fall Time
1.4 V
OUTPUT
3.3 V
2.0 V
2.0 V
1.4 V
V DD
2
OUTPUT
t5
t6
Figure 5. Output − Output Skew
Figure 6. Input − Output Propagation Delay
V DD
2
CLKOUT, Device 1
V DD
2
CLKOUT, Device 2
t7
Figure 7. Device − Device Skew
TEST CIRCUITS
VDD
VDD
0.1 F
OUTPUTS
VDD
CLKOUT
0.1 F
CLOAD
GND
OUTPUTS
1 k
VDD
0.1 F
1 k
10 pF
VDD
0.1 F
GND
Figure 8. Test Circuit #1
GND
GND
Figure 9. Test Circuit #2
For parameter t8 (output slew rate) on −1H devices
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6
NB2309A
ORDERING INFORMATION
Marking
Operating Range
Package
Shipping†
NB2309AC1DG
2309AC1G
Commercial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2309AC1DR2G
2309AC1G
Commercial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2309AI1DG
2309AI1G
Industrial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2309AI1DR2G
2309AI1G
Industrial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2309AC1HDG
2309AC1HG
Commercial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2309AC1HDR2G
2309AC1HG
Commercial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2309AI1HDG
2309AI1HG
Industrial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2309AI1HDR2G
2309AI1HG
Industrial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2309AC1DTG
2309AC1
Commercial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2309AC1DTR2G
2309AC1
Commercial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2309AI1DTG
2309AI1
Industrial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2309AI1DTR2G
2309AI1
Industrial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2309AC1HDTG
2309AC1H
Commercial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2309AC1HDTR2G
2309AC1H
Commercial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2309AI1HDTG
2309AI1H
Industrial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2309AI1HDTR2G
2309AI1H
Industrial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
Device
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
NB2309A
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE A
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
G
DETAIL E
H
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8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
NB2309A
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
Pentium is a registered trademark of Intel Corporation.
Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your local
Sales Representative
NB2309A/D