Intersil DG508A Cmos analog multiplexer Datasheet

DG506A, DG507A, DG508A, DG509A
Data Sheet
November 1999
CMOS Analog Multiplexers
Features
The DG506A, DG507A, DG508A and DG509A are CMOS
Monolithic 16-Channel/Dual 8-Channel and 8-Channel/Dual
4-Channel Analog Multiplexers, which can also be used as
demultiplexers. An enable input is provided. When the
enable input is high, a channel is selected by the address
inputs, and when low, all channels are off.
• Low Power Consumption
File Number
3137.3
• TTL and CMOS-Compatible Address and Enable Inputs
• 44V Maximum Power Supply Rating
• High Latch-Up Immunity
• Break-Before-Make Switching
A channel in the ON state conducts current equally well in
both directions. In the OFF state each channel blocks
voltages up to the supply rails. The address inputs and the
enable input are TTL and CMOS compatible over the full
specified operating temperature range.
The DG506A, DG507A, DG508A and DG509A are pinout
compatible with the industry standard devices.
• Alternate Source
Applications
• Data Acquisition Systems
• Communication Systems
• Signal Multiplexing/Demultiplexing
• Audio Signal Multiplexing
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
DG506AAK
-55 to 125
28 Ld CERDIP
F28.6
DG508AAK
-55 to 125
16 Ld CERDIP
F16.3
DG506ACJ
0 to 70
28 Ld PDIP
E28.6
DG508ABK
-25 to 85
16 Ld CERDIP
F16.3
DG506ACY
0 to 70
28 Ld SOIC
M28.3
DG508ACJ
0 to 70
16 Ld PDIP
E16.3
DG507ABK
-25 to 85
28 Ld CERDIP
F28.6
DG509ACJ
0 to 70
16 Ld PDIP
E16.3
DG507ACJ
0 to 70
28 Ld PDIP
E28.6
DG509ACY
0 to 70
16 Ld SOIC
M16.3
DG507ACY
0 to 70
28 Ld SOIC
M28.3
Pinouts
DG506A (PDIP, CERDIP, SOIC)
TOP VIEW
DG507A (PDIP, CERDIP, SOIC)
TOP VIEW
DG508A (PDIP, CERDIP)
TOP VIEW
DG509A (PDIP, SOIC)
TOP VIEW
28 D
V+ 1
28 DA
A0
1
16 A1
A0 1
16 A1
NC 2
27 V-
DB 2
27 V-
EN 2
15 A2
EN 2
15 GND
NC 3
26 S8
NC 3
26 S8A
S16 4
25 S7
S8B 4
25 S7A
S15 5
24 S6
S7B 5
24 S6A
S14 6
23 S5
S6B 6
23 S5A
S13 7
22 S4
S5B 7
22 S4A
S12 8
21 S3
S4B 8
21 S3A
S11 9
20 S2
S3B 9
20 S2A
S10 10
19 S1
S2B 10
19 S1A
V+ 1
S9 11
18 EN
S1B 11
18 EN
GND 12
17 A0
GND 12
17 A0
NC 13
16 A1
NC 13
16 A1
A3 14
15 A2
NC 14
15 A2
1
V- 3
S1
14 GND
V- 3
14 V+
4
13 V+
S1A 4
13 S1B
S2
5
12 S5
S2A 5
12 S2B
S3
6
11 S6
S3A 6
11 S3B
7
10 S7
S4A 7
10 S4B
D 8
9 S8
DA 8
9 DB
S4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
DG506A, DG507A, DG508A, DG509A
Truth Tables
DG506A
DG507A
A3
A2
A1
A0
EN
ON SWITCH
A2
A1
A0
EN
ON SWITCH
X
X
X
X
0
None
X
X
X
0
None
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
2
0
0
1
1
2
0
0
1
0
1
3
0
1
0
1
3
0
0
1
1
1
4
0
1
1
1
4
0
1
0
0
1
5
1
0
0
1
5
0
1
0
1
1
6
1
0
1
1
6
0
1
1
0
1
7
1
1
0
1
7
0
1
1
1
1
8
1
1
1
1
8
1
0
0
0
1
9
1
0
0
1
1
10
1
0
1
0
1
11
1
0
1
1
1
12
1
1
0
0
1
13
1
1
0
1
1
14
1
1
1
0
1
15
1
1
1
1
1
16
Logic “0” = VAL , VENL ≤ 0.8V, Logic “1” = VAH , VENH ≥ 2.4V.
Logic “0” = VAL , VENL ≤ 0.8V, Logic “1” = VAH , VENH ≥ 2.4V.
DG509A
A1
A0
EN
ON SWITCH
X
X
0
None
0
0
1
1A, 1B
0
1
1
2A, 2B
1
0
1
3A, 3B
1
1
1
4A, 4B
A0 , A1 , EN
Logic “1” = VAH ≥ 2.4V, Logic “0” = VAL ≤ 0.8V.
DG508A
A2
A1
A0
EN
ON SWITCH
X
X
X
0
None
0
0
0
1
1
0
0
1
1
2
0
1
0
1
3
0
1
1
1
4
1
0
0
1
5
1
0
1
1
6
1
1
0
1
7
1
1
1
1
8
A0 , A1 , A2 , EN
Logic “1” = VAH ≥ 2.4V, Logic “0” = VAL ≤ 0.8V
2
DG506A, DG507A, DG508A, DG509A
Functional Diagrams
DG506A
DG507A
S1
S1A
S2
S2A
S3
S3A
S4
S4A
S5
S5A
S6
S6A
S7
S7A
S8
DA
S8A
D
S9
S1B
S10
S2B
S11
S3B
S12
S4B
S13
S5B
ADDRESS DECODER
1 OF 16
S14
ENABLE
1 OF 4
DB
ADDRESS DECODER
1 OF 8
S6B
S15
S7B
S16
A0
A1
A2
A3
S8B
EN
4 Line Binary Address Inputs
(0 0 0 1) and EN = 5V
Above example shows channel 2 turned ON.
A0
A1
A2
EN (ENABLE INPUT)
3 Line Binary Address Inputs
(0 0 0) and EN = 5V
Above example shows channels 1A and 1B turned ON.
DG508A
DG509A
S1
S1A
S2
S2A
S3
S3A
S4
S4A
S5
ENABLE
1 OF 2
DA
D
S1B
ADDRESS DECODER
1 OF 8
S6
S2B
S7
DB
S3B
S8
A0
A1
A2
EN (ENABLE INPUT)
S4B
3 Line Binary Address Inputs
(1 0 1) and EN = 1
Above example shows channel 6 turned ON.
2 Line Binary Address Inputs
(0 0) and EN = 1
Above example shows channels 1A and 1B turned ON.
Schematic Diagram
V+
LOGIC TRIP
POINT REF
DECODER
+
-
V+
SX
AX
GND
DX
LOGIC AX
INPUT OR EN
VLOGIC INTERFACE
AND LEVEL SHIFTER
3
TYPICAL
SWITCH
DG506A, DG507A, DG508A, DG509A
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, VS, VD (Note 1) . . . . . . . . . . . . . .(V- -2V) To (V+ +2V)
Continuous Current, (Any Terminal Except S or D) . . . . . . . . . 30mA
Continuous Current, (S or D) . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 40mA
Thermal Resistance (Typical, Note 2)
θJA (oC/W) θJC (oC/W)
16 Ld CERDIP Package. . . . . . . . . . . .
75
20
28 Ld CERDIP Package. . . . . . . . . . . .
55
18
16 Ld PDIP Package . . . . . . . . . . . . . .
90
N/A
28 Ld PDIP Package . . . . . . . . . . . . . .
55
N/A
16 Ld SOIC Package . . . . . . . . . . . . . .
100
N/A
28 Ld SOIC Package . . . . . . . . . . . . . .
70
N/A
Maximum Junction Temperature
CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature
“A” and “B” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 150oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 125oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range
“A” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
“B” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on SX , DX, EN, or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
TA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified
Electrical Specifications
“A” SUFFIX
PARAMETER
TEST CONDITIONS
“B” AND “C” SUFFIX
(NOTE 4) (NOTE 3) (NOTE 4) (NOTE 4) (NOTE 3) (NOTE 4)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Switching Time of
Multiplexer, tTRANSITION
See Figure 1
-
0.6
1
-
0.6
-
µs
Break-Before-Make
Interval, tOPEN
See Figure 3
-
0.2
-
-
0.2
-
µs
Enable Turn-ON Time,
tON(EN)
See Figure 2
-
1
1.5
-
1
-
µs
Enable Turn-OFF Time,
tOFF(EN)
See Figure 2
-
0.4
1.0
-
0.4
-
µs
OFF Isolation, OIRR
VEN = 0V, RL = 1kΩ, CL = 15pF,
VS = 7VRMS , f = 500kHz (Note 5)
-
68
-
-
68
-
dB
Source OFF Capacitance,
CS(OFF)
VS = 0V, VEN = 0V, f = 140kHz
-
6
-
-
6
-
pF
-
5
-
-
5
-
pF
DG506A
-
45
-
-
45
-
pF
DG507A
-
23
-
-
23
-
pF
DG508A
-
25
-
-
25
-
pF
DG509A
-
12
-
-
12
-
pF
-
6
-
-
6
-
pC
-
4
-
-
4
-
pC
VA = 2.4V
-10
-0.002
-
-10
-0.002
-
µA
VA = 15V
-
0.006
10
-
0.006
10
µA
DG506A, DG507A
DG508A, DG509A
Drain OFF Capacitance,
CD(OFF)
Charge Injection, Q
DG506A, DG507A
VD = 0V, VEN = 0V, f = 140kHz
See Figure 4
DG508A, DG509A
DIGITAL INPUT CHARACTERISTICS
Address Input Current,
Input Voltage High, IAH
Address Input Current
Input Voltage Low, IAL
VEN = 2.4V
VEN = 0V
4
VA = 0V
-10
-0.002
-
-10
-0.002
-
µA
-10
-0.002
-
-10
-0.0002
-
µA
DG506A, DG507A, DG508A, DG509A
TA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified (Continued)
Electrical Specifications
“A” SUFFIX
PARAMETER
TEST CONDITIONS
“B” AND “C” SUFFIX
(NOTE 4) (NOTE 3) (NOTE 4) (NOTE 4) (NOTE 3) (NOTE 4)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
(Note 7)
-15
-
+15
-15
-
+15
V
Drain-Source ON
Resistance, rDS(ON)
Sequence Each IS = -200µA, VD = +10V
Switch ON
IS = -200µA, VD = -10V
VAL = 0.8V
VAH = 2.4V
-
270
400
-
-
230
400
-
270
450
Ω
230
450
Ω
rDS(ON) Matching
Between Channels
-10V ≤ VS ≤ +10V
-
6
-
-
6
-
%
Source OFF Leakage
Current, IS(OFF)
VEN = 0V
VS = +10V, VD = -10V
-1
0.002
1
-5
0.002
5
nA
VS = -10V, VD = +10V
-1
-0.005
1
Drain OFF Leakage
Current, ID(OFF)
DG506A
VEN = 0V
-5
-0.005
5
nA
VS = -10V, VD = +10V
-10
0.02
10
-20
0.02
20
nA
VS = +10V, VD = -10V
-10
-0.03
10
-20
-0.03
20
nA
DG507A
VS = -10V, VD = +10V
-5
0.007
5
-10
0.007
10
nA
VS = +10V, VD = -10V
-5
-0.015
5
-10
-0.015
10
nA
DG508A
VS = -10V, VD = +10V
-
0.01
10
-
0.01
20
nA
VS = +10V, VD = -10V
-10
-0.015
-
-20
-0.015
-
nA
DG509A
VS = -10V, VD = +10V
-
0.005
10
-
0.005
20
nA
VS = +10V, VD = -10V
-10
-0.008
-
-20
-0.008
-
nA
r DS(ON)MAX – r DS ( ON )MIN
∆r DS ( ON ) = -----------------------------------------------------------------------r DS ( ON )AVG
Drain ON Leakage Current, (Note 6)
Sequence Each
ID(ON)
Switch ON
DG506A
VD = VS(ALL) = +10V
VAL = 0.8V
VD = VS(ALL) = -10V
VAH = 2.4V
DG507A
VD = VS(ALL) = +10V
DG508A
DG509A
-10
0.03
10
-20
0.03
20
nA
-10
-0.06
10
-20
-0.06
20
nA
-5
0.015
5
-10
0.015
10
nA
VD = VS(ALL) = -10V
-5
-0.03
5
-10
-0.03
10
nA
VD = VS(ALL) = +10V
-
0.015
10
-
0.015
20
nA
VD = VS(ALL) = -10V
-10
-0.03
-
-20
-0.03
-
nA
VD = VS(ALL) = +10V
-
0.007
10
-
0.007
20
nA
VD = VS(ALL) = -10V
-10
-0.015
-
-20
-0.015
-
nA
-
1.3
2.4
-
1.3
2.4
mA
-1.5
-0.7
-
-1.5
-0.7
-
mA
-
1.3
2.4
-
1.3
2.4
mA
-1.5
-0.7
-
-1.5
-0.7
-
mA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current,
I+
VEN = 5.0V, VA = 0V
(Enabled)
Negative Supply Current,
IPositive Supply Current,
I+ Standby
VEN = 0V, VA = 0V
(Standby)
Negative Supply Current,
I- Standby
5
DG506A, DG507A, DG508A, DG509A
Electrical Specifications
TA = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V,
Unless Otherwise Specified
“A” SUFFIX
PARAMETER
TEST CONDITIONS
“B” AND “C” SUFFIX
MIN
(NOTE 3)
TYP
-30
-
-
-
-
-
30
-
-30
-
-
-
-
-
µA
-30
-
-
-
-
-
µA
-15
-
+15
-
-
-
V
MAX
MIN
(NOTE 3)
TYP
MAX
UNITS
-
-
µA
-
-
µA
DIGITAL INPUT CHARACTERISTICS
Address Input Current, Input VA = 2.4V
Voltage High, IAH
VA = 15V
Address Input Current Input
Voltage Low, IAL
VEN = 2.4V
VA = 0V
VEN = 0V
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
(Note 7)
Drain-Source ON
Resistance, rDS(ON)
Sequence Each
Switch ON
VAL = 0.8V
VAH = 2.4V
IS = -200µA, VD = +10V
-
-
500
-
-
-
Ω
IS = -200µA, VD = -10V
-
-
500
-
-
-
Ω
Source OFF Leakage
Current, IS(OFF)
VEN = 0V
VS = +10V, VD = -10V
-
-
50
-
-
-
nA
VS = -10V, VD = +10V
-50
-
-
-
-
-
nA
VS = -10V, VD = +10V
-
-
300
-
-
-
nA
VS = +10V, VD = -10V
-300
-
-
-
-
-
nA
VS = -10V, VD = +10V
-
-
200
-
-
-
nA
VS = +10V, VD = -10V
-200
-
-
-
-
-
nA
VS = -10V, VD = +10V
-
-
200
-
-
-
nA
VS = +10V, VD = -10V
-200
-
-
-
-
-
nA
Drain OFF Leakage Current, VEN = 0V
ID(OFF)
DG506A
DG507A
DG508A
DG509A
Drain ON Leakage Current,
ID(ON)
DG506A
(Note 6)
Sequence Each
Switch ON
VAL = 0.8V
VAH = 2.4V
DG507A
DG508A
DG509A
VS = -10V, VD = +10V
-
-
100
-
-
-
nA
VS = +10V, VD = -10V
-100
-
-
-
-
-
nA
VD = VS(ALL) = +10V
-
-
300
-
-
-
nA
VD = VS(ALL) = -10V
-300
-
-
-
-
-
nA
VD = VS(ALL) = +10V
-
-
200
-
-
-
nA
VD = VS(ALL) = -10V
-200
-
-
-
-
-
nA
VD = VS(ALL) = +10V
-
-
200
-
-
-
nA
VD = VS(ALL) = -10V
-200
-
-
-
-
-
nA
VD = VS(ALL) = +10V
-
-
100
-
-
-
nA
VD = VS(ALL) = -10V
-100
-
-
-
-
-
nA
VEN = 5.0V, VA = 0V
-3.2
-
4.5
-
-
-
mA
-3.2
-
4.5
-
-
-
mA
-3.2
-
4.5
-
-
-
mA
-3.2
-
4.5
-
-
-
mA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
Negative Supply Current, IPositive Standby Supply Current, I+
VEN = 0V, VA = 0V
Negative Standby Supply Current, INOTES:
3. Typical values are for design aid only, not guaranteed and not subject to production testing.
4. The algebraic convention whereby the most negative value is a minimum, and the most positive value is a maximum, is used in this data sheet.
5. Off isolation = 20Log |VS |/|VD |, where VS = input to Off switch, and VD = output due to VS .
6. ID(ON) is leakage from driver into “ON” switch.
7. Parameter not tested. Parameter guaranteed by design or characterization.
6
DG506A, DG507A, DG508A, DG509A
Test Circuits and Waveforms
+15V
+2.4V
+15V
+2.4V
V+
V+
EN
DG506A
(NOTE)
A3
±10V
S1
S1A THRU S8A ,
DA
A2 S2B , AND S7B
S2 THRU S15
A2
S16
A1
A0
LOGIC
INPUT
+10V
GND
V1MΩ
S8B
A1
SWITCH
OUTPUT
VO
D
50Ω
±10V
EN DG507A S1B
(NOTE)
LOGIC
INPUT
A0
DB
GND
V-
50Ω
35pF
+10V
SWITCH
OUTPUT
VO
1MΩ
35pF
-15V
-15V
NOTE: Similar connections for DG508A.
NOTE: Similar connections for DG509A.
FIGURE 1A. DG506A TEST CIRCUIT
FIGURE 1B. DG507A TEST CIRCUIT
3V
tr < 20ns
tf < 20ns
LOGIC INPUT 50%
0
VS1 S1 ON
0.8VS1
SWITCH
OUTPUT
VO
0
0.8VS8
VS8
S8 ON
TRANSITION
TIME
TRANSITION
TIME
FIGURE 1C. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIME
+15V
+15V
V+
EN
S1
V+
-5V
EN
DG506A
(NOTE)
A3
S2 THRU S16
A2
A0
A0
50Ω
-5V
S1A THRU S8A ,
DA ,
S2B THRU S8B
A1
A1
EN
S1B
DG507A
(NOTE)
SWITCH
OUTPUT
VO
D
GND
V-
EN
1kΩ
-15V
NOTE: Similar connections for DG508A.
FIGURE 2A. DG506A TEST CIRCUIT
7
A2
35pF
50Ω
GND
SWITCH
OUTPUT
VO
DB
V-
1kΩ
-15V
NOTE: Similar connections for DG509A.
FIGURE 2B. DG507A TEST CIRCUIT
35pF
DG506A, DG507A, DG508A, DG509A
Test Circuits and Waveforms
(Continued)
tr < 20ns
tf < 20ns
50%
3V
EN
50%
0V
tON (EN)
tOFF (EN)
0V
0.1VO
SWITCH
OUTPUT
VO
0.9VO
VO
FIGURE 2C. MEASUREMENT POINTS
FIGURE 2. ENABLE TIMES
+15V
+2.4V
V+
EN
A0
+5V (VS)
ALL S AND DA
tr < 20ns
tf < 20ns
3V
LOGIC
INPUT
DG506A
DG507A
(NOTE)
0V
A1
VS
A2
A3
LOGIC
INPUT
SWITCH
OUTPUT
VO
DB
GND
SWITCH
OUTPUT
VO
V-
0V
1kΩ
50Ω
50%
50%
35pF
tOPEN
-15V
NOTE: Similar connections for DG508A, DG509A.
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3A. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
+15V
+15V
V+
V+
EN
EN
DG506A
(NOTE)
A3
DG507A
(NOTE)
S1
A2
A2
A1
A1
A0
LOGIC
INPUT
D
GND
VO
V-
A0
LOGIC
INPUT
GND
S1A, S1B
DA OR DB
1000pF
-15V
NOTE: Similar connections for DG508A.
FIGURE 4A. DG506A TEST CIRCUIT
8
VO
V1000pF
-15V
NOTE: Similar connections for DG509A.
FIGURE 4B. DG507A TEST CIRCUIT
DG506A, DG507A, DG508A, DG509A
Test Circuits and Waveforms
(Continued)
3V
EN
0
∆VO
VO
∆VO is the measured voltage error due to charge injection.
The charge transfer error in Coulombs is Q = CL x ∆VO .
FIGURE 4C. CHARGE INJECTION WAVEFORMS
FIGURE 4. CHARGE INJECTION
Typical Performance Curves
400
550
V+ = +15V V- = -15V
VEN = 2.4V
IO = -200µA
+10V SIGNALS
300
350
rDS(ON) (Ω)
rDS(ON) (Ω)
V+ = +15V, V- = -15V
500 V+ = +10V, V- = -10V
450 V+ = +12V, V- = -12V
V+ = +7.5V, V- = -7.5V
400
300
250
+10V SIGNALS
200
200
150
100
100
50
0
-15
-10
-5
0
5
10
ANALOG SIGNAL VOLTAGE (V)
FIGURE 5. rDS(ON) vs ANALOG SIGNAL VOLTAGE vs
SUPPLY VOLTAGE
9
15
0
-55
-25
0
20
45
70
100
125
TEMPERATURE (oC)
FIGURE 6. TYPICAL rDS(ON) VARIATION WITH TEMPERATURE
DG506A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3810µm x 2770µm
Type: PSG/Nitride
Thickness: PSG: 7kÅ ±1.4kÅ
Nitride: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG506A
NC
NC
V+
D
V-
S16
S8
S15
S7
S14
S6
S13
S5
S12
S4
S11
S3
S10
S2
S9
S1
GND
10
NC
A3
A2
A1
A0
EN
DG507A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3810µm x 2770µm
Type: PSG/Nitride
Thickness: PSG: 7kÅ ±1.4kÅ
Nitride: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG507A
NC
DB
V+
DA
V-
S8B
S8A
S7B
S7A
S6B
S6A
S5B
S5A
S4B
S4A
S3B
S3A
S2B
S2A
S1B
S1A
GND
11
NC
NC
A2
A1
A0
EN
DG508A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3100µm x 2083µm
Type: PSG/Nitride
Thickness: PSG: 7kÅ ±1.4kÅww
Nitride: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG508A
EN
A0
A1
A2
GND
VV+
S1
S5
S2
S6
S3
S7
S4
12
D
S8
DG509A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3100µm x 2083µm
Type: PSG/Nitride
Thickness: PSG: 7kÅ ±1.4kÅ
Nitride: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG509A
EN
A0
A1
GND
V+
VS1B
S1A
S2B
S2A
S3B
S3A
S4B
S4A
13
DA
DB
DG506A, DG507A, DG508A, DG509A
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
C
D
0.735
0.775
D1
0.005
-
E
0.300
0.325
E1
0.240
0.280
6.10
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
14
MILLIMETERS
e
0.100 BSC
eA
0.300 BSC
eB
-
L
0.115
N
16
0.204
0.355
18.66
-
19.68
5
0.13
-
5
7.62
8.25
6
7.11
5
2.54 BSC
-
7.62 BSC
6
0.430
-
0.150
2.93
16
10.92
7
3.81
4
9
Rev. 0 12/93
DG506A, DG507A, DG508A, DG509A
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-001-BF ISSUE D)
N
28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC
PACKAGE
E1
INDEX
AREA
1 2 3
N/2
INCHES
-B-
-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
eA
A1
eC
B
0.010 (0.25) M
C
L
C A B S
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
15
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.250
-
6.35
4
A1
0.015
-
0.39
-
4
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.030
0.070
0.77
1.77
8
C
0.008
0.015
D
1.380
1.565
D1
0.005
-
0.13
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
e
0.204
0.381
35.1
0.100 BSC
-
39.7
5
-
5
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
6
eB
-
0.700
-
17.78
7
L
0.115
0.200
2.93
5.08
4
N
28
28
9
Rev. 0 12/93
DG506A, DG507A, DG508A, DG509A
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
H
0.25(0.010) M
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
α
e
A1
B
0.25(0.010) M
0.10(0.004)
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
16
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e
C
MIN
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
16
0o
16
7
8o
Rev. 0 12/93
DG506A, DG507A, DG508A, DG509A
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
17
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
e
α
MIN
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
28
0o
28
7
8o
Rev. 0 12/93
DG506A, DG507A, DG508A, DG509A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
LEAD FINISH
c1
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
eA
ccc M C A - B S
e
eA/2
c
aaa M C A - B S D S
D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
18
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
5
E
0.220
0.310
5.59
7.87
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
16
16
8
Rev. 0 4/94
DG506A, DG507A, DG508A, DG509A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
LEAD FINISH
c1
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.232
-
5.92
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
eA
e
ccc M C A - B S
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
1.490
-
37.85
5
E
0.500
0.610
15.49
5
e
12.70
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
-
eA/2
0.300 BSC
7.62 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
28
28
8
Rev. 0 4/94
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
19
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
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Republic of China
TEL: (886) 2 2716 9310
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