LTC4100
Smart Battery
Charger Controller
U
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
The LTC®4100 Smart Battery Charger is a single chip
charging solution that dramatically simplifies construction of an SBS compliant system. The LTC4100 implements a Level 2 charger function whereby the charger can
be programmed by the battery or by the host. A SafetySignal
on the battery being charged is monitored for temperature, connectivity and battery type information. The SMBus
interface remains alive when the AC power adapter is
removed and responds to all SMBus activity directed to
it, including SafetySignal status (via the ChargerStatus
command). The charger also provides an interrupt to the
host whenever a status change is detected (e.g., battery
removal, AC adapter connection).
Single Chip Smart Battery Charger Controller
100% Compliant (Rev. 1.1) SMBus Support allows
for Operation with or without Host
SMBus Accelerator Improves SMBus Timing*
Wide Output Voltage Range: 6.4V to 26V
Hardware Interrupt and SMBAlert Response
Eliminate Interrupt Polling
High Efficiency Synchronous Buck Charger
0.5V Dropout Voltage; Maximum Duty Cycle > 98%
AC Adapter Current Limit Maximizes Charge Rate
±0.8% Voltage Accuracy; ±5% Current Accuracy
Up to 4A Charging Current Capability
10-Bit DAC for Charge Current Programming
11-Bit DAC for Charger Voltage Programming
User-Selectable Overvoltage and Overcurrent Limits
High Noise Immunity SafetySignal Sensor
Small 24-Pin Narrow (0.209") SSOP Package
Charging current and voltage are restricted to chemistry
specific limits for improved system safety and reliability.
Limits are programmable by two external resistors. Additionally, the maximum average current from the AC adapter
is programmable to avoid overloading the adapter when
simultaneously supplying load current and charging
current. When supplying system load current, charging
current is automatically reduced to prevent adapter overload.**
U
APPLICATIO S
■
■
July 2003
DESCRIPTIO
FEATURES
Portable Instruments and Computers
Data Storage Systems and Battery Backup Servers
, LTC and LT are registered trademarks of Linear Technology Corporation.
*U.S. Patent No. 6,650,174 **U.S. Patent No. 5,723,970
U
TYPICAL APPLICATIO
DCIN
0.1µF
13.7k
3V
TO 5.5V
1.21k
17
11
6
CHGEN
10
ACP
7
9
8
15
16
13
1.13k
14
10k
20
LTC4100
VDD
DCIN
DCDIV
INFET
CHGEN
CLP
ACP
CLN
SMBALERT
TGATE
SCL
BGATE
SDA
PGND
THB
CSP
THA
BAT
ILIM
VSET
VLIM
ITH
IDC
GND
0.1µF
5
4
5k
24
23
20µF
1
3
SMART BATTERY
0.025Ω
10µH
2
20µF
21
22
18
19
12
0.01µF
100Ω
6.04k
0.0015µF
54.9k
0.082µF
SMBALERT#
0.033Ω
0.12µF
0.1µF
SafetySignal
SMBCLK
SMBCLK
SMBDAT
SMBDAT
4100 TA01
Figure 1. 4A Smart Battery Charger
sn4100 4100is
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1
LTC4100
U
W W
W
ABSOLUTE
AXI U RATI GS
U
W
U
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
TOP VIEW
Voltage from VDD to GND ................................ 7V/–0.3V
Voltage from CHGEN, DCDIV, SDA, SCL
and SMBALERT to GND .............................. 7V/–0.3V
Voltage from DCIN, CLP, CLN to GND ........... 32V/–0.3V
PGND wrt. GND .................................................... ±0.3V
CSP, BAT to GND .............................................. 28V/–5V
Operating Ambient Temperature Range (Note 4)
........................................................... – 40°C to 85°C
Junction Temperature Range ............... – 40°C to 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TGATE
1
24 CLP
PGND
2
23 CLN
BGATE
3
22 BAT
INFET
4
21 CSP
DCIN
5
20 IDC
CHGEN
6
19 ITH
SMBALERT
7
18 VSET
SDA
8
17 VDD
SCL
9
16 THA
ACP 10
15 THB
DCDIV 11
14 VLIM
GND 12
13 ILIM
LTC4100EG
G PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 90°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
DCIN Operating Range
MAX
UNITS
6
●
–0.8
–1
VCSP – VBAT Target = 102.3mV
IDAC = 0xFFFF
●
–3
–5
3
5
%
%
VDD Operating Voltage
0V ≤ VDCIN ≤ 32V
●
3
5.5
V
Battery Leakage Current
DCIN = 0V, VCLP = VCLN = VCSP = VBAT
●
15
30
µA
Undervoltage Lockout Threshold
DCIN Rising, VBAT = 0V
●
4.7
5.5
V
VDD Power-Fail
Part Held in Reset Until this VDD Present
●
3
V
DCIN Current in Shutdown
VCHGEN = 0V
3
mA
DCIN Operating Current
Charging
VTOL
Charge Voltage Accuracy
(Note 2)
VDD
TYP
●
IDCIN
ITOL
MIN
Charge Current Accuracy (Note 3)
3
28
V
5
mA
0.8
1
%
%
Shutdown
UVLO
4.2
2
Current Sense Amplifier, CA1
Input Bias Current into BAT Pin
CMSL
CA1/I1 Input Common Mode Low
CMSH
CA1/I1 Input Common Mode High
µA
11.66
●
VDCIN ≤ 28V
●
0
V
VCLN-0.2
V
sn4100 4100is
2
LTC4100
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
140
165
200
mV
Current Comparators ICMP and IREV
ITMAX
Maximum Current Sense Threshold (VCSP-VBAT)
ITREV
Reverse Current Threshold (VCSP-VBAT)
VITH = 2.4V
●
– 30
mV
Current Sense Amplifier, CA2
Transconductance
1
mmho
Source Current
Measured at ITH, VITH = 1.4V
–40
µA
Sink Current
Measured at ITH, VITH = 1.4V
40
µA
Current Limit Amplifier
Transconductance
VCLP
Current Limit Threshold
ICLP
CLP Input Bias Current
1.5
●
93
100
mmho
107
100
mV
nA
Voltage Error Amplifier, EA
Transconductance
Sink Current
OVSD
Measured at ITH, VITH = 1.4V
Overvoltage Shutdown Threshold as a Percent
of Programmed Charger Voltage
1
mmho
36
µA
●
102
107
110
%
●
0.0
0.17
0.25
V
25
50
Input P-Channel FET Driver (INFET)
DCIN DetectionThreshold (VDCIN-VCLP)
DCIN Voltage Ramping Up
from VCLP-0.05V
Forward Regulation Voltage (VDCIN-VCLP)
●
Reverse Voltage Turn-Off Voltage (VDCIN-VCLP)
INFET “ON” Clamping Voltage (VDCIN-VINFET)
IINFET = 1µA
INFET “OFF” Clamping Voltage (VDCIN-VINFET)
IINFET = –25µA
●
–60
–25
●
5
5.8
mV
mV
6.5
V
0.25
V
345
kHz
Oscillator
fOSC
Regulator Switching Frequency
fMIN
Regulator Switching Frequency in Drop Out
DCMAX
Regulator Maximum Duty Cycle
255
300
Duty Cycle ≥ 98%
20
25
kHz
VCSP = VBAT
98
99
%
Gate Drivers (TGATE, BGATE)
VTGATE High (VCLN-VTGATE)
ITGATE = –1mA
50
mV
VBGATE High
IBGATE = –1mA
VTGATE Low (VCLN-VTGATE)
ITGATE = 1mA
5.6
10
V
5.6
10
V
VBGATE Low
IBGATE = 1mA
50
mV
TGTR
TGTF
TGATE Transition Time
TGATE Rise Time
TGATE Fall Time
CLOAD = 3000pF, 10% to 90%
CLOAD = 3000pF, 10% to 90%
50
50
110
100
ns
ns
BGTR
BGTF
BGATE Transition Time
BGATE Rise Time
BGATE Fall Time
CLOAD = 3000pF, 10% to 90%
CLOAD = 3000pF, 10% to 90%
40
40
90
80
ns
ns
VTGATE at Shutdown (VCLN-VTGATE)
ITGATE = –1µA
100
mV
VBGATE at Shutdown
ITGATE = 1µA
100
mV
sn4100 4100is
3
LTC4100
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.14
1.20
1.26
V
AC Present Comparator
VACP
DCDIV Threshold
VDCDIV Rising from 1V to 1.4V
●
DCDIV Hysteresis
25
DCDIV Input Bias Current
VDCDIV = 1.2V
–1
ACP VOH
IACP = –2mA
2
mV
µA
1
V
ACP VOL
IACP = 1mA
0.5
V
DCDIV to ACP Delay
VDCDIV = 1.3V
10
µs
SafetySignal Decoder
SafetySignal Trip (RES_COLD/RES_OR)
RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9Ω ±1%
●
95
100
105
kΩ
SafetySignal Trip (RES_IDEAL/RES_COLD)
RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9Ω ±1%
●
28.5
30
31.5
kΩ
SafetySignal Trip (RES_HOT/RES_IDEAL)
RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9Ω ±1%
●
2.85
3
3.15
kΩ
SafetySignal Trip (RES_UR/RES_HOT)
RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9Ω ±1%
●
425
500
575
Ω
Time Between SafetySignal Measurements
DCDIV = 1.3V
DCDIV = 1V
250
ms
ms
32
DACs
Charging Current Resolution
Guaranteed Monotonic Above IMAX/16
Charging Current Granularity
RLIMIT = 0
RLIMIT = 10k ±1%
RLIMIT = 33k ±1%
RLIMIT = Open (or Short to VDD)
Wake-Up Charging Current (IWAKE-UP)
All Values of RILIM
All Values of RVLIM
Charging Current Limit
CSP – BAT
RLIMIT = 0 (0-1A)
Charging Current = 0x03FF (0x0400 Note 7)
97.3
107.3
mV
RLIMIT = 10k ±1%, (0-2A)
Charging Current = 0x07FE (0x0800 Note 7)
97.3
107.3
mV
RLIMIT = 33k ±1% (0-3A)
Charging Current = 0x0BFC (0x0C00 Note 7)
72.3
82.3
mV
RLIMIT = 0pen (or Short to VDD) (0-4A)
Charging Current = 0x0FFC (0x1000 Note 7)
97.3
107.3
mV
Guaranteed Monotonic (2.9V ≤ VBAT ≤ 28V)
11
Charging Voltage Resolution
Charging Voltage Granularity
10
Bits
1
2
4
4
mA
mA
mA
mA
80 (NOTE 5)
mA
Bits
16
mV
sn4100 4100is
4
LTC4100
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Charging Voltage Limit
RVLIM = 0
Charging Voltage = 0x2260 (Note 7)
8.730
8.800
8.870
V
RVLIM = 10k ±1%
Charging Voltage = 0x3330 (Note 7)
12.999
13.104
13.209
V
RVLIM = 33k ±1%
Charging Voltage = 0x4400 (Note 7)
17.269
17.408
17.547
V
RVLIM = 100k ±1%
Charging Voltage = 0x5400 DCIN ≥ 22V (Note 7)
21.538
21.712
21.886
V
RVLIM = 0pen (or Short to VDD)
Charging Voltage = 0x6D60 DCIN ≥ 29V (Note 7)
27.781
28.006
28.231
V
0.8
V
0.4
V
1
µA
Logic Levels
VIL
SCL/SDA Input Low Voltage
VIH
SCL/SDA Input High Voltage
VOL
SDA Output Low Voltage
IPULL-UP = 350µA
IIL
SCL/SDA Input Current
VSDA, VSCL = VIL
IIH
SCL/SDA Input Current
VSDA, VSCL = VIH
VOL
SMBALERT Output Low Voltage
IPULL-UP = 500µA
SMBALERT Output Pull-Up Current
VSMBALERT = VOL
CHGEN Output Low Voltage
IOL = 100µA
CHGEN Output Pull-Up Current
VCHGEN = VOL
VOL
VIL
CHGEN Input Low Voltage
VIH
CHGEN Input High Voltage
Power-On Reset Duration
●
●
2.1
V
●
–1
–1
●
V
µA
–10
–3.5
0.4
V
–17.5
–10
–3.5
µA
0.9
V
V
●
●
µA
–17.5
●
VDD = 3V
VDD = 5.5V
1
0.5
2.5
VDD Ramp from 0V to >3V in <5µs
3.9
V
V
100
µs
SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)
tHIGH
SCL Serial Clock High Period
tLOW
tR
µs
IPULL-UP = 350µA, CLOAD = 250pF, RPU = 9.31k
●
4
SCL Serial Clock Low Period
IPULL-UP = 350µA, CLOAD = 250pF, RPU = 9.31k
●
4.7
15000
µs
SDA/SCL Rise Time
CLOAD = 250pF, RPU = 9.31k
●
1000
ns
tF
SDA/SCL Fall Time
CLOAD = 250pF, RPU = 9.31k
●
300
ns
tSU:STA
Start Condition Setup Time
●
4.7
µs
tHD:STA
StartCondition Hold Time
●
4
µs
tHD:DAT
SDA to SCL Falling-Edge Hold Time,
Slave Clocking in Data
●
300
ns
tTIMEOUT
Time Between Receiving Valid
ChargingCurrent() and
ChargingVoltage() Commands
●
140
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: See Test Circuit.
Note 3: Does not include tolerance of current sense resistor.
Note 4: The LTC4100E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
175
210
sec
Note 5: Current accuracy dependent upon circuit compensation and sense
resistor.
Note 6: CTH is defined as the sum of capacitance on THA, THB and
SafetySignal.
Note 7: The corresponding overrange bit will be set when a HEX value
greater than or equal to this value is used.
sn4100 4100is
5
LTC4100
U
U
U
PI FU CTIO S
TGATE (Pin 1): Drives the Top External P-MOSFET of the
Battery Charger Buck Converter.
PGND (Pin 2): High Current Ground Return for BGATE
Driver.
BGATE (Pin 3): Drives the Bottom External N-MOSFET of
the Battery Charger Buck Converter.
INFET (Pin 4): Drives the Gate of the External Input
P-MOSFET.
DCIN (Pin 5): External DC Power Source Input.
CHGEN (Pin 6): Digital Bidirectional Pin to Enable Charger
Function. This pin is connected as a wired AND bus.
The following events will cause the POWER_FAIL bit in
the ChargerStatus register to become set:
1. An external device pulling the CHGEN signal to within
0.9V to GND;
2. The AC adapter voltage is not above the battery
voltage.
SMBALERT (Pin 7): Active Low Interrupt Output to Host
(referred to as the SMBALERT# signal in the SMBus
Revision 1.1 specification). Signals host that there has
been a change of status in the charger registers and that
the host should read the LTC4100 status registers to
determine if any action on its part is required. This signal
can be connected to the optional SMBALERT# line of the
SMBus. Open drain with weak current source pull-up to
VDD (with Schottky to allow it to be pulled to 5V externally).
SDA (Pin 8): SMBus Data Signal from Main (host-controlled) SMBus. External pull-up resistor is required.
SCL (Pin 9): SMBus Clock Signal from Main (host-controlled) SMBus. External pull-up resistor is required.
ACP (Pin 10): This Output Indicates the Value of the DCDIV
Comparator. It can be used to indicate whether AC is
present or not.
DCDIV (Pin 11): Supply Divider Input. This is a high
impedance comparator input with a 1.2V threshold (rising
edge) and hysteresis.
GND (Pin 12): Ground for Digital and Analog Circuitry.
ILIM (Pin 13): An external resistor is connected between
this pin and GND. The value of the external resistor
programs the range and resolution of the programmed
charger current.
VLIM (Pin 14): An external resistor is connected between
this pin and GND. The value of the external resistor
programs the range and resolution of the charging voltage.
THB (Pin 15): SafetySignal Force/Sense Pin to Smart
Battery. See description of operation for more detail. The
maximum allowed combined capacitance on THA, THB
and SafetySignal is 1nF (see Figure 4). A series resistor
54.9k needs to be connected between this pin and the
battery’s SafetySignal for this circuit to work correctly.
THA (Pin 16): SafetySignal Force/Sense Pin to Smart
Battery. See description of operation for more detail. The
maximum allowed combined capacitance on THA, THB
and SafetySignal is 1nF (see Figure 4). A series resistor
1130Ω needs to be connected between this pin and the
battery’s SafetySignal for this circuit to work correctly.
VDD (Pin 17): Power Supply Input for the LTC4100 Digital
Circuitry. Bypass this pin with 0.1µF. Typically between
3.3V and 5VDC.
VSET (Pin 18): Tap Point of the Programmable Resistor
Divider, which Provides Battery Voltage Feedback to the
Charger.
ITH (Pin 19): Control Signal of the Inner Loop of the
Current Mode PWM. Higher ITH corresponds to higher
charging current in normal operation. A 0.0015µF capacitor to GND filters out PWM ripple. Typical full-scale output
current is 40µA. Nominal voltage range for this pin is 0V
to 3V.
IDC (Pin 20): Bypass to GND with a 0.082µF Capacitor.
CSP (Pin 21): Current Amplifier CA1 Input. This pin and
the BAT pin measure the voltage across the sense resistor,
RSENSE, to provide the instantaneous current signals required for both peak and average current mode operation.
BAT (Pin 22): Battery Sense Input and the Negative
Reference for the Current Sense Resistor. A bypass capacitor of at least 10µF is required.
sn4100 4100is
6
LTC4100
U
U
U
PI FU CTIO S
CLN (Pin 23): Negative Input to the Input Current Limiting
Circuit Block. If no current limit function is desired, connect this pin to CLP. The threshold is set at 100mV below
the voltage at the CLP pin. When used to limit supply
current, a filter is needed to filter out the switching noise.
CLP (Pin 24): Positive Input to the Input Current Limiting
Circuit Block. This pin also serves as a power supply for
the IC. Bypass to ground with a 1µF capacitor.
W
BLOCK DIAGRA
0.01µF
VSET
+
0.1µF
GND
VBAT
–
18
11-BIT
VDAC
DCIN
1.28V
OSCILLATOR
WATCHDOG
DETECT tON
22
3k
21
1.19V
+
÷5
EA
+
–
CLP
D1
Q3
BGATE
PGND
CLN
RCL
CLP
DCIN
Q1
INFET
Q
1
ICMP
R
PWM
LOGIC
–
IREV
17mV
+
3
20 IDC
–
2
100mV
+
CL1
–
23
24
gm = 1.5m
Ω
Q2
S
gm = 1m
Ω
SW
TGATE
+
1.19V
19 ITH
10-BIT
IDAC
5
5.8V
10 ACP
DCDIV
11
4
CLP
VIN
SW
BUFFERED
ITH
gm = 1m
–
20µF
CSP
0V
9k
20µF
L1
BAT
RSENSE
–
CA1
+
12
Ω
100Ω
VBAT
CHGEN 6
VDD
VIN
1.2V
10µA
17 VDD
SMBALERT 7
SMBus
INTERFACE
AND CONTROL
SDA 8
LIMIT
DECODER
SCL 9
THA 16
THERMISTER
INTERFACE
THB 15
13
14
ILIM
VLIM
RVLIM
RILIM
Figure 2.
TEST CIRCUIT
LTC4100
–
+
1.19V
+
–
EA
VTOL =
VDAC
ITH
BAT VSET
–
LT1055
+
CSP
VBAT – VVDAC
• 100
VVDAC
FOR VVDAC = 17.56V(0x44A0)
DCIN = 21V
0.6V
4100 TC01
sn4100 4100is
7
LTC4100
U
OPERATIO
Overview (Refer to Block Diagram)
The LTC4100 is composed of a battery charger section, a
charger controller, a 10-bit DAC to control charger current, an 11-bit DAC to control charger voltage, a SafetySignal
decoder, limit decoder and an SMBus controller block. If
no battery is present, the SafetySignal decoder indicates a
RES_OR condition and charging is disabled by the charger
controller (CHGEN = Low). Charging will also be disabled
if DCDIV is low, or the SafetySignal is decoded as
RES_HOT. If a battery is inserted and AC power is connected, the battery will be charged with an 80mA “wakeup” current. The wake-up current is discontinued after
tTIMEOUT if the SafetySignal is decoded as RES_UR or
RES_C0LD, and the battery or host doesn’t transmit
charging commands.
The SMBus interface and control block receives
ChargingCurrent() and ChargingVoltage() commands via
the SMBus. If ChargingCurrent() and ChargingVoltage()
command pairs are received within a tTIMEOUT interval, the
values are stored in the current and voltage DACs and the
charger controller asserts the CHGEN line if the decoded
SafetySignal value will allow charging to commence.
ChargingCurrent() and ChargingVoltage() values are compared against limits programmed by the limit decoder
block; if the commands exceed the programmed limits
these limits are substituted and overrange flags are set.
The charger controller will assert SMBALERT whenever a
status change is detected, namely: AC_PRESENT,
BATTERY_PRESENT, ALARM_INHIBITED, or V DD
power-fail. The host may query the charger, via the
SMBus, to obtain ChargerStatus() information. SMBALERT
will be deasserted upon a successful read of
ChargerStatus() or a successful Alert Response
Address (ARA) request.
Battery Charger Controller
The LTC4100 charger controller uses a constant off-time,
current mode step-down architecture. During normal
operation, the top MOSFET is turned on each cycle when
the oscillator sets the SR latch and turned off when the
main current comparator ICMP resets the SR latch. While
the top MOSFET is off, the bottom MOSFET is turned
on until either the inductor current trips the current
comparator IREV, or the beginning of the next cycle.
The oscillator uses the equation,
tOFF =
(VDCIN – VBAT )
(VDCIN • fOSC )
to set the bottom MOSFET on time. The result is quasiconstant frequency operation: the converter frequency
remains nearly constant over a wide range of output
voltages. This activity is diagrammed in Figure 3.
OFF
TGATE
ON
ON
tOFF
BGATE
OFF
TRIP POINT SET
BY ITH VOLTAGE
INDUCTOR
CURRENT
4100 F01
Figure 3.
The peak inductor current, at which ICMP resets the SR
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by the IDAC at the IDC pin and adjusts
ITH for the desired voltage across RSENSE.
The voltage at BAT is divided down by an internal resistor
divider set by the VDAC and is used by error amp EA to
decrease ITH if the divider voltage is above the 1.19V
reference.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (100mV/
RCL). At input current limit, CL1 will decrease the ITH
voltage to reduce charging current.
An overvoltage comparator, OV, guards against transient
overshoots (>7%). In this case, the top MOSFET is turned
off until the overvoltage condition is cleared. This feature
is useful for batteries that "load dump" themselves by
opening their protection switch to perform functions such
as calibration or pulse mode charging.
sn4100 4100is
8
LTC4100
U
OPERATIO
PWM Watchdog Timer
Description of Supported Battery Charger Functions
There is a watchdog timer that observes the activity on the
TGATE pin. If TGATE stops switching for more than 40µs,
the watchdog activates and turns off the top MOSFET for
about 400ns. The watchdog engages to prevent very low
frequency operation in dropout – a potential source of
audible noise when using ceramic input and output capacitors.
The functions are described as follows (see Table 1 also):
Charger Start-Up
When the charger is enabled, it will not begin switching
until the ITH voltage exceeds a threshold that assures initial
current will be positive. This threshold is 5% to 15% of the
maximum programmed current. After the charger begins
switching, the various loops will control the current at a
level that is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation, but is typically less than 1ms.
SMBus Interface
All communications over the SMBus are interpreted by the
SMBus interface block. The SMBus interface is an SMBus
slave device. All internal LTC4100 registers may be updated and accessed through the SMBus interface, and
charger controller as required. The SMBus protocol is a
derivative of the I2CTM bus (Reference “I 2C-Bus and How
to Use It, V1.0” by Philips, and "System Management Bus
Specification", Version 1.1, from the SBS Implementers
Forum, for a complete description of the bus protocol
requirements.)
All data is clocked into the shift register on the rising edge
of SCL. All data is clocked out of the shift register on the
falling edge of SCL. Detection of an SMBus Stop condition,
or power-on reset via the VDD power-fail, will reset the
SMBus interface to an initial state at any time.
The LTC4100 command set is interpreted by the SMBus
interface and passed onto the charger controller block as
control signals or updates to internal registers.
FunctionName() 'hnn (command code)
Description: A brief description of the function.
Purpose: The purpose of the function, and an example
where appropriate.
• SMBus Protocol: Refer to Section 5 of the Smart
Battery Charger specification for more details.
Input, Output or Input/Output: A description of the data
supplied to or returned by the function.
ChargerSpecInfo() ('h11)
Description: The SMBus Host uses this command to read
the LTC4100’s extended status bits.
Purpose: Allows the System Host to determine the specification revision the charger supports as well as other
extended status information.
• SMBus Protocol: Read Word.
Output: The CHARGER_SPEC indicates that the LTC4100
supports Version 1.1 of the Smart Battery Charger Specification. The SELECTOR_SUPPORT indicates that the
LTC4100 does not support the optional Smart Battery
Selector Commands.
ChargerMode() ('h12)
Description: The SMBus Host uses this command to set
the various charger modes. The default values are set to
allow a Smart Battery and the LTC4100 to work in concert
without requiring an SMBus Host.
Purpose: Allows the SMBus Host to configure the charger
and change the default modes. This is a write only function, but the value of the “mode” bit, INHIBIT_CHARGE
may be determined using the ChargerStatus() function.
• SMBus Protocol: Write Word.
Input: The INHIBIT_CHARGE bit allows charging to be
inhibited without changing the ChargingCurrent() and
ChargingVoltage() values. The charging may be resumed
by clearing this bit. This bit is automatically cleared when
power is re-applied or when a battery is re-inserted.
I2C is a trademark of Philips Electronics N.V.
*http://www. SBS-FORUM.org
sn4100 4100is
9
LTC4100
U
OPERATIO
Table 1: Summary of Supported Charger Functions
7'b0001_001
8'h12
0
0
0
0
0
0
0
0
0
0
0
0
0
Control
Reserved
Permitted
Values
Return
Values
Control
7'b0001_001
8'h3C
Register
Reserved
Permitted
Values
Return
Values
Write
Read
Alert Response
Address
7'b0001_100
N/A
LEVEL:3/LEVEL:2
VOLTAGE_OR
CURRENT_OR
RES_OR
RES_COLD
RES_HOT
Permitted
Values 1/0 1/0 1/0 1/0
Write
LTCO()
RES_UR
Unsigned integer representing voltage in mV
Ignored
0
0
1/0
Ign 1/0
0
0
1/0
Ignored
LTC4100's Version Identification
Ignored
1/0
0
0
0
1
0
0
0
Status
0
0
0
0
1
0
LTC4100's Address
Not Supported
Read
Byte
Return
Values
0
0
FULLY DISCHARGED
8'h16
Permitted
Values
FULLY_CHARGED
7'b0001_001
CHARGING_VOLTAGE[15:0]
OVER_CHARGED_ALARM
AlarmWarning()
Value
DISCHARGING
Write
Unsigned integer representing current in mA
INITIALIZED
8'h15
1
Permitted
Values
REMAINING_TIME_ALARM
7'b0001_001
0
CHARGING_CURRENT[15:0]
REMAINING_CAPACITY_ALARM
ChargingVoltage()
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
Reserved
Write
1/0 1/0
Value
TERMINATE_DISCHARGE_ALARM
8'h14
OVER_TEMP_ALARM
7'b0001_001
NO_LOWI
ChargingCurrent()
TERMINATE_CHARGE_ALARM
Read
ALARM_INHIBITED
Status
POWER_FAIL
8'h13
BATTERY_PRESENT
7'b0001_001
AC_PRESENT
ChargerStatus()
Ignored
RESERVED_ALARM
Write
1
CHARGE_INHIBITED
ChargerMode()
0
Undefined
Return
Values
Read
CHARGER_SPEC
INHIBIT_CHARGE
Reserved
ENABLE_POLLING
Info
D1 DO
POLLING_ENABLED
8'h11
D5 D4 D3 D2
POR_RESET
7'b0001_001
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
RESET_TO_ZERO
Data
Type
VOLTAGE_NOTREG
Command
Code
CURRENT_NOTREG
ChargerSpecInfo()
SMBus
Address
ERROR
Access
SELECTOR_SUPPORT
Function
0
0
0
1
0
0
1
X
sn4100 4100is
10
LTC4100
U
OPERATIO
The ENABLE_POLLING bit is not supported by the LTC4100.
Values written to this bit are ignored.
The POR_RESET bit sets the LTC4100 to its power-on
default condition.
The RES_COLD bit is set only when the SafetySignal
resistance value is greater than 28.5kΩ. The SafetySignal
indicates a cold battery. The RES_COLD bit will be set
whenever the RES_OR bit is set.
The RESET_TO_ZERO bit sets the ChargingCurrent()and
ChargingVoltage() values to zero. This function ALWAYS
clears the ChargingVoltage() and ChargingCurrent() values to zero even if the INHIBIT_CHARGE bit is set.
The RES_HOT bit is set only when the SafetySignal resistance is less than 3150Ω, which indicates a hot battery.
The RES_HOT bit will be set whenever the RES_UR bit is
set.
ChargerStatus() ('h13)
The RES_UR bit is set only when the SafetySignal resistance value is less than 575Ω.
Description: The SMBus Host uses this command to read
the LTC4100’s status bits.
Purpose: Allows the SMBus Host to determine the status
and level of the LTC4100.
• SMBus Protocol: Read Word.
Output: The CHARGE_INHIBITED bit reflects the status of
the LTC4100 set by the INHIBIT_CHARGE bit in the
ChargerMode() function.
The POLLING_ENABLED, VOLTAGE_NOTREG, and
CURRENT_NOTREG are not supported by the LTC4100.
The LTC4100 always reports itself as a Level 2 Smart
Battery Charger.
CURRENT_OR bit is set only when ChargingCurrent() is
set to a value outside the current regulation range of the
LTC4100. This bit may be used in conjunction with the
INHIBIT_CHARGE bit of the ChargerMode() and
ChargingCurrent() to determine the current capability of
the LTC4100. When ChargingCurrent() is set to the programmatic maximum current + 1, the CURRENT_OR bit
will be set.
ALARM_INHIBITED bit is set if a valid AlarmWarning()
message has been received and charging is inhibited as a
result. This bit is cleared if both ChargingVoltage() and
ChargingCurrent() are re-written to the LTC4100, power is
removed (DCDIV < VACP), or if a battery is removed. The
setting of the ALARM_INHIBITED will activate the LTC4100
SMBALERT pull-down.
POWER_FAIL bit is set if the LTC4100 does not have
sufficient DCIN voltage to charge the battery or if an
external device is pulling the CHGEN input signal low.
Charging is disabled whenever this bit is set. The setting
of this bit does not clear the values in the ChargingVoltage()
and ChargingCurrent() function values, nor does it necessarily affect the charging modes of the LTC4100.
VOLTAGE_OR bit is set only when ChargingVoltage() is
set to a value outside the voltage regulation range of the
LTC4100. This bit may be used in conjunction with the
INHIBIT_CHARGE bit of the ChargerMode() and
ChargingVoltage() to determine the voltage capability of
the LTC4100. When ChargingVoltage() is set to the
programmatic maximum voltage, the VOLTAGE_OR bit
will be set.
BATTERY_PRESENT is set if a battery is present otherwise
it is cleared. The LTC4100 uses the SafetySignal
in order to determine battery presence. If the LTC4100
detects a RES_OR condition, the BATTERY_PRESENT bit
is cleared immediately. The LTC4100 will not set the
BATTERY_PRESENT bit until it successfully samples the
SafetySignal twice and does not detect a RES_OR condition on either sampling. If AC is not present (e.g. DCDIV <
VACP), this bit may not be set for up to one-half second
after the battery is connected to the SafetySignal. The
ChargingCurrent() and ChargingVoltage() function values
are immediately cleared whenever this bit is cleared.
Charging will never be allowed if this bit is cleared. A
change in BATTERY_PRESENT will activate the LTC4100
SMBALERT pull-down.
The RES_OR bit is set only when the SafetySignal resistance value is greater than 95kΩ. This indicates that the
SafetySignal is to be considered as an open circuit.
AC_PRESENT is set if the voltage on DCDIV is greater than
VACP. This does not necessarily indicate that the voltage on
DCIN is sufficient to charge the battery. A change in
sn4100 4100is
11
LTC4100
U
OPERATIO
AC_PRESENT will activate the LTC4100 SMBALERT pulldown.
ChargingCurrent() ('h14)
Description: The Battery, System Host or other master
device sends the desired charging current (mA) to the
LTC4100 .
Purpose: The LTC4100 uses RILIM, the granularity of the
IDAC, and the value of the ChargingCurrent() function to
determine its charging current supplied to the battery. The
charging current will never exceed the maximum current
permitted by RILIM. The ChargingCurrent() value will be
truncated to the granularity of the IDAC. The charging
current will also be reduced if the battery voltage exceeds
the programmed charging voltage.
• SMBus Protocol: Write Word.
Input: The CHARGING_CURRENT is an unsigned 16 bit
integer specifying the requested charging current in mA.
The following table defines the maximum permissible
value of CHARGING_CURRENT that will not set the
CURRENT_OR in the ChargerStatus() function for a given
value of the RILIM:
RILIM
ChargingCurrent()
Current
Short to GND
0x0000 through 0x03FF 0mA through 1023mA
10kΩ ±1%
0x0000 through 0x07FF 0mA through 2047mA
33kΩ ±1%
0x0000 through 0x0BFF 0mA through 3071mA
Open (or short to VDD) 0x0000 through 0x0FFF 0mA through 4095mA
ChargingVoltage() ('h15)
Description: The Battery, SMBus Host or other master
device sends the desired charging voltage (mV) to the
LTC4100.
Purpose: The LTC4100 uses RVLIM, the granularity of the
VDAC, and the value of the ChargingVoltage() function to
determine its charging voltage supplied to the battery. The
charging voltage will never be forced beyond the voltage
permitted by RVLIM. The ChargingVoltage() value will be
truncated to the granularity of the VDAC. The charging
voltage will also be reduced if the battery current exceeds
the programmed charging current.
• SMBus Protocol: Write Word.
Input: The CHARGING_VOLTAGE is an unsigned 16-bit
integer specifying the requested charging voltage in mV.
The LTC4100 considers any value from 0x0001 through
0x049F the same as writing 0x0000. The following
table defines the maximum permissible value of
CHARGING_VOLTAGE that will not set the VOLTAGE_OR
in the ChargerStatus() function for a given value of RVLIM:
RVLIM
Maximum ChargingVoltage()
Short to GND
0x225F (8796mV)
10kΩ ±1%
0x332F (13100mV)
33kΩ ±1%
0x43FF (17404mV)
100kΩ ±1%
0x54CF (21708mV)
Open (or short to VDD)
0x6D5F (27999mV)
AlarmWarning() ('h16)
Description: The Smart Battery, acting as a bus master
device, sends the AlarmWarning() message to the LTC4100
to notify it that one or more alarm conditions exist. Alarm
indications are encoded as bit fields in the Battery’s Status
register, which is then sent to the LTC4100 by this function.
Purpose: The LTC4100 will use the information sent by
this function to properly charge the battery. The LTC4100
will only respond to certain alarm bits. Writing to this
function does not necessarily cause an alarm condition
that inhibits battery charging.
• SMBus Protocol: Write Word.
Input: Only the OVER_CHARGED_ALARM, TERMINATE
_CHARGE_ALARM,reserved (0x2000), and OVER
_TEMP_ALARM bits are supported by the LTC4100.
Writing a one to any of these specified bits will inhibit
the charging by the LTC4100 and will set the
ALARM_INHIBITED bit in the ChargerStatus() function.␣ The
TERMINATE_DISCHARGE_ALARM,␣ REMAINING_
CAPACITY_ALARM, REMAINING_TIME_ALARM, and the
ERROR bits are ignored by the LTC4100.
LTC0() ('h3C)
Description: The SMBus Host uses this command to
determine the version number of the LTC4100 and set
extended operation modes not defined by the Smart
Battery Charger Specification.
sn4100 4100is
12
LTC4100
U
OPERATIO
Purpose: This function allows the SMBus Host to determine if the battery charger is an LTC4100. Identifying the
manufacturer and version of the Smart Battery Charger
permits software to perform tasks specific to a given
charger. The LTC4100 also provides a means of disabling
the LOWI current mode of the IDAC.
• SMBus Protocol: Write Word.
Input: The NO_LOWI is the only bit recognized by this
function. The default value of NO_LOWI is zero. The
LTC4100 LOWI current mode provides a more accurate
average charge current when the charge current is less
than 1/16 of the full-scale IDAC value. When the NO_LOWI
is set, a less accurate IDAC algorithm is used to generate
the charging current, but because the charger is not
pulsed on and off, it may be preferred.
• Change of BATTERY_PRESENT in the ChargerStatus()
function.
• Setting ALARM_INHIBITED in the ChargerStatus()
function.
• Internal power-on reset condition.
SMBus Accelerator Pull-Ups
The LTC Version Identification will always be 0x202 for the
LTC4100.
Both SCL and SDA have SMBus accelerator circuits which
reduce the rise time on systems with significant capacitance on the two SMBus signals. The dynamic pull-up
circuitry detects a rising edge on SDA or SCL and applies
1mA to 10mA pull-up to VDD when VIN > 0.8V until VIN
< VDD – 0.8V (external pull-up resistors are still required
to supply DC current). This action allows the bus to meet
SMBus rise time requirements with as much as 250pF on
each SMBus signal. The improved rise time will benefit all
of the devices which use the SMBus, especially those
devices that use the I2C logic levels. Note that the dynamic
pull-up circuits only pull to VDD, so some SMBus devices
that are not compliant to the SMBus specifications may
still have rise time compliance problems if the SMBus pullup resistors are terminated with voltages higher than VDD.
Alert Response Address (ARA)
The Control Block
Description: The SMBus system host uses the Alert
Response Address to quickly identify the generator of an
SMBALERT# event.
The LTC4100 charger operations are handled by the
control block. This block is capable of charging the selected battery autonomously or under SMBus Host control. The control block can request communications with
the system management host (SMBus Host) by asserting
SMBALERT = 0; this will cause the SMBus Host, if present,
to poll the LTC4100.
• SMBus Protocol: Read Word.
Output: The NO_LOWI indicates the IDAC mode of operation. If clear, then the LOWI current mode will be used
when the charging current is less than 1/16 of the fullscale IDAC value.
Purpose: The LTC4100 will respond to an ARA if the
SMBALERT signal is actively pulling down the SMBALERT#
bus. The LTC4100 will follow the prioritization reporting as
defined in the System Management Bus Specification,
Version 1.1, from the SBS Implementers Forum.
• SMBus Protocol: A 7-bit Addressable Device Responds to an ARA.
Output: The Device Address will be sent to the SMBus
system host. The LTC4100 Device address is 0x12 (or
0x09 if just looking at the 7-bit address field).
The following events will cause the LTC4100 to pull-down
the SMBALERT# bus through the SMBALERT pin:
• Change of AC_PRESENT in the ChargerStatus() function.
The control block receives SMBus slave commands from
the SMBus interface block.
The control block allows the LTC4100 to meet the following Smart Battery-controlled (Level 2) charger
requirements:
1. Implements the Smart Battery’s critical warning messages over the SMBus.
2. Operates as an SMBus slave device that responds to
ChargingVoltage() and ChargingCurrent() commands
and adjusts the charger output parameters accordingly.
sn4100 4100is
13
LTC4100
U
OPERATIO
3. The host may control charging by disabling the Smart
Battery’s ability to transmit ChargingCurrent() and
ChargingVoltage() request functions and broadcasting
the charging commands to the LTC4100 over the SMBus.
9. There is insufficient DCIN voltage to charge the battery.
The LTC4100 will resume wake-up charging when there is
sufficient DCIN voltage to charge the battery. This condition will not reset the TTIMEOUT timer.
4. The LTC4100 will still respond to Smart Battery critical
warning messages without host intervention.
Controlled Charging Algorithm Overview
Wake-up Charging Mode
The following conditions must be met in order to allow
controlled charging to start on the LTC4100:
The following conditions must be met in order to allow
wake-up charging of the battery:
1. The ChargingVoltage() AND ChargingCurrent() function must be written to non-zero values.
1. The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.
2. The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.
2. AC must be present. This is qualified by DCDIV > VACP.
3. AC must be present. This is qualified by DCDIV > VACP.
Wake-up charging initiates when a newly inserted battery
does not send ChargingCurrent() and ChargingVoltage()
functions to the LTC4100.
The following conditions will stop the Controlled Charging
Algorithm and will cause the Battery Charger Controller to
stop charging:
The following conditions will terminate the Wake-up Charging Mode.
1. The ChargingCurrent() AND ChargingVoltage() functions have not been written for TTIMEOUT.
1. A TTIMEOUT period is reached when the SafetySignal is
RES_COLD or RES_UR.
2. The SafetySignal is registering RES_OR.
2. The SafetySignal is registering RES_OR.
4. The AC power is no longer present. (DCDIV < VACP)
3. The successful writing of the ChargingCurrent() AND
ChargingVoltage() function. The LTC4100 will proceed to
the controlled charging mode after these two functions are
written.
5. ALARM_INHIBITED is set in the ChargerStatus() function.
4. The SafetySignal is registering RES_HOT.
5. The AC power is no longer present. (DCDIV < VACP)
6. The ALARM_INHIBITED becomes set in the
ChargerStatus() function.
7. The INHIBIT_CHARGE is set in the ChargerMode()
function.
8. The CHGEN pin is pulled low by an external device. The
LTC4100 will resume wake-up charging, if the CHGEN pin
is released by the external device. Toggling the CHGEN pin
will not reset the TTIMEOUT timer.
3. The SafetySignal is registering RES_HOT.
6. INHIBIT_CHARGE is set in the ChargerMode() function.
Clearing INHIBIT_CHARGE will cause the LTC4100 to
resume charging using the previous ChargingVoltage()
AND ChargingCurrent() function values.
7. RESET_TO_ZERO is set in the ChargerMode() function.
8. CHGEN pin is pulled low by an external device. The
LTC4100 will resume charging using the previous
ChargingVoltage() AND ChargingCurrent() function values, if the CHGEN pin is released by the external device.
9. Insufficient DCIN voltage to charge the battery. The
LTC4100 will resume charging using the previous
ChargingVoltage() AND ChargingCurrent() function val-
sn4100 4100is
14
LTC4100
U
OPERATIO
ues, when there is sufficient DCIN voltage to charge the
battery.
10. Writing a zero value to ChargingVoltage() function.
11. Writing a zero value to ChargingCurrent() function.
The SafetySignal Decoder Block
This block measures the resistance of the SafetySignal
and features high noise immunity at critical trip points. The
low power standby mode supports only battery presence
SMB charger reporting requirements when AC is not
present. The SafetySignal decoder is shown in Figure 4.
The value of RTHA is 1.13k and RTHB is 54.9k.
SafetySignal sensing is accomplished by a state machine
that reconfigures the switches of Figure 4 using THA_SELB
and THB_SELB, a selectable reference generator, and two
comparators. This circuit has two modes of operation
based upon whether AC is present.
When AC is present, the LTC4100 samples the value of the
SafetySignal and updates the ChargerStatus register approximately every 32ms. The state machine successively
samples the SafetySignal value starting with the RES_OR
≥ RES_COLD threshold, then RES_C0LD ≥ RES_IDEAL
threshold, RES_IDEAL ≥ RES_HOT threshold, and finally
the RES_HOT ≥ RES_UR threshold. Once the SafetySignal
range is determined, the lower value thresholds are not
sampled. The SafetySignal decoder block uses the previously determined SafetySignal value to provide the appropriate adjustment in threshold to add hysteresis. The RTHB
resistor value is used to measure the RES_OR ≥ RES_COLD
and RES_COLD ≥ RES_IDEAL thresholds by connecting
the THB pin to VDD and measuring the voltage resultant on
the THA pin. The RTHA resistor value is used to measure
the RES_IDEAL ≥ RES_HOT and RES_HOT ≥ RES_UR
thresholds by connecting the THA pin to VDD and measuring the voltage resultant on the THB pin.
The SafetySignal decoder block uses a voltage divider
network between VDD and GND to determine SafetySignal
range thresholds. Since the THA and THB inputs are
sequentially connected to VDD, this provides VDD noise
immunity during SafetySignal measurement.
When AC power is not available the SafetySignal block
supports the following low power operating features:
1. The SafetySignal is sampled every 250ms or less,
instead of 32ms.
2. A full SafetySignal status is sampled every 30s or less,
instead of every 32ms
The SafetySignal impedance is interpreted according to
Table 4.
VDD
VDD
THA_SELB
RTHA
1.13k
AC_PRESENT
+
MUX
THA
–
HI_REF
REF
LO_REF
VDD
THB_SELB
RTHB
54.9k
TH_HI
+
12.5k
TH_LO
+
–
33k
25k
VLIM
+
RVLIM
THB
RSafetySignal
RES_COLD
LATCH
–
25k
RES_OR
CSS
–
+
SafetySignal
CONTROL
25k
4
VLIM [3:0]
ENCODER
–
+
RES_H0T
12.5k
–
RES_UR
4100 F04
Figure 4. SafetySignal Decoder Block
4100 F05
Figure 5. Simplified VLIM Circuit Concept (ILIM is Similar)
sn4100 4100is
15
LTC4100
U
OPERATIO
Table 4. SafetySignal State Ranges
Table 6. ILIM Trip Points and Ranges
SafetySignal
RESISTANCE
CHARGE
STATUS BITS
0Ω to 500Ω
RES_UR,
RES_HOT
BATTERY_PRESENT
Underrange
500Ω to 3kΩ
RES_HOT
BATTERY_PRESENT
Hot
3kΩ to 30kΩ
BATTERY_PRESENT
Ideal
30kΩ to 100kΩ
RES_COLD
BATTERY_PRESENT
Cold
Above 100kΩ
RES_OR
RES_COLD
Overrange
DESCRIPTION
Note: The underrange detection scheme is a very important feature of the
LTC4100. The RTHA/RSafetySignal divider trip point of 0.333 • VDD (1V) is
well above the 0.047 • VDD (140mV) threshold of a system using a 10k
pull-up. A system using a 10k pull-up would not be able to resolve the
important underrange to hot transition point with a modest 100mV of
ground offset between battery and SafetySignal detection circuitry. Such
offsets are anticipated when charging at normal current levels.
EXTERNAL
RESISTOR
(RILIM)
CONTROLLED
CHARGING
CURRENT RANGE GRANULARITY
ILIM VOLTAGE
Short to GND
VILIM < 0.09VDD
0 < I < 1023mA
1mA
10k ±1%
0.17VVDD < VILIM
< 0.34VVDD
0 < I < 2046mA
2mA
33k ±1%
0.42VVDD < VILIM
< 0.59V
0 < I < 3068mA
4mA
Open (>250k,
or Short to VDD)
0.66VVDD < VILIM
0 < I < 4092mA
4mA
The VLIM Decoder Block
The value of an external resistor connected from this pin
to GND determines one of five voltage limits that are
applied to the charger output value. These limits provide
a measure of safety with a hardware restriction on charging voltage which cannot be overridden by software.
Table 7. VLIM Trip Points and Ranges (See Figure 5)
The required values for RTHA and RTHB are shown in
Table 5.
EXTERNAL
RESISTOR
(RVLIM)
Short to
GND
VVLIM < 0.09VVCCP
2900mV < VOUT
< 8800mV
16mV
Table 5. SafetySignal External Resistor Values
10k ±1%
0.17VVDD < VVLIM
< 0.34VVDD
2900mV < VOUT
< 13.104mV
16mV
33k ±1%
0.42VVCCP < VVLIM
< 0.59VVDD
2900mV < VOUT
< 17.408mV
16mV
100k ±1%
0.66VVDD < VVLIM
< 0.84VVDD
2900mV < VOUT
< 21.712mV
16mV
Open or
Tied to VDD
0.91VVDD < VVLIM
2900mV < VOUT
< 28000mV
16mV
EXTERNAL RESISTOR
VALUE (Ω)
RTHA
1130 ±1%
RTHB
54.9k ±1%
CSS represents the capacitance between the SafetySignal
and GND. CSS may be added to provide additional noise
immunity from transients in the application. CSS can not
exceed 1nF if the LTC4100 is to properly sense the value
of RSafetySignal.
The ILIM Decoder Block
The value of an external resistor connected from this pin
to GND determines one of four current limits that are used
for maximum charging current value. These limits provide
a measure of safety with a hardware restriction on charging current which cannot be overridden by software.
VLIM VOLTAGE
CONTROLLED
CHARGING VOLTAGE
(VOUT) RANGE
GRANULARITY
The Voltage DAC Block
Note that the charger output voltage is offset by VREF.
Therefore, the value of VREF is subtracted from the SMBus
ChargingVoltage() value in order for the output voltage to
be programmed properly (without offset). If the
ChargingVoltage() value is below the nominal reference
voltage of the charger, nominally 1.184V, the charger
output voltage is programmed to zero. In addition, if the
ChargingVoltage() value is above the limit set by the VLIM
pin, then the charger output voltage is set to the value
determined by the VLIM resistor and the VOLTAGE_OR bit
is set. These limits are demonstrated in Figure 6.
sn4100 4100is
16
LTC4100
U
OPERATIO
25
IPROG
(FROM CA1 AMP)
RVLIM = 33k
IDC
CHARGER VOUT (V)
20
RSET
15
–
VREF
∆-∑
MODULATOR
10
ITH
+
CHARGING_CURRENT
VALUE
4100 F07
5
Figure 7. Current DAC Operation
0
0
5
35
20
15
10
25
30
PROGRAMMED VALUE (V)
4100 F06
NOTE: THE LTC4100 CAN BE PROGRAMMED WITH ChargingVoltage() FUNCTION VALUES
BETWEEN 1.184V AND 2.9V, HOWEVER, THE BATTERY CHARGER CONTROLLER OUTPUT
VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2.9V.
Figure 6. Transfer Function of Charger
The Current DAC Block
The current DAC is a delta-sigma modulator which controls the effective value of an external resistor, RSET, used
to set the current limit of the charger. Figure 7 is a
simplified diagram of the DAC operation. The delta-sigma
modulator and switch convert the ChargingCurrent() value,
received via the SMBus, to a variable resistance equal to:
1.25RSET/ChargingCurrent()/ILIM[x])
Therefore, programmed current is equal to:
(102.3mV/RSENSE) (ChargingCurrent()/ILIM[x]),
for ChargingCurrent() < ILIM[x].
When a value less than 1/16th of the maximum current
allowed by ILIM is applied to the current DAC input, the
current DAC enters a different mode of operation called
LOWI. The current DAC output is pulse width modulated
with a high frequency clock having a duty cycle value of
1/8. Therefore, the maximum output current provided by
the charger is IMAX/8. The delta-sigma output gates this
low duty cycle signal on and off. The delta-sigma shift
registers are then clocked at a slower rate, about 45ms/bit,
so that the charger has time to settle to the IMAX/8 value.
The resulting average charging current is equal to that
requested by the ChargingCurrent() value.
AVERAGE CHARGER CURRENT
ILIMIT/8
0
~40ms
4100 F08
Figure 8. Charging Current Waveform in Low Current Mode
When wake-up is asserted to the current DAC block, the
delta-sigma is then fixed at a value equal to 80mA, independent of the ILIM setting.
Input FET
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLP pin,
and provides an indication of this condition at both the
CHGEN pin and the PWR_FAIL bit in the ChargerStatus()
register. It also controls the gate of the input FET to keep
a low forward voltage drop when charging and prevents
reverse current flow through the input FET.
If the input voltage is less than VCLP, it must go at least
130mV higher than VCLP to activate the charger. The
CHGEN pin is forced low unless this condition is met. The
gate of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLP drops to less than 25mV,
the input FET is turned off slowly. If the voltage between
DCIN and CLP is ever less than –25mV, then the input FET
is turned off quickly to prevent significant reverse current
from flowing in the input FET. In this condition the CHGEN
pin is driven low and the charger is disabled.
Note: The LOWI mode can be disabled by setting the
NO_LOWI bit in the LTC0() function.
sn4100 4100is
17
LTC4100
U
OPERATIO
The AC Present Block (AC_PRESENT)
The DCDIV pin is used to determine AC presence. If the
DCDIV voltage is above the DCDIV comparator threshold
(VACP), then the ACP output pin will be switched to VDD and
the AC_PRESENT bit in the ChargerStatus() function will
be set. If the DCDIV voltage is below the DCDIV comparator threshold minus the DCDIV comparator hysteresis,
then the ACP output pin is switched to GND and the
AC_PRESENT bit in the ChargerStatus() function is cleared.
The ACP output pin is designed to drive 2mA continuously.
U
W
U U
APPLICATIO S I FOR ATIO
Adapter Limiting
An important feature of the LTC4100 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the product to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
maximum possible rate of which the adapter is capable.
This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1
in Figure 9 senses the voltage across RCL, connected
between the CLP and CLN pins. When this voltage exceeds
100mV, the amplifier will override programmed charging
current to limit adapter current to 100mV/RCL. A lowpass
filter formed by 4.99k and 0.1µF is required to eliminate
switching noise. If the current limit is not used, CLP should
be connected to CLN.
input current limit tolerance and use that current to
determine the resistor value.
RCL = 100mV/ILIM
ILIM = Adapter Min Current –
(Adapter Min Current • 7%)
Table 8. Common RCL Resistor Values
ADAPTER
RATING (A)
RCL VALUE*
(Ω) 1%
RCL POWER
DISSIPATION (W)
RCL POWER
RATING (W)
1.5
0.06
0.135
0.25
1.8
0.05
0.162
0.25
2
0.045
0.18
0.25
2.3
0.039
0.206
0.25
2.5
0.036
0.225
0.5
2.7
0.033
0.241
0.5
3
0.03
0.27
0.5
* Values shown above are rounded to nearest standard value.
As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one can
simply set the adapter current limit value to the actual
adapter rating (see Table 8).
LTC4100
CLP
–
VIN
0.1µF
CL1
CLN
+
+
4.99k
100mV
INFET
*RCL =
100mV
ADAPTER CURRENT LIMIT
RCL*
TO LOAD
4100 F09
Charge Termination Issues
Batteries with constant current charging and voltagebased charger termination might experience problems
with reductions of charger current caused by adapter
limiting. It is recommended that input limiting feature be
defeated in such cases. Consult the battery manufacturer
for information on how your battery terminates charging.
Figure 9. Adapter Current Limiting
Setting Output Current Limit (Refer to Figure 1)
Setting Input Current Limit
To set the input current limit, you need to know the
minimum wall adapter current rating. Subtract 7% for the
The LTC4100 current DAC and the PWM analog circuitry
must coordinate the setting of the charger current. Failure
to do so will result in incorrect charge currents.
sn4100 4100is
18
LTC4100
U
U
W
U
APPLICATIO S I FOR ATIO
Table 10 Recommended Inductor Values
Table 9. Recommended Resistor Values
IMAX (A)
RSENSE (Ω) 1%
RSENSE (W)
1.023
0.100
0.25
0
2.046
0.05
0.25
10k
3.068
0.025
0.5
33k
4.092
0.025
0.5
RILIM (Ω) 1%
Open
Warning
DO NOT CHANGE THE VALUE OF RILIM DURING OPERATION. The value must remain fixed and track the RSENSE
value at all times. Changing the current setting can result
in currents that greatly exceed the requested value and
potentially damage the battery or overload the wall adapter
if no input current limiting is provided.
Inductor Selection
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value on
ripple current and low current operation must also be
considered. The inductor ripple current ∆IL decreases
with higher frequency and increases with higher VIN.
∆IL =
V
VOUT 1 − OUT
VIN
f L
1
( )( )
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(IMAX). Remember the
maximum ∆IL occurs at the maximum input voltage. The
inductor value also has an effect on low current operation.
The transition to low current operation begins when the
inductor current reaches zero while the bottom MOSFET is
on. Lower inductor values (higher ∆IL) will cause this to
occur at higher load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
practice 10µH is the lowest value recommended for use.
Maxaimum
Average Current (A)
Input
Voltage (V)
Minimum Inductor
Value (µH)
1
≤20
40 ± 20%
1
>20
56 ± 20%
2
≤20
20 ± 20%
2
>20
30 ± 20%
3
≤20
15 ± 20%
3
>20
20 ± 20%
4
≤20
10 ± 20%
4
>20
15 ± 20%
Calculating IC Power Dissipation
The power dissipation of the LTC4100 is dependent upon
the gate charge of the top and bottom MOSFETs (Q2 & Q3
respectively) The gate charge (QG) is determined from the
manufacturer’s data sheet and is dependent upon both the
gate voltage swing and the drain voltage swing of the
MOSFET. Use 6V for the gate voltage swing and VDCIN for
the drain voltage swing.
PD = VDCIN • (fOSC (QGQ2 + QGQ3) + IDCIN)
Example: VDCIN = 19V, fOSC = 345kHz, QGQ2 = 25nC,
QGQ3 = 15nC, IDCIN = 3mA.
PD = 320mW
Soft Start and Undervoltage Lockout
The LTC4100 is soft started by the 0.12µF capacitor on the
ITH pin. On start-up, ITH pin voltage will rise quickly to 0.5V,
then ramp up at a rate set by the internal 30µA pull-up
current and the external capacitor. Battery charging
current starts ramping up when ITH voltage reaches 0.8V
and full current is achieved with ITH at 2V. With a 0.12µF
capacitor, time to reach full charge current is about 2ms
and it is assumed that input voltage to the charger will
reach full value in less than 2ms. The capacitor can be
increased up to 1µF if longer input start-up times are
needed.
sn4100 4100is
19
LTC4100
U
W
U U
APPLICATIO S I FOR ATIO
In any switching regulator, conventional timer-based soft
starting can be defeated if the input voltage rises much
slower than the time out period. This happens because the
switching regulators in the battery charger and the computer power supply are typically supplying a fixed amount
of power to the load. If input voltage comes up slowly
compared to the soft start time, the regulators will try to
deliver full power to the load when the input voltage is still
well below its final value. If the adapter is current limited,
it cannot deliver full power at reduced output voltages and
the possibility exists for a quasi “latch” state where the
adapter output stays in a current limited state at reduced
output voltage. For instance, if maximum charger plus
computer load power is 30W, a 15V adapter might be
current limited at 2.5A. If adapter voltage is less than
(30W/2.5A = 12V) when full power is drawn, the adapter
voltage will be pulled down by the constant 30W load until
it reaches a lower stable state where the switching regulators can no longer supply full load. This situation can be
prevented by utilizing the DCDIV resistor divider, set
higher than the minimum adapter voltage where full power
can be achieved.
Input and Output Capacitors
In the 4A Lithium Battery Charger (Typical Application on
back page), the input capacitor (C2) is assumed to absorb
all input switching ripple current in the converter, so it
must have adequate ripple current rating. Worst-case
RMS ripple current will be equal to one half of output
charging current. Actual capacitance value is not critical.
Solid tantalum low ESR capacitors have high ripple current rating in a relatively small surface mount package, but
caution must be used when tantalum capacitors are used
for input or output bypass. High input surge currents can
be created when the adapter is hot-plugged to the charger
or when a battery is connected to the charger. Solid
tantalum capacitors have a known failure mechanism
when subjected to very high turn-on surge currents. Only
Kemet T495 series of “Surge Robust” low ESR tantalums
are rated for high surge conditions such as battery to
ground.
The relatively high ESR of an aluminum electrolytic for C1,
located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event. Refer to AN88
for more information.
The highest possible voltage rating on the capacitor will
minimize problems. Consult with the manufacturer before
use. Alternatives include new high capacity ceramic (at
least 20µF) from Tokin, United Chemi-Con/Marcon, et al.
Other alternative capacitors include OSCON capacitors
from Sanyo.
The output capacitor (C3) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
IRMS
V
0.29(VBAT ) 1 – BAT
VDCIN
=
(L1)(f)
For example, VDCIN = 19V, VBAT = 12.6V, L1 = 10µH, and
f = 300kHz, IRMS = 0.41A.
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
may be added to increase battery impedance at the300kHz
switching frequency. Switching ripple current splits between the battery and the output capacitor depending on
the ESR of the output capacitor and the battery impedance. If the ESR of C3 is 0.2Ω and the battery impedance
is raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.
sn4100 4100is
20
LTC4100
U
W
U U
APPLICATIO S I FOR ATIO
Protecting SMBus Inputs
PCB Layout Considerations
The SMBus inputs, SCL and SDA, are exposed to uncontrolled transient signals whenever a battery is connected
to the system. If the battery contains a static charge, the
SMBus inputs are subjected to transients which can cause
damage after repeated exposure. Also, if the battery’s
positive terminal makes contact to the connector before
the negative terminal, the SMBus inputs can be forced
below ground with the full battery potential, causing a
potential for latch-up in any of the devices connected to the
SMBus inputs. Therefore it is good design practice to
protect the SMBus inputs as shown in Figure 10.
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC
is essential. (See Figure 11.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
SWITCH NODE
L1
VBAT
VDD
CONNECTOR
TO BATTERY
VIN
TO SYSTEM
C2
HIGH
FREQUENCY
CIRCULATING
PATH
D1
C4
4100 F13
Figure 10. Recommended SMBus Transient Protection
BAT
4100 F15
Figure 11. High Speed Switching Path
sn4100 4100is
21
LTC4100
U
W
U U
APPLICATIO S I FOR ATIO
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that connect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.
smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at the
sense resistor location.
5. Place output capacitors next to the sense resistor
output and ground.
6. Output capacitor ground connections need to feed
into same copper that connects to the input capacitor
ground before tying back into system ground.
Interfacing with a Selector
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
The LTC4100 is designed to be used with a true analog
multiplexer for the SafetySignal sensing path. Some selector ICs from various manufacturers may not implement
this. Consult LTC applications department for more information.
4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time with
The LTC4100 is designed to work with a real battery.
Electronic loads will create instability within the LTC4100
preventing accurate programming currents and voltages.
Consult LTC applications department for more information.
Electronic Loads
DIRECTION OF CHARGING CURRENT
RSENSE
4100 F14
TO CSP AND BAT
Figure 12. Kelvin Sensing of Charging Current
sn4100 4100is
22
LTC4100
U
PACKAGE DESCRIPTIO
G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
7.90 – 8.50*
(.311 – .335)
24 23 22 21 20 19 18 17 16 15 14 13
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10 11 12
5.00 – 5.60**
(.197 – .221)
2.0
(.079)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
0.05
(.002)
G24 SSOP 0802
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
sn4100 4100is
23
LTC4100
U
TYPICAL APPLICATIO
LTC4100 Li-Ion Battery Charger ILIM = 4A/VLIM = 17.4V, Adapter Rating = 2.7A
15V TO 20V
DCIN
FROM WALL
ADAPTER
RCL
0.033Ω
0.5W
1%
Q1
C9
0.1µF
10V
C1
0.1µF
R10
13.7k
1%
4
5
11
R11
1.21k
1%
R5
6.04k
1%
24
13
10
6
10k
D2
7
SDA
D3
9
D4
8
SCL
CLN
TGATE
DCIN
1
Q2
C2, C3
10µF × 2
25V
DCDIV
ITH
PGND
3
D1
Q3
2
L1
10µH
4A
LTC4100
IDC
C8, 0.082µF
12
10V, X7R
GND
0.1µF
17
10V
VDD
R6, RVLIM 33k 14
VLIM
10k
23
INFET CLP
BGATE
19
C6, 0.12µF
10V, X7R
C7, 0.0015µF
10V, X7R
20
3V TO 5.5V
R1
4.9k
ILIM
CSP
BAT
21
22
C4
0.01µF
25V
VSET
18
C5
0.1µF
10V
ACP
CHGEN
THA
SMBALERT
THB
SDA
SCL
D5
RSNS
0.025Ω
0.5W, 1%
16
C4,C5
10µF × 2
25V
R4
100Ω
10k
RTHA
1.13k
1%
SafetySignal
15
RTHB
54.9k
1%
D1: MBRM140T3
D2-D5: SMALL SIGNAL SCHOTTKY
Q1: 1/2 Si4825
Q2: Si4431ADY
Q3: Si3456DY
SMART
BATTERY
4100 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1760
Smart Battery System Manager
Autonomous Power Management and Battery Charging for Two Smart
Batteries, SMBus Rev 1.1 Compliant.
LTC1960
Dual Battery Charger/Selector with SPI Interface
Simultaneous Charge or Discharge of 2 Batteries; DAC Programmable
Current and Voltage; Input Current Limiting Maximizes Charge Current
LTC1980
Combination Battery Charger and DC/DC Converter Input Supply Maybe Above or Below Battery Voltage, Up to 8.4V Float Voltage,
24-Pin SSOP Package
LTC4006
Small, High Efficiency, Fixed Voltage,
Lithium-ion Battery Charger
Constant Current/ Constant Voltage Switching Regulator with Termination
Timer; AC Adapter Current Limit and SafetySignal Sensor
in a Small 16pin Package
LTC4007
High Efficiency, Programmable Voltage
Battery Charger with Termination.
Complete Charger for 3- or 4-Cell Li-Ion batteries, AC Adapter
Current Limit, SafetySignal Sensor and Indicator Outputs.
LTC4008
High Efficiency, Programmable Voltage/Current
Battery Charger
Constant Current/Constant Voltage Switching Regulator; Resistor Voltage/
Current Programming, AC Adapter Current Limit and SafetySignal Sensor
LTC4412
Low Loss PowerPath Controller
Very Low Loss Replacement for Power Supply OR’ing Diodes using
Minimal External Components
sn4100 4100is
24
Linear Technology Corporation
LT/TP 0703 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002